Re: [PATCH] riscv: Add semihosting support [v4]

[Peter Maydell <peter.maydell@linaro.org>]

On Wed, 29 Jan 2020 at 16:45, Keith Packard <keithp@keithp.com> wrote:
>
> Peter Maydell <peter.maydell@linaro.org> writes:
>
> > True but irrelevant. You need to refer to a proper
> > risc-v specification for your semihosting.
>
> The RISC-V Foundation defined semihosting as relative to the existing
> ARM specification, so using a link to that is appropriate here.
>
> Here's the current specification of the unprivileged ISA, which includes
> the definition of semihosting
>
>         https://riscv.org/specifications/
>
> While it may be nice in some abstract sense to create a "better"
> semihosting spec, that's not what the RISC-V foundation has decided to
> do.

We've gone round this several times. You can't just
say "it's the arm spec", because you're not arm and
your architecture is different. You need to actually
document what the architecture-specific parts are,
even if you want to mostly say "and we follow the
Arm spec most of the time". If you really really want
to say "32 bit RISC-V is gratuitously different from
64-bit RISC-V in these areas because we just blindly
copied the way Arm happened to have historically
developed" then you can do that if you like, but you
need to actually write it down in a document somewhere.

You're trying to implement an ABI which has multiple
different implementations of both consumers and
producers; it's not a good idea to shortcut the
process of actually writing down what the requirements
between the two ends are.

thanks
-- PMM