* [Qemu-devel] [PATCH v2] nvic: Change NVIC to support ARMv6-M
@ 2018-07-19 12:16 Julia Suvorova
2018-07-19 16:25 ` Peter Maydell
0 siblings, 1 reply; 4+ messages in thread
From: Julia Suvorova @ 2018-07-19 12:16 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Stefan Hajnoczi, Joel Stanley, Jim Mussared,
Steffen Görtz, Julia Suvorova
The differences from ARMv7-M NVIC are:
* ARMv6-M only supports up to 32 external interrupts
(configurable feature already). The ICTR is reserved.
* Active Bit Register is reserved.
* ARMv6-M supports 4 priority levels against 256 in ARMv7-M.
Signed-off-by: Julia Suvorova <jusual@mail.ru>
---
v2:
* Added num_prio_bits field
* AIRCR.PRIGROUP is set as RAZ/WI for Baseline
hw/intc/armv7m_nvic.c | 21 ++++++++++++++++++---
include/hw/intc/armv7m_nvic.h | 1 +
2 files changed, 19 insertions(+), 3 deletions(-)
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
index 7ba87a050e..70967e795c 100644
--- a/hw/intc/armv7m_nvic.c
+++ b/hw/intc/armv7m_nvic.c
@@ -420,6 +420,8 @@ static void set_prio(NVICState *s, unsigned irq, bool secure, uint8_t prio)
assert(irq > ARMV7M_EXCP_NMI); /* only use for configurable prios */
assert(irq < s->num_irq);
+ prio &= MAKE_64BIT_MASK(8 - s->num_prio_bits, s->num_prio_bits);
+
if (secure) {
assert(exc_is_banked(irq));
s->sec_vectors[irq].prio = prio;
@@ -775,6 +777,9 @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs)
switch (offset) {
case 4: /* Interrupt Control Type. */
+ if (!arm_feature(&cpu->env, ARM_FEATURE_V7)) {
+ goto bad_offset;
+ }
return ((s->num_irq - NVIC_FIRST_IRQ) / 32) - 1;
case 0xc: /* CPPWR */
if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) {
@@ -1274,9 +1279,12 @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value,
"Setting VECTRESET when not in DEBUG mode "
"is UNPREDICTABLE\n");
}
- s->prigroup[attrs.secure] = extract32(value,
- R_V7M_AIRCR_PRIGROUP_SHIFT,
- R_V7M_AIRCR_PRIGROUP_LENGTH);
+ if (arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) {
+ s->prigroup[attrs.secure] =
+ extract32(value,
+ R_V7M_AIRCR_PRIGROUP_SHIFT,
+ R_V7M_AIRCR_PRIGROUP_LENGTH);
+ }
if (attrs.secure) {
/* These bits are only writable by secure */
cpu->env.v7m.aircr = value &
@@ -1787,6 +1795,11 @@ static MemTxResult nvic_sysreg_read(void *opaque, hwaddr addr,
break;
case 0x300 ... 0x33f: /* NVIC Active */
val = 0;
+
+ if (!arm_feature(&s->cpu->env, ARM_FEATURE_V7)) {
+ break;
+ }
+
startvec = 8 * (offset - 0x300) + NVIC_FIRST_IRQ; /* vector # */
for (i = 0, end = size * 8; i < end && startvec + i < s->num_irq; i++) {
@@ -2256,6 +2269,8 @@ static void armv7m_nvic_realize(DeviceState *dev, Error **errp)
/* include space for internal exception vectors */
s->num_irq += NVIC_FIRST_IRQ;
+ s->num_prio_bits = arm_feature(&s->cpu->env, ARM_FEATURE_V7) ? 8 : 2;
+
object_property_set_bool(OBJECT(&s->systick[M_REG_NS]), true,
"realized", &err);
if (err != NULL) {
diff --git a/include/hw/intc/armv7m_nvic.h b/include/hw/intc/armv7m_nvic.h
index 8bc29112e3..a472c9b8f0 100644
--- a/include/hw/intc/armv7m_nvic.h
+++ b/include/hw/intc/armv7m_nvic.h
@@ -57,6 +57,7 @@ typedef struct NVICState {
VecInfo sec_vectors[NVIC_INTERNAL_VECTORS];
/* The PRIGROUP field in AIRCR is banked */
uint32_t prigroup[M_REG_NUM_BANKS];
+ uint8_t num_prio_bits;
/* v8M NVIC_ITNS state (stored as a bool per bit) */
bool itns[NVIC_MAX_VECTORS];
--
2.17.1
^ permalink raw reply related [flat|nested] 4+ messages in thread
* Re: [Qemu-devel] [PATCH v2] nvic: Change NVIC to support ARMv6-M
2018-07-19 12:16 [Qemu-devel] [PATCH v2] nvic: Change NVIC to support ARMv6-M Julia Suvorova
@ 2018-07-19 16:25 ` Peter Maydell
2018-07-20 8:09 ` Julia Suvorova
0 siblings, 1 reply; 4+ messages in thread
From: Peter Maydell @ 2018-07-19 16:25 UTC (permalink / raw)
To: Julia Suvorova
Cc: qemu-devel, Stefan Hajnoczi, Joel Stanley, Jim Mussared,
Steffen Görtz
On 19 July 2018 at 13:16, Julia Suvorova <jusual@mail.ru> wrote:
> The differences from ARMv7-M NVIC are:
> * ARMv6-M only supports up to 32 external interrupts
> (configurable feature already). The ICTR is reserved.
> * Active Bit Register is reserved.
> * ARMv6-M supports 4 priority levels against 256 in ARMv7-M.
>
> Signed-off-by: Julia Suvorova <jusual@mail.ru>
> ---
> v2:
> * Added num_prio_bits field
> * AIRCR.PRIGROUP is set as RAZ/WI for Baseline
Applied to target-arm.for-3.1, thanks.
-- PMM
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [Qemu-devel] [PATCH v2] nvic: Change NVIC to support ARMv6-M
2018-07-19 16:25 ` Peter Maydell
@ 2018-07-20 8:09 ` Julia Suvorova
2018-07-20 9:07 ` Peter Maydell
0 siblings, 1 reply; 4+ messages in thread
From: Julia Suvorova @ 2018-07-20 8:09 UTC (permalink / raw)
To: Peter Maydell
Cc: qemu-devel, Stefan Hajnoczi, Joel Stanley, Jim Mussared,
Steffen Görtz
On 19.07.2018 19:25, Peter Maydell wrote:
> On 19 July 2018 at 13:16, Julia Suvorova <jusual@mail.ru> wrote:
>> The differences from ARMv7-M NVIC are:
>> * ARMv6-M only supports up to 32 external interrupts
>> (configurable feature already). The ICTR is reserved.
>> * Active Bit Register is reserved.
>> * ARMv6-M supports 4 priority levels against 256 in ARMv7-M.
>>
>> Signed-off-by: Julia Suvorova <jusual@mail.ru>
>> ---
>> v2:
>> * Added num_prio_bits field
>> * AIRCR.PRIGROUP is set as RAZ/WI for Baseline
>
> Applied to target-arm.for-3.1, thanks.
It seems like you applied the first version of this patch.
Can you check this, please?
Best regards, Julia Suvorova.
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [Qemu-devel] [PATCH v2] nvic: Change NVIC to support ARMv6-M
2018-07-20 8:09 ` Julia Suvorova
@ 2018-07-20 9:07 ` Peter Maydell
0 siblings, 0 replies; 4+ messages in thread
From: Peter Maydell @ 2018-07-20 9:07 UTC (permalink / raw)
To: Julia Suvorova
Cc: qemu-devel, Stefan Hajnoczi, Joel Stanley, Jim Mussared,
Steffen Görtz
On 20 July 2018 at 09:09, Julia Suvorova <jusual@mail.ru> wrote:
> On 19.07.2018 19:25, Peter Maydell wrote:
>>
>> On 19 July 2018 at 13:16, Julia Suvorova <jusual@mail.ru> wrote:
>>>
>>> The differences from ARMv7-M NVIC are:
>>> * ARMv6-M only supports up to 32 external interrupts
>>> (configurable feature already). The ICTR is reserved.
>>> * Active Bit Register is reserved.
>>> * ARMv6-M supports 4 priority levels against 256 in ARMv7-M.
>>>
>>> Signed-off-by: Julia Suvorova <jusual@mail.ru>
>>> ---
>>> v2:
>>> * Added num_prio_bits field
>>> * AIRCR.PRIGROUP is set as RAZ/WI for Baseline
>>
>>
>> Applied to target-arm.for-3.1, thanks.
>
>
> It seems like you applied the first version of this patch.
> Can you check this, please?
Oops, yes, you're right (v2 didn't get into the 'patches' db
for some reason). Now fixed.
thanks
-- PMM
^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2018-07-20 9:07 UTC | newest]
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2018-07-19 12:16 [Qemu-devel] [PATCH v2] nvic: Change NVIC to support ARMv6-M Julia Suvorova
2018-07-19 16:25 ` Peter Maydell
2018-07-20 8:09 ` Julia Suvorova
2018-07-20 9:07 ` Peter Maydell
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