All of lore.kernel.org
 help / color / mirror / Atom feed
* [PATCH] target/arm: add PMU feature to cortex-r5 and cortex-r5f
@ 2020-01-14 10:59 Clement Deschamps
  2020-01-14 12:44 ` Philippe Mathieu-Daudé
  0 siblings, 1 reply; 3+ messages in thread
From: Clement Deschamps @ 2020-01-14 10:59 UTC (permalink / raw)
  To: qemu-trivial, qemu-devel, qemu-arm; +Cc: Peter Maydell, Clement Deschamps

Signed-off-by: Clement Deschamps <clement.deschamps@greensocs.com>
---
See cortex-r5 TRM - 1.3 Features

PMU is not optional on cortex-r5 and cortex-r5f
---
 target/arm/cpu.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index d62fd5fdc6..64cd0a7d73 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -2121,6 +2121,7 @@ static void cortex_r5_initfn(Object *obj)
     set_feature(&cpu->env, ARM_FEATURE_V7);
     set_feature(&cpu->env, ARM_FEATURE_V7MP);
     set_feature(&cpu->env, ARM_FEATURE_PMSA);
+    set_feature(&cpu->env, ARM_FEATURE_PMU);
     cpu->midr = 0x411fc153; /* r1p3 */
     cpu->id_pfr0 = 0x0131;
     cpu->id_pfr1 = 0x001;
-- 
2.24.1



^ permalink raw reply related	[flat|nested] 3+ messages in thread

* Re: [PATCH] target/arm: add PMU feature to cortex-r5 and cortex-r5f
  2020-01-14 10:59 [PATCH] target/arm: add PMU feature to cortex-r5 and cortex-r5f Clement Deschamps
@ 2020-01-14 12:44 ` Philippe Mathieu-Daudé
  2020-01-20 13:00   ` Peter Maydell
  0 siblings, 1 reply; 3+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-01-14 12:44 UTC (permalink / raw)
  To: Clement Deschamps, qemu-trivial, qemu-devel, qemu-arm; +Cc: Peter Maydell

On 1/14/20 11:59 AM, Clement Deschamps wrote:

Maybe describe here:

The PMU is not optional on cortex-r5 and cortex-r5f (see
the "Features" chapter of the Technical Reference Manual).

> Signed-off-by: Clement Deschamps <clement.deschamps@greensocs.com>

Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>

> ---
> See cortex-r5 TRM - 1.3 Features
> 
> PMU is not optional on cortex-r5 and cortex-r5f
> ---
>   target/arm/cpu.c | 1 +
>   1 file changed, 1 insertion(+)
> 
> diff --git a/target/arm/cpu.c b/target/arm/cpu.c
> index d62fd5fdc6..64cd0a7d73 100644
> --- a/target/arm/cpu.c
> +++ b/target/arm/cpu.c
> @@ -2121,6 +2121,7 @@ static void cortex_r5_initfn(Object *obj)
>       set_feature(&cpu->env, ARM_FEATURE_V7);
>       set_feature(&cpu->env, ARM_FEATURE_V7MP);
>       set_feature(&cpu->env, ARM_FEATURE_PMSA);
> +    set_feature(&cpu->env, ARM_FEATURE_PMU);
>       cpu->midr = 0x411fc153; /* r1p3 */
>       cpu->id_pfr0 = 0x0131;
>       cpu->id_pfr1 = 0x001;
> 



^ permalink raw reply	[flat|nested] 3+ messages in thread

* Re: [PATCH] target/arm: add PMU feature to cortex-r5 and cortex-r5f
  2020-01-14 12:44 ` Philippe Mathieu-Daudé
@ 2020-01-20 13:00   ` Peter Maydell
  0 siblings, 0 replies; 3+ messages in thread
From: Peter Maydell @ 2020-01-20 13:00 UTC (permalink / raw)
  To: Philippe Mathieu-Daudé
  Cc: QEMU Trivial, Clement Deschamps, QEMU Developers, qemu-arm

On Tue, 14 Jan 2020 at 12:44, Philippe Mathieu-Daudé <philmd@redhat.com> wrote:
>
> On 1/14/20 11:59 AM, Clement Deschamps wrote:
>
> Maybe describe here:
>
> The PMU is not optional on cortex-r5 and cortex-r5f (see
> the "Features" chapter of the Technical Reference Manual).
>
> > Signed-off-by: Clement Deschamps <clement.deschamps@greensocs.com>
>
> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>



Applied to target-arm.next, thanks (with the suggested
improvement to the commit message).

-- PMM


^ permalink raw reply	[flat|nested] 3+ messages in thread

end of thread, other threads:[~2020-01-20 13:01 UTC | newest]

Thread overview: 3+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-01-14 10:59 [PATCH] target/arm: add PMU feature to cortex-r5 and cortex-r5f Clement Deschamps
2020-01-14 12:44 ` Philippe Mathieu-Daudé
2020-01-20 13:00   ` Peter Maydell

This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.