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From: Peter Maydell <peter.maydell@linaro.org>
To: Shannon Zhao <zhaoshenglong@huawei.com>
Cc: qemu-arm <qemu-arm@nongnu.org>,
	QEMU Developers <qemu-devel@nongnu.org>,
	Patch Tracking <patches@linaro.org>,
	Shlomo Pongratz <shlomo.pongratz@huawei.com>,
	Shlomo Pongratz <shlomopongratz@gmail.com>,
	Pavel Fedin <p.fedin@samsung.com>,
	Shannon Zhao <shannon.zhao@linaro.org>,
	Christoffer Dall <christoffer.dall@linaro.org>
Subject: Re: [Qemu-devel] [PATCH 10/23] hw/intc/arm_gicv3: Implement functions to identify next pending irq
Date: Thu, 19 May 2016 14:21:31 +0100	[thread overview]
Message-ID: <CAFEAcA93G2YF2M2X3cQQnMkb5V9uY0kOk-s36uwgOuVFY85Cgw@mail.gmail.com> (raw)
In-Reply-To: <573DB8A2.1000701@huawei.com>

On 19 May 2016 at 13:59, Shannon Zhao <zhaoshenglong@huawei.com> wrote:
>
>
> On 2016/5/10 1:29, Peter Maydell wrote:
>> +    uint32_t pend, grpmask;
>> +    uint32_t pending = *gic_bmp_ptr32(s->pending, irq - GIC_INTERNAL);
>> +    uint32_t edge_trigger = *gic_bmp_ptr32(s->edge_trigger, irq - GIC_INTERNAL);
>> +    uint32_t level = *gic_bmp_ptr32(s->level, irq - GIC_INTERNAL);
>> +    uint32_t group = *gic_bmp_ptr32(s->group, irq - GIC_INTERNAL);
>> +    uint32_t grpmod = *gic_bmp_ptr32(s->grpmod, irq - GIC_INTERNAL);
>> +    uint32_t enable = *gic_bmp_ptr32(s->enabled, irq - GIC_INTERNAL);
>> +
> Since you use "irq - GIC_INTERNAL" many times, how about moving into the
> gic_bmp_ptr32()?

The bmp* functions are supposed to be generic (with APIs matching
the bitmap.h ones), so passing it X should give you bit X in the bitmap.

Maybe it would be less confusing to make the bitmaps all have 32 unused
bits at the start, so the bit for interrupt X is bit X in the bitmap...
That only costs us five words of memory per CPU, so it seems worth
it for the code clarity and avoiding annoying bugs.

>>  /**
>> + * gicv3_irq_group:
>> + *
>> + * Return the group which this interrupt is configured as (GICV3_G0,
>> + * GICV3_G1 or GICV3_G1NS).
>> + */
>> +static inline int gicv3_irq_group(GICv3State *s, GICv3CPUState *cs, int irq)
> use uint32_t instead of int in this and other functions?

Neither interrupt numbers nor group numbers are particularly
large or specifically 32-bit, so 'int' seemed the most reasonable
type to use.

thanks
-- PMM

  reply	other threads:[~2016-05-19 13:22 UTC|newest]

Thread overview: 40+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-05-09 17:29 [Qemu-devel] [PATCH 00/23] GICv3 emulation Peter Maydell
2016-05-09 17:29 ` [Qemu-devel] [PATCH 01/23] migration: Define VMSTATE_UINT64_2DARRAY Peter Maydell
2016-05-09 17:29 ` [Qemu-devel] [PATCH 02/23] bitops.h: Implement half-shuffle and half-unshuffle ops Peter Maydell
2016-05-09 17:29 ` [Qemu-devel] [PATCH 03/23] target-arm: Define new arm_is_el3_or_mon() function Peter Maydell
2016-05-10 13:42   ` Shannon Zhao
2016-05-09 17:29 ` [Qemu-devel] [PATCH 04/23] target-arm: Provide hook to tell GICv3 about changes of security state Peter Maydell
2016-05-09 17:29 ` [Qemu-devel] [PATCH 05/23] target-arm: Add mp-affinity property for ARM CPU class Peter Maydell
2016-05-09 17:29 ` [Qemu-devel] [PATCH 06/23] hw/intc/arm_gicv3: Add state information Peter Maydell
2016-05-19  9:36   ` Shannon Zhao
2016-05-19  9:47     ` Peter Maydell
2016-05-09 17:29 ` [Qemu-devel] [PATCH 07/23] hw/intc/arm_gicv3: Move irq lines into GICv3CPUState structure Peter Maydell
2016-05-09 17:29 ` [Qemu-devel] [PATCH 08/23] hw/intc/arm_gicv3: Add vmstate descriptors Peter Maydell
2016-05-09 17:29 ` [Qemu-devel] [PATCH 09/23] hw/intc/arm_gicv3: ARM GICv3 device framework Peter Maydell
2016-05-09 17:29 ` [Qemu-devel] [PATCH 10/23] hw/intc/arm_gicv3: Implement functions to identify next pending irq Peter Maydell
2016-05-19 12:59   ` Shannon Zhao
2016-05-19 13:21     ` Peter Maydell [this message]
2016-05-09 17:29 ` [Qemu-devel] [PATCH 11/23] hw/intc/arm_gicv3: Implement GICv3 distributor registers Peter Maydell
2016-05-13 15:05   ` Shannon Zhao
2016-05-13 15:24     ` Peter Maydell
2016-05-16  8:56       ` Peter Maydell
2016-05-09 17:29 ` [Qemu-devel] [PATCH 12/23] hw/intc/arm_gicv3: Implement GICv3 redistributor registers Peter Maydell
2016-05-09 17:29 ` [Qemu-devel] [PATCH 13/23] hw/intc/arm_gicv3: Wire up distributor and redistributor MMIO regions Peter Maydell
2016-05-09 17:29 ` [Qemu-devel] [PATCH 14/23] hw/intc/arm_gicv3: Implement gicv3_set_irq() Peter Maydell
2016-05-09 17:29 ` [Qemu-devel] [PATCH 15/23] hw/intc/arm_gicv3: Implement GICv3 CPU interface registers Peter Maydell
2016-05-09 17:29 ` [Qemu-devel] [PATCH 16/23] hw/intc/arm_gicv3: Implement gicv3_cpuif_update() Peter Maydell
2016-05-09 17:29 ` [Qemu-devel] [PATCH 17/23] hw/intc/arm_gicv3: Implement CPU i/f SGI generation registers Peter Maydell
2016-05-09 17:29 ` [Qemu-devel] [PATCH 18/23] hw/intc/arm_gicv3: Add IRQ handling CPU interface registers Peter Maydell
2016-05-09 17:29 ` [Qemu-devel] [PATCH 19/23] target-arm/machine.c: Allow user to request GICv3 emulation Peter Maydell
2016-05-09 17:29 ` [Qemu-devel] [PATCH 20/23] target-arm/monitor.c: Advertise emulated GICv3 in capabilities Peter Maydell
2016-05-09 17:29 ` [Qemu-devel] [PATCH 21/23] hw/intc/arm_gicv3: Work around Linux assuming interrupts are group 1 Peter Maydell
2016-05-09 17:29 ` [Qemu-devel] [PATCH 22/23] NOT-FOR-UPSTREAM: kernel: Add definitions for GICv3 attributes Peter Maydell
2016-05-09 17:29 ` [Qemu-devel] [PATCH 23/23] RFC: hw/intc/arm_gicv3_kvm: Implement get/put functions Peter Maydell
2016-05-11  6:51 ` [Qemu-devel] [PATCH 00/23] GICv3 emulation Shannon Zhao
2016-05-12 13:53   ` Peter Maydell
2016-05-12 14:31     ` Shannon Zhao
2016-05-12 14:35       ` Peter Maydell
2016-05-12 15:01         ` Shannon Zhao
2016-05-12 15:22           ` Peter Maydell
2016-05-13 14:35             ` Shannon Zhao
2016-05-25 14:50 ` Shannon Zhao

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