[Qemu-devel] [PATCH v3 00/14] tcg: remainder and tcg-arm updates

[Qemu-devel] [PATCH v3 00/14] tcg: remainder and tcg-arm updates

[Richard Henderson]

Changes v2-v3:
  * Add myself to tcg maintainers, as per afaerber's suggestion.
  * Fix rebase error wrt aarch64, as per claudio.
  * Include tcg-arm unwind patch set; no point in half measures.


r~


The following changes since commit ab8bf29078e0ab8347e2ff8b4e5542f7a0c751cf:

  Merge remote-tracking branch 'qemu-kvm/uq/master' into staging (2013-07-03 08:37:00 -0500)

are available in the git repository at:

  git://github.com/rth7680/qemu.git tcg-next

for you to fetch changes up to 6688d5d7eefa67b5f50b6f03a2456e4635781b3b:

  tcg-arm: Implement tcg_register_jit (2013-07-03 11:17:57 -0700)

----------------------------------------------------------------
Richard Henderson (14):
      tcg: Add myself to general TCG maintainership
      tcg: Split rem requirement from div requirement
      tcg-arm: Don't implement rem
      tcg-ppc: Don't implement rem
      tcg-ppc64: Don't implement rem
      tcg: Allow non-constant control macros
      tcg: Simplify logic using TCG_OPF_NOT_PRESENT
      tcg-arm: Make use of conditional availability of opcodes for divide
      tcg-arm: Simplify logic in detecting the ARM ISA in use
      tcg-arm: Use AT_PLATFORM to detect the host ISA
      tcg: Fix high_pc fields in .debug_info
      tcg: Move the CIE and FDE header definitions to common code
      tcg-i386: Use QEMU_BUILD_BUG_ON instead of assert for frame size
      tcg-arm: Implement tcg_register_jit

 MAINTAINERS              |   1 +
 tcg/aarch64/tcg-target.h |   2 +
 tcg/arm/tcg-target.c     | 172 ++++++++++++++++++++++++++++++-----------------
 tcg/arm/tcg-target.h     |  15 +++--
 tcg/hppa/tcg-target.c    |  35 +++-------
 tcg/hppa/tcg-target.h    |   1 +
 tcg/i386/tcg-target.c    |  45 +++++--------
 tcg/ia64/tcg-target.h    |   2 +
 tcg/mips/tcg-target.h    |   1 +
 tcg/ppc/tcg-target.c     |  14 ----
 tcg/ppc/tcg-target.h     |   1 +
 tcg/ppc64/tcg-target.c   |  26 -------
 tcg/ppc64/tcg-target.h   |   2 +
 tcg/sparc/tcg-target.c   |  35 +++-------
 tcg/sparc/tcg-target.h   |   2 +
 tcg/tcg-op.h             |  32 +++++++--
 tcg/tcg-opc.h            |  36 +++++-----
 tcg/tcg.c                |  26 +++++--
 tcg/tcg.h                |   6 +-
 tcg/tci/tcg-target.h     |   2 +
 20 files changed, 242 insertions(+), 214 deletions(-)

[Qemu-devel] [PATCH v3 01/14] tcg: Add myself to general TCG maintainership

[Richard Henderson]

Signed-off-by: Richard Henderson <rth@twiddle.net>
---
 MAINTAINERS | 1 +
 1 file changed, 1 insertion(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index ad9c860..7847e60 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -772,6 +772,7 @@ Tiny Code Generator (TCG)
 -------------------------
 Common code
 M: qemu-devel@nongnu.org
+M: Richard Henderson <rth@twiddle.net>
 S: Maintained
 F: tcg/
 
-- 
1.8.1.4

[Qemu-devel] [PATCH v3 02/14] tcg: Split rem requirement from div requirement

[Richard Henderson]

There are several hosts with only a "div" insn.  Remainder is computed
manually from the quotient and inputs.  We can do this generically.

Signed-off-by: Richard Henderson <rth@twiddle.net>
---
 tcg/aarch64/tcg-target.h |  2 ++
 tcg/arm/tcg-target.h     |  2 ++
 tcg/hppa/tcg-target.h    |  1 +
 tcg/ia64/tcg-target.h    |  2 ++
 tcg/mips/tcg-target.h    |  1 +
 tcg/ppc/tcg-target.h     |  1 +
 tcg/ppc64/tcg-target.h   |  2 ++
 tcg/sparc/tcg-target.h   |  2 ++
 tcg/tcg-op.h             | 32 ++++++++++++++++++++++++++++----
 tcg/tcg-opc.h            |  8 ++++----
 tcg/tcg.h                |  3 +++
 tcg/tci/tcg-target.h     |  2 ++
 12 files changed, 50 insertions(+), 8 deletions(-)

diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h
index 97e4a5b..51e5092 100644
--- a/tcg/aarch64/tcg-target.h
+++ b/tcg/aarch64/tcg-target.h
@@ -40,6 +40,7 @@ typedef enum {
 
 /* optional instructions */
 #define TCG_TARGET_HAS_div_i32          0
+#define TCG_TARGET_HAS_rem_i32          0
 #define TCG_TARGET_HAS_ext8s_i32        1
 #define TCG_TARGET_HAS_ext16s_i32       1
 #define TCG_TARGET_HAS_ext8u_i32        1
@@ -62,6 +63,7 @@ typedef enum {
 #define TCG_TARGET_HAS_muls2_i32        0
 
 #define TCG_TARGET_HAS_div_i64          0
+#define TCG_TARGET_HAS_rem_i64          0
 #define TCG_TARGET_HAS_ext8s_i64        1
 #define TCG_TARGET_HAS_ext16s_i64       1
 #define TCG_TARGET_HAS_ext32s_i64       1
diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h
index 3be41cc..2c5b4e7 100644
--- a/tcg/arm/tcg-target.h
+++ b/tcg/arm/tcg-target.h
@@ -76,8 +76,10 @@ typedef enum {
 
 #ifdef __ARM_ARCH_EXT_IDIV__
 #define TCG_TARGET_HAS_div_i32          1
+#define TCG_TARGET_HAS_rem_i32          1
 #else
 #define TCG_TARGET_HAS_div_i32          0
+#define TCG_TARGET_HAS_rem_i32          0
 #endif
 
 extern bool tcg_target_deposit_valid(int ofs, int len);
diff --git a/tcg/hppa/tcg-target.h b/tcg/hppa/tcg-target.h
index ebd53d9..25467bd 100644
--- a/tcg/hppa/tcg-target.h
+++ b/tcg/hppa/tcg-target.h
@@ -85,6 +85,7 @@ typedef enum {
 
 /* optional instructions */
 #define TCG_TARGET_HAS_div_i32          0
+#define TCG_TARGET_HAS_rem_i32          0
 #define TCG_TARGET_HAS_rot_i32          1
 #define TCG_TARGET_HAS_ext8s_i32        1
 #define TCG_TARGET_HAS_ext16s_i32       1
diff --git a/tcg/ia64/tcg-target.h b/tcg/ia64/tcg-target.h
index e3d72ea..f32d519 100644
--- a/tcg/ia64/tcg-target.h
+++ b/tcg/ia64/tcg-target.h
@@ -104,7 +104,9 @@ typedef enum {
 
 /* optional instructions */
 #define TCG_TARGET_HAS_div_i32          0
+#define TCG_TARGET_HAS_rem_i32          0
 #define TCG_TARGET_HAS_div_i64          0
+#define TCG_TARGET_HAS_rem_i64          0
 #define TCG_TARGET_HAS_andc_i32         1
 #define TCG_TARGET_HAS_andc_i64         1
 #define TCG_TARGET_HAS_bswap16_i32      1
diff --git a/tcg/mips/tcg-target.h b/tcg/mips/tcg-target.h
index 6155327..a438950 100644
--- a/tcg/mips/tcg-target.h
+++ b/tcg/mips/tcg-target.h
@@ -79,6 +79,7 @@ typedef enum {
 
 /* optional instructions */
 #define TCG_TARGET_HAS_div_i32          1
+#define TCG_TARGET_HAS_rem_i32          1
 #define TCG_TARGET_HAS_not_i32          1
 #define TCG_TARGET_HAS_nor_i32          1
 #define TCG_TARGET_HAS_ext8s_i32        1
diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h
index 17a6bb3..01b880e 100644
--- a/tcg/ppc/tcg-target.h
+++ b/tcg/ppc/tcg-target.h
@@ -78,6 +78,7 @@ typedef enum {
 
 /* optional instructions */
 #define TCG_TARGET_HAS_div_i32          1
+#define TCG_TARGET_HAS_rem_i32          1
 #define TCG_TARGET_HAS_rot_i32          1
 #define TCG_TARGET_HAS_ext8s_i32        1
 #define TCG_TARGET_HAS_ext16s_i32       1
diff --git a/tcg/ppc64/tcg-target.h b/tcg/ppc64/tcg-target.h
index cb77634..7c600f1 100644
--- a/tcg/ppc64/tcg-target.h
+++ b/tcg/ppc64/tcg-target.h
@@ -76,6 +76,7 @@ typedef enum {
 
 /* optional instructions */
 #define TCG_TARGET_HAS_div_i32          1
+#define TCG_TARGET_HAS_rem_i32          1
 #define TCG_TARGET_HAS_rot_i32          1
 #define TCG_TARGET_HAS_ext8s_i32        1
 #define TCG_TARGET_HAS_ext16s_i32       1
@@ -96,6 +97,7 @@ typedef enum {
 #define TCG_TARGET_HAS_muls2_i32        0
 
 #define TCG_TARGET_HAS_div_i64          1
+#define TCG_TARGET_HAS_rem_i64          1
 #define TCG_TARGET_HAS_rot_i64          1
 #define TCG_TARGET_HAS_ext8s_i64        1
 #define TCG_TARGET_HAS_ext16s_i64       1
diff --git a/tcg/sparc/tcg-target.h b/tcg/sparc/tcg-target.h
index b5217be..dab52d7 100644
--- a/tcg/sparc/tcg-target.h
+++ b/tcg/sparc/tcg-target.h
@@ -86,6 +86,7 @@ typedef enum {
 
 /* optional instructions */
 #define TCG_TARGET_HAS_div_i32		1
+#define TCG_TARGET_HAS_rem_i32		1
 #define TCG_TARGET_HAS_rot_i32          0
 #define TCG_TARGET_HAS_ext8s_i32        0
 #define TCG_TARGET_HAS_ext16s_i32       0
@@ -109,6 +110,7 @@ typedef enum {
 
 #if TCG_TARGET_REG_BITS == 64
 #define TCG_TARGET_HAS_div_i64          1
+#define TCG_TARGET_HAS_rem_i64          1
 #define TCG_TARGET_HAS_rot_i64          0
 #define TCG_TARGET_HAS_ext8s_i64        0
 #define TCG_TARGET_HAS_ext16s_i64       0
diff --git a/tcg/tcg-op.h b/tcg/tcg-op.h
index 94f6043..364964d 100644
--- a/tcg/tcg-op.h
+++ b/tcg/tcg-op.h
@@ -731,8 +731,14 @@ static inline void tcg_gen_div_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
 
 static inline void tcg_gen_rem_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
 {
-    if (TCG_TARGET_HAS_div_i32) {
+    if (TCG_TARGET_HAS_rem_i32) {
         tcg_gen_op3_i32(INDEX_op_rem_i32, ret, arg1, arg2);
+    } else if (TCG_TARGET_HAS_div_i32) {
+        TCGv_i32 t0 = tcg_temp_new_i32();
+        tcg_gen_op3_i32(INDEX_op_div_i32, t0, arg1, arg2);
+        tcg_gen_mul_i32(t0, t0, arg2);
+        tcg_gen_sub_i32(ret, arg1, t0);
+        tcg_temp_free_i32(t0);
     } else if (TCG_TARGET_HAS_div2_i32) {
         TCGv_i32 t0 = tcg_temp_new_i32();
         tcg_gen_sari_i32(t0, arg1, 31);
@@ -769,8 +775,14 @@ static inline void tcg_gen_divu_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
 
 static inline void tcg_gen_remu_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
 {
-    if (TCG_TARGET_HAS_div_i32) {
+    if (TCG_TARGET_HAS_rem_i32) {
         tcg_gen_op3_i32(INDEX_op_remu_i32, ret, arg1, arg2);
+    } else if (TCG_TARGET_HAS_div_i32) {
+        TCGv_i32 t0 = tcg_temp_new_i32();
+        tcg_gen_op3_i32(INDEX_op_divu_i32, t0, arg1, arg2);
+        tcg_gen_mul_i32(t0, t0, arg2);
+        tcg_gen_sub_i32(ret, arg1, t0);
+        tcg_temp_free_i32(t0);
     } else if (TCG_TARGET_HAS_div2_i32) {
         TCGv_i32 t0 = tcg_temp_new_i32();
         tcg_gen_movi_i32(t0, 0);
@@ -1361,8 +1373,14 @@ static inline void tcg_gen_div_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
 
 static inline void tcg_gen_rem_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
 {
-    if (TCG_TARGET_HAS_div_i64) {
+    if (TCG_TARGET_HAS_rem_i64) {
         tcg_gen_op3_i64(INDEX_op_rem_i64, ret, arg1, arg2);
+    } else if (TCG_TARGET_HAS_div_i64) {
+        TCGv_i64 t0 = tcg_temp_new_i64();
+        tcg_gen_op3_i64(INDEX_op_div_i64, t0, arg1, arg2);
+        tcg_gen_mul_i64(t0, t0, arg2);
+        tcg_gen_sub_i64(ret, arg1, t0);
+        tcg_temp_free_i64(t0);
     } else if (TCG_TARGET_HAS_div2_i64) {
         TCGv_i64 t0 = tcg_temp_new_i64();
         tcg_gen_sari_i64(t0, arg1, 63);
@@ -1399,8 +1417,14 @@ static inline void tcg_gen_divu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
 
 static inline void tcg_gen_remu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
 {
-    if (TCG_TARGET_HAS_div_i64) {
+    if (TCG_TARGET_HAS_rem_i64) {
         tcg_gen_op3_i64(INDEX_op_remu_i64, ret, arg1, arg2);
+    } else if (TCG_TARGET_HAS_div_i64) {
+        TCGv_i64 t0 = tcg_temp_new_i64();
+        tcg_gen_op3_i64(INDEX_op_divu_i64, t0, arg1, arg2);
+        tcg_gen_mul_i64(t0, t0, arg2);
+        tcg_gen_sub_i64(ret, arg1, t0);
+        tcg_temp_free_i64(t0);
     } else if (TCG_TARGET_HAS_div2_i64) {
         TCGv_i64 t0 = tcg_temp_new_i64();
         tcg_gen_movi_i64(t0, 0);
diff --git a/tcg/tcg-opc.h b/tcg/tcg-opc.h
index 4246e9c..12967fb 100644
--- a/tcg/tcg-opc.h
+++ b/tcg/tcg-opc.h
@@ -66,8 +66,8 @@ DEF(sub_i32, 1, 2, 0, 0)
 DEF(mul_i32, 1, 2, 0, 0)
 DEF(div_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_div_i32))
 DEF(divu_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_div_i32))
-DEF(rem_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_div_i32))
-DEF(remu_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_div_i32))
+DEF(rem_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_rem_i32))
+DEF(remu_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_rem_i32))
 DEF(div2_i32, 2, 3, 0, IMPL(TCG_TARGET_HAS_div2_i32))
 DEF(divu2_i32, 2, 3, 0, IMPL(TCG_TARGET_HAS_div2_i32))
 DEF(and_i32, 1, 2, 0, 0)
@@ -126,8 +126,8 @@ DEF(sub_i64, 1, 2, 0, IMPL64)
 DEF(mul_i64, 1, 2, 0, IMPL64)
 DEF(div_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_div_i64))
 DEF(divu_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_div_i64))
-DEF(rem_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_div_i64))
-DEF(remu_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_div_i64))
+DEF(rem_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_rem_i64))
+DEF(remu_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_rem_i64))
 DEF(div2_i64, 2, 3, 0, IMPL64 | IMPL(TCG_TARGET_HAS_div2_i64))
 DEF(divu2_i64, 2, 3, 0, IMPL64 | IMPL(TCG_TARGET_HAS_div2_i64))
 DEF(and_i64, 1, 2, 0, IMPL64)
diff --git a/tcg/tcg.h b/tcg/tcg.h
index df375cf..28ca1bd 100644
--- a/tcg/tcg.h
+++ b/tcg/tcg.h
@@ -60,6 +60,7 @@ typedef uint64_t TCGRegSet;
 #if TCG_TARGET_REG_BITS == 32
 /* Turn some undef macros into false macros.  */
 #define TCG_TARGET_HAS_div_i64          0
+#define TCG_TARGET_HAS_rem_i64          0
 #define TCG_TARGET_HAS_div2_i64         0
 #define TCG_TARGET_HAS_rot_i64          0
 #define TCG_TARGET_HAS_ext8s_i64        0
@@ -102,11 +103,13 @@ typedef uint64_t TCGRegSet;
 #define TCG_TARGET_HAS_div2_i32         0
 #elif defined(TCG_TARGET_HAS_div2_i32)
 #define TCG_TARGET_HAS_div_i32          0
+#define TCG_TARGET_HAS_rem_i32          0
 #endif
 #if defined(TCG_TARGET_HAS_div_i64)
 #define TCG_TARGET_HAS_div2_i64         0
 #elif defined(TCG_TARGET_HAS_div2_i64)
 #define TCG_TARGET_HAS_div_i64          0
+#define TCG_TARGET_HAS_rem_i64          0
 #endif
 
 typedef enum TCGOpcode {
diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h
index 0395bbb..9aa1256 100644
--- a/tcg/tci/tcg-target.h
+++ b/tcg/tci/tcg-target.h
@@ -61,6 +61,7 @@
 #define TCG_TARGET_HAS_bswap32_i32      1
 /* Not more than one of the next two defines must be 1. */
 #define TCG_TARGET_HAS_div_i32          1
+#define TCG_TARGET_HAS_rem_i32          1
 #define TCG_TARGET_HAS_div2_i32         0
 #define TCG_TARGET_HAS_ext8s_i32        1
 #define TCG_TARGET_HAS_ext16s_i32       1
@@ -85,6 +86,7 @@
 #define TCG_TARGET_HAS_deposit_i64      1
 /* Not more than one of the next two defines must be 1. */
 #define TCG_TARGET_HAS_div_i64          0
+#define TCG_TARGET_HAS_rem_i64          0
 #define TCG_TARGET_HAS_div2_i64         0
 #define TCG_TARGET_HAS_ext8s_i64        1
 #define TCG_TARGET_HAS_ext16s_i64       1
-- 
1.8.1.4

[Qemu-devel] [PATCH v3 03/14] tcg-arm: Don't implement rem

[Richard Henderson]

Signed-off-by: Richard Henderson <rth@twiddle.net>
---
 tcg/arm/tcg-target.c | 14 --------------
 tcg/arm/tcg-target.h |  3 +--
 2 files changed, 1 insertion(+), 16 deletions(-)

diff --git a/tcg/arm/tcg-target.c b/tcg/arm/tcg-target.c
index 6be736b..8321f80 100644
--- a/tcg/arm/tcg-target.c
+++ b/tcg/arm/tcg-target.c
@@ -1926,18 +1926,6 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
     case INDEX_op_divu_i32:
         tcg_out_udiv(s, COND_AL, args[0], args[1], args[2]);
         break;
-    case INDEX_op_rem_i32:
-        tcg_out_sdiv(s, COND_AL, TCG_REG_TMP, args[1], args[2]);
-        tcg_out_mul32(s, COND_AL, TCG_REG_TMP, TCG_REG_TMP, args[2]);
-        tcg_out_dat_reg(s, COND_AL, ARITH_SUB, args[0], args[1], TCG_REG_TMP,
-                        SHIFT_IMM_LSL(0));
-        break;
-    case INDEX_op_remu_i32:
-        tcg_out_udiv(s, COND_AL, TCG_REG_TMP, args[1], args[2]);
-        tcg_out_mul32(s, COND_AL, TCG_REG_TMP, TCG_REG_TMP, args[2]);
-        tcg_out_dat_reg(s, COND_AL, ARITH_SUB, args[0], args[1], TCG_REG_TMP,
-                        SHIFT_IMM_LSL(0));
-        break;
 
     default:
         tcg_abort();
@@ -2043,9 +2031,7 @@ static const TCGTargetOpDef arm_op_defs[] = {
 
 #if TCG_TARGET_HAS_div_i32
     { INDEX_op_div_i32, { "r", "r", "r" } },
-    { INDEX_op_rem_i32, { "r", "r", "r" } },
     { INDEX_op_divu_i32, { "r", "r", "r" } },
-    { INDEX_op_remu_i32, { "r", "r", "r" } },
 #endif
 
     { -1 },
diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h
index 2c5b4e7..263ea03 100644
--- a/tcg/arm/tcg-target.h
+++ b/tcg/arm/tcg-target.h
@@ -76,11 +76,10 @@ typedef enum {
 
 #ifdef __ARM_ARCH_EXT_IDIV__
 #define TCG_TARGET_HAS_div_i32          1
-#define TCG_TARGET_HAS_rem_i32          1
 #else
 #define TCG_TARGET_HAS_div_i32          0
-#define TCG_TARGET_HAS_rem_i32          0
 #endif
+#define TCG_TARGET_HAS_rem_i32          0
 
 extern bool tcg_target_deposit_valid(int ofs, int len);
 #define TCG_TARGET_deposit_i32_valid  tcg_target_deposit_valid
-- 
1.8.1.4

[Qemu-devel] [PATCH v3 04/14] tcg-ppc: Don't implement rem

[Richard Henderson]

Reviewed-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
 tcg/ppc/tcg-target.c | 14 --------------
 tcg/ppc/tcg-target.h |  2 +-
 2 files changed, 1 insertion(+), 15 deletions(-)

diff --git a/tcg/ppc/tcg-target.c b/tcg/ppc/tcg-target.c
index 29ca934..453ab6b 100644
--- a/tcg/ppc/tcg-target.c
+++ b/tcg/ppc/tcg-target.c
@@ -1671,18 +1671,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
         tcg_out32 (s, DIVWU | TAB (args[0], args[1], args[2]));
         break;
 
-    case INDEX_op_rem_i32:
-        tcg_out32 (s, DIVW | TAB (0, args[1], args[2]));
-        tcg_out32 (s, MULLW | TAB (0, 0, args[2]));
-        tcg_out32 (s, SUBF | TAB (args[0], 0, args[1]));
-        break;
-
-    case INDEX_op_remu_i32:
-        tcg_out32 (s, DIVWU | TAB (0, args[1], args[2]));
-        tcg_out32 (s, MULLW | TAB (0, 0, args[2]));
-        tcg_out32 (s, SUBF | TAB (args[0], 0, args[1]));
-        break;
-
     case INDEX_op_mulu2_i32:
         if (args[0] == args[2] || args[0] == args[3]) {
             tcg_out32 (s, MULLW | TAB (0, args[2], args[3]));
@@ -1992,8 +1980,6 @@ static const TCGTargetOpDef ppc_op_defs[] = {
     { INDEX_op_mul_i32, { "r", "r", "ri" } },
     { INDEX_op_div_i32, { "r", "r", "r" } },
     { INDEX_op_divu_i32, { "r", "r", "r" } },
-    { INDEX_op_rem_i32, { "r", "r", "r" } },
-    { INDEX_op_remu_i32, { "r", "r", "r" } },
     { INDEX_op_mulu2_i32, { "r", "r", "r", "r" } },
     { INDEX_op_sub_i32, { "r", "r", "ri" } },
     { INDEX_op_and_i32, { "r", "r", "ri" } },
diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h
index 01b880e..b42d97c 100644
--- a/tcg/ppc/tcg-target.h
+++ b/tcg/ppc/tcg-target.h
@@ -78,7 +78,7 @@ typedef enum {
 
 /* optional instructions */
 #define TCG_TARGET_HAS_div_i32          1
-#define TCG_TARGET_HAS_rem_i32          1
+#define TCG_TARGET_HAS_rem_i32          0
 #define TCG_TARGET_HAS_rot_i32          1
 #define TCG_TARGET_HAS_ext8s_i32        1
 #define TCG_TARGET_HAS_ext16s_i32       1
-- 
1.8.1.4

[Qemu-devel] [PATCH v3 05/14] tcg-ppc64: Don't implement rem

[Richard Henderson]

Reviewed-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
 tcg/ppc64/tcg-target.c | 26 --------------------------
 tcg/ppc64/tcg-target.h |  4 ++--
 2 files changed, 2 insertions(+), 28 deletions(-)

diff --git a/tcg/ppc64/tcg-target.c b/tcg/ppc64/tcg-target.c
index 606b73d..0678de2 100644
--- a/tcg/ppc64/tcg-target.c
+++ b/tcg/ppc64/tcg-target.c
@@ -1617,18 +1617,6 @@ static void tcg_out_op (TCGContext *s, TCGOpcode opc, const TCGArg *args,
         tcg_out32 (s, DIVWU | TAB (args[0], args[1], args[2]));
         break;
 
-    case INDEX_op_rem_i32:
-        tcg_out32 (s, DIVW | TAB (0, args[1], args[2]));
-        tcg_out32 (s, MULLW | TAB (0, 0, args[2]));
-        tcg_out32 (s, SUBF | TAB (args[0], 0, args[1]));
-        break;
-
-    case INDEX_op_remu_i32:
-        tcg_out32 (s, DIVWU | TAB (0, args[1], args[2]));
-        tcg_out32 (s, MULLW | TAB (0, 0, args[2]));
-        tcg_out32 (s, SUBF | TAB (args[0], 0, args[1]));
-        break;
-
     case INDEX_op_shl_i32:
         if (const_args[2]) {
             tcg_out_rlw(s, RLWINM, args[0], args[1], args[2], 0, 31 - args[2]);
@@ -1786,16 +1774,6 @@ static void tcg_out_op (TCGContext *s, TCGOpcode opc, const TCGArg *args,
     case INDEX_op_divu_i64:
         tcg_out32 (s, DIVDU | TAB (args[0], args[1], args[2]));
         break;
-    case INDEX_op_rem_i64:
-        tcg_out32 (s, DIVD | TAB (0, args[1], args[2]));
-        tcg_out32 (s, MULLD | TAB (0, 0, args[2]));
-        tcg_out32 (s, SUBF | TAB (args[0], 0, args[1]));
-        break;
-    case INDEX_op_remu_i64:
-        tcg_out32 (s, DIVDU | TAB (0, args[1], args[2]));
-        tcg_out32 (s, MULLD | TAB (0, 0, args[2]));
-        tcg_out32 (s, SUBF | TAB (args[0], 0, args[1]));
-        break;
 
     case INDEX_op_qemu_ld8u:
         tcg_out_qemu_ld (s, args, 0);
@@ -2064,8 +2042,6 @@ static const TCGTargetOpDef ppc_op_defs[] = {
     { INDEX_op_mul_i32, { "r", "r", "rI" } },
     { INDEX_op_div_i32, { "r", "r", "r" } },
     { INDEX_op_divu_i32, { "r", "r", "r" } },
-    { INDEX_op_rem_i32, { "r", "r", "r" } },
-    { INDEX_op_remu_i32, { "r", "r", "r" } },
     { INDEX_op_sub_i32, { "r", "rI", "ri" } },
     { INDEX_op_and_i32, { "r", "r", "ri" } },
     { INDEX_op_or_i32, { "r", "r", "ri" } },
@@ -2108,8 +2084,6 @@ static const TCGTargetOpDef ppc_op_defs[] = {
     { INDEX_op_mul_i64, { "r", "r", "rI" } },
     { INDEX_op_div_i64, { "r", "r", "r" } },
     { INDEX_op_divu_i64, { "r", "r", "r" } },
-    { INDEX_op_rem_i64, { "r", "r", "r" } },
-    { INDEX_op_remu_i64, { "r", "r", "r" } },
 
     { INDEX_op_neg_i64, { "r", "r" } },
     { INDEX_op_not_i64, { "r", "r" } },
diff --git a/tcg/ppc64/tcg-target.h b/tcg/ppc64/tcg-target.h
index 7c600f1..48fc6e2 100644
--- a/tcg/ppc64/tcg-target.h
+++ b/tcg/ppc64/tcg-target.h
@@ -76,7 +76,7 @@ typedef enum {
 
 /* optional instructions */
 #define TCG_TARGET_HAS_div_i32          1
-#define TCG_TARGET_HAS_rem_i32          1
+#define TCG_TARGET_HAS_rem_i32          0
 #define TCG_TARGET_HAS_rot_i32          1
 #define TCG_TARGET_HAS_ext8s_i32        1
 #define TCG_TARGET_HAS_ext16s_i32       1
@@ -97,7 +97,7 @@ typedef enum {
 #define TCG_TARGET_HAS_muls2_i32        0
 
 #define TCG_TARGET_HAS_div_i64          1
-#define TCG_TARGET_HAS_rem_i64          1
+#define TCG_TARGET_HAS_rem_i64          0
 #define TCG_TARGET_HAS_rot_i64          1
 #define TCG_TARGET_HAS_ext8s_i64        1
 #define TCG_TARGET_HAS_ext16s_i64       1
-- 
1.8.1.4

[Qemu-devel] [PATCH v3 06/14] tcg: Allow non-constant control macros

[Richard Henderson]

This allows TCG_TARGET_HAS_* to be a variable rather than a constant,
which allows easier support for differing ISA levels for the host.

Signed-off-by: Richard Henderson <rth@twiddle.net>
---
 tcg/tcg-opc.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/tcg/tcg-opc.h b/tcg/tcg-opc.h
index 12967fb..c94e255 100644
--- a/tcg/tcg-opc.h
+++ b/tcg/tcg-opc.h
@@ -40,7 +40,7 @@ DEF(set_label, 0, 0, 1, TCG_OPF_BB_END)
 DEF(call, 0, 1, 2, TCG_OPF_CALL_CLOBBER) /* variable number of parameters */
 DEF(br, 0, 0, 1, TCG_OPF_BB_END)
 
-#define IMPL(X) (X ? 0 : TCG_OPF_NOT_PRESENT)
+#define IMPL(X) (__builtin_constant_p(X) && !(X) ? TCG_OPF_NOT_PRESENT : 0)
 #if TCG_TARGET_REG_BITS == 32
 # define IMPL64  TCG_OPF_64BIT | TCG_OPF_NOT_PRESENT
 #else
-- 
1.8.1.4

[Qemu-devel] [PATCH v3 07/14] tcg: Simplify logic using TCG_OPF_NOT_PRESENT

[Richard Henderson]

Expand the definition of "not present" to include "should not be present".
This means we can simplify the logic surrounding the generic tcg opcodes
for which the host backend ought not be providing definitions.

Signed-off-by: Richard Henderson <rth@twiddle.net>
---
 tcg/tcg-opc.h | 26 +++++++++++++++-----------
 tcg/tcg.c     |  4 +---
 tcg/tcg.h     |  3 ++-
 3 files changed, 18 insertions(+), 15 deletions(-)

diff --git a/tcg/tcg-opc.h b/tcg/tcg-opc.h
index c94e255..a8af5b9 100644
--- a/tcg/tcg-opc.h
+++ b/tcg/tcg-opc.h
@@ -27,17 +27,21 @@
  */
 
 /* predefined ops */
-DEF(end, 0, 0, 0, 0) /* must be kept first */
-DEF(nop, 0, 0, 0, 0)
-DEF(nop1, 0, 0, 1, 0)
-DEF(nop2, 0, 0, 2, 0)
-DEF(nop3, 0, 0, 3, 0)
-DEF(nopn, 0, 0, 1, 0) /* variable number of parameters */
+DEF(end, 0, 0, 0, TCG_OPF_NOT_PRESENT) /* must be kept first */
+DEF(nop, 0, 0, 0, TCG_OPF_NOT_PRESENT)
+DEF(nop1, 0, 0, 1, TCG_OPF_NOT_PRESENT)
+DEF(nop2, 0, 0, 2, TCG_OPF_NOT_PRESENT)
+DEF(nop3, 0, 0, 3, TCG_OPF_NOT_PRESENT)
 
-DEF(discard, 1, 0, 0, 0)
+/* variable number of parameters */
+DEF(nopn, 0, 0, 1, TCG_OPF_NOT_PRESENT)
+
+DEF(discard, 1, 0, 0, TCG_OPF_NOT_PRESENT)
+DEF(set_label, 0, 0, 1, TCG_OPF_BB_END | TCG_OPF_NOT_PRESENT)
+
+/* variable number of parameters */
+DEF(call, 0, 1, 2, TCG_OPF_CALL_CLOBBER)
 
-DEF(set_label, 0, 0, 1, TCG_OPF_BB_END)
-DEF(call, 0, 1, 2, TCG_OPF_CALL_CLOBBER) /* variable number of parameters */
 DEF(br, 0, 0, 1, TCG_OPF_BB_END)
 
 #define IMPL(X) (__builtin_constant_p(X) && !(X) ? TCG_OPF_NOT_PRESENT : 0)
@@ -166,9 +170,9 @@ DEF(muls2_i64, 2, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_muls2_i64))
 
 /* QEMU specific */
 #if TARGET_LONG_BITS > TCG_TARGET_REG_BITS
-DEF(debug_insn_start, 0, 0, 2, 0)
+DEF(debug_insn_start, 0, 0, 2, TCG_OPF_NOT_PRESENT)
 #else
-DEF(debug_insn_start, 0, 0, 1, 0)
+DEF(debug_insn_start, 0, 0, 1, TCG_OPF_NOT_PRESENT)
 #endif
 DEF(exit_tb, 0, 0, 1, TCG_OPF_BB_END)
 DEF(goto_tb, 0, 0, 1, TCG_OPF_BB_END)
diff --git a/tcg/tcg.c b/tcg/tcg.c
index 1d8099c..c7e6567 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -1160,9 +1160,7 @@ void tcg_add_target_add_op_defs(const TCGTargetOpDef *tdefs)
     i = 0;
     for (op = 0; op < ARRAY_SIZE(tcg_op_defs); op++) {
         const TCGOpDef *def = &tcg_op_defs[op];
-        if (op < INDEX_op_call
-            || op == INDEX_op_debug_insn_start
-            || (def->flags & TCG_OPF_NOT_PRESENT)) {
+        if (def->flags & TCG_OPF_NOT_PRESENT) {
             /* Wrong entry in op definitions? */
             if (def->used) {
                 fprintf(stderr, "Invalid op definition for %s\n", def->name);
diff --git a/tcg/tcg.h b/tcg/tcg.h
index 28ca1bd..f3f9889 100644
--- a/tcg/tcg.h
+++ b/tcg/tcg.h
@@ -596,7 +596,8 @@ enum {
     TCG_OPF_SIDE_EFFECTS = 0x04,
     /* Instruction operands are 64-bits (otherwise 32-bits).  */
     TCG_OPF_64BIT        = 0x08,
-    /* Instruction is optional and not implemented by the host.  */
+    /* Instruction is optional and not implemented by the host, or insn
+       is generic and should not be implemened by the host.  */
     TCG_OPF_NOT_PRESENT  = 0x10,
 };
 
-- 
1.8.1.4

[Qemu-devel] [PATCH v3 08/14] tcg-arm: Make use of conditional availability of opcodes for divide

[Richard Henderson]

We can now detect and use divide instructions at runtime, rather than
having to restrict their availability to compile-time.

Signed-off-by: Richard Henderson <rth@twiddle.net>
---
 tcg/arm/tcg-target.c | 16 ++++++++++++++--
 tcg/arm/tcg-target.h | 14 ++++++++------
 2 files changed, 22 insertions(+), 8 deletions(-)

diff --git a/tcg/arm/tcg-target.c b/tcg/arm/tcg-target.c
index 8321f80..2c46ceb 100644
--- a/tcg/arm/tcg-target.c
+++ b/tcg/arm/tcg-target.c
@@ -67,6 +67,13 @@ static const int use_armv7_instructions = 0;
 #endif
 #undef USE_ARMV7_INSTRUCTIONS
 
+#ifndef use_idiv_instructions
+bool use_idiv_instructions;
+#endif
+#ifdef CONFIG_GETAUXVAL
+# include <sys/auxv.h>
+#endif
+
 #ifndef NDEBUG
 static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
     "%r0",
@@ -2029,16 +2036,21 @@ static const TCGTargetOpDef arm_op_defs[] = {
 
     { INDEX_op_deposit_i32, { "r", "0", "rZ" } },
 
-#if TCG_TARGET_HAS_div_i32
     { INDEX_op_div_i32, { "r", "r", "r" } },
     { INDEX_op_divu_i32, { "r", "r", "r" } },
-#endif
 
     { -1 },
 };
 
 static void tcg_target_init(TCGContext *s)
 {
+#if defined(CONFIG_GETAUXVAL) && !defined(use_idiv_instructions)
+    {
+        unsigned long hwcap = getauxval(AT_HWCAP);
+        use_idiv_instructions = hwcap & (HWCAP_ARM_IDIVA | HWCAP_ARM_IDIVT);
+    }
+#endif
+
     tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I32], 0, 0xffff);
     tcg_regset_set32(tcg_target_call_clobber_regs, 0,
                      (1 << TCG_REG_R0) |
diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h
index 263ea03..5cd9d6a 100644
--- a/tcg/arm/tcg-target.h
+++ b/tcg/arm/tcg-target.h
@@ -49,6 +49,13 @@ typedef enum {
 
 #define TCG_TARGET_NB_REGS 16
 
+#ifdef __ARM_ARCH_EXT_IDIV__
+#define use_idiv_instructions  1
+#else
+extern bool use_idiv_instructions;
+#endif
+
+
 /* used for function call generation */
 #define TCG_REG_CALL_STACK		TCG_REG_R13
 #define TCG_TARGET_STACK_ALIGN		8
@@ -73,12 +80,7 @@ typedef enum {
 #define TCG_TARGET_HAS_deposit_i32      1
 #define TCG_TARGET_HAS_movcond_i32      1
 #define TCG_TARGET_HAS_muls2_i32        1
-
-#ifdef __ARM_ARCH_EXT_IDIV__
-#define TCG_TARGET_HAS_div_i32          1
-#else
-#define TCG_TARGET_HAS_div_i32          0
-#endif
+#define TCG_TARGET_HAS_div_i32          use_idiv_instructions
 #define TCG_TARGET_HAS_rem_i32          0
 
 extern bool tcg_target_deposit_valid(int ofs, int len);
-- 
1.8.1.4

[Qemu-devel] [PATCH v3 09/14] tcg-arm: Simplify logic in detecting the ARM ISA in use

[Richard Henderson]

GCC 4.8 defines a handy __ARM_ARCH symbol that we can use, which
will make us nicely forward compatible with ARMv8 AArch32.

Signed-off-by: Richard Henderson <rth@twiddle.net>
---
 tcg/arm/tcg-target.c | 62 +++++++++++++++++-----------------------------------
 1 file changed, 20 insertions(+), 42 deletions(-)

diff --git a/tcg/arm/tcg-target.c b/tcg/arm/tcg-target.c
index 2c46ceb..763b173 100644
--- a/tcg/arm/tcg-target.c
+++ b/tcg/arm/tcg-target.c
@@ -22,50 +22,28 @@
  * THE SOFTWARE.
  */
 
-#if defined(__ARM_ARCH_7__) ||  \
-    defined(__ARM_ARCH_7A__) || \
-    defined(__ARM_ARCH_7EM__) || \
-    defined(__ARM_ARCH_7M__) || \
-    defined(__ARM_ARCH_7R__)
-#define USE_ARMV7_INSTRUCTIONS
+/* The __ARM_ARCH define is provided by gcc 4.8.  Construct it otherwise.  */
+#ifndef __ARM_ARCH
+# if defined(__ARM_ARCH_7__) || defined(__ARM_ARCH_7A__) \
+     || defined(__ARM_ARCH_7R__) || defined(__ARM_ARCH_7M__) \
+     || defined(__ARM_ARCH_7EM__)
+#  define __ARM_ARCH 7
+# elif defined(__ARM_ARCH_6__) || defined(__ARM_ARCH_6J__) \
+       || defined(__ARM_ARCH_6Z__) || defined(__ARM_ARCH_6ZK__) \
+       || defined(__ARM_ARCH_6K__) || defined(__ARM_ARCH_6T2__)
+#  define __ARM_ARCH 6
+# elif defined(__ARM_ARCH_5__) || defined(__ARM_ARCH_5E__) \
+       || defined(__ARM_ARCH_5T__) || defined(__ARM_ARCH_5TE__) \
+       || defined(__ARM_ARCH_5TEJ__)
+#  define __ARM_ARCH 5
+# else
+#  define __ARM_ARCH 4
+# endif
 #endif
 
-#if defined(USE_ARMV7_INSTRUCTIONS) || \
-    defined(__ARM_ARCH_6J__) || \
-    defined(__ARM_ARCH_6K__) || \
-    defined(__ARM_ARCH_6T2__) || \
-    defined(__ARM_ARCH_6Z__) || \
-    defined(__ARM_ARCH_6ZK__)
-#define USE_ARMV6_INSTRUCTIONS
-#endif
-
-#if defined(USE_ARMV6_INSTRUCTIONS) || \
-    defined(__ARM_ARCH_5T__) || \
-    defined(__ARM_ARCH_5TE__) || \
-    defined(__ARM_ARCH_5TEJ__)
-#define USE_ARMV5_INSTRUCTIONS
-#endif
-
-#ifdef USE_ARMV5_INSTRUCTIONS
-static const int use_armv5_instructions = 1;
-#else
-static const int use_armv5_instructions = 0;
-#endif
-#undef USE_ARMV5_INSTRUCTIONS
-
-#ifdef USE_ARMV6_INSTRUCTIONS
-static const int use_armv6_instructions = 1;
-#else
-static const int use_armv6_instructions = 0;
-#endif
-#undef USE_ARMV6_INSTRUCTIONS
-
-#ifdef USE_ARMV7_INSTRUCTIONS
-static const int use_armv7_instructions = 1;
-#else
-static const int use_armv7_instructions = 0;
-#endif
-#undef USE_ARMV7_INSTRUCTIONS
+#define use_armv5_instructions  (__ARM_ARCH >= 5)
+#define use_armv6_instructions  (__ARM_ARCH >= 6)
+#define use_armv7_instructions  (__ARM_ARCH >= 7)
 
 #ifndef use_idiv_instructions
 bool use_idiv_instructions;
-- 
1.8.1.4

[Qemu-devel] [PATCH v3 10/14] tcg-arm: Use AT_PLATFORM to detect the host ISA

[Richard Henderson]

With this we can generate armv7 insns even when the OS compiles for a
lower common denominator.  The macros are arranged so that when we do
compile for a given ISA, all of the runtime checks for that ISA are
optimized away.

Signed-off-by: Richard Henderson <rth@twiddle.net>
---
 tcg/arm/tcg-target.c | 22 +++++++++++++++++-----
 1 file changed, 17 insertions(+), 5 deletions(-)

diff --git a/tcg/arm/tcg-target.c b/tcg/arm/tcg-target.c
index 763b173..a46d2e0 100644
--- a/tcg/arm/tcg-target.c
+++ b/tcg/arm/tcg-target.c
@@ -41,9 +41,11 @@
 # endif
 #endif
 
-#define use_armv5_instructions  (__ARM_ARCH >= 5)
-#define use_armv6_instructions  (__ARM_ARCH >= 6)
-#define use_armv7_instructions  (__ARM_ARCH >= 7)
+static int arm_arch = __ARM_ARCH;
+
+#define use_armv5_instructions  (__ARM_ARCH >= 5 || arm_arch >= 5)
+#define use_armv6_instructions  (__ARM_ARCH >= 6 || arm_arch >= 6)
+#define use_armv7_instructions  (__ARM_ARCH >= 7 || arm_arch >= 7)
 
 #ifndef use_idiv_instructions
 bool use_idiv_instructions;
@@ -2022,12 +2024,22 @@ static const TCGTargetOpDef arm_op_defs[] = {
 
 static void tcg_target_init(TCGContext *s)
 {
-#if defined(CONFIG_GETAUXVAL) && !defined(use_idiv_instructions)
+#if defined(CONFIG_GETAUXVAL)
+    /* Only probe for the platform and capabilities if we havn't already
+       determined maximum values at compile time.  */
+# if !defined(use_idiv_instructions)
     {
         unsigned long hwcap = getauxval(AT_HWCAP);
         use_idiv_instructions = hwcap & (HWCAP_ARM_IDIVA | HWCAP_ARM_IDIVT);
     }
-#endif
+# endif
+    if (__ARM_ARCH < 7) {
+        const char *pl = (const char *)getauxval(AT_PLATFORM);
+        if (pl != NULL && pl[0] == 'v' && pl[1] >= '4' && pl[1] <= '9') {
+            arm_arch = pl[1] - '0';
+        }
+    }
+#endif /* GETAUXVAL */
 
     tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I32], 0, 0xffff);
     tcg_regset_set32(tcg_target_call_clobber_regs, 0,
-- 
1.8.1.4

[Qemu-devel] [PATCH v3 11/14] tcg: Fix high_pc fields in .debug_info

[Richard Henderson]

I don't think the debugger actually looks at this for anything,
using the correct .debug_frame contents, but might as well get
it all correct.

Signed-off-by: Richard Henderson <rth@twiddle.net>
---
 tcg/tcg.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/tcg/tcg.c b/tcg/tcg.c
index c7e6567..42dc958 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -2657,9 +2657,9 @@ static void tcg_register_jit_int(void *buf_ptr, size_t buf_size,
     img->sym[1].st_size = buf_size;
 
     img->di.cu_low_pc = buf;
-    img->di.cu_high_pc = buf_size;
+    img->di.cu_high_pc = buf + buf_size;
     img->di.fn_low_pc = buf;
-    img->di.fn_high_pc = buf_size;
+    img->di.fn_high_pc = buf + buf_size;
 
 #ifdef DEBUG_JIT
     /* Enable this block to be able to debug the ELF image file creation.
-- 
1.8.1.4

[Qemu-devel] [PATCH v3 12/14] tcg: Move the CIE and FDE header definitions to common code

[Richard Henderson]

These will necessarily be the same layout for all hosts.  This limits
the amount of boilerplate required to implement jit debug for a host.

Signed-off-by: Richard Henderson <rth@twiddle.net>
---
 tcg/hppa/tcg-target.c  | 35 ++++++++++-------------------------
 tcg/i386/tcg-target.c  | 39 +++++++++++++--------------------------
 tcg/sparc/tcg-target.c | 35 ++++++++++-------------------------
 tcg/tcg.c              | 18 ++++++++++++++++++
 4 files changed, 51 insertions(+), 76 deletions(-)

diff --git a/tcg/hppa/tcg-target.c b/tcg/hppa/tcg-target.c
index 656e736..68f77ba 100644
--- a/tcg/hppa/tcg-target.c
+++ b/tcg/hppa/tcg-target.c
@@ -1766,28 +1766,11 @@ static void tcg_target_init(TCGContext *s)
 }
 
 typedef struct {
-    uint32_t len __attribute__((aligned((sizeof(void *)))));
-    uint32_t id;
-    uint8_t version;
-    char augmentation[1];
-    uint8_t code_align;
-    uint8_t data_align;
-    uint8_t return_column;
-} DebugFrameCIE;
-
-typedef struct {
-    uint32_t len __attribute__((aligned((sizeof(void *)))));
-    uint32_t cie_offset;
-    tcg_target_long func_start __attribute__((packed));
-    tcg_target_long func_len __attribute__((packed));
-    uint8_t def_cfa[4];
-    uint8_t ret_ofs[3];
-    uint8_t reg_ofs[ARRAY_SIZE(tcg_target_callee_save_regs) * 2];
-} DebugFrameFDE;
-
-typedef struct {
     DebugFrameCIE cie;
-    DebugFrameFDE fde;
+    DebugFrameFDEHeader fde;
+    uint8_t fde_def_cfa[4];
+    uint8_t fde_ret_ofs[3];
+    uint8_t fde_reg_ofs[ARRAY_SIZE(tcg_target_callee_save_regs) * 2];
 } DebugFrame;
 
 #define ELF_HOST_MACHINE  EM_PARISC
@@ -1806,16 +1789,18 @@ static DebugFrame debug_frame = {
     .cie.data_align = 1,
     .cie.return_column = 2,
 
-    .fde.len = sizeof(DebugFrameFDE)-4, /* length after .len member */
-    .fde.def_cfa = {
+    /* Total FDE size does not include the "len" member.  */
+    .fde.len = sizeof(DebugFrame) - offsetof(DebugFrame, fde.cie_offset),
+
+    .fde_def_cfa = {
         0x12, 30,                       /* DW_CFA_def_cfa_sf sp, ... */
         (-FRAME_SIZE & 0x7f) | 0x80,     /* ... sleb128 -FRAME_SIZE */
         (-FRAME_SIZE >> 7) & 0x7f
     },
-    .fde.ret_ofs = {
+    .fde_ret_ofs = {
         0x11, 2, (-20 / 4) & 0x7f       /* DW_CFA_offset_extended_sf r2, 20 */
     },
-    .fde.reg_ofs = {
+    .fde_reg_ofs = {
         /* This must match the ordering in tcg_target_callee_save_regs.  */
         0x80 + 4, 0,                    /* DW_CFA_offset r4, 0 */
         0x80 + 5, 4,                    /* DW_CFA_offset r5, 4 */
diff --git a/tcg/i386/tcg-target.c b/tcg/i386/tcg-target.c
index 9e95477..ae3de09 100644
--- a/tcg/i386/tcg-target.c
+++ b/tcg/i386/tcg-target.c
@@ -2312,27 +2312,10 @@ static void tcg_target_init(TCGContext *s)
 }
 
 typedef struct {
-    uint32_t len __attribute__((aligned((sizeof(void *)))));
-    uint32_t id;
-    uint8_t version;
-    char augmentation[1];
-    uint8_t code_align;
-    uint8_t data_align;
-    uint8_t return_column;
-} DebugFrameCIE;
-
-typedef struct {
-    uint32_t len __attribute__((aligned((sizeof(void *)))));
-    uint32_t cie_offset;
-    tcg_target_long func_start __attribute__((packed));
-    tcg_target_long func_len __attribute__((packed));
-    uint8_t def_cfa[4];
-    uint8_t reg_ofs[14];
-} DebugFrameFDE;
-
-typedef struct {
     DebugFrameCIE cie;
-    DebugFrameFDE fde;
+    DebugFrameFDEHeader fde;
+    uint8_t fde_def_cfa[4];
+    uint8_t fde_reg_ofs[14];
 } DebugFrame;
 
 #if !defined(__ELF__)
@@ -2347,13 +2330,15 @@ static DebugFrame debug_frame = {
     .cie.data_align = 0x78,             /* sleb128 -8 */
     .cie.return_column = 16,
 
-    .fde.len = sizeof(DebugFrameFDE)-4, /* length after .len member */
-    .fde.def_cfa = {
+    /* Total FDE size does not include the "len" member.  */
+    .fde.len = sizeof(DebugFrame) - offsetof(DebugFrame, fde.cie_offset),
+
+    .fde_def_cfa = {
         12, 7,                          /* DW_CFA_def_cfa %rsp, ... */
         (FRAME_SIZE & 0x7f) | 0x80,     /* ... uleb128 FRAME_SIZE */
         (FRAME_SIZE >> 7)
     },
-    .fde.reg_ofs = {
+    .fde_reg_ofs = {
         0x90, 1,                        /* DW_CFA_offset, %rip, -8 */
         /* The following ordering must match tcg_target_callee_save_regs.  */
         0x86, 2,                        /* DW_CFA_offset, %rbp, -16 */
@@ -2374,13 +2359,15 @@ static DebugFrame debug_frame = {
     .cie.data_align = 0x7c,             /* sleb128 -4 */
     .cie.return_column = 8,
 
-    .fde.len = sizeof(DebugFrameFDE)-4, /* length after .len member */
-    .fde.def_cfa = {
+    /* Total FDE size does not include the "len" member.  */
+    .fde.len = sizeof(DebugFrame) - offsetof(DebugFrame, fde.cie_offset),
+
+    .fde_def_cfa = {
         12, 4,                          /* DW_CFA_def_cfa %esp, ... */
         (FRAME_SIZE & 0x7f) | 0x80,     /* ... uleb128 FRAME_SIZE */
         (FRAME_SIZE >> 7)
     },
-    .fde.reg_ofs = {
+    .fde_reg_ofs = {
         0x88, 1,                        /* DW_CFA_offset, %eip, -4 */
         /* The following ordering must match tcg_target_callee_save_regs.  */
         0x85, 2,                        /* DW_CFA_offset, %ebp, -8 */
diff --git a/tcg/sparc/tcg-target.c b/tcg/sparc/tcg-target.c
index 025af9b..5bfd29c 100644
--- a/tcg/sparc/tcg-target.c
+++ b/tcg/sparc/tcg-target.c
@@ -1647,28 +1647,11 @@ static void tcg_target_init(TCGContext *s)
 #endif
 
 typedef struct {
-    uint32_t len __attribute__((aligned((sizeof(void *)))));
-    uint32_t id;
-    uint8_t version;
-    char augmentation[1];
-    uint8_t code_align;
-    uint8_t data_align;
-    uint8_t return_column;
-} DebugFrameCIE;
-
-typedef struct {
-    uint32_t len __attribute__((aligned((sizeof(void *)))));
-    uint32_t cie_offset;
-    tcg_target_long func_start __attribute__((packed));
-    tcg_target_long func_len __attribute__((packed));
-    uint8_t def_cfa[TCG_TARGET_REG_BITS == 64 ? 4 : 2];
-    uint8_t win_save;
-    uint8_t ret_save[3];
-} DebugFrameFDE;
-
-typedef struct {
     DebugFrameCIE cie;
-    DebugFrameFDE fde;
+    DebugFrameFDEHeader fde;
+    uint8_t fde_def_cfa[TCG_TARGET_REG_BITS == 64 ? 4 : 2];
+    uint8_t fde_win_save;
+    uint8_t fde_ret_save[3];
 } DebugFrame;
 
 static DebugFrame debug_frame = {
@@ -1679,8 +1662,10 @@ static DebugFrame debug_frame = {
     .cie.data_align = -sizeof(void *) & 0x7f,
     .cie.return_column = 15,            /* o7 */
 
-    .fde.len = sizeof(DebugFrameFDE)-4, /* length after .len member */
-    .fde.def_cfa = {
+    /* Total FDE size does not include the "len" member.  */
+    .fde.len = sizeof(DebugFrame) - offsetof(DebugFrame, fde.cie_offset),
+
+    .fde_def_cfa = {
 #if TCG_TARGET_REG_BITS == 64
         12, 30,                         /* DW_CFA_def_cfa i6, 2047 */
         (2047 & 0x7f) | 0x80, (2047 >> 7)
@@ -1688,8 +1673,8 @@ static DebugFrame debug_frame = {
         13, 30                          /* DW_CFA_def_cfa_register i6 */
 #endif
     },
-    .fde.win_save = 0x2d,               /* DW_CFA_GNU_window_save */
-    .fde.ret_save = { 9, 15, 31 },      /* DW_CFA_register o7, i7 */
+    .fde_win_save = 0x2d,               /* DW_CFA_GNU_window_save */
+    .fde_ret_save = { 9, 15, 31 },      /* DW_CFA_register o7, i7 */
 };
 
 void tcg_register_jit(void *buf, size_t buf_size)
diff --git a/tcg/tcg.c b/tcg/tcg.c
index 42dc958..dac8224 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -68,6 +68,24 @@ static void tcg_target_qemu_prologue(TCGContext *s);
 static void patch_reloc(uint8_t *code_ptr, int type, 
                         tcg_target_long value, tcg_target_long addend);
 
+/* The CIE and FDE header definitions will be common to all hosts.  */
+typedef struct {
+    uint32_t len __attribute__((aligned((sizeof(void *)))));
+    uint32_t id;
+    uint8_t version;
+    char augmentation[1];
+    uint8_t code_align;
+    uint8_t data_align;
+    uint8_t return_column;
+} DebugFrameCIE;
+
+typedef struct QEMU_PACKED {
+    uint32_t len __attribute__((aligned((sizeof(void *)))));
+    uint32_t cie_offset;
+    tcg_target_long func_start;
+    tcg_target_long func_len;
+} DebugFrameFDEHeader;
+
 static void tcg_register_jit_int(void *buf, size_t size,
                                  void *debug_frame, size_t debug_frame_size)
     __attribute__((unused));
-- 
1.8.1.4

[Qemu-devel] [PATCH v3 13/14] tcg-i386: Use QEMU_BUILD_BUG_ON instead of assert for frame size

[Richard Henderson]

We can check the condition at compile time, rather than run time.

Reviewed-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
 tcg/i386/tcg-target.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/tcg/i386/tcg-target.c b/tcg/i386/tcg-target.c
index ae3de09..87eeab3 100644
--- a/tcg/i386/tcg-target.c
+++ b/tcg/i386/tcg-target.c
@@ -2318,6 +2318,9 @@ typedef struct {
     uint8_t fde_reg_ofs[14];
 } DebugFrame;
 
+/* We're expecting a 2 byte uleb128 encoded value.  */
+QEMU_BUILD_BUG_ON(FRAME_SIZE >= (1 << 14));
+
 #if !defined(__ELF__)
     /* Host machine without ELF. */
 #elif TCG_TARGET_REG_BITS == 64
@@ -2381,9 +2384,6 @@ static DebugFrame debug_frame = {
 #if defined(ELF_HOST_MACHINE)
 void tcg_register_jit(void *buf, size_t buf_size)
 {
-    /* We're expecting a 2 byte uleb128 encoded value.  */
-    assert(FRAME_SIZE >> 14 == 0);
-
     debug_frame.fde.func_start = (tcg_target_long) buf;
     debug_frame.fde.func_len = buf_size;
 
-- 
1.8.1.4

[Qemu-devel] [PATCH v3 14/14] tcg-arm: Implement tcg_register_jit

[Richard Henderson]

Allows unwinding past the code_gen_buffer.

Signed-off-by: Richard Henderson <rth@twiddle.net>
---
 tcg/arm/tcg-target.c | 76 +++++++++++++++++++++++++++++++++++++++++++++-------
 1 file changed, 67 insertions(+), 9 deletions(-)

diff --git a/tcg/arm/tcg-target.c b/tcg/arm/tcg-target.c
index a46d2e0..f87464e 100644
--- a/tcg/arm/tcg-target.c
+++ b/tcg/arm/tcg-target.c
@@ -2082,23 +2082,31 @@ static inline void tcg_out_movi(TCGContext *s, TCGType type,
     tcg_out_movi32(s, COND_AL, ret, arg);
 }
 
+/* Compute frame size via macros, to share between tcg_target_qemu_prologue
+   and tcg_register_jit.  */
+
+#define PUSH_SIZE  ((11 - 4 + 1 + 1) * sizeof(tcg_target_long))
+
+#define FRAME_SIZE \
+    ((PUSH_SIZE \
+      + TCG_STATIC_CALL_ARGS_SIZE \
+      + CPU_TEMP_BUF_NLONGS * sizeof(long) \
+      + TCG_TARGET_STACK_ALIGN - 1) \
+     & -TCG_TARGET_STACK_ALIGN)
+
 static void tcg_target_qemu_prologue(TCGContext *s)
 {
-    int frame_size;
+    int stack_addend;
 
     /* Calling convention requires us to save r4-r11 and lr.  */
     /* stmdb sp!, { r4 - r11, lr } */
     tcg_out32(s, (COND_AL << 28) | 0x092d4ff0);
 
-    /* Allocate the local stack frame.  */
-    frame_size = TCG_STATIC_CALL_ARGS_SIZE;
-    frame_size += CPU_TEMP_BUF_NLONGS * sizeof(long);
-    /* We saved an odd number of registers above; keep an 8 aligned stack.  */
-    frame_size = ((frame_size + TCG_TARGET_STACK_ALIGN - 1)
-                  & -TCG_TARGET_STACK_ALIGN) + 4;
+    /* Reserve callee argument and tcg temp space.  */
+    stack_addend = FRAME_SIZE - PUSH_SIZE;
 
     tcg_out_dat_rI(s, COND_AL, ARITH_SUB, TCG_REG_CALL_STACK,
-                   TCG_REG_CALL_STACK, frame_size, 1);
+                   TCG_REG_CALL_STACK, stack_addend, 1);
     tcg_set_frame(s, TCG_REG_CALL_STACK, TCG_STATIC_CALL_ARGS_SIZE,
                   CPU_TEMP_BUF_NLONGS * sizeof(long));
 
@@ -2109,8 +2117,58 @@ static void tcg_target_qemu_prologue(TCGContext *s)
 
     /* Epilogue.  We branch here via tb_ret_addr.  */
     tcg_out_dat_rI(s, COND_AL, ARITH_ADD, TCG_REG_CALL_STACK,
-                   TCG_REG_CALL_STACK, frame_size, 1);
+                   TCG_REG_CALL_STACK, stack_addend, 1);
 
     /* ldmia sp!, { r4 - r11, pc } */
     tcg_out32(s, (COND_AL << 28) | 0x08bd8ff0);
 }
+
+typedef struct {
+    DebugFrameCIE cie;
+    DebugFrameFDEHeader fde;
+    uint8_t fde_def_cfa[4];
+    uint8_t fde_reg_ofs[18];
+} DebugFrame;
+
+#define ELF_HOST_MACHINE EM_ARM
+
+/* We're expecting a 2 byte uleb128 encoded value.  */
+QEMU_BUILD_BUG_ON(FRAME_SIZE >= (1 << 14));
+
+static DebugFrame debug_frame = {
+    .cie.len = sizeof(DebugFrameCIE)-4, /* length after .len member */
+    .cie.id = -1,
+    .cie.version = 1,
+    .cie.code_align = 1,
+    .cie.data_align = 0x7c,             /* sleb128 -4 */
+    .cie.return_column = 14,
+
+    /* Total FDE size does not include the "len" member.  */
+    .fde.len = sizeof(DebugFrame) - offsetof(DebugFrame, fde.cie_offset),
+
+    .fde_def_cfa = {
+        12, 13,                         /* DW_CFA_def_cfa sp, ... */
+        (FRAME_SIZE & 0x7f) | 0x80,     /* ... uleb128 FRAME_SIZE */
+        (FRAME_SIZE >> 7)
+    },
+    .fde_reg_ofs = {
+        /* The following must match the stmdb in the prologue.  */
+        0x8e, 1,                        /* DW_CFA_offset, lr, -4 */
+        0x8b, 2,                        /* DW_CFA_offset, r11, -8 */
+        0x8a, 3,                        /* DW_CFA_offset, r10, -12 */
+        0x89, 4,                        /* DW_CFA_offset, r9, -16 */
+        0x88, 5,                        /* DW_CFA_offset, r8, -20 */
+        0x87, 6,                        /* DW_CFA_offset, r7, -24 */
+        0x86, 7,                        /* DW_CFA_offset, r6, -28 */
+        0x85, 8,                        /* DW_CFA_offset, r5, -32 */
+        0x84, 9,                        /* DW_CFA_offset, r4, -36 */
+    }
+};
+
+void tcg_register_jit(void *buf, size_t buf_size)
+{
+    debug_frame.fde.func_start = (tcg_target_long) buf;
+    debug_frame.fde.func_len = buf_size;
+
+    tcg_register_jit_int(buf, buf_size, &debug_frame, sizeof(debug_frame));
+}
-- 
1.8.1.4

Re: [Qemu-devel] [PATCH v3 00/14] tcg: remainder and tcg-arm updates

[Claudio Fontana]

On 03.07.2013 23:29, Richard Henderson wrote:
> Changes v2-v3:
>   * Add myself to tcg maintainers, as per afaerber's suggestion.
>   * Fix rebase error wrt aarch64, as per claudio.
>   * Include tcg-arm unwind patch set; no point in half measures.
> 
> 
> r~
> 
> 
> The following changes since commit ab8bf29078e0ab8347e2ff8b4e5542f7a0c751cf:
> 
>   Merge remote-tracking branch 'qemu-kvm/uq/master' into staging (2013-07-03 08:37:00 -0500)
> 
> are available in the git repository at:
> 
>   git://github.com/rth7680/qemu.git tcg-next
> 
> for you to fetch changes up to 6688d5d7eefa67b5f50b6f03a2456e4635781b3b:
> 
>   tcg-arm: Implement tcg_register_jit (2013-07-03 11:17:57 -0700)
> 
> ----------------------------------------------------------------
> Richard Henderson (14):
>       tcg: Add myself to general TCG maintainership
>       tcg: Split rem requirement from div requirement
>       tcg-arm: Don't implement rem
>       tcg-ppc: Don't implement rem
>       tcg-ppc64: Don't implement rem
>       tcg: Allow non-constant control macros
>       tcg: Simplify logic using TCG_OPF_NOT_PRESENT
>       tcg-arm: Make use of conditional availability of opcodes for divide
>       tcg-arm: Simplify logic in detecting the ARM ISA in use
>       tcg-arm: Use AT_PLATFORM to detect the host ISA
>       tcg: Fix high_pc fields in .debug_info
>       tcg: Move the CIE and FDE header definitions to common code
>       tcg-i386: Use QEMU_BUILD_BUG_ON instead of assert for frame size
>       tcg-arm: Implement tcg_register_jit
> 
>  MAINTAINERS              |   1 +
>  tcg/aarch64/tcg-target.h |   2 +
>  tcg/arm/tcg-target.c     | 172 ++++++++++++++++++++++++++++++-----------------
>  tcg/arm/tcg-target.h     |  15 +++--
>  tcg/hppa/tcg-target.c    |  35 +++-------
>  tcg/hppa/tcg-target.h    |   1 +
>  tcg/i386/tcg-target.c    |  45 +++++--------
>  tcg/ia64/tcg-target.h    |   2 +
>  tcg/mips/tcg-target.h    |   1 +
>  tcg/ppc/tcg-target.c     |  14 ----
>  tcg/ppc/tcg-target.h     |   1 +
>  tcg/ppc64/tcg-target.c   |  26 -------
>  tcg/ppc64/tcg-target.h   |   2 +
>  tcg/sparc/tcg-target.c   |  35 +++-------
>  tcg/sparc/tcg-target.h   |   2 +
>  tcg/tcg-op.h             |  32 +++++++--
>  tcg/tcg-opc.h            |  36 +++++-----
>  tcg/tcg.c                |  26 +++++--
>  tcg/tcg.h                |   6 +-
>  tcg/tci/tcg-target.h     |   2 +
>  20 files changed, 242 insertions(+), 214 deletions(-)
> 

Tested tcg/aarch64 on Aarch64 Foundationv8 (sparc-softmmu, arm-softmmu, x86_64-softmmu).

Tested-by: Claudio Fontana <claudio.fontana@huawei.com>
Reviewed-by: Claudio Fontana <claudio.fontana@huawei.com>

Re: [Qemu-devel] [PATCH v3 01/14] tcg: Add myself to general TCG maintainership

[Peter Maydell]

On 3 July 2013 22:29, Richard Henderson <rth@twiddle.net> wrote:
> Signed-off-by: Richard Henderson <rth@twiddle.net>

I think this is definitely a good idea; thanks!

Acked-by: Peter Maydell <peter.maydell@linaro.org>

-- PMM

Re: [Qemu-devel] [PATCH v3 02/14] tcg: Split rem requirement from div requirement

[Peter Maydell]

On 3 July 2013 22:29, Richard Henderson <rth@twiddle.net> wrote:
> There are several hosts with only a "div" insn.  Remainder is computed
> manually from the quotient and inputs.  We can do this generically.
>
> Signed-off-by: Richard Henderson <rth@twiddle.net>
> --- a/tcg/tci/tcg-target.h
> +++ b/tcg/tci/tcg-target.h
> @@ -61,6 +61,7 @@
>  #define TCG_TARGET_HAS_bswap32_i32      1
>  /* Not more than one of the next two defines must be 1. */
>  #define TCG_TARGET_HAS_div_i32          1
> +#define TCG_TARGET_HAS_rem_i32          1
>  #define TCG_TARGET_HAS_div2_i32         0
>  #define TCG_TARGET_HAS_ext8s_i32        1
>  #define TCG_TARGET_HAS_ext16s_i32       1
> @@ -85,6 +86,7 @@
>  #define TCG_TARGET_HAS_deposit_i64      1
>  /* Not more than one of the next two defines must be 1. */
>  #define TCG_TARGET_HAS_div_i64          0
> +#define TCG_TARGET_HAS_rem_i64          0
>  #define TCG_TARGET_HAS_div2_i64         0
>  #define TCG_TARGET_HAS_ext8s_i64        1
>  #define TCG_TARGET_HAS_ext16s_i64       1

The added line in the these two hunks makes the comments wrong,
doesn't it?

Other than that,
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>

-- PMM

Re: [Qemu-devel] [PATCH v3 03/14] tcg-arm: Don't implement rem

[Peter Maydell]

On 3 July 2013 22:29, Richard Henderson <rth@twiddle.net> wrote:
> Signed-off-by: Richard Henderson <rth@twiddle.net>

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>

-- PMM

Re: [Qemu-devel] [PATCH v3 06/14] tcg: Allow non-constant control macros

[Peter Maydell]

On 3 July 2013 22:29, Richard Henderson <rth@twiddle.net> wrote:
> This allows TCG_TARGET_HAS_* to be a variable rather than a constant,
> which allows easier support for differing ISA levels for the host.

The effect of this is that TCG_OPF_NOT_PRESENT means "if set,
op is definitely not present; if not set, op might or might
not be present", right? Which is OK because it's just a debug
guard/sanity check. (That might be worth noting in a comment
I guess.)

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>

-- PMM

Re: [Qemu-devel] [PATCH v3 07/14] tcg: Simplify logic using TCG_OPF_NOT_PRESENT

[Peter Maydell]

On 3 July 2013 22:29, Richard Henderson <rth@twiddle.net> wrote:
> Expand the definition of "not present" to include "should not be present".
> This means we can simplify the logic surrounding the generic tcg opcodes
> for which the host backend ought not be providing definitions.
>
> Signed-off-by: Richard Henderson <rth@twiddle.net>

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>

-- PMM

Re: [Qemu-devel] [PATCH v3 08/14] tcg-arm: Make use of conditional availability of opcodes for divide

[Peter Maydell]

On 3 July 2013 22:29, Richard Henderson <rth@twiddle.net> wrote:
> We can now detect and use divide instructions at runtime, rather than
> having to restrict their availability to compile-time.
>
> Signed-off-by: Richard Henderson <rth@twiddle.net>
> ---
>  tcg/arm/tcg-target.c | 16 ++++++++++++++--
>  tcg/arm/tcg-target.h | 14 ++++++++------
>  2 files changed, 22 insertions(+), 8 deletions(-)
>
> diff --git a/tcg/arm/tcg-target.c b/tcg/arm/tcg-target.c
> index 8321f80..2c46ceb 100644
> --- a/tcg/arm/tcg-target.c
> +++ b/tcg/arm/tcg-target.c
> @@ -67,6 +67,13 @@ static const int use_armv7_instructions = 0;
>  #endif
>  #undef USE_ARMV7_INSTRUCTIONS
>
> +#ifndef use_idiv_instructions
> +bool use_idiv_instructions;
> +#endif
> +#ifdef CONFIG_GETAUXVAL
> +# include <sys/auxv.h>
> +#endif

My ARM system doesn't have a sys/auxv.h, which renders most of this patch
a bit moot (and certainly untestable :-)). Do newer glibc have this?

> +
>  #ifndef NDEBUG
>  static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
>      "%r0",
> @@ -2029,16 +2036,21 @@ static const TCGTargetOpDef arm_op_defs[] = {
>
>      { INDEX_op_deposit_i32, { "r", "0", "rZ" } },
>
> -#if TCG_TARGET_HAS_div_i32
>      { INDEX_op_div_i32, { "r", "r", "r" } },
>      { INDEX_op_divu_i32, { "r", "r", "r" } },
> -#endif
>
>      { -1 },
>  };
>
>  static void tcg_target_init(TCGContext *s)
>  {
> +#if defined(CONFIG_GETAUXVAL) && !defined(use_idiv_instructions)
> +    {
> +        unsigned long hwcap = getauxval(AT_HWCAP);
> +        use_idiv_instructions = hwcap & (HWCAP_ARM_IDIVA | HWCAP_ARM_IDIVT);

Doesn't this mean we'll try to use the ARM division
insns even if the CPU only supports the Thumb encodings?
I think you should only be testing for whether HWCAP_ARM_IDIVA
is set.

> +    }
> +#endif

thanks
-- PMM

Re: [Qemu-devel] [PATCH v3 09/14] tcg-arm: Simplify logic in detecting the ARM ISA in use

[Peter Maydell]

On 3 July 2013 22:29, Richard Henderson <rth@twiddle.net> wrote:
> -#if defined(__ARM_ARCH_7__) ||  \
> -    defined(__ARM_ARCH_7A__) || \
> -    defined(__ARM_ARCH_7EM__) || \
> -    defined(__ARM_ARCH_7M__) || \
> -    defined(__ARM_ARCH_7R__)
> -#define USE_ARMV7_INSTRUCTIONS
> +/* The __ARM_ARCH define is provided by gcc 4.8.  Construct it otherwise.  */
> +#ifndef __ARM_ARCH
> +# if defined(__ARM_ARCH_7__) || defined(__ARM_ARCH_7A__) \
> +     || defined(__ARM_ARCH_7R__) || defined(__ARM_ARCH_7M__) \
> +     || defined(__ARM_ARCH_7EM__)
> +#  define __ARM_ARCH 7
> +# elif defined(__ARM_ARCH_6__) || defined(__ARM_ARCH_6J__) \
> +       || defined(__ARM_ARCH_6Z__) || defined(__ARM_ARCH_6ZK__) \
> +       || defined(__ARM_ARCH_6K__) || defined(__ARM_ARCH_6T2__)
> +#  define __ARM_ARCH 6
> +# elif defined(__ARM_ARCH_5__) || defined(__ARM_ARCH_5E__) \
> +       || defined(__ARM_ARCH_5T__) || defined(__ARM_ARCH_5TE__) \
> +       || defined(__ARM_ARCH_5TEJ__)
> +#  define __ARM_ARCH 5
> +# else
> +#  define __ARM_ARCH 4
> +# endif
>  #endif
>
> -#if defined(USE_ARMV7_INSTRUCTIONS) || \
> -    defined(__ARM_ARCH_6J__) || \
> -    defined(__ARM_ARCH_6K__) || \
> -    defined(__ARM_ARCH_6T2__) || \
> -    defined(__ARM_ARCH_6Z__) || \
> -    defined(__ARM_ARCH_6ZK__)
> -#define USE_ARMV6_INSTRUCTIONS
> -#endif
> -
> -#if defined(USE_ARMV6_INSTRUCTIONS) || \
> -    defined(__ARM_ARCH_5T__) || \
> -    defined(__ARM_ARCH_5TE__) || \
> -    defined(__ARM_ARCH_5TEJ__)
> -#define USE_ARMV5_INSTRUCTIONS
> -#endif

This change means we now set use_armv5_instructions
for __ARCH_ARCH_5__ and __ARM_ARCH_5E__, which we didn't
before. However one of the things that bool is gating is
whether we use the 'blx' insn, which is ARMv5T and above only.
So this will break v5-but-not-v5T CPUs.

(use_armv6_instructions is similarly now set for __ARCH_ARCH_6__
where it was not before, but none of the things we guard with
that test are insns that aren't in base v6.)

thanks
-- PMM

Re: [Qemu-devel] [PATCH v3 11/14] tcg: Fix high_pc fields in .debug_info

[Peter Maydell]

On 3 July 2013 22:29, Richard Henderson <rth@twiddle.net> wrote:
> I don't think the debugger actually looks at this for anything,
> using the correct .debug_frame contents, but might as well get
> it all correct.
>
> Signed-off-by: Richard Henderson <rth@twiddle.net>

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>

-- PMM

Re: [Qemu-devel] [PATCH v3 12/14] tcg: Move the CIE and FDE header definitions to common code

[Peter Maydell]

On 3 July 2013 22:29, Richard Henderson <rth@twiddle.net> wrote:
> These will necessarily be the same layout for all hosts.  This limits
> the amount of boilerplate required to implement jit debug for a host.
>
> Signed-off-by: Richard Henderson <rth@twiddle.net>

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>

-- PMM

Re: [Qemu-devel] [PATCH v3 14/14] tcg-arm: Implement tcg_register_jit

[Peter Maydell]

On 3 July 2013 22:29, Richard Henderson <rth@twiddle.net> wrote:
> Allows unwinding past the code_gen_buffer.
>
> Signed-off-by: Richard Henderson <rth@twiddle.net>

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>

-- PMM

Re: [Qemu-devel] [PATCH v3 06/14] tcg: Allow non-constant control macros

[Richard Henderson]

On 07/04/2013 03:53 AM, Peter Maydell wrote:
> On 3 July 2013 22:29, Richard Henderson <rth@twiddle.net> wrote:
>> This allows TCG_TARGET_HAS_* to be a variable rather than a constant,
>> which allows easier support for differing ISA levels for the host.
> 
> The effect of this is that TCG_OPF_NOT_PRESENT means "if set,
> op is definitely not present; if not set, op might or might
> not be present", right? Which is OK because it's just a debug
> guard/sanity check. (That might be worth noting in a comment
> I guess.)

Well, if not set, an entry must be present in the operands table.

E.g. for arm division, the { INDEX_op_div_i32, "r", "r", "r" } entry
is always there, even if TCG_TARGET_HAS_div_i32 evaluates to false
at runtime.  The entry must be there Just In Case the expression might
be true.


r~

Re: [Qemu-devel] [PATCH v3 08/14] tcg-arm: Make use of conditional availability of opcodes for divide

[Richard Henderson]

On 07/04/2013 04:02 AM, Peter Maydell wrote:
> 
> My ARM system doesn't have a sys/auxv.h, which renders most of this patch
> a bit moot (and certainly untestable :-)). Do newer glibc have this?

glibc 2.16 has this.

I've also got another pending patch set that implements getauxval inside
qemu if it's not present in the system library.  Which means that we can
eliminate some of the ifdefery seen here.

>> +        unsigned long hwcap = getauxval(AT_HWCAP);
>> +        use_idiv_instructions = hwcap & (HWCAP_ARM_IDIVA | HWCAP_ARM_IDIVT);
> 
> Doesn't this mean we'll try to use the ARM division
> insns even if the CPU only supports the Thumb encodings?
> I think you should only be testing for whether HWCAP_ARM_IDIVA
> is set.

I suppose.  Though later kernels have actually merged these bits:

uapi/asm/hwcap.h:27:#define HWCAP_IDIV	(HWCAP_IDIVA | HWCAP_IDIVT)


r~

Re: [Qemu-devel] [PATCH v3 08/14] tcg-arm: Make use of conditional availability of opcodes for divide

[Peter Maydell]

On 4 July 2013 18:33, Richard Henderson <rth@twiddle.net> wrote:
> On 07/04/2013 04:02 AM, Peter Maydell wrote:
>>> +        unsigned long hwcap = getauxval(AT_HWCAP);
>>> +        use_idiv_instructions = hwcap & (HWCAP_ARM_IDIVA | HWCAP_ARM_IDIVT);
>>
>> Doesn't this mean we'll try to use the ARM division
>> insns even if the CPU only supports the Thumb encodings?
>> I think you should only be testing for whether HWCAP_ARM_IDIVA
>> is set.
>
> I suppose.  Though later kernels have actually merged these bits:
>
> uapi/asm/hwcap.h:27:#define HWCAP_IDIV  (HWCAP_IDIVA | HWCAP_IDIVT)

Yes, but the two bits are still separate values:

 #define HWCAP_IDIVA     (1 << 17)
 #define HWCAP_IDIVT     (1 << 18)

Presumably the HWCAP_IDIV is if you want to check that you
have full division support via
  (hwcap & HWCAP_IDIV) == HWCAP_IDIV

We could do that if you prefer; it would be effectively
the same as just testing the IDIVA bit though.

-- PMM

Re: [Qemu-devel] [PATCH v3 09/14] tcg-arm: Simplify logic in detecting the ARM ISA in use

[Richard Henderson]

On 07/04/2013 04:22 AM, Peter Maydell wrote:
> 
> This change means we now set use_armv5_instructions
> for __ARCH_ARCH_5__ and __ARM_ARCH_5E__, which we didn't
> before. However one of the things that bool is gating is
> whether we use the 'blx' insn, which is ARMv5T and above only.
> So this will break v5-but-not-v5T CPUs.

Hmm.  And thus platform=v5 plus HWCAP_THUMB ought to detect that too, eh?


r~

Re: [Qemu-devel] [PATCH v3 09/14] tcg-arm: Simplify logic in detecting the ARM ISA in use

[Peter Maydell]

On 4 July 2013 18:44, Richard Henderson <rth@twiddle.net> wrote:
> On 07/04/2013 04:22 AM, Peter Maydell wrote:
>>
>> This change means we now set use_armv5_instructions
>> for __ARCH_ARCH_5__ and __ARM_ARCH_5E__, which we didn't
>> before. However one of the things that bool is gating is
>> whether we use the 'blx' insn, which is ARMv5T and above only.
>> So this will break v5-but-not-v5T CPUs.
>
> Hmm.  And thus platform=v5 plus HWCAP_THUMB ought to detect
> that too, eh?

Should do, yes. (v5-but-not-v5T is pretty rare though; the
v7 ARM ARM describes it as an "obsolete variant", putting it
in the same class as ARMv1, v2 and v3. So if you wanted to
argue that we should just not support running on v5-not-T
you'd have a fairly reasonable case.)

-- PMM