From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-arm@nongnu.org, qemu-devel@nongnu.org
Cc: Richard Henderson <richard.henderson@linaro.org>
Subject: Re: [PATCH 1/2] target/arm/translate-neon: UNDEF if VLD1/VST1 stride bits are non-zero
Date: Thu, 3 Mar 2022 11:43:56 +0000 [thread overview]
Message-ID: <CAFEAcA9H3Cc+E9G91xrvH-YcD-fJU-84hOekbekca-MOz7d_eA@mail.gmail.com> (raw)
In-Reply-To: <20220303113741.2156877-2-peter.maydell@linaro.org>
On Thu, 3 Mar 2022 at 11:37, Peter Maydell <peter.maydell@linaro.org> wrote:
>
> For VLD1/VST1 (single element to one lane) we are only accessing one
> register, and so the 'stride' is meaningless. The bits that would
> specify stride (insn bit [4] for size=1, bit [6] for size=2) are
This should say "bit [5] for size=1".
> specified to be zero in the encoding (which would correspond to a
> stride of 1 for VLD2/VLD3/VLD4 etc), and we must UNDEF if they are
> not.
-- PMM
next prev parent reply other threads:[~2022-03-03 11:45 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-03-03 11:37 [PATCH 0/2] target/arm: Check Neon VLD1/VST1 stride bits are zero Peter Maydell
2022-03-03 11:37 ` [PATCH 1/2] target/arm/translate-neon: UNDEF if VLD1/VST1 stride bits are non-zero Peter Maydell
2022-03-03 11:43 ` Peter Maydell [this message]
2022-03-03 16:10 ` Richard Henderson
2022-03-03 11:37 ` [PATCH 2/2] target/arm/translate-neon: Simplify align field check for VLD3 Peter Maydell
2022-03-03 16:11 ` Richard Henderson
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