* [Qemu-devel] [PATCH 00/14] target-arm: Create QOM subclass per CPU implementation
@ 2012-03-30 12:51 Peter Maydell
2012-03-30 12:51 ` [Qemu-devel] [PATCH 01/14] target-arm: Add QOM subclasses for each ARM cpu implementation Peter Maydell
` (13 more replies)
0 siblings, 14 replies; 17+ messages in thread
From: Peter Maydell @ 2012-03-30 12:51 UTC (permalink / raw)
To: qemu-devel; +Cc: Paul Brook, Anthony Liguori, Andreas Färber
This patch series builds on Andreas' basic QOMification of the ARM
CPU by creating a QOM subclass for each ARM CPU implementation
(926,1176,A8,etc). We can then move the setup of feature bits, register
reset values, constant ID register values, etc, from the big switch
statement in cpu_reset_model_id() into the per-cpu init function.
This allows us to:
* drop that big switch completely
* get rid of the ugly "copy values across the memset" code we had
for a few CPUARMState fields
* remove the nasty implicit dependency on reset function ordering
we were using on the Highbank board
* easily make some of these fields QOM properties in future (this
needs support for a realize method first, though)
Peter Maydell (14):
target-arm: Add QOM subclasses for each ARM cpu implementation
target-arm: Move feature bit settings to CPU init fns
target-arm: Move FPSID config to cpu init fns
target-arm: Move MVFR* setup to per cpu init fns
target-arm: Move CTR setup to per cpu init fns
target-arm: Move SCTLR reset value setup to per cpu init fns
target-arm: Drop JTAG_ID documentation
target-arm: Move iWMMXT wCID reset to cpu_state_reset
target-arm: Move feature register setup to per-CPU init fns
target-arm: Move OMAP cp15_i_{max,min} reset to cpu_state_reset
target-arm: Move cache ID register setup to cpu specific init fns
target-arm: Drop cpu_reset_model_id()
target-arm: Move reset handling to arm_cpu_reset
target-arm: Move A9 config_base_address reset value to ARMCPU
hw/highbank.c | 12 +-
target-arm/cpu-qom.h | 27 ++
target-arm/cpu.c | 646 +++++++++++++++++++++++++++++++++++++++++++++++++-
target-arm/cpu.h | 6 +-
target-arm/helper.c | 452 ++++-------------------------------
5 files changed, 726 insertions(+), 417 deletions(-)
^ permalink raw reply [flat|nested] 17+ messages in thread
* [Qemu-devel] [PATCH 01/14] target-arm: Add QOM subclasses for each ARM cpu implementation
2012-03-30 12:51 [Qemu-devel] [PATCH 00/14] target-arm: Create QOM subclass per CPU implementation Peter Maydell
@ 2012-03-30 12:51 ` Peter Maydell
2012-03-30 12:51 ` [Qemu-devel] [PATCH 02/14] target-arm: Move feature bit settings to CPU init fns Peter Maydell
` (12 subsequent siblings)
13 siblings, 0 replies; 17+ messages in thread
From: Peter Maydell @ 2012-03-30 12:51 UTC (permalink / raw)
To: qemu-devel; +Cc: Paul Brook, Anthony Liguori, Andreas Färber
Register subclasses for each ARM CPU implementation (with the
exception of "pxa270", which is an alias for "pxa270-a0").
Let arm_cpu_list() enumerate CPU subclasses in alphabetical order,
except for special value "any".
Replace cpu_arm_find_by_name()'s string -> CPUID lookup by storing the
CPUID (aka MIDR, Main ID Register) value in the class.
Signed-off-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target-arm/cpu-qom.h | 5 +
target-arm/cpu.c | 229 +++++++++++++++++++++++++++++++++++++++++++++++++-
target-arm/helper.c | 114 +++++++++++--------------
3 files changed, 283 insertions(+), 65 deletions(-)
diff --git a/target-arm/cpu-qom.h b/target-arm/cpu-qom.h
index 42d2a6b..1a3965f 100644
--- a/target-arm/cpu-qom.h
+++ b/target-arm/cpu-qom.h
@@ -58,6 +58,11 @@ typedef struct ARMCPU {
/*< public >*/
CPUARMState env;
+
+ /* Configuration values (set by the instance init function);
+ * some of these might become properties eventually.
+ */
+ uint32_t midr;
} ARMCPU;
static inline ARMCPU *arm_env_get_cpu(CPUARMState *env)
diff --git a/target-arm/cpu.c b/target-arm/cpu.c
index c3ed45b..a09e24e 100644
--- a/target-arm/cpu.c
+++ b/target-arm/cpu.c
@@ -34,6 +34,212 @@ static void arm_cpu_reset(CPUState *s)
cpu_state_reset(&cpu->env);
}
+static void arm_cpu_initfn(Object *obj)
+{
+ ARMCPU *cpu = ARM_CPU(obj);
+
+ memset(&cpu->env, 0, sizeof(CPUARMState));
+ cpu_exec_init(&cpu->env);
+
+ cpu->env.cpu_model_str = object_get_typename(obj);
+}
+
+/* CPU models */
+
+static void arm926_initfn(Object *obj)
+{
+ ARMCPU *cpu = ARM_CPU(obj);
+ cpu->midr = ARM_CPUID_ARM926;
+}
+
+static void arm946_initfn(Object *obj)
+{
+ ARMCPU *cpu = ARM_CPU(obj);
+ cpu->midr = ARM_CPUID_ARM946;
+}
+
+static void arm1026_initfn(Object *obj)
+{
+ ARMCPU *cpu = ARM_CPU(obj);
+ cpu->midr = ARM_CPUID_ARM1026;
+}
+
+static void arm1136_r2_initfn(Object *obj)
+{
+ ARMCPU *cpu = ARM_CPU(obj);
+ cpu->midr = ARM_CPUID_ARM1136_R2;
+}
+
+static void arm1136_initfn(Object *obj)
+{
+ ARMCPU *cpu = ARM_CPU(obj);
+ cpu->midr = ARM_CPUID_ARM1136;
+}
+
+static void arm1176_initfn(Object *obj)
+{
+ ARMCPU *cpu = ARM_CPU(obj);
+ cpu->midr = ARM_CPUID_ARM1176;
+}
+
+static void arm11mpcore_initfn(Object *obj)
+{
+ ARMCPU *cpu = ARM_CPU(obj);
+ cpu->midr = ARM_CPUID_ARM11MPCORE;
+}
+
+static void cortex_m3_initfn(Object *obj)
+{
+ ARMCPU *cpu = ARM_CPU(obj);
+ cpu->midr = ARM_CPUID_CORTEXM3;
+}
+
+static void cortex_a8_initfn(Object *obj)
+{
+ ARMCPU *cpu = ARM_CPU(obj);
+ cpu->midr = ARM_CPUID_CORTEXA8;
+}
+
+static void cortex_a9_initfn(Object *obj)
+{
+ ARMCPU *cpu = ARM_CPU(obj);
+ cpu->midr = ARM_CPUID_CORTEXA9;
+}
+
+static void cortex_a15_initfn(Object *obj)
+{
+ ARMCPU *cpu = ARM_CPU(obj);
+ cpu->midr = ARM_CPUID_CORTEXA15;
+}
+
+static void ti925t_initfn(Object *obj)
+{
+ ARMCPU *cpu = ARM_CPU(obj);
+ cpu->midr = ARM_CPUID_TI925T;
+}
+
+static void sa1100_initfn(Object *obj)
+{
+ ARMCPU *cpu = ARM_CPU(obj);
+ cpu->midr = ARM_CPUID_SA1100;
+}
+
+static void sa1110_initfn(Object *obj)
+{
+ ARMCPU *cpu = ARM_CPU(obj);
+ cpu->midr = ARM_CPUID_SA1110;
+}
+
+static void pxa250_initfn(Object *obj)
+{
+ ARMCPU *cpu = ARM_CPU(obj);
+ cpu->midr = ARM_CPUID_PXA250;
+}
+
+static void pxa255_initfn(Object *obj)
+{
+ ARMCPU *cpu = ARM_CPU(obj);
+ cpu->midr = ARM_CPUID_PXA255;
+}
+
+static void pxa260_initfn(Object *obj)
+{
+ ARMCPU *cpu = ARM_CPU(obj);
+ cpu->midr = ARM_CPUID_PXA260;
+}
+
+static void pxa261_initfn(Object *obj)
+{
+ ARMCPU *cpu = ARM_CPU(obj);
+ cpu->midr = ARM_CPUID_PXA261;
+}
+
+static void pxa262_initfn(Object *obj)
+{
+ ARMCPU *cpu = ARM_CPU(obj);
+ cpu->midr = ARM_CPUID_PXA262;
+}
+
+static void pxa270a0_initfn(Object *obj)
+{
+ ARMCPU *cpu = ARM_CPU(obj);
+ cpu->midr = ARM_CPUID_PXA270_A0;
+}
+
+static void pxa270a1_initfn(Object *obj)
+{
+ ARMCPU *cpu = ARM_CPU(obj);
+ cpu->midr = ARM_CPUID_PXA270_A1;
+}
+
+static void pxa270b0_initfn(Object *obj)
+{
+ ARMCPU *cpu = ARM_CPU(obj);
+ cpu->midr = ARM_CPUID_PXA270_B0;
+}
+
+static void pxa270b1_initfn(Object *obj)
+{
+ ARMCPU *cpu = ARM_CPU(obj);
+ cpu->midr = ARM_CPUID_PXA270_B1;
+}
+
+static void pxa270c0_initfn(Object *obj)
+{
+ ARMCPU *cpu = ARM_CPU(obj);
+ cpu->midr = ARM_CPUID_PXA270_C0;
+}
+
+static void pxa270c5_initfn(Object *obj)
+{
+ ARMCPU *cpu = ARM_CPU(obj);
+ cpu->midr = ARM_CPUID_PXA270_C5;
+}
+
+static void arm_any_initfn(Object *obj)
+{
+ ARMCPU *cpu = ARM_CPU(obj);
+ cpu->midr = ARM_CPUID_ANY;
+}
+
+typedef struct ARMCPUInfo {
+ const char *name;
+ void (*initfn)(Object *obj);
+} ARMCPUInfo;
+
+static const ARMCPUInfo arm_cpus[] = {
+ { .name = "arm926", .initfn = arm926_initfn },
+ { .name = "arm946", .initfn = arm946_initfn },
+ { .name = "arm1026", .initfn = arm1026_initfn },
+ /* What QEMU calls "arm1136-r2" is actually the 1136 r0p2, i.e. an
+ * older core than plain "arm1136". In particular this does not
+ * have the v6K features.
+ */
+ { .name = "arm1136-r2", .initfn = arm1136_r2_initfn },
+ { .name = "arm1136", .initfn = arm1136_initfn },
+ { .name = "arm1176", .initfn = arm1176_initfn },
+ { .name = "arm11mpcore", .initfn = arm11mpcore_initfn },
+ { .name = "cortex-m3", .initfn = cortex_m3_initfn },
+ { .name = "cortex-a8", .initfn = cortex_a8_initfn },
+ { .name = "cortex-a9", .initfn = cortex_a9_initfn },
+ { .name = "cortex-a15", .initfn = cortex_a15_initfn },
+ { .name = "ti925t", .initfn = ti925t_initfn },
+ { .name = "sa1100", .initfn = sa1100_initfn },
+ { .name = "sa1110", .initfn = sa1110_initfn },
+ { .name = "pxa250", .initfn = pxa250_initfn },
+ { .name = "pxa255", .initfn = pxa255_initfn },
+ { .name = "pxa260", .initfn = pxa260_initfn },
+ { .name = "pxa261", .initfn = pxa261_initfn },
+ { .name = "pxa262", .initfn = pxa262_initfn },
+ { .name = "pxa270-a0", .initfn = pxa270a0_initfn },
+ { .name = "pxa270-a1", .initfn = pxa270a1_initfn },
+ { .name = "pxa270-b0", .initfn = pxa270b0_initfn },
+ { .name = "pxa270-b1", .initfn = pxa270b1_initfn },
+ { .name = "pxa270-c0", .initfn = pxa270c0_initfn },
+ { .name = "pxa270-c5", .initfn = pxa270c5_initfn },
+ { .name = "any", .initfn = arm_any_initfn },
+};
+
static void arm_cpu_class_init(ObjectClass *oc, void *data)
{
ARMCPUClass *acc = ARM_CPU_CLASS(oc);
@@ -43,18 +249,37 @@ static void arm_cpu_class_init(ObjectClass *oc, void *data)
cc->reset = arm_cpu_reset;
}
+static void cpu_register(const ARMCPUInfo *info)
+{
+ TypeInfo type = {
+ .name = info->name,
+ .parent = TYPE_ARM_CPU,
+ .instance_size = sizeof(ARMCPU),
+ .instance_init = info->initfn,
+ .class_size = sizeof(ARMCPUClass),
+ .class_init = arm_cpu_class_init,
+ };
+
+ type_register_static(&type);
+}
+
static const TypeInfo arm_cpu_type_info = {
.name = TYPE_ARM_CPU,
.parent = TYPE_CPU,
.instance_size = sizeof(ARMCPU),
- .abstract = false,
+ .instance_init = arm_cpu_initfn,
+ .abstract = true,
.class_size = sizeof(ARMCPUClass),
- .class_init = arm_cpu_class_init,
};
static void arm_cpu_register_types(void)
{
+ int i;
+
type_register_static(&arm_cpu_type_info);
+ for (i = 0; i < ARRAY_SIZE(arm_cpus); i++) {
+ cpu_register(&arm_cpus[i]);
+ }
}
type_init(arm_cpu_register_types)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index d974b57..4748f80 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -6,6 +6,7 @@
#include "hw/loader.h"
#endif
#include "sysemu.h"
+#include "cpu-qom.h"
static uint32_t cortexa15_cp15_c0_c1[8] = {
0x00001131, 0x00011011, 0x02010555, 0x00000000,
@@ -46,8 +47,6 @@ static uint32_t arm1176_cp15_c0_c1[8] =
static uint32_t arm1176_cp15_c0_c2[8] =
{ 0x0140011, 0x12002111, 0x11231121, 0x01102131, 0x01141, 0, 0, 0 };
-static uint32_t cpu_arm_find_by_name(const char *name);
-
static inline void set_feature(CPUARMState *env, int feature)
{
env->features |= 1u << feature;
@@ -55,7 +54,6 @@ static inline void set_feature(CPUARMState *env, int feature)
static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
{
- env->cp15.c0_cpuid = id;
switch (id) {
case ARM_CPUID_ARM926:
set_feature(env, ARM_FEATURE_V5);
@@ -201,7 +199,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
case ARM_CPUID_TI925T:
set_feature(env, ARM_FEATURE_V4T);
set_feature(env, ARM_FEATURE_OMAPCP);
- env->cp15.c0_cpuid = ARM_CPUID_TI925T; /* Depends on wiring. */
env->cp15.c0_cachetype = 0x5109149;
env->cp15.c1_sys = 0x00000070;
env->cp15.c15_i_max = 0x000;
@@ -287,6 +284,7 @@ void cpu_state_reset(CPUARMState *env)
{
uint32_t id;
uint32_t tmp = 0;
+ ARMCPU *cpu = arm_env_get_cpu(env);
if (qemu_loglevel_mask(CPU_LOG_RESET)) {
qemu_log("CPU Reset (CPU %d)\n", env->cpu_index);
@@ -299,6 +297,7 @@ void cpu_state_reset(CPUARMState *env)
if (id)
cpu_reset_model_id(env, id);
env->cp15.c15_config_base_address = tmp;
+ env->cp15.c0_cpuid = cpu->midr;
#if defined (CONFIG_USER_ONLY)
env->uncached_cpsr = ARM_CPU_MODE_USR;
/* For user mode we must enable access to coprocessors */
@@ -405,24 +404,28 @@ static int vfp_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg)
CPUARMState *cpu_arm_init(const char *cpu_model)
{
+ ObjectClass *klass;
ARMCPU *cpu;
CPUARMState *env;
- uint32_t id;
static int inited = 0;
- id = cpu_arm_find_by_name(cpu_model);
- if (id == 0)
+ /* One legacy alias to check */
+ if (strcmp(cpu_model, "pxa270") == 0) {
+ cpu_model = "pxa270-a0";
+ }
+
+ klass = object_class_by_name(cpu_model);
+ if (klass == NULL) {
return NULL;
- cpu = ARM_CPU(object_new(TYPE_ARM_CPU));
+ }
+ cpu = ARM_CPU(object_new(cpu_model));
env = &cpu->env;
- cpu_exec_init(env);
+
if (tcg_enabled() && !inited) {
inited = 1;
arm_translate_init();
}
- env->cpu_model_str = cpu_model;
- env->cp15.c0_cpuid = id;
cpu_state_reset(env);
if (arm_feature(env, ARM_FEATURE_NEON)) {
gdb_register_coprocessor(env, vfp_gdb_get_reg, vfp_gdb_set_reg,
@@ -438,66 +441,51 @@ CPUARMState *cpu_arm_init(const char *cpu_model)
return env;
}
-struct arm_cpu_t {
- uint32_t id;
- const char *name;
-};
-
-static const struct arm_cpu_t arm_cpu_names[] = {
- { ARM_CPUID_ARM926, "arm926"},
- { ARM_CPUID_ARM946, "arm946"},
- { ARM_CPUID_ARM1026, "arm1026"},
- { ARM_CPUID_ARM1136, "arm1136"},
- { ARM_CPUID_ARM1136_R2, "arm1136-r2"},
- { ARM_CPUID_ARM1176, "arm1176"},
- { ARM_CPUID_ARM11MPCORE, "arm11mpcore"},
- { ARM_CPUID_CORTEXM3, "cortex-m3"},
- { ARM_CPUID_CORTEXA8, "cortex-a8"},
- { ARM_CPUID_CORTEXA9, "cortex-a9"},
- { ARM_CPUID_CORTEXA15, "cortex-a15" },
- { ARM_CPUID_TI925T, "ti925t" },
- { ARM_CPUID_PXA250, "pxa250" },
- { ARM_CPUID_SA1100, "sa1100" },
- { ARM_CPUID_SA1110, "sa1110" },
- { ARM_CPUID_PXA255, "pxa255" },
- { ARM_CPUID_PXA260, "pxa260" },
- { ARM_CPUID_PXA261, "pxa261" },
- { ARM_CPUID_PXA262, "pxa262" },
- { ARM_CPUID_PXA270, "pxa270" },
- { ARM_CPUID_PXA270_A0, "pxa270-a0" },
- { ARM_CPUID_PXA270_A1, "pxa270-a1" },
- { ARM_CPUID_PXA270_B0, "pxa270-b0" },
- { ARM_CPUID_PXA270_B1, "pxa270-b1" },
- { ARM_CPUID_PXA270_C0, "pxa270-c0" },
- { ARM_CPUID_PXA270_C5, "pxa270-c5" },
- { ARM_CPUID_ANY, "any"},
- { 0, NULL}
-};
+typedef struct ARMCPUListState {
+ fprintf_function cpu_fprintf;
+ FILE *file;
+} ARMCPUListState;
-void arm_cpu_list(FILE *f, fprintf_function cpu_fprintf)
+/* Sort alphabetically by type name, except for "any". */
+static gint arm_cpu_list_compare(gconstpointer a, gconstpointer b)
{
- int i;
+ ObjectClass *class_a = (ObjectClass *)a;
+ ObjectClass *class_b = (ObjectClass *)b;
+ const char *name_a, *name_b;
- (*cpu_fprintf)(f, "Available CPUs:\n");
- for (i = 0; arm_cpu_names[i].name; i++) {
- (*cpu_fprintf)(f, " %s\n", arm_cpu_names[i].name);
+ name_a = object_class_get_name(class_a);
+ name_b = object_class_get_name(class_b);
+ if (strcmp(name_a, "any") == 0) {
+ return 1;
+ } else if (strcmp(name_b, "any") == 0) {
+ return -1;
+ } else {
+ return strcmp(name_a, name_b);
}
}
-/* return 0 if not found */
-static uint32_t cpu_arm_find_by_name(const char *name)
+static void arm_cpu_list_entry(gpointer data, gpointer user_data)
{
- int i;
- uint32_t id;
+ ObjectClass *klass = data;
+ ARMCPUListState *s = user_data;
- id = 0;
- for (i = 0; arm_cpu_names[i].name; i++) {
- if (strcmp(name, arm_cpu_names[i].name) == 0) {
- id = arm_cpu_names[i].id;
- break;
- }
- }
- return id;
+ (*s->cpu_fprintf)(s->file, " %s\n",
+ object_class_get_name(klass));
+}
+
+void arm_cpu_list(FILE *f, fprintf_function cpu_fprintf)
+{
+ ARMCPUListState s = {
+ .file = f,
+ .cpu_fprintf = cpu_fprintf,
+ };
+ GSList *list;
+
+ list = object_class_get_list(TYPE_ARM_CPU, false);
+ list = g_slist_sort(list, arm_cpu_list_compare);
+ (*cpu_fprintf)(f, "Available CPUs:\n");
+ g_slist_foreach(list, arm_cpu_list_entry, &s);
+ g_slist_free(list);
}
static int bad_mode_switch(CPUARMState *env, int mode)
--
1.7.1
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [Qemu-devel] [PATCH 02/14] target-arm: Move feature bit settings to CPU init fns
2012-03-30 12:51 [Qemu-devel] [PATCH 00/14] target-arm: Create QOM subclass per CPU implementation Peter Maydell
2012-03-30 12:51 ` [Qemu-devel] [PATCH 01/14] target-arm: Add QOM subclasses for each ARM cpu implementation Peter Maydell
@ 2012-03-30 12:51 ` Peter Maydell
2012-03-30 12:51 ` [Qemu-devel] [PATCH 03/14] target-arm: Move FPSID config to cpu " Peter Maydell
` (11 subsequent siblings)
13 siblings, 0 replies; 17+ messages in thread
From: Peter Maydell @ 2012-03-30 12:51 UTC (permalink / raw)
To: qemu-devel; +Cc: Paul Brook, Anthony Liguori, Andreas Färber
Move the setting of the feature bits from cpu_reset_model_id()
to each CPU's instance init function. This requires us to move
the features field in CPUARMState so that it is not cleared
on reset.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target-arm/cpu.c | 155 +++++++++++++++++++++++++++++++++++++++++++++++++++
target-arm/cpu.h | 6 +-
target-arm/helper.c | 96 -------------------------------
3 files changed, 158 insertions(+), 99 deletions(-)
diff --git a/target-arm/cpu.c b/target-arm/cpu.c
index a09e24e..0dad352 100644
--- a/target-arm/cpu.c
+++ b/target-arm/cpu.c
@@ -34,6 +34,11 @@ static void arm_cpu_reset(CPUState *s)
cpu_state_reset(&cpu->env);
}
+static inline void set_feature(CPUARMState *env, int feature)
+{
+ env->features |= 1u << feature;
+}
+
static void arm_cpu_initfn(Object *obj)
{
ARMCPU *cpu = ARM_CPU(obj);
@@ -44,162 +49,312 @@ static void arm_cpu_initfn(Object *obj)
cpu->env.cpu_model_str = object_get_typename(obj);
}
+static void arm_cpu_postconfig_init(ARMCPU *cpu)
+{
+ /* This function is called as the last thing the init
+ * functions for the CPU model specific subclasses do,
+ * so it can do common actions based on feature bits, etc.
+ * When we have realize support it should probably become
+ * a realize function.
+ */
+ CPUARMState *env = &cpu->env;
+ /* Some features automatically imply others: */
+ if (arm_feature(env, ARM_FEATURE_V7)) {
+ set_feature(env, ARM_FEATURE_VAPA);
+ set_feature(env, ARM_FEATURE_THUMB2);
+ if (!arm_feature(env, ARM_FEATURE_M)) {
+ set_feature(env, ARM_FEATURE_V6K);
+ } else {
+ set_feature(env, ARM_FEATURE_V6);
+ }
+ }
+ if (arm_feature(env, ARM_FEATURE_V6K)) {
+ set_feature(env, ARM_FEATURE_V6);
+ set_feature(env, ARM_FEATURE_MVFR);
+ }
+ if (arm_feature(env, ARM_FEATURE_V6)) {
+ set_feature(env, ARM_FEATURE_V5);
+ if (!arm_feature(env, ARM_FEATURE_M)) {
+ set_feature(env, ARM_FEATURE_AUXCR);
+ }
+ }
+ if (arm_feature(env, ARM_FEATURE_V5)) {
+ set_feature(env, ARM_FEATURE_V4T);
+ }
+ if (arm_feature(env, ARM_FEATURE_M)) {
+ set_feature(env, ARM_FEATURE_THUMB_DIV);
+ }
+ if (arm_feature(env, ARM_FEATURE_ARM_DIV)) {
+ set_feature(env, ARM_FEATURE_THUMB_DIV);
+ }
+ if (arm_feature(env, ARM_FEATURE_VFP4)) {
+ set_feature(env, ARM_FEATURE_VFP3);
+ }
+ if (arm_feature(env, ARM_FEATURE_VFP3)) {
+ set_feature(env, ARM_FEATURE_VFP);
+ }
+}
+
/* CPU models */
static void arm926_initfn(Object *obj)
{
ARMCPU *cpu = ARM_CPU(obj);
+ set_feature(&cpu->env, ARM_FEATURE_V5);
+ set_feature(&cpu->env, ARM_FEATURE_VFP);
cpu->midr = ARM_CPUID_ARM926;
+ arm_cpu_postconfig_init(cpu);
}
static void arm946_initfn(Object *obj)
{
ARMCPU *cpu = ARM_CPU(obj);
+ set_feature(&cpu->env, ARM_FEATURE_V5);
+ set_feature(&cpu->env, ARM_FEATURE_MPU);
cpu->midr = ARM_CPUID_ARM946;
+ arm_cpu_postconfig_init(cpu);
}
static void arm1026_initfn(Object *obj)
{
ARMCPU *cpu = ARM_CPU(obj);
+ set_feature(&cpu->env, ARM_FEATURE_V5);
+ set_feature(&cpu->env, ARM_FEATURE_VFP);
+ set_feature(&cpu->env, ARM_FEATURE_AUXCR);
cpu->midr = ARM_CPUID_ARM1026;
+ arm_cpu_postconfig_init(cpu);
}
static void arm1136_r2_initfn(Object *obj)
{
ARMCPU *cpu = ARM_CPU(obj);
+ set_feature(&cpu->env, ARM_FEATURE_V6);
+ set_feature(&cpu->env, ARM_FEATURE_VFP);
cpu->midr = ARM_CPUID_ARM1136_R2;
+ arm_cpu_postconfig_init(cpu);
}
static void arm1136_initfn(Object *obj)
{
ARMCPU *cpu = ARM_CPU(obj);
+ set_feature(&cpu->env, ARM_FEATURE_V6K);
+ set_feature(&cpu->env, ARM_FEATURE_V6);
+ set_feature(&cpu->env, ARM_FEATURE_VFP);
cpu->midr = ARM_CPUID_ARM1136;
+ arm_cpu_postconfig_init(cpu);
}
static void arm1176_initfn(Object *obj)
{
ARMCPU *cpu = ARM_CPU(obj);
+ set_feature(&cpu->env, ARM_FEATURE_V6K);
+ set_feature(&cpu->env, ARM_FEATURE_VFP);
+ set_feature(&cpu->env, ARM_FEATURE_VAPA);
cpu->midr = ARM_CPUID_ARM1176;
+ arm_cpu_postconfig_init(cpu);
}
static void arm11mpcore_initfn(Object *obj)
{
ARMCPU *cpu = ARM_CPU(obj);
+ set_feature(&cpu->env, ARM_FEATURE_V6K);
+ set_feature(&cpu->env, ARM_FEATURE_VFP);
+ set_feature(&cpu->env, ARM_FEATURE_VAPA);
cpu->midr = ARM_CPUID_ARM11MPCORE;
+ arm_cpu_postconfig_init(cpu);
}
static void cortex_m3_initfn(Object *obj)
{
ARMCPU *cpu = ARM_CPU(obj);
+ set_feature(&cpu->env, ARM_FEATURE_V7);
+ set_feature(&cpu->env, ARM_FEATURE_M);
cpu->midr = ARM_CPUID_CORTEXM3;
+ arm_cpu_postconfig_init(cpu);
}
static void cortex_a8_initfn(Object *obj)
{
ARMCPU *cpu = ARM_CPU(obj);
+ set_feature(&cpu->env, ARM_FEATURE_V7);
+ set_feature(&cpu->env, ARM_FEATURE_VFP3);
+ set_feature(&cpu->env, ARM_FEATURE_NEON);
+ set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
cpu->midr = ARM_CPUID_CORTEXA8;
+ arm_cpu_postconfig_init(cpu);
}
static void cortex_a9_initfn(Object *obj)
{
ARMCPU *cpu = ARM_CPU(obj);
+ set_feature(&cpu->env, ARM_FEATURE_V7);
+ set_feature(&cpu->env, ARM_FEATURE_VFP3);
+ set_feature(&cpu->env, ARM_FEATURE_VFP_FP16);
+ set_feature(&cpu->env, ARM_FEATURE_NEON);
+ set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
+ /* Note that A9 supports the MP extensions even for
+ * A9UP and single-core A9MP (which are both different
+ * and valid configurations; we don't model A9UP).
+ */
+ set_feature(&cpu->env, ARM_FEATURE_V7MP);
cpu->midr = ARM_CPUID_CORTEXA9;
+ arm_cpu_postconfig_init(cpu);
}
static void cortex_a15_initfn(Object *obj)
{
ARMCPU *cpu = ARM_CPU(obj);
+ set_feature(&cpu->env, ARM_FEATURE_V7);
+ set_feature(&cpu->env, ARM_FEATURE_VFP4);
+ set_feature(&cpu->env, ARM_FEATURE_VFP_FP16);
+ set_feature(&cpu->env, ARM_FEATURE_NEON);
+ set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
+ set_feature(&cpu->env, ARM_FEATURE_ARM_DIV);
+ set_feature(&cpu->env, ARM_FEATURE_V7MP);
+ set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
cpu->midr = ARM_CPUID_CORTEXA15;
+ arm_cpu_postconfig_init(cpu);
}
static void ti925t_initfn(Object *obj)
{
ARMCPU *cpu = ARM_CPU(obj);
+ set_feature(&cpu->env, ARM_FEATURE_V4T);
+ set_feature(&cpu->env, ARM_FEATURE_OMAPCP);
cpu->midr = ARM_CPUID_TI925T;
+ arm_cpu_postconfig_init(cpu);
}
static void sa1100_initfn(Object *obj)
{
ARMCPU *cpu = ARM_CPU(obj);
+ set_feature(&cpu->env, ARM_FEATURE_STRONGARM);
cpu->midr = ARM_CPUID_SA1100;
+ arm_cpu_postconfig_init(cpu);
}
static void sa1110_initfn(Object *obj)
{
ARMCPU *cpu = ARM_CPU(obj);
+ set_feature(&cpu->env, ARM_FEATURE_STRONGARM);
cpu->midr = ARM_CPUID_SA1110;
+ arm_cpu_postconfig_init(cpu);
}
static void pxa250_initfn(Object *obj)
{
ARMCPU *cpu = ARM_CPU(obj);
+ set_feature(&cpu->env, ARM_FEATURE_V5);
+ set_feature(&cpu->env, ARM_FEATURE_XSCALE);
cpu->midr = ARM_CPUID_PXA250;
+ arm_cpu_postconfig_init(cpu);
}
static void pxa255_initfn(Object *obj)
{
ARMCPU *cpu = ARM_CPU(obj);
+ set_feature(&cpu->env, ARM_FEATURE_V5);
+ set_feature(&cpu->env, ARM_FEATURE_XSCALE);
cpu->midr = ARM_CPUID_PXA255;
+ arm_cpu_postconfig_init(cpu);
}
static void pxa260_initfn(Object *obj)
{
ARMCPU *cpu = ARM_CPU(obj);
+ set_feature(&cpu->env, ARM_FEATURE_V5);
+ set_feature(&cpu->env, ARM_FEATURE_XSCALE);
cpu->midr = ARM_CPUID_PXA260;
+ arm_cpu_postconfig_init(cpu);
}
static void pxa261_initfn(Object *obj)
{
ARMCPU *cpu = ARM_CPU(obj);
+ set_feature(&cpu->env, ARM_FEATURE_V5);
+ set_feature(&cpu->env, ARM_FEATURE_XSCALE);
cpu->midr = ARM_CPUID_PXA261;
+ arm_cpu_postconfig_init(cpu);
}
static void pxa262_initfn(Object *obj)
{
ARMCPU *cpu = ARM_CPU(obj);
+ set_feature(&cpu->env, ARM_FEATURE_V5);
+ set_feature(&cpu->env, ARM_FEATURE_XSCALE);
cpu->midr = ARM_CPUID_PXA262;
+ arm_cpu_postconfig_init(cpu);
}
static void pxa270a0_initfn(Object *obj)
{
ARMCPU *cpu = ARM_CPU(obj);
+ set_feature(&cpu->env, ARM_FEATURE_V5);
+ set_feature(&cpu->env, ARM_FEATURE_XSCALE);
+ set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
cpu->midr = ARM_CPUID_PXA270_A0;
+ arm_cpu_postconfig_init(cpu);
}
static void pxa270a1_initfn(Object *obj)
{
ARMCPU *cpu = ARM_CPU(obj);
+ set_feature(&cpu->env, ARM_FEATURE_V5);
+ set_feature(&cpu->env, ARM_FEATURE_XSCALE);
+ set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
cpu->midr = ARM_CPUID_PXA270_A1;
+ arm_cpu_postconfig_init(cpu);
}
static void pxa270b0_initfn(Object *obj)
{
ARMCPU *cpu = ARM_CPU(obj);
+ set_feature(&cpu->env, ARM_FEATURE_V5);
+ set_feature(&cpu->env, ARM_FEATURE_XSCALE);
+ set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
cpu->midr = ARM_CPUID_PXA270_B0;
+ arm_cpu_postconfig_init(cpu);
}
static void pxa270b1_initfn(Object *obj)
{
ARMCPU *cpu = ARM_CPU(obj);
+ set_feature(&cpu->env, ARM_FEATURE_V5);
+ set_feature(&cpu->env, ARM_FEATURE_XSCALE);
+ set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
cpu->midr = ARM_CPUID_PXA270_B1;
+ arm_cpu_postconfig_init(cpu);
}
static void pxa270c0_initfn(Object *obj)
{
ARMCPU *cpu = ARM_CPU(obj);
+ set_feature(&cpu->env, ARM_FEATURE_V5);
+ set_feature(&cpu->env, ARM_FEATURE_XSCALE);
+ set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
cpu->midr = ARM_CPUID_PXA270_C0;
+ arm_cpu_postconfig_init(cpu);
}
static void pxa270c5_initfn(Object *obj)
{
ARMCPU *cpu = ARM_CPU(obj);
+ set_feature(&cpu->env, ARM_FEATURE_V7);
+ set_feature(&cpu->env, ARM_FEATURE_VFP4);
+ set_feature(&cpu->env, ARM_FEATURE_VFP_FP16);
+ set_feature(&cpu->env, ARM_FEATURE_NEON);
+ set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
+ set_feature(&cpu->env, ARM_FEATURE_ARM_DIV);
+ set_feature(&cpu->env, ARM_FEATURE_V7MP);
cpu->midr = ARM_CPUID_PXA270_C5;
+ arm_cpu_postconfig_init(cpu);
}
static void arm_any_initfn(Object *obj)
{
ARMCPU *cpu = ARM_CPU(obj);
cpu->midr = ARM_CPUID_ANY;
+ arm_cpu_postconfig_init(cpu);
}
typedef struct ARMCPUInfo {
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index e176c5f..85246dd 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -170,9 +170,6 @@ typedef struct CPUARMState {
uint32_t teecr;
uint32_t teehbr;
- /* Internal CPU feature flags. */
- uint32_t features;
-
/* VFP coprocessor state. */
struct {
float64 regs[32];
@@ -225,6 +222,9 @@ typedef struct CPUARMState {
/* These fields after the common ones so they are preserved on reset. */
+ /* Internal CPU feature flags. */
+ uint32_t features;
+
/* Coprocessor IO used by peripherals */
struct {
ARMReadCPFunc *cp_read;
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 4748f80..af752e4 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -47,46 +47,30 @@ static uint32_t arm1176_cp15_c0_c1[8] =
static uint32_t arm1176_cp15_c0_c2[8] =
{ 0x0140011, 0x12002111, 0x11231121, 0x01102131, 0x01141, 0, 0, 0 };
-static inline void set_feature(CPUARMState *env, int feature)
-{
- env->features |= 1u << feature;
-}
-
static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
{
switch (id) {
case ARM_CPUID_ARM926:
- set_feature(env, ARM_FEATURE_V5);
- set_feature(env, ARM_FEATURE_VFP);
env->vfp.xregs[ARM_VFP_FPSID] = 0x41011090;
env->cp15.c0_cachetype = 0x1dd20d2;
env->cp15.c1_sys = 0x00090078;
break;
case ARM_CPUID_ARM946:
- set_feature(env, ARM_FEATURE_V5);
- set_feature(env, ARM_FEATURE_MPU);
env->cp15.c0_cachetype = 0x0f004006;
env->cp15.c1_sys = 0x00000078;
break;
case ARM_CPUID_ARM1026:
- set_feature(env, ARM_FEATURE_V5);
- set_feature(env, ARM_FEATURE_VFP);
- set_feature(env, ARM_FEATURE_AUXCR);
env->vfp.xregs[ARM_VFP_FPSID] = 0x410110a0;
env->cp15.c0_cachetype = 0x1dd20d2;
env->cp15.c1_sys = 0x00090078;
break;
case ARM_CPUID_ARM1136:
/* This is the 1136 r1, which is a v6K core */
- set_feature(env, ARM_FEATURE_V6K);
- /* Fall through */
case ARM_CPUID_ARM1136_R2:
/* What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an
* older core than plain "arm1136". In particular this does not
* have the v6K features.
*/
- set_feature(env, ARM_FEATURE_V6);
- set_feature(env, ARM_FEATURE_VFP);
/* These ID register values are correct for 1136 but may be wrong
* for 1136_r2 (in particular r0p2 does not actually implement most
* of the ID registers).
@@ -100,9 +84,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
env->cp15.c1_sys = 0x00050078;
break;
case ARM_CPUID_ARM1176:
- set_feature(env, ARM_FEATURE_V6K);
- set_feature(env, ARM_FEATURE_VFP);
- set_feature(env, ARM_FEATURE_VAPA);
env->vfp.xregs[ARM_VFP_FPSID] = 0x410120b5;
env->vfp.xregs[ARM_VFP_MVFR0] = 0x11111111;
env->vfp.xregs[ARM_VFP_MVFR1] = 0x00000000;
@@ -112,9 +93,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
env->cp15.c1_sys = 0x00050078;
break;
case ARM_CPUID_ARM11MPCORE:
- set_feature(env, ARM_FEATURE_V6K);
- set_feature(env, ARM_FEATURE_VFP);
- set_feature(env, ARM_FEATURE_VAPA);
env->vfp.xregs[ARM_VFP_FPSID] = 0x410120b4;
env->vfp.xregs[ARM_VFP_MVFR0] = 0x11111111;
env->vfp.xregs[ARM_VFP_MVFR1] = 0x00000000;
@@ -123,10 +101,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
env->cp15.c0_cachetype = 0x1dd20d2;
break;
case ARM_CPUID_CORTEXA8:
- set_feature(env, ARM_FEATURE_V7);
- set_feature(env, ARM_FEATURE_VFP3);
- set_feature(env, ARM_FEATURE_NEON);
- set_feature(env, ARM_FEATURE_THUMB2EE);
env->vfp.xregs[ARM_VFP_FPSID] = 0x410330c0;
env->vfp.xregs[ARM_VFP_MVFR0] = 0x11110222;
env->vfp.xregs[ARM_VFP_MVFR1] = 0x00011100;
@@ -140,16 +114,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
env->cp15.c1_sys = 0x00c50078;
break;
case ARM_CPUID_CORTEXA9:
- set_feature(env, ARM_FEATURE_V7);
- set_feature(env, ARM_FEATURE_VFP3);
- set_feature(env, ARM_FEATURE_VFP_FP16);
- set_feature(env, ARM_FEATURE_NEON);
- set_feature(env, ARM_FEATURE_THUMB2EE);
- /* Note that A9 supports the MP extensions even for
- * A9UP and single-core A9MP (which are both different
- * and valid configurations; we don't model A9UP).
- */
- set_feature(env, ARM_FEATURE_V7MP);
env->vfp.xregs[ARM_VFP_FPSID] = 0x41033090;
env->vfp.xregs[ARM_VFP_MVFR0] = 0x11110222;
env->vfp.xregs[ARM_VFP_MVFR1] = 0x01111111;
@@ -162,14 +126,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
env->cp15.c1_sys = 0x00c50078;
break;
case ARM_CPUID_CORTEXA15:
- set_feature(env, ARM_FEATURE_V7);
- set_feature(env, ARM_FEATURE_VFP4);
- set_feature(env, ARM_FEATURE_VFP_FP16);
- set_feature(env, ARM_FEATURE_NEON);
- set_feature(env, ARM_FEATURE_THUMB2EE);
- set_feature(env, ARM_FEATURE_ARM_DIV);
- set_feature(env, ARM_FEATURE_V7MP);
- set_feature(env, ARM_FEATURE_GENERIC_TIMER);
env->vfp.xregs[ARM_VFP_FPSID] = 0x410430f0;
env->vfp.xregs[ARM_VFP_MVFR0] = 0x10110222;
env->vfp.xregs[ARM_VFP_MVFR1] = 0x11111111;
@@ -183,22 +139,11 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
env->cp15.c1_sys = 0x00c50078;
break;
case ARM_CPUID_CORTEXM3:
- set_feature(env, ARM_FEATURE_V7);
- set_feature(env, ARM_FEATURE_M);
break;
case ARM_CPUID_ANY: /* For userspace emulation. */
- set_feature(env, ARM_FEATURE_V7);
- set_feature(env, ARM_FEATURE_VFP4);
- set_feature(env, ARM_FEATURE_VFP_FP16);
- set_feature(env, ARM_FEATURE_NEON);
- set_feature(env, ARM_FEATURE_THUMB2EE);
- set_feature(env, ARM_FEATURE_ARM_DIV);
- set_feature(env, ARM_FEATURE_V7MP);
break;
case ARM_CPUID_TI915T:
case ARM_CPUID_TI925T:
- set_feature(env, ARM_FEATURE_V4T);
- set_feature(env, ARM_FEATURE_OMAPCP);
env->cp15.c0_cachetype = 0x5109149;
env->cp15.c1_sys = 0x00000070;
env->cp15.c15_i_max = 0x000;
@@ -209,8 +154,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
case ARM_CPUID_PXA260:
case ARM_CPUID_PXA261:
case ARM_CPUID_PXA262:
- set_feature(env, ARM_FEATURE_V5);
- set_feature(env, ARM_FEATURE_XSCALE);
/* JTAG_ID is ((id << 28) | 0x09265013) */
env->cp15.c0_cachetype = 0xd172172;
env->cp15.c1_sys = 0x00000078;
@@ -221,17 +164,13 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
case ARM_CPUID_PXA270_B1:
case ARM_CPUID_PXA270_C0:
case ARM_CPUID_PXA270_C5:
- set_feature(env, ARM_FEATURE_V5);
- set_feature(env, ARM_FEATURE_XSCALE);
/* JTAG_ID is ((id << 28) | 0x09265013) */
- set_feature(env, ARM_FEATURE_IWMMXT);
env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q';
env->cp15.c0_cachetype = 0xd172172;
env->cp15.c1_sys = 0x00000078;
break;
case ARM_CPUID_SA1100:
case ARM_CPUID_SA1110:
- set_feature(env, ARM_FEATURE_STRONGARM);
env->cp15.c1_sys = 0x00000070;
break;
default:
@@ -239,41 +178,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
break;
}
- /* Some features automatically imply others: */
- if (arm_feature(env, ARM_FEATURE_V7)) {
- set_feature(env, ARM_FEATURE_VAPA);
- set_feature(env, ARM_FEATURE_THUMB2);
- if (!arm_feature(env, ARM_FEATURE_M)) {
- set_feature(env, ARM_FEATURE_V6K);
- } else {
- set_feature(env, ARM_FEATURE_V6);
- }
- }
- if (arm_feature(env, ARM_FEATURE_V6K)) {
- set_feature(env, ARM_FEATURE_V6);
- set_feature(env, ARM_FEATURE_MVFR);
- }
- if (arm_feature(env, ARM_FEATURE_V6)) {
- set_feature(env, ARM_FEATURE_V5);
- if (!arm_feature(env, ARM_FEATURE_M)) {
- set_feature(env, ARM_FEATURE_AUXCR);
- }
- }
- if (arm_feature(env, ARM_FEATURE_V5)) {
- set_feature(env, ARM_FEATURE_V4T);
- }
- if (arm_feature(env, ARM_FEATURE_M)) {
- set_feature(env, ARM_FEATURE_THUMB_DIV);
- }
- if (arm_feature(env, ARM_FEATURE_ARM_DIV)) {
- set_feature(env, ARM_FEATURE_THUMB_DIV);
- }
- if (arm_feature(env, ARM_FEATURE_VFP4)) {
- set_feature(env, ARM_FEATURE_VFP3);
- }
- if (arm_feature(env, ARM_FEATURE_VFP3)) {
- set_feature(env, ARM_FEATURE_VFP);
- }
}
/* TODO Move contents into arm_cpu_reset() in cpu.c,
--
1.7.1
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [Qemu-devel] [PATCH 03/14] target-arm: Move FPSID config to cpu init fns
2012-03-30 12:51 [Qemu-devel] [PATCH 00/14] target-arm: Create QOM subclass per CPU implementation Peter Maydell
2012-03-30 12:51 ` [Qemu-devel] [PATCH 01/14] target-arm: Add QOM subclasses for each ARM cpu implementation Peter Maydell
2012-03-30 12:51 ` [Qemu-devel] [PATCH 02/14] target-arm: Move feature bit settings to CPU init fns Peter Maydell
@ 2012-03-30 12:51 ` Peter Maydell
2012-03-30 12:51 ` [Qemu-devel] [PATCH 04/14] target-arm: Move MVFR* setup to per " Peter Maydell
` (10 subsequent siblings)
13 siblings, 0 replies; 17+ messages in thread
From: Peter Maydell @ 2012-03-30 12:51 UTC (permalink / raw)
To: qemu-devel; +Cc: Paul Brook, Anthony Liguori, Andreas Färber
Move the reset FPSID to the ARMCPU struct, and set it in the
per-implementation instance init function. At reset we then
just copy the reset value into the CPUARMState field.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target-arm/cpu-qom.h | 1 +
target-arm/cpu.c | 9 +++++++++
target-arm/helper.c | 10 ++--------
3 files changed, 12 insertions(+), 8 deletions(-)
diff --git a/target-arm/cpu-qom.h b/target-arm/cpu-qom.h
index 1a3965f..a842917 100644
--- a/target-arm/cpu-qom.h
+++ b/target-arm/cpu-qom.h
@@ -63,6 +63,7 @@ typedef struct ARMCPU {
* some of these might become properties eventually.
*/
uint32_t midr;
+ uint32_t reset_fpsid;
} ARMCPU;
static inline ARMCPU *arm_env_get_cpu(CPUARMState *env)
diff --git a/target-arm/cpu.c b/target-arm/cpu.c
index 0dad352..2b881ac 100644
--- a/target-arm/cpu.c
+++ b/target-arm/cpu.c
@@ -103,6 +103,7 @@ static void arm926_initfn(Object *obj)
set_feature(&cpu->env, ARM_FEATURE_V5);
set_feature(&cpu->env, ARM_FEATURE_VFP);
cpu->midr = ARM_CPUID_ARM926;
+ cpu->reset_fpsid = 0x41011090;
arm_cpu_postconfig_init(cpu);
}
@@ -122,6 +123,7 @@ static void arm1026_initfn(Object *obj)
set_feature(&cpu->env, ARM_FEATURE_VFP);
set_feature(&cpu->env, ARM_FEATURE_AUXCR);
cpu->midr = ARM_CPUID_ARM1026;
+ cpu->reset_fpsid = 0x410110a0;
arm_cpu_postconfig_init(cpu);
}
@@ -131,6 +133,7 @@ static void arm1136_r2_initfn(Object *obj)
set_feature(&cpu->env, ARM_FEATURE_V6);
set_feature(&cpu->env, ARM_FEATURE_VFP);
cpu->midr = ARM_CPUID_ARM1136_R2;
+ cpu->reset_fpsid = 0x410120b4;
arm_cpu_postconfig_init(cpu);
}
@@ -141,6 +144,7 @@ static void arm1136_initfn(Object *obj)
set_feature(&cpu->env, ARM_FEATURE_V6);
set_feature(&cpu->env, ARM_FEATURE_VFP);
cpu->midr = ARM_CPUID_ARM1136;
+ cpu->reset_fpsid = 0x410120b4;
arm_cpu_postconfig_init(cpu);
}
@@ -151,6 +155,7 @@ static void arm1176_initfn(Object *obj)
set_feature(&cpu->env, ARM_FEATURE_VFP);
set_feature(&cpu->env, ARM_FEATURE_VAPA);
cpu->midr = ARM_CPUID_ARM1176;
+ cpu->reset_fpsid = 0x410120b5;
arm_cpu_postconfig_init(cpu);
}
@@ -161,6 +166,7 @@ static void arm11mpcore_initfn(Object *obj)
set_feature(&cpu->env, ARM_FEATURE_VFP);
set_feature(&cpu->env, ARM_FEATURE_VAPA);
cpu->midr = ARM_CPUID_ARM11MPCORE;
+ cpu->reset_fpsid = 0x410120b4;
arm_cpu_postconfig_init(cpu);
}
@@ -181,6 +187,7 @@ static void cortex_a8_initfn(Object *obj)
set_feature(&cpu->env, ARM_FEATURE_NEON);
set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
cpu->midr = ARM_CPUID_CORTEXA8;
+ cpu->reset_fpsid = 0x410330c0;
arm_cpu_postconfig_init(cpu);
}
@@ -198,6 +205,7 @@ static void cortex_a9_initfn(Object *obj)
*/
set_feature(&cpu->env, ARM_FEATURE_V7MP);
cpu->midr = ARM_CPUID_CORTEXA9;
+ cpu->reset_fpsid = 0x41033090;
arm_cpu_postconfig_init(cpu);
}
@@ -213,6 +221,7 @@ static void cortex_a15_initfn(Object *obj)
set_feature(&cpu->env, ARM_FEATURE_V7MP);
set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
cpu->midr = ARM_CPUID_CORTEXA15;
+ cpu->reset_fpsid = 0x410430f0;
arm_cpu_postconfig_init(cpu);
}
diff --git a/target-arm/helper.c b/target-arm/helper.c
index af752e4..c7cde4f 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -51,7 +51,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
{
switch (id) {
case ARM_CPUID_ARM926:
- env->vfp.xregs[ARM_VFP_FPSID] = 0x41011090;
env->cp15.c0_cachetype = 0x1dd20d2;
env->cp15.c1_sys = 0x00090078;
break;
@@ -60,7 +59,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
env->cp15.c1_sys = 0x00000078;
break;
case ARM_CPUID_ARM1026:
- env->vfp.xregs[ARM_VFP_FPSID] = 0x410110a0;
env->cp15.c0_cachetype = 0x1dd20d2;
env->cp15.c1_sys = 0x00090078;
break;
@@ -75,7 +73,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
* for 1136_r2 (in particular r0p2 does not actually implement most
* of the ID registers).
*/
- env->vfp.xregs[ARM_VFP_FPSID] = 0x410120b4;
env->vfp.xregs[ARM_VFP_MVFR0] = 0x11111111;
env->vfp.xregs[ARM_VFP_MVFR1] = 0x00000000;
memcpy(env->cp15.c0_c1, arm1136_cp15_c0_c1, 8 * sizeof(uint32_t));
@@ -84,7 +81,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
env->cp15.c1_sys = 0x00050078;
break;
case ARM_CPUID_ARM1176:
- env->vfp.xregs[ARM_VFP_FPSID] = 0x410120b5;
env->vfp.xregs[ARM_VFP_MVFR0] = 0x11111111;
env->vfp.xregs[ARM_VFP_MVFR1] = 0x00000000;
memcpy(env->cp15.c0_c1, arm1176_cp15_c0_c1, 8 * sizeof(uint32_t));
@@ -93,7 +89,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
env->cp15.c1_sys = 0x00050078;
break;
case ARM_CPUID_ARM11MPCORE:
- env->vfp.xregs[ARM_VFP_FPSID] = 0x410120b4;
env->vfp.xregs[ARM_VFP_MVFR0] = 0x11111111;
env->vfp.xregs[ARM_VFP_MVFR1] = 0x00000000;
memcpy(env->cp15.c0_c1, mpcore_cp15_c0_c1, 8 * sizeof(uint32_t));
@@ -101,7 +96,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
env->cp15.c0_cachetype = 0x1dd20d2;
break;
case ARM_CPUID_CORTEXA8:
- env->vfp.xregs[ARM_VFP_FPSID] = 0x410330c0;
env->vfp.xregs[ARM_VFP_MVFR0] = 0x11110222;
env->vfp.xregs[ARM_VFP_MVFR1] = 0x00011100;
memcpy(env->cp15.c0_c1, cortexa8_cp15_c0_c1, 8 * sizeof(uint32_t));
@@ -114,7 +108,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
env->cp15.c1_sys = 0x00c50078;
break;
case ARM_CPUID_CORTEXA9:
- env->vfp.xregs[ARM_VFP_FPSID] = 0x41033090;
env->vfp.xregs[ARM_VFP_MVFR0] = 0x11110222;
env->vfp.xregs[ARM_VFP_MVFR1] = 0x01111111;
memcpy(env->cp15.c0_c1, cortexa9_cp15_c0_c1, 8 * sizeof(uint32_t));
@@ -126,7 +119,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
env->cp15.c1_sys = 0x00c50078;
break;
case ARM_CPUID_CORTEXA15:
- env->vfp.xregs[ARM_VFP_FPSID] = 0x410430f0;
env->vfp.xregs[ARM_VFP_MVFR0] = 0x10110222;
env->vfp.xregs[ARM_VFP_MVFR1] = 0x11111111;
memcpy(env->cp15.c0_c1, cortexa15_cp15_c0_c1, 8 * sizeof(uint32_t));
@@ -202,6 +194,8 @@ void cpu_state_reset(CPUARMState *env)
cpu_reset_model_id(env, id);
env->cp15.c15_config_base_address = tmp;
env->cp15.c0_cpuid = cpu->midr;
+ env->vfp.xregs[ARM_VFP_FPSID] = cpu->reset_fpsid;
+
#if defined (CONFIG_USER_ONLY)
env->uncached_cpsr = ARM_CPU_MODE_USR;
/* For user mode we must enable access to coprocessors */
--
1.7.1
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [Qemu-devel] [PATCH 04/14] target-arm: Move MVFR* setup to per cpu init fns
2012-03-30 12:51 [Qemu-devel] [PATCH 00/14] target-arm: Create QOM subclass per CPU implementation Peter Maydell
` (2 preceding siblings ...)
2012-03-30 12:51 ` [Qemu-devel] [PATCH 03/14] target-arm: Move FPSID config to cpu " Peter Maydell
@ 2012-03-30 12:51 ` Peter Maydell
2012-03-30 12:51 ` [Qemu-devel] [PATCH 05/14] target-arm: Move CTR " Peter Maydell
` (9 subsequent siblings)
13 siblings, 0 replies; 17+ messages in thread
From: Peter Maydell @ 2012-03-30 12:51 UTC (permalink / raw)
To: qemu-devel; +Cc: Paul Brook, Anthony Liguori, Andreas Färber
Move the MVFR* VFP feature register values to ARMCPU,
so they are set up by the implementation-specific instance
init functions rather than in cpu_reset_model_id().
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target-arm/cpu-qom.h | 2 ++
target-arm/cpu.c | 14 ++++++++++++++
target-arm/helper.c | 14 ++------------
3 files changed, 18 insertions(+), 12 deletions(-)
diff --git a/target-arm/cpu-qom.h b/target-arm/cpu-qom.h
index a842917..e63ff76 100644
--- a/target-arm/cpu-qom.h
+++ b/target-arm/cpu-qom.h
@@ -64,6 +64,8 @@ typedef struct ARMCPU {
*/
uint32_t midr;
uint32_t reset_fpsid;
+ uint32_t mvfr0;
+ uint32_t mvfr1;
} ARMCPU;
static inline ARMCPU *arm_env_get_cpu(CPUARMState *env)
diff --git a/target-arm/cpu.c b/target-arm/cpu.c
index 2b881ac..444ba77 100644
--- a/target-arm/cpu.c
+++ b/target-arm/cpu.c
@@ -134,6 +134,8 @@ static void arm1136_r2_initfn(Object *obj)
set_feature(&cpu->env, ARM_FEATURE_VFP);
cpu->midr = ARM_CPUID_ARM1136_R2;
cpu->reset_fpsid = 0x410120b4;
+ cpu->mvfr0 = 0x11111111;
+ cpu->mvfr1 = 0x00000000;
arm_cpu_postconfig_init(cpu);
}
@@ -145,6 +147,8 @@ static void arm1136_initfn(Object *obj)
set_feature(&cpu->env, ARM_FEATURE_VFP);
cpu->midr = ARM_CPUID_ARM1136;
cpu->reset_fpsid = 0x410120b4;
+ cpu->mvfr0 = 0x11111111;
+ cpu->mvfr1 = 0x00000000;
arm_cpu_postconfig_init(cpu);
}
@@ -156,6 +160,8 @@ static void arm1176_initfn(Object *obj)
set_feature(&cpu->env, ARM_FEATURE_VAPA);
cpu->midr = ARM_CPUID_ARM1176;
cpu->reset_fpsid = 0x410120b5;
+ cpu->mvfr0 = 0x11111111;
+ cpu->mvfr1 = 0x00000000;
arm_cpu_postconfig_init(cpu);
}
@@ -167,6 +173,8 @@ static void arm11mpcore_initfn(Object *obj)
set_feature(&cpu->env, ARM_FEATURE_VAPA);
cpu->midr = ARM_CPUID_ARM11MPCORE;
cpu->reset_fpsid = 0x410120b4;
+ cpu->mvfr0 = 0x11111111;
+ cpu->mvfr1 = 0x00000000;
arm_cpu_postconfig_init(cpu);
}
@@ -188,6 +196,8 @@ static void cortex_a8_initfn(Object *obj)
set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
cpu->midr = ARM_CPUID_CORTEXA8;
cpu->reset_fpsid = 0x410330c0;
+ cpu->mvfr0 = 0x11110222;
+ cpu->mvfr1 = 0x00011100;
arm_cpu_postconfig_init(cpu);
}
@@ -206,6 +216,8 @@ static void cortex_a9_initfn(Object *obj)
set_feature(&cpu->env, ARM_FEATURE_V7MP);
cpu->midr = ARM_CPUID_CORTEXA9;
cpu->reset_fpsid = 0x41033090;
+ cpu->mvfr0 = 0x11110222;
+ cpu->mvfr1 = 0x01111111;
arm_cpu_postconfig_init(cpu);
}
@@ -222,6 +234,8 @@ static void cortex_a15_initfn(Object *obj)
set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
cpu->midr = ARM_CPUID_CORTEXA15;
cpu->reset_fpsid = 0x410430f0;
+ cpu->mvfr0 = 0x10110222;
+ cpu->mvfr1 = 0x11111111;
arm_cpu_postconfig_init(cpu);
}
diff --git a/target-arm/helper.c b/target-arm/helper.c
index c7cde4f..aeffd6b 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -73,31 +73,23 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
* for 1136_r2 (in particular r0p2 does not actually implement most
* of the ID registers).
*/
- env->vfp.xregs[ARM_VFP_MVFR0] = 0x11111111;
- env->vfp.xregs[ARM_VFP_MVFR1] = 0x00000000;
memcpy(env->cp15.c0_c1, arm1136_cp15_c0_c1, 8 * sizeof(uint32_t));
memcpy(env->cp15.c0_c2, arm1136_cp15_c0_c2, 8 * sizeof(uint32_t));
env->cp15.c0_cachetype = 0x1dd20d2;
env->cp15.c1_sys = 0x00050078;
break;
case ARM_CPUID_ARM1176:
- env->vfp.xregs[ARM_VFP_MVFR0] = 0x11111111;
- env->vfp.xregs[ARM_VFP_MVFR1] = 0x00000000;
memcpy(env->cp15.c0_c1, arm1176_cp15_c0_c1, 8 * sizeof(uint32_t));
memcpy(env->cp15.c0_c2, arm1176_cp15_c0_c2, 8 * sizeof(uint32_t));
env->cp15.c0_cachetype = 0x1dd20d2;
env->cp15.c1_sys = 0x00050078;
break;
case ARM_CPUID_ARM11MPCORE:
- env->vfp.xregs[ARM_VFP_MVFR0] = 0x11111111;
- env->vfp.xregs[ARM_VFP_MVFR1] = 0x00000000;
memcpy(env->cp15.c0_c1, mpcore_cp15_c0_c1, 8 * sizeof(uint32_t));
memcpy(env->cp15.c0_c2, mpcore_cp15_c0_c2, 8 * sizeof(uint32_t));
env->cp15.c0_cachetype = 0x1dd20d2;
break;
case ARM_CPUID_CORTEXA8:
- env->vfp.xregs[ARM_VFP_MVFR0] = 0x11110222;
- env->vfp.xregs[ARM_VFP_MVFR1] = 0x00011100;
memcpy(env->cp15.c0_c1, cortexa8_cp15_c0_c1, 8 * sizeof(uint32_t));
memcpy(env->cp15.c0_c2, cortexa8_cp15_c0_c2, 8 * sizeof(uint32_t));
env->cp15.c0_cachetype = 0x82048004;
@@ -108,8 +100,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
env->cp15.c1_sys = 0x00c50078;
break;
case ARM_CPUID_CORTEXA9:
- env->vfp.xregs[ARM_VFP_MVFR0] = 0x11110222;
- env->vfp.xregs[ARM_VFP_MVFR1] = 0x01111111;
memcpy(env->cp15.c0_c1, cortexa9_cp15_c0_c1, 8 * sizeof(uint32_t));
memcpy(env->cp15.c0_c2, cortexa9_cp15_c0_c2, 8 * sizeof(uint32_t));
env->cp15.c0_cachetype = 0x80038003;
@@ -119,8 +109,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
env->cp15.c1_sys = 0x00c50078;
break;
case ARM_CPUID_CORTEXA15:
- env->vfp.xregs[ARM_VFP_MVFR0] = 0x10110222;
- env->vfp.xregs[ARM_VFP_MVFR1] = 0x11111111;
memcpy(env->cp15.c0_c1, cortexa15_cp15_c0_c1, 8 * sizeof(uint32_t));
memcpy(env->cp15.c0_c2, cortexa15_cp15_c0_c2, 8 * sizeof(uint32_t));
env->cp15.c0_cachetype = 0x8444c004;
@@ -195,6 +183,8 @@ void cpu_state_reset(CPUARMState *env)
env->cp15.c15_config_base_address = tmp;
env->cp15.c0_cpuid = cpu->midr;
env->vfp.xregs[ARM_VFP_FPSID] = cpu->reset_fpsid;
+ env->vfp.xregs[ARM_VFP_MVFR0] = cpu->mvfr0;
+ env->vfp.xregs[ARM_VFP_MVFR1] = cpu->mvfr1;
#if defined (CONFIG_USER_ONLY)
env->uncached_cpsr = ARM_CPU_MODE_USR;
--
1.7.1
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [Qemu-devel] [PATCH 05/14] target-arm: Move CTR setup to per cpu init fns
2012-03-30 12:51 [Qemu-devel] [PATCH 00/14] target-arm: Create QOM subclass per CPU implementation Peter Maydell
` (3 preceding siblings ...)
2012-03-30 12:51 ` [Qemu-devel] [PATCH 04/14] target-arm: Move MVFR* setup to per " Peter Maydell
@ 2012-03-30 12:51 ` Peter Maydell
2012-03-30 12:51 ` [Qemu-devel] [PATCH 06/14] target-arm: Move SCTLR reset value " Peter Maydell
` (8 subsequent siblings)
13 siblings, 0 replies; 17+ messages in thread
From: Peter Maydell @ 2012-03-30 12:51 UTC (permalink / raw)
To: qemu-devel; +Cc: Paul Brook, Anthony Liguori, Andreas Färber
Move CTR (cache type register) value to an ARMCPU field
set up by per-cpu init fns.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target-arm/cpu-qom.h | 1 +
target-arm/cpu.c | 22 ++++++++++++++++++++++
target-arm/helper.c | 13 +------------
3 files changed, 24 insertions(+), 12 deletions(-)
diff --git a/target-arm/cpu-qom.h b/target-arm/cpu-qom.h
index e63ff76..fc147c4 100644
--- a/target-arm/cpu-qom.h
+++ b/target-arm/cpu-qom.h
@@ -66,6 +66,7 @@ typedef struct ARMCPU {
uint32_t reset_fpsid;
uint32_t mvfr0;
uint32_t mvfr1;
+ uint32_t ctr;
} ARMCPU;
static inline ARMCPU *arm_env_get_cpu(CPUARMState *env)
diff --git a/target-arm/cpu.c b/target-arm/cpu.c
index 444ba77..115561c 100644
--- a/target-arm/cpu.c
+++ b/target-arm/cpu.c
@@ -104,6 +104,7 @@ static void arm926_initfn(Object *obj)
set_feature(&cpu->env, ARM_FEATURE_VFP);
cpu->midr = ARM_CPUID_ARM926;
cpu->reset_fpsid = 0x41011090;
+ cpu->ctr = 0x1dd20d2;
arm_cpu_postconfig_init(cpu);
}
@@ -113,6 +114,7 @@ static void arm946_initfn(Object *obj)
set_feature(&cpu->env, ARM_FEATURE_V5);
set_feature(&cpu->env, ARM_FEATURE_MPU);
cpu->midr = ARM_CPUID_ARM946;
+ cpu->ctr = 0x0f004006;
arm_cpu_postconfig_init(cpu);
}
@@ -124,6 +126,7 @@ static void arm1026_initfn(Object *obj)
set_feature(&cpu->env, ARM_FEATURE_AUXCR);
cpu->midr = ARM_CPUID_ARM1026;
cpu->reset_fpsid = 0x410110a0;
+ cpu->ctr = 0x1dd20d2;
arm_cpu_postconfig_init(cpu);
}
@@ -136,6 +139,7 @@ static void arm1136_r2_initfn(Object *obj)
cpu->reset_fpsid = 0x410120b4;
cpu->mvfr0 = 0x11111111;
cpu->mvfr1 = 0x00000000;
+ cpu->ctr = 0x1dd20d2;
arm_cpu_postconfig_init(cpu);
}
@@ -149,6 +153,7 @@ static void arm1136_initfn(Object *obj)
cpu->reset_fpsid = 0x410120b4;
cpu->mvfr0 = 0x11111111;
cpu->mvfr1 = 0x00000000;
+ cpu->ctr = 0x1dd20d2;
arm_cpu_postconfig_init(cpu);
}
@@ -162,6 +167,7 @@ static void arm1176_initfn(Object *obj)
cpu->reset_fpsid = 0x410120b5;
cpu->mvfr0 = 0x11111111;
cpu->mvfr1 = 0x00000000;
+ cpu->ctr = 0x1dd20d2;
arm_cpu_postconfig_init(cpu);
}
@@ -175,6 +181,7 @@ static void arm11mpcore_initfn(Object *obj)
cpu->reset_fpsid = 0x410120b4;
cpu->mvfr0 = 0x11111111;
cpu->mvfr1 = 0x00000000;
+ cpu->ctr = 0x1dd20d2;
arm_cpu_postconfig_init(cpu);
}
@@ -198,6 +205,7 @@ static void cortex_a8_initfn(Object *obj)
cpu->reset_fpsid = 0x410330c0;
cpu->mvfr0 = 0x11110222;
cpu->mvfr1 = 0x00011100;
+ cpu->ctr = 0x82048004;
arm_cpu_postconfig_init(cpu);
}
@@ -218,6 +226,7 @@ static void cortex_a9_initfn(Object *obj)
cpu->reset_fpsid = 0x41033090;
cpu->mvfr0 = 0x11110222;
cpu->mvfr1 = 0x01111111;
+ cpu->ctr = 0x80038003;
arm_cpu_postconfig_init(cpu);
}
@@ -236,6 +245,7 @@ static void cortex_a15_initfn(Object *obj)
cpu->reset_fpsid = 0x410430f0;
cpu->mvfr0 = 0x10110222;
cpu->mvfr1 = 0x11111111;
+ cpu->ctr = 0x8444c004;
arm_cpu_postconfig_init(cpu);
}
@@ -245,6 +255,7 @@ static void ti925t_initfn(Object *obj)
set_feature(&cpu->env, ARM_FEATURE_V4T);
set_feature(&cpu->env, ARM_FEATURE_OMAPCP);
cpu->midr = ARM_CPUID_TI925T;
+ cpu->ctr = 0x5109149;
arm_cpu_postconfig_init(cpu);
}
@@ -270,6 +281,7 @@ static void pxa250_initfn(Object *obj)
set_feature(&cpu->env, ARM_FEATURE_V5);
set_feature(&cpu->env, ARM_FEATURE_XSCALE);
cpu->midr = ARM_CPUID_PXA250;
+ cpu->ctr = 0xd172172;
arm_cpu_postconfig_init(cpu);
}
@@ -279,6 +291,7 @@ static void pxa255_initfn(Object *obj)
set_feature(&cpu->env, ARM_FEATURE_V5);
set_feature(&cpu->env, ARM_FEATURE_XSCALE);
cpu->midr = ARM_CPUID_PXA255;
+ cpu->ctr = 0xd172172;
arm_cpu_postconfig_init(cpu);
}
@@ -288,6 +301,7 @@ static void pxa260_initfn(Object *obj)
set_feature(&cpu->env, ARM_FEATURE_V5);
set_feature(&cpu->env, ARM_FEATURE_XSCALE);
cpu->midr = ARM_CPUID_PXA260;
+ cpu->ctr = 0xd172172;
arm_cpu_postconfig_init(cpu);
}
@@ -297,6 +311,7 @@ static void pxa261_initfn(Object *obj)
set_feature(&cpu->env, ARM_FEATURE_V5);
set_feature(&cpu->env, ARM_FEATURE_XSCALE);
cpu->midr = ARM_CPUID_PXA261;
+ cpu->ctr = 0xd172172;
arm_cpu_postconfig_init(cpu);
}
@@ -306,6 +321,7 @@ static void pxa262_initfn(Object *obj)
set_feature(&cpu->env, ARM_FEATURE_V5);
set_feature(&cpu->env, ARM_FEATURE_XSCALE);
cpu->midr = ARM_CPUID_PXA262;
+ cpu->ctr = 0xd172172;
arm_cpu_postconfig_init(cpu);
}
@@ -316,6 +332,7 @@ static void pxa270a0_initfn(Object *obj)
set_feature(&cpu->env, ARM_FEATURE_XSCALE);
set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
cpu->midr = ARM_CPUID_PXA270_A0;
+ cpu->ctr = 0xd172172;
arm_cpu_postconfig_init(cpu);
}
@@ -326,6 +343,7 @@ static void pxa270a1_initfn(Object *obj)
set_feature(&cpu->env, ARM_FEATURE_XSCALE);
set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
cpu->midr = ARM_CPUID_PXA270_A1;
+ cpu->ctr = 0xd172172;
arm_cpu_postconfig_init(cpu);
}
@@ -336,6 +354,7 @@ static void pxa270b0_initfn(Object *obj)
set_feature(&cpu->env, ARM_FEATURE_XSCALE);
set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
cpu->midr = ARM_CPUID_PXA270_B0;
+ cpu->ctr = 0xd172172;
arm_cpu_postconfig_init(cpu);
}
@@ -346,6 +365,7 @@ static void pxa270b1_initfn(Object *obj)
set_feature(&cpu->env, ARM_FEATURE_XSCALE);
set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
cpu->midr = ARM_CPUID_PXA270_B1;
+ cpu->ctr = 0xd172172;
arm_cpu_postconfig_init(cpu);
}
@@ -356,6 +376,7 @@ static void pxa270c0_initfn(Object *obj)
set_feature(&cpu->env, ARM_FEATURE_XSCALE);
set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
cpu->midr = ARM_CPUID_PXA270_C0;
+ cpu->ctr = 0xd172172;
arm_cpu_postconfig_init(cpu);
}
@@ -370,6 +391,7 @@ static void pxa270c5_initfn(Object *obj)
set_feature(&cpu->env, ARM_FEATURE_ARM_DIV);
set_feature(&cpu->env, ARM_FEATURE_V7MP);
cpu->midr = ARM_CPUID_PXA270_C5;
+ cpu->ctr = 0xd172172;
arm_cpu_postconfig_init(cpu);
}
diff --git a/target-arm/helper.c b/target-arm/helper.c
index aeffd6b..e1314c2 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -51,15 +51,12 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
{
switch (id) {
case ARM_CPUID_ARM926:
- env->cp15.c0_cachetype = 0x1dd20d2;
env->cp15.c1_sys = 0x00090078;
break;
case ARM_CPUID_ARM946:
- env->cp15.c0_cachetype = 0x0f004006;
env->cp15.c1_sys = 0x00000078;
break;
case ARM_CPUID_ARM1026:
- env->cp15.c0_cachetype = 0x1dd20d2;
env->cp15.c1_sys = 0x00090078;
break;
case ARM_CPUID_ARM1136:
@@ -75,24 +72,20 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
*/
memcpy(env->cp15.c0_c1, arm1136_cp15_c0_c1, 8 * sizeof(uint32_t));
memcpy(env->cp15.c0_c2, arm1136_cp15_c0_c2, 8 * sizeof(uint32_t));
- env->cp15.c0_cachetype = 0x1dd20d2;
env->cp15.c1_sys = 0x00050078;
break;
case ARM_CPUID_ARM1176:
memcpy(env->cp15.c0_c1, arm1176_cp15_c0_c1, 8 * sizeof(uint32_t));
memcpy(env->cp15.c0_c2, arm1176_cp15_c0_c2, 8 * sizeof(uint32_t));
- env->cp15.c0_cachetype = 0x1dd20d2;
env->cp15.c1_sys = 0x00050078;
break;
case ARM_CPUID_ARM11MPCORE:
memcpy(env->cp15.c0_c1, mpcore_cp15_c0_c1, 8 * sizeof(uint32_t));
memcpy(env->cp15.c0_c2, mpcore_cp15_c0_c2, 8 * sizeof(uint32_t));
- env->cp15.c0_cachetype = 0x1dd20d2;
break;
case ARM_CPUID_CORTEXA8:
memcpy(env->cp15.c0_c1, cortexa8_cp15_c0_c1, 8 * sizeof(uint32_t));
memcpy(env->cp15.c0_c2, cortexa8_cp15_c0_c2, 8 * sizeof(uint32_t));
- env->cp15.c0_cachetype = 0x82048004;
env->cp15.c0_clid = (1 << 27) | (2 << 24) | 3;
env->cp15.c0_ccsid[0] = 0xe007e01a; /* 16k L1 dcache. */
env->cp15.c0_ccsid[1] = 0x2007e01a; /* 16k L1 icache. */
@@ -102,7 +95,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
case ARM_CPUID_CORTEXA9:
memcpy(env->cp15.c0_c1, cortexa9_cp15_c0_c1, 8 * sizeof(uint32_t));
memcpy(env->cp15.c0_c2, cortexa9_cp15_c0_c2, 8 * sizeof(uint32_t));
- env->cp15.c0_cachetype = 0x80038003;
env->cp15.c0_clid = (1 << 27) | (1 << 24) | 3;
env->cp15.c0_ccsid[0] = 0xe00fe015; /* 16k L1 dcache. */
env->cp15.c0_ccsid[1] = 0x200fe015; /* 16k L1 icache. */
@@ -111,7 +103,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
case ARM_CPUID_CORTEXA15:
memcpy(env->cp15.c0_c1, cortexa15_cp15_c0_c1, 8 * sizeof(uint32_t));
memcpy(env->cp15.c0_c2, cortexa15_cp15_c0_c2, 8 * sizeof(uint32_t));
- env->cp15.c0_cachetype = 0x8444c004;
env->cp15.c0_clid = 0x0a200023;
env->cp15.c0_ccsid[0] = 0x701fe00a; /* 32K L1 dcache */
env->cp15.c0_ccsid[1] = 0x201fe00a; /* 32K L1 icache */
@@ -124,7 +115,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
break;
case ARM_CPUID_TI915T:
case ARM_CPUID_TI925T:
- env->cp15.c0_cachetype = 0x5109149;
env->cp15.c1_sys = 0x00000070;
env->cp15.c15_i_max = 0x000;
env->cp15.c15_i_min = 0xff0;
@@ -135,7 +125,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
case ARM_CPUID_PXA261:
case ARM_CPUID_PXA262:
/* JTAG_ID is ((id << 28) | 0x09265013) */
- env->cp15.c0_cachetype = 0xd172172;
env->cp15.c1_sys = 0x00000078;
break;
case ARM_CPUID_PXA270_A0:
@@ -146,7 +135,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
case ARM_CPUID_PXA270_C5:
/* JTAG_ID is ((id << 28) | 0x09265013) */
env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q';
- env->cp15.c0_cachetype = 0xd172172;
env->cp15.c1_sys = 0x00000078;
break;
case ARM_CPUID_SA1100:
@@ -185,6 +173,7 @@ void cpu_state_reset(CPUARMState *env)
env->vfp.xregs[ARM_VFP_FPSID] = cpu->reset_fpsid;
env->vfp.xregs[ARM_VFP_MVFR0] = cpu->mvfr0;
env->vfp.xregs[ARM_VFP_MVFR1] = cpu->mvfr1;
+ env->cp15.c0_cachetype = cpu->ctr;
#if defined (CONFIG_USER_ONLY)
env->uncached_cpsr = ARM_CPU_MODE_USR;
--
1.7.1
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [Qemu-devel] [PATCH 06/14] target-arm: Move SCTLR reset value setup to per cpu init fns
2012-03-30 12:51 [Qemu-devel] [PATCH 00/14] target-arm: Create QOM subclass per CPU implementation Peter Maydell
` (4 preceding siblings ...)
2012-03-30 12:51 ` [Qemu-devel] [PATCH 05/14] target-arm: Move CTR " Peter Maydell
@ 2012-03-30 12:51 ` Peter Maydell
2012-03-30 12:51 ` [Qemu-devel] [PATCH 07/14] target-arm: Drop JTAG_ID documentation Peter Maydell
` (7 subsequent siblings)
13 siblings, 0 replies; 17+ messages in thread
From: Peter Maydell @ 2012-03-30 12:51 UTC (permalink / raw)
To: qemu-devel; +Cc: Paul Brook, Anthony Liguori, Andreas Färber
Move the reset value of SCTLR to ARMCPU, initialised in
the per-cpu init functions. It can then be reset by a
simple copy, and we can drop the code from cpu_reset_model_id().
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target-arm/cpu-qom.h | 1 +
target-arm/cpu.c | 23 +++++++++++++++++++++++
target-arm/helper.c | 13 +------------
3 files changed, 25 insertions(+), 12 deletions(-)
diff --git a/target-arm/cpu-qom.h b/target-arm/cpu-qom.h
index fc147c4..5e7a558 100644
--- a/target-arm/cpu-qom.h
+++ b/target-arm/cpu-qom.h
@@ -67,6 +67,7 @@ typedef struct ARMCPU {
uint32_t mvfr0;
uint32_t mvfr1;
uint32_t ctr;
+ uint32_t reset_sctlr;
} ARMCPU;
static inline ARMCPU *arm_env_get_cpu(CPUARMState *env)
diff --git a/target-arm/cpu.c b/target-arm/cpu.c
index 115561c..c33a451 100644
--- a/target-arm/cpu.c
+++ b/target-arm/cpu.c
@@ -105,6 +105,7 @@ static void arm926_initfn(Object *obj)
cpu->midr = ARM_CPUID_ARM926;
cpu->reset_fpsid = 0x41011090;
cpu->ctr = 0x1dd20d2;
+ cpu->reset_sctlr = 0x00090078;
arm_cpu_postconfig_init(cpu);
}
@@ -115,6 +116,7 @@ static void arm946_initfn(Object *obj)
set_feature(&cpu->env, ARM_FEATURE_MPU);
cpu->midr = ARM_CPUID_ARM946;
cpu->ctr = 0x0f004006;
+ cpu->reset_sctlr = 0x00000078;
arm_cpu_postconfig_init(cpu);
}
@@ -127,6 +129,7 @@ static void arm1026_initfn(Object *obj)
cpu->midr = ARM_CPUID_ARM1026;
cpu->reset_fpsid = 0x410110a0;
cpu->ctr = 0x1dd20d2;
+ cpu->reset_sctlr = 0x00090078;
arm_cpu_postconfig_init(cpu);
}
@@ -140,6 +143,7 @@ static void arm1136_r2_initfn(Object *obj)
cpu->mvfr0 = 0x11111111;
cpu->mvfr1 = 0x00000000;
cpu->ctr = 0x1dd20d2;
+ cpu->reset_sctlr = 0x00050078;
arm_cpu_postconfig_init(cpu);
}
@@ -154,6 +158,7 @@ static void arm1136_initfn(Object *obj)
cpu->mvfr0 = 0x11111111;
cpu->mvfr1 = 0x00000000;
cpu->ctr = 0x1dd20d2;
+ cpu->reset_sctlr = 0x00050078;
arm_cpu_postconfig_init(cpu);
}
@@ -168,6 +173,7 @@ static void arm1176_initfn(Object *obj)
cpu->mvfr0 = 0x11111111;
cpu->mvfr1 = 0x00000000;
cpu->ctr = 0x1dd20d2;
+ cpu->reset_sctlr = 0x00050078;
arm_cpu_postconfig_init(cpu);
}
@@ -206,6 +212,7 @@ static void cortex_a8_initfn(Object *obj)
cpu->mvfr0 = 0x11110222;
cpu->mvfr1 = 0x00011100;
cpu->ctr = 0x82048004;
+ cpu->reset_sctlr = 0x00c50078;
arm_cpu_postconfig_init(cpu);
}
@@ -227,6 +234,7 @@ static void cortex_a9_initfn(Object *obj)
cpu->mvfr0 = 0x11110222;
cpu->mvfr1 = 0x01111111;
cpu->ctr = 0x80038003;
+ cpu->reset_sctlr = 0x00c50078;
arm_cpu_postconfig_init(cpu);
}
@@ -246,6 +254,7 @@ static void cortex_a15_initfn(Object *obj)
cpu->mvfr0 = 0x10110222;
cpu->mvfr1 = 0x11111111;
cpu->ctr = 0x8444c004;
+ cpu->reset_sctlr = 0x00c50078;
arm_cpu_postconfig_init(cpu);
}
@@ -256,6 +265,7 @@ static void ti925t_initfn(Object *obj)
set_feature(&cpu->env, ARM_FEATURE_OMAPCP);
cpu->midr = ARM_CPUID_TI925T;
cpu->ctr = 0x5109149;
+ cpu->reset_sctlr = 0x00000070;
arm_cpu_postconfig_init(cpu);
}
@@ -264,6 +274,7 @@ static void sa1100_initfn(Object *obj)
ARMCPU *cpu = ARM_CPU(obj);
set_feature(&cpu->env, ARM_FEATURE_STRONGARM);
cpu->midr = ARM_CPUID_SA1100;
+ cpu->reset_sctlr = 0x00000070;
arm_cpu_postconfig_init(cpu);
}
@@ -272,6 +283,7 @@ static void sa1110_initfn(Object *obj)
ARMCPU *cpu = ARM_CPU(obj);
set_feature(&cpu->env, ARM_FEATURE_STRONGARM);
cpu->midr = ARM_CPUID_SA1110;
+ cpu->reset_sctlr = 0x00000070;
arm_cpu_postconfig_init(cpu);
}
@@ -282,6 +294,7 @@ static void pxa250_initfn(Object *obj)
set_feature(&cpu->env, ARM_FEATURE_XSCALE);
cpu->midr = ARM_CPUID_PXA250;
cpu->ctr = 0xd172172;
+ cpu->reset_sctlr = 0x00000078;
arm_cpu_postconfig_init(cpu);
}
@@ -292,6 +305,7 @@ static void pxa255_initfn(Object *obj)
set_feature(&cpu->env, ARM_FEATURE_XSCALE);
cpu->midr = ARM_CPUID_PXA255;
cpu->ctr = 0xd172172;
+ cpu->reset_sctlr = 0x00000078;
arm_cpu_postconfig_init(cpu);
}
@@ -302,6 +316,7 @@ static void pxa260_initfn(Object *obj)
set_feature(&cpu->env, ARM_FEATURE_XSCALE);
cpu->midr = ARM_CPUID_PXA260;
cpu->ctr = 0xd172172;
+ cpu->reset_sctlr = 0x00000078;
arm_cpu_postconfig_init(cpu);
}
@@ -312,6 +327,7 @@ static void pxa261_initfn(Object *obj)
set_feature(&cpu->env, ARM_FEATURE_XSCALE);
cpu->midr = ARM_CPUID_PXA261;
cpu->ctr = 0xd172172;
+ cpu->reset_sctlr = 0x00000078;
arm_cpu_postconfig_init(cpu);
}
@@ -322,6 +338,7 @@ static void pxa262_initfn(Object *obj)
set_feature(&cpu->env, ARM_FEATURE_XSCALE);
cpu->midr = ARM_CPUID_PXA262;
cpu->ctr = 0xd172172;
+ cpu->reset_sctlr = 0x00000078;
arm_cpu_postconfig_init(cpu);
}
@@ -333,6 +350,7 @@ static void pxa270a0_initfn(Object *obj)
set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
cpu->midr = ARM_CPUID_PXA270_A0;
cpu->ctr = 0xd172172;
+ cpu->reset_sctlr = 0x00000078;
arm_cpu_postconfig_init(cpu);
}
@@ -344,6 +362,7 @@ static void pxa270a1_initfn(Object *obj)
set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
cpu->midr = ARM_CPUID_PXA270_A1;
cpu->ctr = 0xd172172;
+ cpu->reset_sctlr = 0x00000078;
arm_cpu_postconfig_init(cpu);
}
@@ -355,6 +374,7 @@ static void pxa270b0_initfn(Object *obj)
set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
cpu->midr = ARM_CPUID_PXA270_B0;
cpu->ctr = 0xd172172;
+ cpu->reset_sctlr = 0x00000078;
arm_cpu_postconfig_init(cpu);
}
@@ -366,6 +386,7 @@ static void pxa270b1_initfn(Object *obj)
set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
cpu->midr = ARM_CPUID_PXA270_B1;
cpu->ctr = 0xd172172;
+ cpu->reset_sctlr = 0x00000078;
arm_cpu_postconfig_init(cpu);
}
@@ -377,6 +398,7 @@ static void pxa270c0_initfn(Object *obj)
set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
cpu->midr = ARM_CPUID_PXA270_C0;
cpu->ctr = 0xd172172;
+ cpu->reset_sctlr = 0x00000078;
arm_cpu_postconfig_init(cpu);
}
@@ -392,6 +414,7 @@ static void pxa270c5_initfn(Object *obj)
set_feature(&cpu->env, ARM_FEATURE_V7MP);
cpu->midr = ARM_CPUID_PXA270_C5;
cpu->ctr = 0xd172172;
+ cpu->reset_sctlr = 0x00000078;
arm_cpu_postconfig_init(cpu);
}
diff --git a/target-arm/helper.c b/target-arm/helper.c
index e1314c2..cb0ae15 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -51,13 +51,10 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
{
switch (id) {
case ARM_CPUID_ARM926:
- env->cp15.c1_sys = 0x00090078;
break;
case ARM_CPUID_ARM946:
- env->cp15.c1_sys = 0x00000078;
break;
case ARM_CPUID_ARM1026:
- env->cp15.c1_sys = 0x00090078;
break;
case ARM_CPUID_ARM1136:
/* This is the 1136 r1, which is a v6K core */
@@ -72,12 +69,10 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
*/
memcpy(env->cp15.c0_c1, arm1136_cp15_c0_c1, 8 * sizeof(uint32_t));
memcpy(env->cp15.c0_c2, arm1136_cp15_c0_c2, 8 * sizeof(uint32_t));
- env->cp15.c1_sys = 0x00050078;
break;
case ARM_CPUID_ARM1176:
memcpy(env->cp15.c0_c1, arm1176_cp15_c0_c1, 8 * sizeof(uint32_t));
memcpy(env->cp15.c0_c2, arm1176_cp15_c0_c2, 8 * sizeof(uint32_t));
- env->cp15.c1_sys = 0x00050078;
break;
case ARM_CPUID_ARM11MPCORE:
memcpy(env->cp15.c0_c1, mpcore_cp15_c0_c1, 8 * sizeof(uint32_t));
@@ -90,7 +85,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
env->cp15.c0_ccsid[0] = 0xe007e01a; /* 16k L1 dcache. */
env->cp15.c0_ccsid[1] = 0x2007e01a; /* 16k L1 icache. */
env->cp15.c0_ccsid[2] = 0xf0000000; /* No L2 icache. */
- env->cp15.c1_sys = 0x00c50078;
break;
case ARM_CPUID_CORTEXA9:
memcpy(env->cp15.c0_c1, cortexa9_cp15_c0_c1, 8 * sizeof(uint32_t));
@@ -98,7 +92,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
env->cp15.c0_clid = (1 << 27) | (1 << 24) | 3;
env->cp15.c0_ccsid[0] = 0xe00fe015; /* 16k L1 dcache. */
env->cp15.c0_ccsid[1] = 0x200fe015; /* 16k L1 icache. */
- env->cp15.c1_sys = 0x00c50078;
break;
case ARM_CPUID_CORTEXA15:
memcpy(env->cp15.c0_c1, cortexa15_cp15_c0_c1, 8 * sizeof(uint32_t));
@@ -107,7 +100,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
env->cp15.c0_ccsid[0] = 0x701fe00a; /* 32K L1 dcache */
env->cp15.c0_ccsid[1] = 0x201fe00a; /* 32K L1 icache */
env->cp15.c0_ccsid[2] = 0x711fe07a; /* 4096K L2 unified cache */
- env->cp15.c1_sys = 0x00c50078;
break;
case ARM_CPUID_CORTEXM3:
break;
@@ -115,7 +107,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
break;
case ARM_CPUID_TI915T:
case ARM_CPUID_TI925T:
- env->cp15.c1_sys = 0x00000070;
env->cp15.c15_i_max = 0x000;
env->cp15.c15_i_min = 0xff0;
break;
@@ -125,7 +116,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
case ARM_CPUID_PXA261:
case ARM_CPUID_PXA262:
/* JTAG_ID is ((id << 28) | 0x09265013) */
- env->cp15.c1_sys = 0x00000078;
break;
case ARM_CPUID_PXA270_A0:
case ARM_CPUID_PXA270_A1:
@@ -135,11 +125,9 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
case ARM_CPUID_PXA270_C5:
/* JTAG_ID is ((id << 28) | 0x09265013) */
env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q';
- env->cp15.c1_sys = 0x00000078;
break;
case ARM_CPUID_SA1100:
case ARM_CPUID_SA1110:
- env->cp15.c1_sys = 0x00000070;
break;
default:
cpu_abort(env, "Bad CPU ID: %x\n", id);
@@ -174,6 +162,7 @@ void cpu_state_reset(CPUARMState *env)
env->vfp.xregs[ARM_VFP_MVFR0] = cpu->mvfr0;
env->vfp.xregs[ARM_VFP_MVFR1] = cpu->mvfr1;
env->cp15.c0_cachetype = cpu->ctr;
+ env->cp15.c1_sys = cpu->reset_sctlr;
#if defined (CONFIG_USER_ONLY)
env->uncached_cpsr = ARM_CPU_MODE_USR;
--
1.7.1
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [Qemu-devel] [PATCH 07/14] target-arm: Drop JTAG_ID documentation
2012-03-30 12:51 [Qemu-devel] [PATCH 00/14] target-arm: Create QOM subclass per CPU implementation Peter Maydell
` (5 preceding siblings ...)
2012-03-30 12:51 ` [Qemu-devel] [PATCH 06/14] target-arm: Move SCTLR reset value " Peter Maydell
@ 2012-03-30 12:51 ` Peter Maydell
2012-03-30 12:51 ` [Qemu-devel] [PATCH 08/14] target-arm: Move iWMMXT wCID reset to cpu_state_reset Peter Maydell
` (6 subsequent siblings)
13 siblings, 0 replies; 17+ messages in thread
From: Peter Maydell @ 2012-03-30 12:51 UTC (permalink / raw)
To: qemu-devel; +Cc: Paul Brook, Anthony Liguori, Andreas Färber
None of the machines in QEMU offer a JTAG debug interface, so this info
was unused. Further, the PXA250 ID contradicts the February 2002
Developer's Manual, which has it as 0xn9264013 with n the MIDR Revision.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target-arm/helper.c | 2 --
1 files changed, 0 insertions(+), 2 deletions(-)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index cb0ae15..e3e019a 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -115,7 +115,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
case ARM_CPUID_PXA260:
case ARM_CPUID_PXA261:
case ARM_CPUID_PXA262:
- /* JTAG_ID is ((id << 28) | 0x09265013) */
break;
case ARM_CPUID_PXA270_A0:
case ARM_CPUID_PXA270_A1:
@@ -123,7 +122,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
case ARM_CPUID_PXA270_B1:
case ARM_CPUID_PXA270_C0:
case ARM_CPUID_PXA270_C5:
- /* JTAG_ID is ((id << 28) | 0x09265013) */
env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q';
break;
case ARM_CPUID_SA1100:
--
1.7.1
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [Qemu-devel] [PATCH 08/14] target-arm: Move iWMMXT wCID reset to cpu_state_reset
2012-03-30 12:51 [Qemu-devel] [PATCH 00/14] target-arm: Create QOM subclass per CPU implementation Peter Maydell
` (6 preceding siblings ...)
2012-03-30 12:51 ` [Qemu-devel] [PATCH 07/14] target-arm: Drop JTAG_ID documentation Peter Maydell
@ 2012-03-30 12:51 ` Peter Maydell
2012-03-30 12:51 ` [Qemu-devel] [PATCH 09/14] target-arm: Move feature register setup to per-CPU init fns Peter Maydell
` (5 subsequent siblings)
13 siblings, 0 replies; 17+ messages in thread
From: Peter Maydell @ 2012-03-30 12:51 UTC (permalink / raw)
To: qemu-devel; +Cc: Paul Brook, Anthony Liguori, Andreas Färber
Move the iWMMXT wCID reset to cpu_state_reset(). Since
we use the same value for all CPUs with this feature
(with the major/minor revision fields set to the QEMU
specific 'Q' value) there's no need to create an ARMCPU
field just for this.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target-arm/helper.c | 5 ++++-
1 files changed, 4 insertions(+), 1 deletions(-)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index e3e019a..0bc5529 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -122,7 +122,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
case ARM_CPUID_PXA270_B1:
case ARM_CPUID_PXA270_C0:
case ARM_CPUID_PXA270_C5:
- env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q';
break;
case ARM_CPUID_SA1100:
case ARM_CPUID_SA1110:
@@ -162,6 +161,10 @@ void cpu_state_reset(CPUARMState *env)
env->cp15.c0_cachetype = cpu->ctr;
env->cp15.c1_sys = cpu->reset_sctlr;
+ if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
+ env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q';
+ }
+
#if defined (CONFIG_USER_ONLY)
env->uncached_cpsr = ARM_CPU_MODE_USR;
/* For user mode we must enable access to coprocessors */
--
1.7.1
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [Qemu-devel] [PATCH 09/14] target-arm: Move feature register setup to per-CPU init fns
2012-03-30 12:51 [Qemu-devel] [PATCH 00/14] target-arm: Create QOM subclass per CPU implementation Peter Maydell
` (7 preceding siblings ...)
2012-03-30 12:51 ` [Qemu-devel] [PATCH 08/14] target-arm: Move iWMMXT wCID reset to cpu_state_reset Peter Maydell
@ 2012-03-30 12:51 ` Peter Maydell
2012-03-30 12:51 ` [Qemu-devel] [PATCH 10/14] target-arm: Move OMAP cp15_i_{max, min} reset to cpu_state_reset Peter Maydell
` (4 subsequent siblings)
13 siblings, 0 replies; 17+ messages in thread
From: Peter Maydell @ 2012-03-30 12:51 UTC (permalink / raw)
To: qemu-devel; +Cc: Paul Brook, Anthony Liguori, Andreas Färber
Move feature register value setup to per-CPU init functions.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target-arm/cpu-qom.h | 14 ++++++++
target-arm/cpu.c | 91 ++++++++++++++++++++++++++++++++++++++++++++++++++
target-arm/helper.c | 73 ++++++++--------------------------------
3 files changed, 119 insertions(+), 59 deletions(-)
diff --git a/target-arm/cpu-qom.h b/target-arm/cpu-qom.h
index 5e7a558..efdc0a8 100644
--- a/target-arm/cpu-qom.h
+++ b/target-arm/cpu-qom.h
@@ -68,6 +68,20 @@ typedef struct ARMCPU {
uint32_t mvfr1;
uint32_t ctr;
uint32_t reset_sctlr;
+ uint32_t id_pfr0;
+ uint32_t id_pfr1;
+ uint32_t id_dfr0;
+ uint32_t id_afr0;
+ uint32_t id_mmfr0;
+ uint32_t id_mmfr1;
+ uint32_t id_mmfr2;
+ uint32_t id_mmfr3;
+ uint32_t id_isar0;
+ uint32_t id_isar1;
+ uint32_t id_isar2;
+ uint32_t id_isar3;
+ uint32_t id_isar4;
+ uint32_t id_isar5;
} ARMCPU;
static inline ARMCPU *arm_env_get_cpu(CPUARMState *env)
diff --git a/target-arm/cpu.c b/target-arm/cpu.c
index c33a451..a58bda2 100644
--- a/target-arm/cpu.c
+++ b/target-arm/cpu.c
@@ -136,6 +136,13 @@ static void arm1026_initfn(Object *obj)
static void arm1136_r2_initfn(Object *obj)
{
ARMCPU *cpu = ARM_CPU(obj);
+ /* What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an
+ * older core than plain "arm1136". In particular this does not
+ * have the v6K features.
+ * These ID register values are correct for 1136 but may be wrong
+ * for 1136_r2 (in particular r0p2 does not actually implement most
+ * of the ID registers).
+ */
set_feature(&cpu->env, ARM_FEATURE_V6);
set_feature(&cpu->env, ARM_FEATURE_VFP);
cpu->midr = ARM_CPUID_ARM1136_R2;
@@ -144,6 +151,18 @@ static void arm1136_r2_initfn(Object *obj)
cpu->mvfr1 = 0x00000000;
cpu->ctr = 0x1dd20d2;
cpu->reset_sctlr = 0x00050078;
+ cpu->id_pfr0 = 0x111;
+ cpu->id_pfr1 = 0x1;
+ cpu->id_dfr0 = 0x2;
+ cpu->id_afr0 = 0x3;
+ cpu->id_mmfr0 = 0x01130003;
+ cpu->id_mmfr1 = 0x10030302;
+ cpu->id_mmfr2 = 0x01222110;
+ cpu->id_isar0 = 0x00140011;
+ cpu->id_isar1 = 0x12002111;
+ cpu->id_isar2 = 0x11231111;
+ cpu->id_isar3 = 0x01102131;
+ cpu->id_isar4 = 0x141;
arm_cpu_postconfig_init(cpu);
}
@@ -159,6 +178,18 @@ static void arm1136_initfn(Object *obj)
cpu->mvfr1 = 0x00000000;
cpu->ctr = 0x1dd20d2;
cpu->reset_sctlr = 0x00050078;
+ cpu->id_pfr0 = 0x111;
+ cpu->id_pfr1 = 0x1;
+ cpu->id_dfr0 = 0x2;
+ cpu->id_afr0 = 0x3;
+ cpu->id_mmfr0 = 0x01130003;
+ cpu->id_mmfr1 = 0x10030302;
+ cpu->id_mmfr2 = 0x01222110;
+ cpu->id_isar0 = 0x00140011;
+ cpu->id_isar1 = 0x12002111;
+ cpu->id_isar2 = 0x11231111;
+ cpu->id_isar3 = 0x01102131;
+ cpu->id_isar4 = 0x141;
arm_cpu_postconfig_init(cpu);
}
@@ -174,6 +205,18 @@ static void arm1176_initfn(Object *obj)
cpu->mvfr1 = 0x00000000;
cpu->ctr = 0x1dd20d2;
cpu->reset_sctlr = 0x00050078;
+ cpu->id_pfr0 = 0x111;
+ cpu->id_pfr1 = 0x11;
+ cpu->id_dfr0 = 0x33;
+ cpu->id_afr0 = 0;
+ cpu->id_mmfr0 = 0x01130003;
+ cpu->id_mmfr1 = 0x10030302;
+ cpu->id_mmfr2 = 0x01222100;
+ cpu->id_isar0 = 0x0140011;
+ cpu->id_isar1 = 0x12002111;
+ cpu->id_isar2 = 0x11231121;
+ cpu->id_isar3 = 0x01102131;
+ cpu->id_isar4 = 0x01141;
arm_cpu_postconfig_init(cpu);
}
@@ -188,6 +231,18 @@ static void arm11mpcore_initfn(Object *obj)
cpu->mvfr0 = 0x11111111;
cpu->mvfr1 = 0x00000000;
cpu->ctr = 0x1dd20d2;
+ cpu->id_pfr0 = 0x111;
+ cpu->id_pfr1 = 0x1;
+ cpu->id_dfr0 = 0;
+ cpu->id_afr0 = 0x2;
+ cpu->id_mmfr0 = 0x01100103;
+ cpu->id_mmfr1 = 0x10020302;
+ cpu->id_mmfr2 = 0x01222000;
+ cpu->id_isar0 = 0x00100011;
+ cpu->id_isar1 = 0x12002111;
+ cpu->id_isar2 = 0x11221011;
+ cpu->id_isar3 = 0x01102131;
+ cpu->id_isar4 = 0x141;
arm_cpu_postconfig_init(cpu);
}
@@ -213,6 +268,18 @@ static void cortex_a8_initfn(Object *obj)
cpu->mvfr1 = 0x00011100;
cpu->ctr = 0x82048004;
cpu->reset_sctlr = 0x00c50078;
+ cpu->id_pfr0 = 0x1031;
+ cpu->id_pfr1 = 0x11;
+ cpu->id_dfr0 = 0x400;
+ cpu->id_afr0 = 0;
+ cpu->id_mmfr0 = 0x31100003;
+ cpu->id_mmfr1 = 0x20000000;
+ cpu->id_mmfr2 = 0x01202000;
+ cpu->id_isar0 = 0x00101111;
+ cpu->id_isar1 = 0x12112111;
+ cpu->id_isar2 = 0x21232031;
+ cpu->id_isar3 = 0x11112131;
+ cpu->id_isar4 = 0x00111142;
arm_cpu_postconfig_init(cpu);
}
@@ -235,6 +302,18 @@ static void cortex_a9_initfn(Object *obj)
cpu->mvfr1 = 0x01111111;
cpu->ctr = 0x80038003;
cpu->reset_sctlr = 0x00c50078;
+ cpu->id_pfr0 = 0x1031;
+ cpu->id_pfr1 = 0x11;
+ cpu->id_dfr0 = 0x000;
+ cpu->id_afr0 = 0;
+ cpu->id_mmfr0 = 0x00100103;
+ cpu->id_mmfr1 = 0x20000000;
+ cpu->id_mmfr2 = 0x01230000;
+ cpu->id_isar0 = 0x00101111;
+ cpu->id_isar1 = 0x13112111;
+ cpu->id_isar2 = 0x21232041;
+ cpu->id_isar3 = 0x11112131;
+ cpu->id_isar4 = 0x00111142;
arm_cpu_postconfig_init(cpu);
}
@@ -255,6 +334,18 @@ static void cortex_a15_initfn(Object *obj)
cpu->mvfr1 = 0x11111111;
cpu->ctr = 0x8444c004;
cpu->reset_sctlr = 0x00c50078;
+ cpu->id_pfr0 = 0x00001131;
+ cpu->id_pfr1 = 0x00011011;
+ cpu->id_dfr0 = 0x02010555;
+ cpu->id_afr0 = 0x00000000;
+ cpu->id_mmfr0 = 0x10201105;
+ cpu->id_mmfr1 = 0x20000000;
+ cpu->id_mmfr2 = 0x01240000;
+ cpu->id_isar0 = 0x02101110;
+ cpu->id_isar1 = 0x13112111;
+ cpu->id_isar2 = 0x21232041;
+ cpu->id_isar3 = 0x11112131;
+ cpu->id_isar4 = 0x10011142;
arm_cpu_postconfig_init(cpu);
}
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 0bc5529..6c21f74 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -8,45 +8,6 @@
#include "sysemu.h"
#include "cpu-qom.h"
-static uint32_t cortexa15_cp15_c0_c1[8] = {
- 0x00001131, 0x00011011, 0x02010555, 0x00000000,
- 0x10201105, 0x20000000, 0x01240000, 0x02102211
-};
-
-static uint32_t cortexa15_cp15_c0_c2[8] = {
- 0x02101110, 0x13112111, 0x21232041, 0x11112131, 0x10011142, 0, 0, 0
-};
-
-static uint32_t cortexa9_cp15_c0_c1[8] =
-{ 0x1031, 0x11, 0x000, 0, 0x00100103, 0x20000000, 0x01230000, 0x00002111 };
-
-static uint32_t cortexa9_cp15_c0_c2[8] =
-{ 0x00101111, 0x13112111, 0x21232041, 0x11112131, 0x00111142, 0, 0, 0 };
-
-static uint32_t cortexa8_cp15_c0_c1[8] =
-{ 0x1031, 0x11, 0x400, 0, 0x31100003, 0x20000000, 0x01202000, 0x11 };
-
-static uint32_t cortexa8_cp15_c0_c2[8] =
-{ 0x00101111, 0x12112111, 0x21232031, 0x11112131, 0x00111142, 0, 0, 0 };
-
-static uint32_t mpcore_cp15_c0_c1[8] =
-{ 0x111, 0x1, 0, 0x2, 0x01100103, 0x10020302, 0x01222000, 0 };
-
-static uint32_t mpcore_cp15_c0_c2[8] =
-{ 0x00100011, 0x12002111, 0x11221011, 0x01102131, 0x141, 0, 0, 0 };
-
-static uint32_t arm1136_cp15_c0_c1[8] =
-{ 0x111, 0x1, 0x2, 0x3, 0x01130003, 0x10030302, 0x01222110, 0 };
-
-static uint32_t arm1136_cp15_c0_c2[8] =
-{ 0x00140011, 0x12002111, 0x11231111, 0x01102131, 0x141, 0, 0, 0 };
-
-static uint32_t arm1176_cp15_c0_c1[8] =
-{ 0x111, 0x11, 0x33, 0, 0x01130003, 0x10030302, 0x01222100, 0 };
-
-static uint32_t arm1176_cp15_c0_c2[8] =
-{ 0x0140011, 0x12002111, 0x11231121, 0x01102131, 0x01141, 0, 0, 0 };
-
static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
{
switch (id) {
@@ -59,43 +20,23 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
case ARM_CPUID_ARM1136:
/* This is the 1136 r1, which is a v6K core */
case ARM_CPUID_ARM1136_R2:
- /* What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an
- * older core than plain "arm1136". In particular this does not
- * have the v6K features.
- */
- /* These ID register values are correct for 1136 but may be wrong
- * for 1136_r2 (in particular r0p2 does not actually implement most
- * of the ID registers).
- */
- memcpy(env->cp15.c0_c1, arm1136_cp15_c0_c1, 8 * sizeof(uint32_t));
- memcpy(env->cp15.c0_c2, arm1136_cp15_c0_c2, 8 * sizeof(uint32_t));
break;
case ARM_CPUID_ARM1176:
- memcpy(env->cp15.c0_c1, arm1176_cp15_c0_c1, 8 * sizeof(uint32_t));
- memcpy(env->cp15.c0_c2, arm1176_cp15_c0_c2, 8 * sizeof(uint32_t));
break;
case ARM_CPUID_ARM11MPCORE:
- memcpy(env->cp15.c0_c1, mpcore_cp15_c0_c1, 8 * sizeof(uint32_t));
- memcpy(env->cp15.c0_c2, mpcore_cp15_c0_c2, 8 * sizeof(uint32_t));
break;
case ARM_CPUID_CORTEXA8:
- memcpy(env->cp15.c0_c1, cortexa8_cp15_c0_c1, 8 * sizeof(uint32_t));
- memcpy(env->cp15.c0_c2, cortexa8_cp15_c0_c2, 8 * sizeof(uint32_t));
env->cp15.c0_clid = (1 << 27) | (2 << 24) | 3;
env->cp15.c0_ccsid[0] = 0xe007e01a; /* 16k L1 dcache. */
env->cp15.c0_ccsid[1] = 0x2007e01a; /* 16k L1 icache. */
env->cp15.c0_ccsid[2] = 0xf0000000; /* No L2 icache. */
break;
case ARM_CPUID_CORTEXA9:
- memcpy(env->cp15.c0_c1, cortexa9_cp15_c0_c1, 8 * sizeof(uint32_t));
- memcpy(env->cp15.c0_c2, cortexa9_cp15_c0_c2, 8 * sizeof(uint32_t));
env->cp15.c0_clid = (1 << 27) | (1 << 24) | 3;
env->cp15.c0_ccsid[0] = 0xe00fe015; /* 16k L1 dcache. */
env->cp15.c0_ccsid[1] = 0x200fe015; /* 16k L1 icache. */
break;
case ARM_CPUID_CORTEXA15:
- memcpy(env->cp15.c0_c1, cortexa15_cp15_c0_c1, 8 * sizeof(uint32_t));
- memcpy(env->cp15.c0_c2, cortexa15_cp15_c0_c2, 8 * sizeof(uint32_t));
env->cp15.c0_clid = 0x0a200023;
env->cp15.c0_ccsid[0] = 0x701fe00a; /* 32K L1 dcache */
env->cp15.c0_ccsid[1] = 0x201fe00a; /* 32K L1 icache */
@@ -160,6 +101,20 @@ void cpu_state_reset(CPUARMState *env)
env->vfp.xregs[ARM_VFP_MVFR1] = cpu->mvfr1;
env->cp15.c0_cachetype = cpu->ctr;
env->cp15.c1_sys = cpu->reset_sctlr;
+ env->cp15.c0_c1[0] = cpu->id_pfr0;
+ env->cp15.c0_c1[1] = cpu->id_pfr1;
+ env->cp15.c0_c1[2] = cpu->id_dfr0;
+ env->cp15.c0_c1[3] = cpu->id_afr0;
+ env->cp15.c0_c1[4] = cpu->id_mmfr0;
+ env->cp15.c0_c1[5] = cpu->id_mmfr1;
+ env->cp15.c0_c1[6] = cpu->id_mmfr2;
+ env->cp15.c0_c1[7] = cpu->id_mmfr3;
+ env->cp15.c0_c2[0] = cpu->id_isar0;
+ env->cp15.c0_c2[1] = cpu->id_isar1;
+ env->cp15.c0_c2[2] = cpu->id_isar2;
+ env->cp15.c0_c2[3] = cpu->id_isar3;
+ env->cp15.c0_c2[4] = cpu->id_isar4;
+ env->cp15.c0_c2[5] = cpu->id_isar5;
if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q';
--
1.7.1
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [Qemu-devel] [PATCH 10/14] target-arm: Move OMAP cp15_i_{max, min} reset to cpu_state_reset
2012-03-30 12:51 [Qemu-devel] [PATCH 00/14] target-arm: Create QOM subclass per CPU implementation Peter Maydell
` (8 preceding siblings ...)
2012-03-30 12:51 ` [Qemu-devel] [PATCH 09/14] target-arm: Move feature register setup to per-CPU init fns Peter Maydell
@ 2012-03-30 12:51 ` Peter Maydell
2012-03-30 12:51 ` [Qemu-devel] [PATCH 11/14] target-arm: Move cache ID register setup to cpu specific init fns Peter Maydell
` (3 subsequent siblings)
13 siblings, 0 replies; 17+ messages in thread
From: Peter Maydell @ 2012-03-30 12:51 UTC (permalink / raw)
To: qemu-devel; +Cc: Paul Brook, Anthony Liguori, Andreas Färber
Move the OMAP-specific cp15_i_{max,min} reset to cpu_state_reset;
since these registers are only accessible on CPUs with the
OMAPCP feature set there's no need to guard this reset with
either a CPUID or feature bit check.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target-arm/helper.c | 3 +--
1 files changed, 1 insertions(+), 2 deletions(-)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 6c21f74..a94f09f 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -48,8 +48,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
break;
case ARM_CPUID_TI915T:
case ARM_CPUID_TI925T:
- env->cp15.c15_i_max = 0x000;
- env->cp15.c15_i_min = 0xff0;
break;
case ARM_CPUID_PXA250:
case ARM_CPUID_PXA255:
@@ -115,6 +113,7 @@ void cpu_state_reset(CPUARMState *env)
env->cp15.c0_c2[3] = cpu->id_isar3;
env->cp15.c0_c2[4] = cpu->id_isar4;
env->cp15.c0_c2[5] = cpu->id_isar5;
+ env->cp15.c15_i_min = 0xff0;
if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q';
--
1.7.1
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [Qemu-devel] [PATCH 11/14] target-arm: Move cache ID register setup to cpu specific init fns
2012-03-30 12:51 [Qemu-devel] [PATCH 00/14] target-arm: Create QOM subclass per CPU implementation Peter Maydell
` (9 preceding siblings ...)
2012-03-30 12:51 ` [Qemu-devel] [PATCH 10/14] target-arm: Move OMAP cp15_i_{max, min} reset to cpu_state_reset Peter Maydell
@ 2012-03-30 12:51 ` Peter Maydell
2012-03-30 12:51 ` [Qemu-devel] [PATCH 12/14] target-arm: Drop cpu_reset_model_id() Peter Maydell
` (2 subsequent siblings)
13 siblings, 0 replies; 17+ messages in thread
From: Peter Maydell @ 2012-03-30 12:51 UTC (permalink / raw)
To: qemu-devel; +Cc: Paul Brook, Anthony Liguori, Andreas Färber
Move cache ID register reset out of cpu_reset_model_id() by
creating a field for the reset value in ARMCPU and setting it
up in the cpu specific init functions.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target-arm/cpu-qom.h | 2 ++
target-arm/cpu.c | 11 +++++++++++
target-arm/helper.c | 13 ++-----------
3 files changed, 15 insertions(+), 11 deletions(-)
diff --git a/target-arm/cpu-qom.h b/target-arm/cpu-qom.h
index efdc0a8..55dc920 100644
--- a/target-arm/cpu-qom.h
+++ b/target-arm/cpu-qom.h
@@ -82,6 +82,8 @@ typedef struct ARMCPU {
uint32_t id_isar3;
uint32_t id_isar4;
uint32_t id_isar5;
+ uint32_t clidr;
+ uint32_t ccsidr[16];
} ARMCPU;
static inline ARMCPU *arm_env_get_cpu(CPUARMState *env)
diff --git a/target-arm/cpu.c b/target-arm/cpu.c
index a58bda2..c2eb998 100644
--- a/target-arm/cpu.c
+++ b/target-arm/cpu.c
@@ -280,6 +280,10 @@ static void cortex_a8_initfn(Object *obj)
cpu->id_isar2 = 0x21232031;
cpu->id_isar3 = 0x11112131;
cpu->id_isar4 = 0x00111142;
+ cpu->clidr = (1 << 27) | (2 << 24) | 3;
+ cpu->ccsidr[0] = 0xe007e01a; /* 16k L1 dcache. */
+ cpu->ccsidr[1] = 0x2007e01a; /* 16k L1 icache. */
+ cpu->ccsidr[2] = 0xf0000000; /* No L2 icache. */
arm_cpu_postconfig_init(cpu);
}
@@ -314,6 +318,9 @@ static void cortex_a9_initfn(Object *obj)
cpu->id_isar2 = 0x21232041;
cpu->id_isar3 = 0x11112131;
cpu->id_isar4 = 0x00111142;
+ cpu->clidr = (1 << 27) | (2 << 24) | 3;
+ cpu->ccsidr[0] = 0xe00fe015; /* 16k L1 dcache. */
+ cpu->ccsidr[1] = 0x200fe015; /* 16k L1 icache. */
arm_cpu_postconfig_init(cpu);
}
@@ -346,6 +353,10 @@ static void cortex_a15_initfn(Object *obj)
cpu->id_isar2 = 0x21232041;
cpu->id_isar3 = 0x11112131;
cpu->id_isar4 = 0x10011142;
+ cpu->clidr = 0x0a200023;
+ cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */
+ cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */
+ cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */
arm_cpu_postconfig_init(cpu);
}
diff --git a/target-arm/helper.c b/target-arm/helper.c
index a94f09f..5c4cfee 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -26,21 +26,10 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
case ARM_CPUID_ARM11MPCORE:
break;
case ARM_CPUID_CORTEXA8:
- env->cp15.c0_clid = (1 << 27) | (2 << 24) | 3;
- env->cp15.c0_ccsid[0] = 0xe007e01a; /* 16k L1 dcache. */
- env->cp15.c0_ccsid[1] = 0x2007e01a; /* 16k L1 icache. */
- env->cp15.c0_ccsid[2] = 0xf0000000; /* No L2 icache. */
break;
case ARM_CPUID_CORTEXA9:
- env->cp15.c0_clid = (1 << 27) | (1 << 24) | 3;
- env->cp15.c0_ccsid[0] = 0xe00fe015; /* 16k L1 dcache. */
- env->cp15.c0_ccsid[1] = 0x200fe015; /* 16k L1 icache. */
break;
case ARM_CPUID_CORTEXA15:
- env->cp15.c0_clid = 0x0a200023;
- env->cp15.c0_ccsid[0] = 0x701fe00a; /* 32K L1 dcache */
- env->cp15.c0_ccsid[1] = 0x201fe00a; /* 32K L1 icache */
- env->cp15.c0_ccsid[2] = 0x711fe07a; /* 4096K L2 unified cache */
break;
case ARM_CPUID_CORTEXM3:
break;
@@ -114,6 +103,8 @@ void cpu_state_reset(CPUARMState *env)
env->cp15.c0_c2[4] = cpu->id_isar4;
env->cp15.c0_c2[5] = cpu->id_isar5;
env->cp15.c15_i_min = 0xff0;
+ env->cp15.c0_clid = cpu->clidr;
+ memcpy(env->cp15.c0_ccsid, cpu->ccsidr, ARRAY_SIZE(cpu->ccsidr));
if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q';
--
1.7.1
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [Qemu-devel] [PATCH 12/14] target-arm: Drop cpu_reset_model_id()
2012-03-30 12:51 [Qemu-devel] [PATCH 00/14] target-arm: Create QOM subclass per CPU implementation Peter Maydell
` (10 preceding siblings ...)
2012-03-30 12:51 ` [Qemu-devel] [PATCH 11/14] target-arm: Move cache ID register setup to cpu specific init fns Peter Maydell
@ 2012-03-30 12:51 ` Peter Maydell
2012-03-30 12:51 ` [Qemu-devel] [PATCH 13/14] target-arm: Move reset handling to arm_cpu_reset Peter Maydell
2012-03-30 12:51 ` [Qemu-devel] [PATCH 14/14] target-arm: Move A9 config_base_address reset value to ARMCPU Peter Maydell
13 siblings, 0 replies; 17+ messages in thread
From: Peter Maydell @ 2012-03-30 12:51 UTC (permalink / raw)
To: qemu-devel; +Cc: Paul Brook, Anthony Liguori, Andreas Färber
cpu_reset_model_id() is now empty and we can remove it.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target-arm/helper.c | 59 +--------------------------------------------------
1 files changed, 1 insertions(+), 58 deletions(-)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 5c4cfee..f48108e 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -8,66 +8,12 @@
#include "sysemu.h"
#include "cpu-qom.h"
-static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
-{
- switch (id) {
- case ARM_CPUID_ARM926:
- break;
- case ARM_CPUID_ARM946:
- break;
- case ARM_CPUID_ARM1026:
- break;
- case ARM_CPUID_ARM1136:
- /* This is the 1136 r1, which is a v6K core */
- case ARM_CPUID_ARM1136_R2:
- break;
- case ARM_CPUID_ARM1176:
- break;
- case ARM_CPUID_ARM11MPCORE:
- break;
- case ARM_CPUID_CORTEXA8:
- break;
- case ARM_CPUID_CORTEXA9:
- break;
- case ARM_CPUID_CORTEXA15:
- break;
- case ARM_CPUID_CORTEXM3:
- break;
- case ARM_CPUID_ANY: /* For userspace emulation. */
- break;
- case ARM_CPUID_TI915T:
- case ARM_CPUID_TI925T:
- break;
- case ARM_CPUID_PXA250:
- case ARM_CPUID_PXA255:
- case ARM_CPUID_PXA260:
- case ARM_CPUID_PXA261:
- case ARM_CPUID_PXA262:
- break;
- case ARM_CPUID_PXA270_A0:
- case ARM_CPUID_PXA270_A1:
- case ARM_CPUID_PXA270_B0:
- case ARM_CPUID_PXA270_B1:
- case ARM_CPUID_PXA270_C0:
- case ARM_CPUID_PXA270_C5:
- break;
- case ARM_CPUID_SA1100:
- case ARM_CPUID_SA1110:
- break;
- default:
- cpu_abort(env, "Bad CPU ID: %x\n", id);
- break;
- }
-
-}
-
/* TODO Move contents into arm_cpu_reset() in cpu.c,
* once cpu_reset_model_id() is eliminated,
* and then forward to cpu_reset() here.
*/
void cpu_state_reset(CPUARMState *env)
{
- uint32_t id;
uint32_t tmp = 0;
ARMCPU *cpu = arm_env_get_cpu(env);
@@ -76,11 +22,8 @@ void cpu_state_reset(CPUARMState *env)
log_cpu_state(env, 0);
}
- id = env->cp15.c0_cpuid;
tmp = env->cp15.c15_config_base_address;
memset(env, 0, offsetof(CPUARMState, breakpoints));
- if (id)
- cpu_reset_model_id(env, id);
env->cp15.c15_config_base_address = tmp;
env->cp15.c0_cpuid = cpu->midr;
env->vfp.xregs[ARM_VFP_FPSID] = cpu->reset_fpsid;
@@ -145,7 +88,7 @@ void cpu_state_reset(CPUARMState *env)
/* v7 performance monitor control register: same implementor
* field as main ID register, and we implement no event counters.
*/
- env->cp15.c9_pmcr = (id & 0xff000000);
+ env->cp15.c9_pmcr = (cpu->midr & 0xff000000);
#endif
set_flush_to_zero(1, &env->vfp.standard_fp_status);
set_flush_inputs_to_zero(1, &env->vfp.standard_fp_status);
--
1.7.1
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [Qemu-devel] [PATCH 13/14] target-arm: Move reset handling to arm_cpu_reset
2012-03-30 12:51 [Qemu-devel] [PATCH 00/14] target-arm: Create QOM subclass per CPU implementation Peter Maydell
` (11 preceding siblings ...)
2012-03-30 12:51 ` [Qemu-devel] [PATCH 12/14] target-arm: Drop cpu_reset_model_id() Peter Maydell
@ 2012-03-30 12:51 ` Peter Maydell
2012-03-30 12:51 ` [Qemu-devel] [PATCH 14/14] target-arm: Move A9 config_base_address reset value to ARMCPU Peter Maydell
13 siblings, 0 replies; 17+ messages in thread
From: Peter Maydell @ 2012-03-30 12:51 UTC (permalink / raw)
To: qemu-devel; +Cc: Paul Brook, Anthony Liguori, Andreas Färber
Now that cpu_reset_model_id() has gone we can move the
reset code over to the class reset function and have cpu_state_reset
simply do a reset on the CPU QOM object.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target-arm/cpu.c | 94 +++++++++++++++++++++++++++++++++++++++++++++++--
target-arm/helper.c | 97 +--------------------------------------------------
2 files changed, 92 insertions(+), 99 deletions(-)
diff --git a/target-arm/cpu.c b/target-arm/cpu.c
index c2eb998..66f76a8 100644
--- a/target-arm/cpu.c
+++ b/target-arm/cpu.c
@@ -20,18 +20,106 @@
#include "cpu-qom.h"
#include "qemu-common.h"
+#if !defined(CONFIG_USER_ONLY)
+#include "hw/loader.h"
+#endif
/* CPUClass::reset() */
static void arm_cpu_reset(CPUState *s)
{
ARMCPU *cpu = ARM_CPU(s);
ARMCPUClass *acc = ARM_CPU_GET_CLASS(cpu);
+ CPUARMState *env = &cpu->env;
+ uint32_t tmp = 0;
+
+ if (qemu_loglevel_mask(CPU_LOG_RESET)) {
+ qemu_log("CPU Reset (CPU %d)\n", env->cpu_index);
+ log_cpu_state(env, 0);
+ }
acc->parent_reset(s);
- /* TODO Inline the current contents of cpu_state_reset(),
- once cpu_reset_model_id() is eliminated. */
- cpu_state_reset(&cpu->env);
+ tmp = env->cp15.c15_config_base_address;
+ memset(env, 0, offsetof(CPUARMState, breakpoints));
+ env->cp15.c15_config_base_address = tmp;
+ env->cp15.c0_cpuid = cpu->midr;
+ env->vfp.xregs[ARM_VFP_FPSID] = cpu->reset_fpsid;
+ env->vfp.xregs[ARM_VFP_MVFR0] = cpu->mvfr0;
+ env->vfp.xregs[ARM_VFP_MVFR1] = cpu->mvfr1;
+ env->cp15.c0_cachetype = cpu->ctr;
+ env->cp15.c1_sys = cpu->reset_sctlr;
+ env->cp15.c0_c1[0] = cpu->id_pfr0;
+ env->cp15.c0_c1[1] = cpu->id_pfr1;
+ env->cp15.c0_c1[2] = cpu->id_dfr0;
+ env->cp15.c0_c1[3] = cpu->id_afr0;
+ env->cp15.c0_c1[4] = cpu->id_mmfr0;
+ env->cp15.c0_c1[5] = cpu->id_mmfr1;
+ env->cp15.c0_c1[6] = cpu->id_mmfr2;
+ env->cp15.c0_c1[7] = cpu->id_mmfr3;
+ env->cp15.c0_c2[0] = cpu->id_isar0;
+ env->cp15.c0_c2[1] = cpu->id_isar1;
+ env->cp15.c0_c2[2] = cpu->id_isar2;
+ env->cp15.c0_c2[3] = cpu->id_isar3;
+ env->cp15.c0_c2[4] = cpu->id_isar4;
+ env->cp15.c0_c2[5] = cpu->id_isar5;
+ env->cp15.c15_i_min = 0xff0;
+ env->cp15.c0_clid = cpu->clidr;
+ memcpy(env->cp15.c0_ccsid, cpu->ccsidr, ARRAY_SIZE(cpu->ccsidr));
+
+ if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
+ env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q';
+ }
+
+#if defined(CONFIG_USER_ONLY)
+ env->uncached_cpsr = ARM_CPU_MODE_USR;
+ /* For user mode we must enable access to coprocessors */
+ env->vfp.xregs[ARM_VFP_FPEXC] = 1 << 30;
+ if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
+ env->cp15.c15_cpar = 3;
+ } else if (arm_feature(env, ARM_FEATURE_XSCALE)) {
+ env->cp15.c15_cpar = 1;
+ }
+#else
+ /* SVC mode with interrupts disabled. */
+ env->uncached_cpsr = ARM_CPU_MODE_SVC | CPSR_A | CPSR_F | CPSR_I;
+ /* On ARMv7-M the CPSR_I is the value of the PRIMASK register, and is
+ clear at reset. Initial SP and PC are loaded from ROM. */
+ if (IS_M(env)) {
+ uint32_t pc;
+ uint8_t *rom;
+ env->uncached_cpsr &= ~CPSR_I;
+ rom = rom_ptr(0);
+ if (rom) {
+ /* We should really use ldl_phys here, in case the guest
+ modified flash and reset itself. However images
+ loaded via -kernel have not been copied yet, so load the
+ values directly from there. */
+ env->regs[13] = ldl_p(rom);
+ pc = ldl_p(rom + 4);
+ env->thumb = pc & 1;
+ env->regs[15] = pc & ~1;
+ }
+ }
+ env->vfp.xregs[ARM_VFP_FPEXC] = 0;
+ env->cp15.c2_base_mask = 0xffffc000u;
+ /* v7 performance monitor control register: same implementor
+ * field as main ID register, and we implement no event counters.
+ */
+ env->cp15.c9_pmcr = (cpu->midr & 0xff000000);
+#endif
+ set_flush_to_zero(1, &env->vfp.standard_fp_status);
+ set_flush_inputs_to_zero(1, &env->vfp.standard_fp_status);
+ set_default_nan_mode(1, &env->vfp.standard_fp_status);
+ set_float_detect_tininess(float_tininess_before_rounding,
+ &env->vfp.fp_status);
+ set_float_detect_tininess(float_tininess_before_rounding,
+ &env->vfp.standard_fp_status);
+ tlb_flush(env, 1);
+ /* Reset is a state change for some CPUARMState fields which we
+ * bake assumptions about into translated code, so we need to
+ * tb_flush().
+ */
+ tb_flush(env);
}
static inline void set_feature(CPUARMState *env, int feature)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index f48108e..94fa49e 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -2,107 +2,12 @@
#include "gdbstub.h"
#include "helper.h"
#include "host-utils.h"
-#if !defined(CONFIG_USER_ONLY)
-#include "hw/loader.h"
-#endif
#include "sysemu.h"
#include "cpu-qom.h"
-/* TODO Move contents into arm_cpu_reset() in cpu.c,
- * once cpu_reset_model_id() is eliminated,
- * and then forward to cpu_reset() here.
- */
void cpu_state_reset(CPUARMState *env)
{
- uint32_t tmp = 0;
- ARMCPU *cpu = arm_env_get_cpu(env);
-
- if (qemu_loglevel_mask(CPU_LOG_RESET)) {
- qemu_log("CPU Reset (CPU %d)\n", env->cpu_index);
- log_cpu_state(env, 0);
- }
-
- tmp = env->cp15.c15_config_base_address;
- memset(env, 0, offsetof(CPUARMState, breakpoints));
- env->cp15.c15_config_base_address = tmp;
- env->cp15.c0_cpuid = cpu->midr;
- env->vfp.xregs[ARM_VFP_FPSID] = cpu->reset_fpsid;
- env->vfp.xregs[ARM_VFP_MVFR0] = cpu->mvfr0;
- env->vfp.xregs[ARM_VFP_MVFR1] = cpu->mvfr1;
- env->cp15.c0_cachetype = cpu->ctr;
- env->cp15.c1_sys = cpu->reset_sctlr;
- env->cp15.c0_c1[0] = cpu->id_pfr0;
- env->cp15.c0_c1[1] = cpu->id_pfr1;
- env->cp15.c0_c1[2] = cpu->id_dfr0;
- env->cp15.c0_c1[3] = cpu->id_afr0;
- env->cp15.c0_c1[4] = cpu->id_mmfr0;
- env->cp15.c0_c1[5] = cpu->id_mmfr1;
- env->cp15.c0_c1[6] = cpu->id_mmfr2;
- env->cp15.c0_c1[7] = cpu->id_mmfr3;
- env->cp15.c0_c2[0] = cpu->id_isar0;
- env->cp15.c0_c2[1] = cpu->id_isar1;
- env->cp15.c0_c2[2] = cpu->id_isar2;
- env->cp15.c0_c2[3] = cpu->id_isar3;
- env->cp15.c0_c2[4] = cpu->id_isar4;
- env->cp15.c0_c2[5] = cpu->id_isar5;
- env->cp15.c15_i_min = 0xff0;
- env->cp15.c0_clid = cpu->clidr;
- memcpy(env->cp15.c0_ccsid, cpu->ccsidr, ARRAY_SIZE(cpu->ccsidr));
-
- if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
- env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q';
- }
-
-#if defined (CONFIG_USER_ONLY)
- env->uncached_cpsr = ARM_CPU_MODE_USR;
- /* For user mode we must enable access to coprocessors */
- env->vfp.xregs[ARM_VFP_FPEXC] = 1 << 30;
- if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
- env->cp15.c15_cpar = 3;
- } else if (arm_feature(env, ARM_FEATURE_XSCALE)) {
- env->cp15.c15_cpar = 1;
- }
-#else
- /* SVC mode with interrupts disabled. */
- env->uncached_cpsr = ARM_CPU_MODE_SVC | CPSR_A | CPSR_F | CPSR_I;
- /* On ARMv7-M the CPSR_I is the value of the PRIMASK register, and is
- clear at reset. Initial SP and PC are loaded from ROM. */
- if (IS_M(env)) {
- uint32_t pc;
- uint8_t *rom;
- env->uncached_cpsr &= ~CPSR_I;
- rom = rom_ptr(0);
- if (rom) {
- /* We should really use ldl_phys here, in case the guest
- modified flash and reset itself. However images
- loaded via -kernel have not been copied yet, so load the
- values directly from there. */
- env->regs[13] = ldl_p(rom);
- pc = ldl_p(rom + 4);
- env->thumb = pc & 1;
- env->regs[15] = pc & ~1;
- }
- }
- env->vfp.xregs[ARM_VFP_FPEXC] = 0;
- env->cp15.c2_base_mask = 0xffffc000u;
- /* v7 performance monitor control register: same implementor
- * field as main ID register, and we implement no event counters.
- */
- env->cp15.c9_pmcr = (cpu->midr & 0xff000000);
-#endif
- set_flush_to_zero(1, &env->vfp.standard_fp_status);
- set_flush_inputs_to_zero(1, &env->vfp.standard_fp_status);
- set_default_nan_mode(1, &env->vfp.standard_fp_status);
- set_float_detect_tininess(float_tininess_before_rounding,
- &env->vfp.fp_status);
- set_float_detect_tininess(float_tininess_before_rounding,
- &env->vfp.standard_fp_status);
- tlb_flush(env, 1);
- /* Reset is a state change for some CPUARMState fields which we
- * bake assumptions about into translated code, so we need to
- * tb_flush().
- */
- tb_flush(env);
+ cpu_reset(ENV_GET_CPU(env));
}
static int vfp_gdb_get_reg(CPUARMState *env, uint8_t *buf, int reg)
--
1.7.1
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [Qemu-devel] [PATCH 14/14] target-arm: Move A9 config_base_address reset value to ARMCPU
2012-03-30 12:51 [Qemu-devel] [PATCH 00/14] target-arm: Create QOM subclass per CPU implementation Peter Maydell
` (12 preceding siblings ...)
2012-03-30 12:51 ` [Qemu-devel] [PATCH 13/14] target-arm: Move reset handling to arm_cpu_reset Peter Maydell
@ 2012-03-30 12:51 ` Peter Maydell
2012-03-30 17:01 ` Mark Langsdorf
13 siblings, 1 reply; 17+ messages in thread
From: Peter Maydell @ 2012-03-30 12:51 UTC (permalink / raw)
To: qemu-devel; +Cc: Paul Brook, Anthony Liguori, Andreas Färber
Move the A9 config_base_address cp15 register reset value to
ARMCPU. This should become a QOM property so that the Highbank
board can set it without having to pull in cpu-qom.h, but at
least this avoids the implicit dependency on reset ordering
that the previous workaround had.
Cc: Mark Langsdorf <mark.langsdorf@calxeda.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/highbank.c | 12 +++++-------
target-arm/cpu-qom.h | 1 +
target-arm/cpu.c | 4 +---
3 files changed, 7 insertions(+), 10 deletions(-)
diff --git a/hw/highbank.c b/hw/highbank.c
index 906eed5..b007f97 100644
--- a/hw/highbank.c
+++ b/hw/highbank.c
@@ -27,6 +27,7 @@
#include "sysbus.h"
#include "blockdev.h"
#include "exec-memory.h"
+#include "cpu-qom.h"
#define SMP_BOOT_ADDR 0x100
#define SMP_BOOT_REG 0x40
@@ -35,12 +36,6 @@
#define NIRQ_GIC 160
/* Board init. */
-static void highbank_cpu_reset(void *opaque)
-{
- CPUARMState *env = opaque;
-
- env->cp15.c15_config_base_address = GIC_BASE_ADDR;
-}
static void hb_write_secondary(CPUARMState *env, const struct arm_boot_info *info)
{
@@ -213,14 +208,17 @@ static void highbank_init(ram_addr_t ram_size,
}
for (n = 0; n < smp_cpus; n++) {
+ ARMCPU *cpu;
env = cpu_init(cpu_model);
if (!env) {
fprintf(stderr, "Unable to find CPU definition\n");
exit(1);
}
+ cpu = arm_env_get_cpu(env);
+ /* This will become a QOM property eventually */
+ cpu->reset_cbar = GIC_BASE_ADDR;
irqp = arm_pic_init_cpu(env);
cpu_irq[n] = irqp[ARM_PIC_CPU_IRQ];
- qemu_register_reset(highbank_cpu_reset, env);
}
sysmem = get_system_memory();
diff --git a/target-arm/cpu-qom.h b/target-arm/cpu-qom.h
index 55dc920..c42755a 100644
--- a/target-arm/cpu-qom.h
+++ b/target-arm/cpu-qom.h
@@ -84,6 +84,7 @@ typedef struct ARMCPU {
uint32_t id_isar5;
uint32_t clidr;
uint32_t ccsidr[16];
+ uint32_t reset_cbar;
} ARMCPU;
static inline ARMCPU *arm_env_get_cpu(CPUARMState *env)
diff --git a/target-arm/cpu.c b/target-arm/cpu.c
index 66f76a8..653e2b3 100644
--- a/target-arm/cpu.c
+++ b/target-arm/cpu.c
@@ -30,7 +30,6 @@ static void arm_cpu_reset(CPUState *s)
ARMCPU *cpu = ARM_CPU(s);
ARMCPUClass *acc = ARM_CPU_GET_CLASS(cpu);
CPUARMState *env = &cpu->env;
- uint32_t tmp = 0;
if (qemu_loglevel_mask(CPU_LOG_RESET)) {
qemu_log("CPU Reset (CPU %d)\n", env->cpu_index);
@@ -39,9 +38,8 @@ static void arm_cpu_reset(CPUState *s)
acc->parent_reset(s);
- tmp = env->cp15.c15_config_base_address;
memset(env, 0, offsetof(CPUARMState, breakpoints));
- env->cp15.c15_config_base_address = tmp;
+ env->cp15.c15_config_base_address = cpu->reset_cbar;
env->cp15.c0_cpuid = cpu->midr;
env->vfp.xregs[ARM_VFP_FPSID] = cpu->reset_fpsid;
env->vfp.xregs[ARM_VFP_MVFR0] = cpu->mvfr0;
--
1.7.1
^ permalink raw reply related [flat|nested] 17+ messages in thread
* Re: [Qemu-devel] [PATCH 14/14] target-arm: Move A9 config_base_address reset value to ARMCPU
2012-03-30 12:51 ` [Qemu-devel] [PATCH 14/14] target-arm: Move A9 config_base_address reset value to ARMCPU Peter Maydell
@ 2012-03-30 17:01 ` Mark Langsdorf
2012-03-30 17:04 ` Peter Maydell
0 siblings, 1 reply; 17+ messages in thread
From: Mark Langsdorf @ 2012-03-30 17:01 UTC (permalink / raw)
To: Peter Maydell
Cc: Andreas Färber, qemu-devel, Anthony Liguori, Paul Brook
Odd that I wasn't actually cc'd by the mailer on this.
Do you want me to pull together a patch to make it a QOM property now,
or is there some other dependency I should wait on? It may take me a
week or so to get time to pull it together and test it.
--Mark Langsdorf
Calxeda, Inc.
On 03/30/2012 07:51 AM, Peter Maydell wrote:
> Move the A9 config_base_address cp15 register reset value to
> ARMCPU. This should become a QOM property so that the Highbank
> board can set it without having to pull in cpu-qom.h, but at
> least this avoids the implicit dependency on reset ordering
> that the previous workaround had.
>
> Cc: Mark Langsdorf <mark.langsdorf@calxeda.com>
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
> ---
> hw/highbank.c | 12 +++++-------
> target-arm/cpu-qom.h | 1 +
> target-arm/cpu.c | 4 +---
> 3 files changed, 7 insertions(+), 10 deletions(-)
>
> diff --git a/hw/highbank.c b/hw/highbank.c
> index 906eed5..b007f97 100644
> --- a/hw/highbank.c
> +++ b/hw/highbank.c
> @@ -27,6 +27,7 @@
> #include "sysbus.h"
> #include "blockdev.h"
> #include "exec-memory.h"
> +#include "cpu-qom.h"
>
> #define SMP_BOOT_ADDR 0x100
> #define SMP_BOOT_REG 0x40
> @@ -35,12 +36,6 @@
> #define NIRQ_GIC 160
>
> /* Board init. */
> -static void highbank_cpu_reset(void *opaque)
> -{
> - CPUARMState *env = opaque;
> -
> - env->cp15.c15_config_base_address = GIC_BASE_ADDR;
> -}
>
> static void hb_write_secondary(CPUARMState *env, const struct arm_boot_info *info)
> {
> @@ -213,14 +208,17 @@ static void highbank_init(ram_addr_t ram_size,
> }
>
> for (n = 0; n < smp_cpus; n++) {
> + ARMCPU *cpu;
> env = cpu_init(cpu_model);
> if (!env) {
> fprintf(stderr, "Unable to find CPU definition\n");
> exit(1);
> }
> + cpu = arm_env_get_cpu(env);
> + /* This will become a QOM property eventually */
> + cpu->reset_cbar = GIC_BASE_ADDR;
> irqp = arm_pic_init_cpu(env);
> cpu_irq[n] = irqp[ARM_PIC_CPU_IRQ];
> - qemu_register_reset(highbank_cpu_reset, env);
> }
>
> sysmem = get_system_memory();
> diff --git a/target-arm/cpu-qom.h b/target-arm/cpu-qom.h
> index 55dc920..c42755a 100644
> --- a/target-arm/cpu-qom.h
> +++ b/target-arm/cpu-qom.h
> @@ -84,6 +84,7 @@ typedef struct ARMCPU {
> uint32_t id_isar5;
> uint32_t clidr;
> uint32_t ccsidr[16];
> + uint32_t reset_cbar;
> } ARMCPU;
>
> static inline ARMCPU *arm_env_get_cpu(CPUARMState *env)
> diff --git a/target-arm/cpu.c b/target-arm/cpu.c
> index 66f76a8..653e2b3 100644
> --- a/target-arm/cpu.c
> +++ b/target-arm/cpu.c
> @@ -30,7 +30,6 @@ static void arm_cpu_reset(CPUState *s)
> ARMCPU *cpu = ARM_CPU(s);
> ARMCPUClass *acc = ARM_CPU_GET_CLASS(cpu);
> CPUARMState *env = &cpu->env;
> - uint32_t tmp = 0;
>
> if (qemu_loglevel_mask(CPU_LOG_RESET)) {
> qemu_log("CPU Reset (CPU %d)\n", env->cpu_index);
> @@ -39,9 +38,8 @@ static void arm_cpu_reset(CPUState *s)
>
> acc->parent_reset(s);
>
> - tmp = env->cp15.c15_config_base_address;
> memset(env, 0, offsetof(CPUARMState, breakpoints));
> - env->cp15.c15_config_base_address = tmp;
> + env->cp15.c15_config_base_address = cpu->reset_cbar;
> env->cp15.c0_cpuid = cpu->midr;
> env->vfp.xregs[ARM_VFP_FPSID] = cpu->reset_fpsid;
> env->vfp.xregs[ARM_VFP_MVFR0] = cpu->mvfr0;
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [Qemu-devel] [PATCH 14/14] target-arm: Move A9 config_base_address reset value to ARMCPU
2012-03-30 17:01 ` Mark Langsdorf
@ 2012-03-30 17:04 ` Peter Maydell
0 siblings, 0 replies; 17+ messages in thread
From: Peter Maydell @ 2012-03-30 17:04 UTC (permalink / raw)
To: Mark Langsdorf
Cc: Andreas Färber, qemu-devel, Anthony Liguori, Paul Brook
On 30 March 2012 18:01, Mark Langsdorf <mark.langsdorf@calxeda.com> wrote:
> Odd that I wasn't actually cc'd by the mailer on this.
Oops, sorry, that's my fault. I added the 'cc' to the patch commit
message but forgot to tweak my git-send-email command line to honour
that.
> Do you want me to pull together a patch to make it a QOM property now,
> or is there some other dependency I should wait on? It may take me a
> week or so to get time to pull it together and test it.
We need realize support in QOM base classes first, so we have somewhere
we can put code which runs after properties have been set. That's
why this version is still using this slightly hacky approach.
-- PMM
^ permalink raw reply [flat|nested] 17+ messages in thread
end of thread, other threads:[~2012-03-30 17:05 UTC | newest]
Thread overview: 17+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2012-03-30 12:51 [Qemu-devel] [PATCH 00/14] target-arm: Create QOM subclass per CPU implementation Peter Maydell
2012-03-30 12:51 ` [Qemu-devel] [PATCH 01/14] target-arm: Add QOM subclasses for each ARM cpu implementation Peter Maydell
2012-03-30 12:51 ` [Qemu-devel] [PATCH 02/14] target-arm: Move feature bit settings to CPU init fns Peter Maydell
2012-03-30 12:51 ` [Qemu-devel] [PATCH 03/14] target-arm: Move FPSID config to cpu " Peter Maydell
2012-03-30 12:51 ` [Qemu-devel] [PATCH 04/14] target-arm: Move MVFR* setup to per " Peter Maydell
2012-03-30 12:51 ` [Qemu-devel] [PATCH 05/14] target-arm: Move CTR " Peter Maydell
2012-03-30 12:51 ` [Qemu-devel] [PATCH 06/14] target-arm: Move SCTLR reset value " Peter Maydell
2012-03-30 12:51 ` [Qemu-devel] [PATCH 07/14] target-arm: Drop JTAG_ID documentation Peter Maydell
2012-03-30 12:51 ` [Qemu-devel] [PATCH 08/14] target-arm: Move iWMMXT wCID reset to cpu_state_reset Peter Maydell
2012-03-30 12:51 ` [Qemu-devel] [PATCH 09/14] target-arm: Move feature register setup to per-CPU init fns Peter Maydell
2012-03-30 12:51 ` [Qemu-devel] [PATCH 10/14] target-arm: Move OMAP cp15_i_{max, min} reset to cpu_state_reset Peter Maydell
2012-03-30 12:51 ` [Qemu-devel] [PATCH 11/14] target-arm: Move cache ID register setup to cpu specific init fns Peter Maydell
2012-03-30 12:51 ` [Qemu-devel] [PATCH 12/14] target-arm: Drop cpu_reset_model_id() Peter Maydell
2012-03-30 12:51 ` [Qemu-devel] [PATCH 13/14] target-arm: Move reset handling to arm_cpu_reset Peter Maydell
2012-03-30 12:51 ` [Qemu-devel] [PATCH 14/14] target-arm: Move A9 config_base_address reset value to ARMCPU Peter Maydell
2012-03-30 17:01 ` Mark Langsdorf
2012-03-30 17:04 ` Peter Maydell
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