From: Peter Maydell <peter.maydell@linaro.org>
To: Alistair Francis <alistair.francis@opensource.wdc.com>
Cc: alistair23@gmail.com, Alistair Francis <alistair.francis@wdc.com>,
qemu-devel@nongnu.org
Subject: Re: [PULL 0/2] riscv-to-apply queue
Date: Fri, 1 Apr 2022 17:16:29 +0100 [thread overview]
Message-ID: <CAFEAcA9uP+ZpetBCdGU=4mcVgXeHbUUiuEVV=WfdpM7+g5fvig@mail.gmail.com> (raw)
In-Reply-To: <20220331234441.15920-1-alistair.francis@opensource.wdc.com>
On Fri, 1 Apr 2022 at 00:50, Alistair Francis
<alistair.francis@opensource.wdc.com> wrote:
>
> From: Alistair Francis <alistair.francis@wdc.com>
>
> The following changes since commit d5341e09135b871199073572f53bc11ae9b44897:
>
> Merge tag 'pull-tcg-20220331' of https://gitlab.com/rth7680/qemu into staging (2022-03-31 18:36:08 +0100)
>
> are available in the Git repository at:
>
> git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20220401
>
> for you to fetch changes up to 8ff8ac63298611c8373b294ec936475b1a33f63f:
>
> target/riscv: rvv: Add missing early exit condition for whole register load/store (2022-04-01 08:40:55 +1000)
>
> ----------------------------------------------------------------
> Sixth RISC-V PR for QEMU 7.0
>
> This is a last minute RISC-V PR for 7.0.
>
> It includes a fix to avoid leaking no translation TLB entries. This
> incorrectly cached uncachable baremetal entries. This would break Linux
> boot while single stepping. As the fix is pretty straight forward (flush
> the cache more often) it's being pulled in for 7.0.
>
> At the same time I have included a RISC-V vector extension fixup patch.
>
> ----------------------------------------------------------------
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/7.0
for any user-visible changes.
-- PMM
next prev parent reply other threads:[~2022-04-01 16:18 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-03-31 23:44 [PULL 0/2] riscv-to-apply queue Alistair Francis
2022-03-31 23:44 ` [PULL 1/2] target/riscv: Avoid leaking "no translation" TLB entries Alistair Francis
2022-03-31 23:44 ` [PULL 2/2] target/riscv: rvv: Add missing early exit condition for whole register load/store Alistair Francis
2022-04-01 16:16 ` Peter Maydell [this message]
-- strict thread matches above, loose matches on Subject: below --
2023-08-11 18:24 [PULL 0/2] riscv-to-apply queue Alistair Francis
2023-08-12 1:16 ` Richard Henderson
2023-03-14 6:38 Alistair Francis
2023-03-14 19:21 ` Peter Maydell
2022-07-28 0:59 Alistair Francis
2022-07-28 18:27 ` Richard Henderson
2021-11-22 6:52 Alistair Francis
2021-11-22 9:32 ` Richard Henderson
2021-11-17 9:20 Alistair Francis
2021-11-17 11:34 ` Richard Henderson
2020-11-14 5:45 Alistair Francis
2020-11-14 15:25 ` Peter Maydell
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