All of lore.kernel.org
 help / color / mirror / Atom feed
From: Peter Maydell <peter.maydell@linaro.org>
To: "Daniel P. Berrangé" <berrange@redhat.com>
Cc: Michael Clark <mjc@sifive.com>,
	QEMU Developers <qemu-devel@nongnu.org>,
	Bastian Koppelmann <kbastian@mail.uni-paderborn.de>,
	Palmer Dabbelt <palmer@sifive.com>,
	Sagar Karandikar <sagark@eecs.berkeley.edu>,
	RISC-V Patches <patches@groups.riscv.org>
Subject: Re: [Qemu-devel] [PATCH v6 00/23] RISC-V QEMU Port Submission
Date: Mon, 26 Feb 2018 11:57:10 +0000	[thread overview]
Message-ID: <CAFEAcA_Gwh3EpVVhZ_zU3LuogZXjh8cpRWrvtHbNdfgQmdzgJg@mail.gmail.com> (raw)
In-Reply-To: <20180226104723.GH14196@redhat.com>

On 26 February 2018 at 10:47, Daniel P. Berrangé <berrange@redhat.com> wrote:
> I accept that MIT is compatible with GPLv2+, so that's not an immediate legal
> problem. The issue is that as we add more & more different licenses to QEMU,
> it becomes a maintenance burden to developers, especially when doing code
> refactoring across files. You have to be careful you're not taking a piece
> of GPLv2+ code and copying/moving it into a file that's MIT licensed, as
> that would be non-compliant. We already suffer this problem with our mixture
> of GPLv2-only and GPLv2+ and LGPLv2+ and BSD licensed code. So I'm personally
> loathe to see us add yet another license to the mix.

Unless I'm confused, we already have a lot of MIT-licensed code in the tree,
including much of the block layer, accel/tcg, the audio subsystem. Looking
at vl.c, it was put under the MIT license by Fabrice in 2003, so we've
been living with it as part of our licensing mix for a very long time already.

thanks
-- PMM

  reply	other threads:[~2018-02-26 11:57 UTC|newest]

Thread overview: 40+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-02-23  0:11 [Qemu-devel] [PATCH v6 00/23] RISC-V QEMU Port Submission Michael Clark
2018-02-23  0:11 ` [Qemu-devel] [PATCH v6 01/23] RISC-V Maintainers Michael Clark
2018-02-23  0:11 ` [Qemu-devel] [PATCH v6 02/23] RISC-V ELF Machine Definition Michael Clark
2018-02-23  0:11 ` [Qemu-devel] [PATCH v6 03/23] RISC-V CPU Core Definition Michael Clark
2018-02-26 15:52   ` Igor Mammedov
2018-02-23  0:11 ` [Qemu-devel] [PATCH v6 04/23] RISC-V Disassembler Michael Clark
2018-02-23  0:11 ` [Qemu-devel] [PATCH v6 05/23] RISC-V CPU Helpers Michael Clark
2018-02-23  0:11 ` [Qemu-devel] [PATCH v6 06/23] RISC-V FPU Support Michael Clark
2018-02-23  0:11 ` [Qemu-devel] [PATCH v6 07/23] RISC-V GDB Stub Michael Clark
2018-02-23  0:11 ` [Qemu-devel] [PATCH v6 08/23] RISC-V TCG Code Generation Michael Clark
2018-02-23  0:11 ` [Qemu-devel] [PATCH v6 09/23] RISC-V Physical Memory Protection Michael Clark
2018-02-23  0:11 ` [Qemu-devel] [PATCH v6 10/23] RISC-V Linux User Emulation Michael Clark
2018-02-23  0:11 ` [Qemu-devel] [PATCH v6 11/23] Add symbol table callback function interface to load_elf Michael Clark
2018-02-23 21:19   ` Richard Henderson
2018-02-23  0:11 ` [Qemu-devel] [PATCH v6 12/23] RISC-V HTIF Console Michael Clark
2018-02-23 21:24   ` Richard Henderson
2018-02-23  0:11 ` [Qemu-devel] [PATCH v6 13/23] RISC-V HART Array Michael Clark
2018-02-23  0:12 ` [Qemu-devel] [PATCH v6 14/23] SiFive RISC-V CLINT Block Michael Clark
2018-02-23  0:12 ` [Qemu-devel] [PATCH v6 15/23] SiFive RISC-V PLIC Block Michael Clark
2018-02-23  0:12 ` [Qemu-devel] [PATCH v6 16/23] RISC-V Spike Machines Michael Clark
2018-02-23  0:12 ` [Qemu-devel] [PATCH v6 17/23] RISC-V VirtIO Machine Michael Clark
2018-02-23  0:12 ` [Qemu-devel] [PATCH v6 18/23] SiFive RISC-V UART Device Michael Clark
2018-02-23  0:12 ` [Qemu-devel] [PATCH v6 19/23] SiFive RISC-V PRCI Block Michael Clark
2018-02-23  0:12 ` [Qemu-devel] [PATCH v6 20/23] SiFive RISC-V Test Finisher Michael Clark
2018-02-23  0:12 ` [Qemu-devel] [PATCH v6 21/23] SiFive Freedom E300 RISC-V Machine Michael Clark
2018-02-23  0:12 ` [Qemu-devel] [PATCH v6 22/23] SiFive Freedom U500 " Michael Clark
2018-02-23  0:12 ` [Qemu-devel] [PATCH v6 23/23] RISC-V Build Infrastructure Michael Clark
2018-02-23  0:39 ` [Qemu-devel] [PATCH v6 00/23] RISC-V QEMU Port Submission no-reply
2018-02-23 10:10 ` Daniel P. Berrangé
2018-02-23 20:05   ` Michael Clark
2018-02-26 10:47     ` Daniel P. Berrangé
2018-02-26 11:57       ` Peter Maydell [this message]
2018-02-26 12:03         ` Daniel P. Berrangé
2018-02-26 12:32           ` Peter Maydell
2018-02-26 13:03             ` Laurent Desnogues
2018-02-23 21:31 ` Richard Henderson
2018-02-23 22:24   ` Michael Clark
2018-02-24 16:18 ` no-reply
2018-02-26 11:30 ` Richard W.M. Jones
2018-02-26 11:56 ` Andreas Schwab

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=CAFEAcA_Gwh3EpVVhZ_zU3LuogZXjh8cpRWrvtHbNdfgQmdzgJg@mail.gmail.com \
    --to=peter.maydell@linaro.org \
    --cc=berrange@redhat.com \
    --cc=kbastian@mail.uni-paderborn.de \
    --cc=mjc@sifive.com \
    --cc=palmer@sifive.com \
    --cc=patches@groups.riscv.org \
    --cc=qemu-devel@nongnu.org \
    --cc=sagark@eecs.berkeley.edu \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.