[Qemu-devel] [PATCH v6 02/23] RISC-V ELF Machine Definition

From: Michael Clark <mjc@sifive.com>
To: qemu-devel@nongnu.org
Cc: Michael Clark <mjc@sifive.com>,
	Palmer Dabbelt <palmer@sifive.com>,
	Sagar Karandikar <sagark@eecs.berkeley.edu>,
	Bastian Koppelmann <kbastian@mail.uni-paderborn.de>,
	RISC-V Patches <patches@groups.riscv.org>
Subject: [Qemu-devel] [PATCH v6 02/23] RISC-V ELF Machine Definition
Date: Fri, 23 Feb 2018 13:11:48 +1300	[thread overview]
Message-ID: <1519344729-73482-3-git-send-email-mjc@sifive.com> (raw)
In-Reply-To: <1519344729-73482-1-git-send-email-mjc@sifive.com>

Define RISC-V ELF machine EM_RISCV 243

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
Signed-off-by: Michael Clark <mjc@sifive.com>
---
 include/elf.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/include/elf.h b/include/elf.h
index e8a515c..8e457fc 100644
--- a/include/elf.h
+++ b/include/elf.h
@@ -112,6 +112,8 @@ typedef int64_t  Elf64_Sxword;
 
 #define EM_UNICORE32    110     /* UniCore32 */
 
+#define EM_RISCV        243     /* RISC-V */
+
 /*
  * This is an interim value that we will use until the committee comes
  * up with a final number.
-- 
2.7.0
