[Qemu-devel] [RESEND PATCH] target/arm: change arch timer registers access permission

[Qemu-devel] [RESEND PATCH] target/arm: change arch timer registers access permission

[gengdongjiu]

From: Dongjiu Geng <gengdongjiu@huawei.com>

Some generic arch timer registers are Config-RW in the EL0,
which means the EL0 exception level can have write permission
if it is appropriately configured.

When VM access registers, it firstly checks whether they have RW
permission, then check whether it is appropriately configured.
If they are defined to Ready only in EL0, even though they have been
appropriately configured, they still do not have write permission.
So need to add the write permission according to ARMV8 spec when
define it.

Signed-off-by: Dongjiu Geng <gengdongjiu@huawei.com>
---
When kernel or Hypervisor configures the timer registers to RW in EL0
user space, it will still have below panic when EL0 user space access
the timer registers.

[INFO ]@(el0_sync:60): UNIMPLEMENTED, esr=2000000
[INFO ]@(unimpl_exception:88): KERNEL UNIMPLEMENTED EXCEPTION
[INFO ]@(unimpl_exception:98): FAR=0000000000000000, ESR=02000000 (EC=0x0, IL=0x1, ISS=0x0)
[INFO ]@(dump_registers:64): KERNEL REGISTERS
[INFO ]@(dump_registers:68): X0=00000000f52b7d50 X1=00000000040d5040
[INFO ]@(dump_registers:68): X2=0000004000033e10 X3=0000000000000000
[INFO ]@(dump_registers:68): X4=000000007fffffff X5=0000000000000020
[INFO ]@(dump_registers:68): X6=0000000000000020 X7=000000000c00b030
---
 target/arm/helper.c | 30 +++++++++++++++---------------
 1 file changed, 15 insertions(+), 15 deletions(-)

diff --git a/target/arm/helper.c b/target/arm/helper.c
index 2607d39..3db94c6 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -2665,7 +2665,7 @@ static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
     /* per-timer control */
     { .name = "CNTP_CTL", .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 1,
       .secure = ARM_CP_SECSTATE_NS,
-      .type = ARM_CP_IO | ARM_CP_ALIAS, .access = PL1_RW | PL0_R,
+      .type = ARM_CP_IO | ARM_CP_ALIAS, .access = PL1_RW | PL0_RW,
       .accessfn = gt_ptimer_access,
       .fieldoffset = offsetoflow32(CPUARMState,
                                    cp15.c14_timer[GTIMER_PHYS].ctl),
@@ -2674,7 +2674,7 @@ static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
     { .name = "CNTP_CTL_S",
       .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 1,
       .secure = ARM_CP_SECSTATE_S,
-      .type = ARM_CP_IO | ARM_CP_ALIAS, .access = PL1_RW | PL0_R,
+      .type = ARM_CP_IO | ARM_CP_ALIAS, .access = PL1_RW | PL0_RW,
       .accessfn = gt_ptimer_access,
       .fieldoffset = offsetoflow32(CPUARMState,
                                    cp15.c14_timer[GTIMER_SEC].ctl),
@@ -2682,14 +2682,14 @@ static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
     },
     { .name = "CNTP_CTL_EL0", .state = ARM_CP_STATE_AA64,
       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 2, .opc2 = 1,
-      .type = ARM_CP_IO, .access = PL1_RW | PL0_R,
+      .type = ARM_CP_IO, .access = PL1_RW | PL0_RW,
       .accessfn = gt_ptimer_access,
       .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].ctl),
       .resetvalue = 0,
       .writefn = gt_phys_ctl_write, .raw_writefn = raw_write,
     },
     { .name = "CNTV_CTL", .cp = 15, .crn = 14, .crm = 3, .opc1 = 0, .opc2 = 1,
-      .type = ARM_CP_IO | ARM_CP_ALIAS, .access = PL1_RW | PL0_R,
+      .type = ARM_CP_IO | ARM_CP_ALIAS, .access = PL1_RW | PL0_RW,
       .accessfn = gt_vtimer_access,
       .fieldoffset = offsetoflow32(CPUARMState,
                                    cp15.c14_timer[GTIMER_VIRT].ctl),
@@ -2697,7 +2697,7 @@ static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
     },
     { .name = "CNTV_CTL_EL0", .state = ARM_CP_STATE_AA64,
       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 3, .opc2 = 1,
-      .type = ARM_CP_IO, .access = PL1_RW | PL0_R,
+      .type = ARM_CP_IO, .access = PL1_RW | PL0_RW,
       .accessfn = gt_vtimer_access,
       .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].ctl),
       .resetvalue = 0,
@@ -2706,31 +2706,31 @@ static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
     /* TimerValue views: a 32 bit downcounting view of the underlying state */
     { .name = "CNTP_TVAL", .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 0,
       .secure = ARM_CP_SECSTATE_NS,
-      .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL1_RW | PL0_R,
+      .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL1_RW | PL0_RW,
       .accessfn = gt_ptimer_access,
       .readfn = gt_phys_tval_read, .writefn = gt_phys_tval_write,
     },
     { .name = "CNTP_TVAL_S",
       .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 0,
       .secure = ARM_CP_SECSTATE_S,
-      .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL1_RW | PL0_R,
+      .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL1_RW | PL0_RW,
       .accessfn = gt_ptimer_access,
       .readfn = gt_sec_tval_read, .writefn = gt_sec_tval_write,
     },
     { .name = "CNTP_TVAL_EL0", .state = ARM_CP_STATE_AA64,
       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 2, .opc2 = 0,
-      .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL1_RW | PL0_R,
+      .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL1_RW | PL0_RW,
       .accessfn = gt_ptimer_access, .resetfn = gt_phys_timer_reset,
       .readfn = gt_phys_tval_read, .writefn = gt_phys_tval_write,
     },
     { .name = "CNTV_TVAL", .cp = 15, .crn = 14, .crm = 3, .opc1 = 0, .opc2 = 0,
-      .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL1_RW | PL0_R,
+      .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL1_RW | PL0_RW,
       .accessfn = gt_vtimer_access,
       .readfn = gt_virt_tval_read, .writefn = gt_virt_tval_write,
     },
     { .name = "CNTV_TVAL_EL0", .state = ARM_CP_STATE_AA64,
       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 3, .opc2 = 0,
-      .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL1_RW | PL0_R,
+      .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL1_RW | PL0_RW,
       .accessfn = gt_vtimer_access, .resetfn = gt_virt_timer_reset,
       .readfn = gt_virt_tval_read, .writefn = gt_virt_tval_write,
     },
@@ -2758,7 +2758,7 @@ static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
     /* Comparison value, indicating when the timer goes off */
     { .name = "CNTP_CVAL", .cp = 15, .crm = 14, .opc1 = 2,
       .secure = ARM_CP_SECSTATE_NS,
-      .access = PL1_RW | PL0_R,
+      .access = PL1_RW | PL0_RW,
       .type = ARM_CP_64BIT | ARM_CP_IO | ARM_CP_ALIAS,
       .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].cval),
       .accessfn = gt_ptimer_access,
@@ -2766,7 +2766,7 @@ static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
     },
     { .name = "CNTP_CVAL_S", .cp = 15, .crm = 14, .opc1 = 2,
       .secure = ARM_CP_SECSTATE_S,
-      .access = PL1_RW | PL0_R,
+      .access = PL1_RW | PL0_RW,
       .type = ARM_CP_64BIT | ARM_CP_IO | ARM_CP_ALIAS,
       .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_SEC].cval),
       .accessfn = gt_ptimer_access,
@@ -2774,14 +2774,14 @@ static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
     },
     { .name = "CNTP_CVAL_EL0", .state = ARM_CP_STATE_AA64,
       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 2, .opc2 = 2,
-      .access = PL1_RW | PL0_R,
+      .access = PL1_RW | PL0_RW,
       .type = ARM_CP_IO,
       .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].cval),
       .resetvalue = 0, .accessfn = gt_ptimer_access,
       .writefn = gt_phys_cval_write, .raw_writefn = raw_write,
     },
     { .name = "CNTV_CVAL", .cp = 15, .crm = 14, .opc1 = 3,
-      .access = PL1_RW | PL0_R,
+      .access = PL1_RW | PL0_RW,
       .type = ARM_CP_64BIT | ARM_CP_IO | ARM_CP_ALIAS,
       .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].cval),
       .accessfn = gt_vtimer_access,
@@ -2789,7 +2789,7 @@ static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
     },
     { .name = "CNTV_CVAL_EL0", .state = ARM_CP_STATE_AA64,
       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 3, .opc2 = 2,
-      .access = PL1_RW | PL0_R,
+      .access = PL1_RW | PL0_RW,
       .type = ARM_CP_IO,
       .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].cval),
       .resetvalue = 0, .accessfn = gt_vtimer_access,
-- 
2.7.4

Re: [Qemu-devel] [RESEND PATCH] target/arm: change arch timer registers access permission

[Peter Maydell]

On Mon, 11 Mar 2019 at 08:29, gengdongjiu <gengdongjiu@huawei.com> wrote:
>
> From: Dongjiu Geng <gengdongjiu@huawei.com>
>
> Some generic arch timer registers are Config-RW in the EL0,
> which means the EL0 exception level can have write permission
> if it is appropriately configured.
>
> When VM access registers, it firstly checks whether they have RW
> permission, then check whether it is appropriately configured.
> If they are defined to Ready only in EL0, even though they have been

"read only" ?

> appropriately configured, they still do not have write permission.
> So need to add the write permission according to ARMV8 spec when
> define it.
>
> Signed-off-by: Dongjiu Geng <gengdongjiu@huawei.com>

Yes, this seems to be a bug which has been present since
I added the generic timer support in commit 55d284af8e31b in 2013.

I'm not sure why the bug is there -- my best guess is that I
incorrectly copied the permission flags from the CNTFRQ register
(which really is RO from PL0 but RW from PL1 and above) to
these other registers which should be fully RW from PL0.

> diff --git a/target/arm/helper.c b/target/arm/helper.c
> index 2607d39..3db94c6 100644
> --- a/target/arm/helper.c
> +++ b/target/arm/helper.c
> @@ -2665,7 +2665,7 @@ static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
>      /* per-timer control */
>      { .name = "CNTP_CTL", .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 1,
>        .secure = ARM_CP_SECSTATE_NS,
> -      .type = ARM_CP_IO | ARM_CP_ALIAS, .access = PL1_RW | PL0_R,
> +      .type = ARM_CP_IO | ARM_CP_ALIAS, .access = PL1_RW | PL0_RW,

The PLx_{R,W,RW} constants all imply access is also possible from
the higher PLs, so this can just be written ".access = PL0_RW".

thanks
-- PMM

Re: [Qemu-devel] [RESEND PATCH] target/arm: change arch timer registers access permission

[gengdongjiu]

understand now，thanks for the explaination, I will update it.
发件人：Peter Maydell <peter.maydell@linaro.org>
收件人：gengdongjiu <gengdongjiu@huawei.com>
抄 送：qemu-arm <qemu-arm@nongnu.org>;QEMU Developers <qemu-devel@nongnu.org>
时间：2019-03-11 23:39:32
主 题：Re: [RESEND PATCH] target/arm: change arch timer registers access permission

On Mon, 11 Mar 2019 at 15:24, gengdongjiu <gengdongjiu@huawei.com> wrote:
> So If QEMU defined the timer registers read only in PL0, even though it has been configured to have write permission in PL0 by high PLx, we still cannot have
> Write permission, because QEMU will firstly check the defined permission and then check the configured permission by high PLx.

I'm afraid I don't understand what you're trying to say here.

Yes, it was a bug that we marked these registers as read-only for PL0,
and we should fix it.

What I am trying to say is that
 .access = PL1_RW | PL0_RW

is exactly equivalent to
 .access = PL0_RW

and we should use the simpler version of the expression.

(If you look at the definitions of all the PL*_ constants,
you can see that PL0_W implies PL1_W:
#define PL0_W (0x01 | PL1_W)
and similarly for PL0_R. So all the bits in the bitfield that would be
set by PL1_RW are also set by PL0_RW.)

thanks
-- PMM

Re: [Qemu-devel] [RESEND PATCH] target/arm: change arch timer registers access permission

[Peter Maydell]

On Mon, 11 Mar 2019 at 15:24, gengdongjiu <gengdongjiu@huawei.com> wrote:
> So If QEMU defined the timer registers read only in PL0, even though it has been configured to have write permission in PL0 by high PLx, we still cannot have
> Write permission, because QEMU will firstly check the defined permission and then check the configured permission by high PLx.

I'm afraid I don't understand what you're trying to say here.

Yes, it was a bug that we marked these registers as read-only for PL0,
and we should fix it.

What I am trying to say is that
 .access = PL1_RW | PL0_RW

is exactly equivalent to
 .access = PL0_RW

and we should use the simpler version of the expression.

(If you look at the definitions of all the PL*_ constants,
you can see that PL0_W implies PL1_W:
#define PL0_W (0x01 | PL1_W)
and similarly for PL0_R. So all the bits in the bitfield that would be
set by PL1_RW are also set by PL0_RW.)

thanks
-- PMM

Re: [Qemu-devel] [RESEND PATCH] target/arm: change arch timer registers access permission

[gengdongjiu]

> Hi Peter,
>    Thanks for the review.
> 
> > >
> > > From: Dongjiu Geng <gengdongjiu@huawei.com>
> > >
> > > Some generic arch timer registers are Config-RW in the EL0, which
> > > means the EL0 exception level can have write permission if it is
> > > appropriately configured.
> > >
> > > When VM access registers, it firstly checks whether they have RW
> > > permission, then check whether it is appropriately configured.
> > > If they are defined to Ready only in EL0, even though they have been
> >
> > "read only" ?
> Yes, read only.
> 
> >
> > > appropriately configured, they still do not have write permission.
> > > So need to add the write permission according to ARMV8 spec when
> > > define it.
> > >
> > > Signed-off-by: Dongjiu Geng <gengdongjiu@huawei.com>
> >
> > Yes, this seems to be a bug which has been present since I added the generic timer support in commit 55d284af8e31b in 2013.
> >
> > I'm not sure why the bug is there -- my best guess is that I
> > incorrectly copied the permission flags from the CNTFRQ register (which really is RO from PL0 but RW from PL1 and above) to these other
> registers which should be fully RW from PL0.
> 
> The current logic is show below[1], handle_sys() will check whether the system register have write permission in PL0, if have, then check
> whether It have been configured in the high PLx by ri->accessfn().

So If QEMU defined the timer registers read only in PL0, even though it has been configured to have write permission in PL0 by high PLx, we still cannot have
Write permission, because QEMU will firstly check the defined permission and then check the configured permission by high PLx.

> 
> 
> [1]:
> handle_sys()
>     ------> cp_access_ok(s->current_el, ri, isread)
>     ------> gen_helper_access_check_cp_reg()
>            ----->ri->accessfn()
> 
> [2]:
> -----------------------------------------------------------------------------------------------------------------------
> static void handle_sys(DisasContext *s, uint32_t insn, bool isread,
>                        unsigned int op0, unsigned int op1, unsigned int op2,
>                        unsigned int crn, unsigned int crm, unsigned int rt) {
> 
>     ---------------------------------------------------------------------------
>        /* Check access permissions */
>     if (!cp_access_ok(s->current_el, ri, isread)) {
>         unallocated_encoding(s);
>         return;
>     }
> 
>     if (ri->accessfn) {
>         ..............................
>         gen_helper_access_check_cp_reg(cpu_env, tmpptr, tcg_syn, tcg_isread);
>         ..............................
> 	}
>     -------------------------------------------
> }
> 
> 
> 
> >
> > > diff --git a/target/arm/helper.c b/target/arm/helper.c index
> > > 2607d39..3db94c6 100644
> > > --- a/target/arm/helper.c
> > > +++ b/target/arm/helper.c
> > > @@ -2665,7 +2665,7 @@ static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
> > >      /* per-timer control */
> > >      { .name = "CNTP_CTL", .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 1,
> > >        .secure = ARM_CP_SECSTATE_NS,
> > > -      .type = ARM_CP_IO | ARM_CP_ALIAS, .access = PL1_RW | PL0_R,
> > > +      .type = ARM_CP_IO | ARM_CP_ALIAS, .access = PL1_RW | PL0_RW,
> >
> > The PLx_{R,W,RW} constants all imply access is also possible from the higher PLs, so this can just be written ".access = PL0_RW".
> 
> Ok, I will uses your suggested method and to see whether it can be workable.
> 
> >
> > thanks
> > -- PMM

Re: [Qemu-devel] [RESEND PATCH] target/arm: change arch timer registers access permission

[gengdongjiu]

Hi Peter,
   Thanks for the review.

> >
> > From: Dongjiu Geng <gengdongjiu@huawei.com>
> >
> > Some generic arch timer registers are Config-RW in the EL0, which
> > means the EL0 exception level can have write permission if it is
> > appropriately configured.
> >
> > When VM access registers, it firstly checks whether they have RW
> > permission, then check whether it is appropriately configured.
> > If they are defined to Ready only in EL0, even though they have been
> 
> "read only" ?
Yes, read only.

> 
> > appropriately configured, they still do not have write permission.
> > So need to add the write permission according to ARMV8 spec when
> > define it.
> >
> > Signed-off-by: Dongjiu Geng <gengdongjiu@huawei.com>
> 
> Yes, this seems to be a bug which has been present since I added the generic timer support in commit 55d284af8e31b in 2013.
> 
> I'm not sure why the bug is there -- my best guess is that I incorrectly copied the permission flags from the CNTFRQ register (which really is
> RO from PL0 but RW from PL1 and above) to these other registers which should be fully RW from PL0.

The current logic is show below[1], handle_sys() will check whether the system register have write permission in PL0, if have, then check whether
It have been configured in the high PLx by ri->accessfn()


[1]:
handle_sys()
    ------> cp_access_ok(s->current_el, ri, isread)
    ------> gen_helper_access_check_cp_reg()
           ----->ri->accessfn()

[2]:
-----------------------------------------------------------------------------------------------------------------------
static void handle_sys(DisasContext *s, uint32_t insn, bool isread,
                       unsigned int op0, unsigned int op1, unsigned int op2,
                       unsigned int crn, unsigned int crm, unsigned int rt)
{
   
    ---------------------------------------------------------------------------
       /* Check access permissions */
    if (!cp_access_ok(s->current_el, ri, isread)) {
        unallocated_encoding(s);
        return;
    }

    if (ri->accessfn) {
        ..............................
        gen_helper_access_check_cp_reg(cpu_env, tmpptr, tcg_syn, tcg_isread);
        ..............................
	}
    -------------------------------------------
}



> 
> > diff --git a/target/arm/helper.c b/target/arm/helper.c index
> > 2607d39..3db94c6 100644
> > --- a/target/arm/helper.c
> > +++ b/target/arm/helper.c
> > @@ -2665,7 +2665,7 @@ static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
> >      /* per-timer control */
> >      { .name = "CNTP_CTL", .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 1,
> >        .secure = ARM_CP_SECSTATE_NS,
> > -      .type = ARM_CP_IO | ARM_CP_ALIAS, .access = PL1_RW | PL0_R,
> > +      .type = ARM_CP_IO | ARM_CP_ALIAS, .access = PL1_RW | PL0_RW,
> 
> The PLx_{R,W,RW} constants all imply access is also possible from the higher PLs, so this can just be written ".access = PL0_RW".

Ok, I will uses your suggested method and to see whether it can be workable.

> 
> thanks
> -- PMM