* [PATCH] target/arm: Init GIC CPU IF regs for A15/A7
@ 2020-05-29 23:06 Adam Lackorzynski
2020-06-01 12:36 ` Peter Maydell
0 siblings, 1 reply; 4+ messages in thread
From: Adam Lackorzynski @ 2020-05-29 23:06 UTC (permalink / raw)
To: qemu-devel, Peter Maydell
Initialize the CPU interface registers also
for Cortex-A15 and Cortex-A7 CPU models, in
the same way as done for 64bit CPU models.
This fixes usage of GICv3 in virtualization
contexts in 32bit configurations.
Signed-off-by: Adam Lackorzynski <adam@l4re.org>
---
target/arm/cpu.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 32bec156f2..f525d45f6a 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -1972,6 +1972,9 @@ static void cortex_a7_initfn(Object *obj)
cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */
cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */
cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */
+ cpu->gic_num_lrs = 4;
+ cpu->gic_vpribits = 5;
+ cpu->gic_vprebits = 5;
define_arm_cp_regs(cpu, cortexa15_cp_reginfo); /* Same as A15 */
}
@@ -2014,6 +2017,9 @@ static void cortex_a15_initfn(Object *obj)
cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */
cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */
cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */
+ cpu->gic_num_lrs = 4;
+ cpu->gic_vpribits = 5;
+ cpu->gic_vprebits = 5;
define_arm_cp_regs(cpu, cortexa15_cp_reginfo);
}
--
2.27.0.rc2
^ permalink raw reply related [flat|nested] 4+ messages in thread
* Re: [PATCH] target/arm: Init GIC CPU IF regs for A15/A7
2020-05-29 23:06 [PATCH] target/arm: Init GIC CPU IF regs for A15/A7 Adam Lackorzynski
@ 2020-06-01 12:36 ` Peter Maydell
2020-06-01 13:01 ` Adam Lackorzynski
0 siblings, 1 reply; 4+ messages in thread
From: Peter Maydell @ 2020-06-01 12:36 UTC (permalink / raw)
To: Adam Lackorzynski; +Cc: QEMU Developers
On Sat, 30 May 2020 at 00:07, Adam Lackorzynski <adam@l4re.org> wrote:
>
> Initialize the CPU interface registers also
> for Cortex-A15 and Cortex-A7 CPU models, in
> the same way as done for 64bit CPU models.
> This fixes usage of GICv3 in virtualization
> contexts in 32bit configurations.
>
> Signed-off-by: Adam Lackorzynski <adam@l4re.org>
Hi; I'm confused by this patch. The Cortex-A15 and Cortex-A7
do not have or support the GICv3, so why would we need
to set GICv3-specific settings for them?
We're probably missing a sanity-check somewhere
to forbid user attempts to use non-GICv3 CPUs with
the GICv3.
thanks
-- PMM
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH] target/arm: Init GIC CPU IF regs for A15/A7
2020-06-01 12:36 ` Peter Maydell
@ 2020-06-01 13:01 ` Adam Lackorzynski
2020-06-01 13:17 ` Peter Maydell
0 siblings, 1 reply; 4+ messages in thread
From: Adam Lackorzynski @ 2020-06-01 13:01 UTC (permalink / raw)
To: Peter Maydell; +Cc: QEMU Developers
On Mon Jun 01, 2020 at 13:36:13 +0100, Peter Maydell wrote:
> On Sat, 30 May 2020 at 00:07, Adam Lackorzynski <adam@l4re.org> wrote:
> >
> > Initialize the CPU interface registers also
> > for Cortex-A15 and Cortex-A7 CPU models, in
> > the same way as done for 64bit CPU models.
> > This fixes usage of GICv3 in virtualization
> > contexts in 32bit configurations.
> >
> > Signed-off-by: Adam Lackorzynski <adam@l4re.org>
>
> Hi; I'm confused by this patch. The Cortex-A15 and Cortex-A7
> do not have or support the GICv3, so why would we need
> to set GICv3-specific settings for them?
>
> We're probably missing a sanity-check somewhere
> to forbid user attempts to use non-GICv3 CPUs with
> the GICv3.
Indeed that's another option. Besides that A15+GICv3 currently just
works with this.
So I guess the alternative is to switch to 32bit from EL3 when using an A57?
Thanks,
Adam
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH] target/arm: Init GIC CPU IF regs for A15/A7
2020-06-01 13:01 ` Adam Lackorzynski
@ 2020-06-01 13:17 ` Peter Maydell
0 siblings, 0 replies; 4+ messages in thread
From: Peter Maydell @ 2020-06-01 13:17 UTC (permalink / raw)
To: Adam Lackorzynski; +Cc: QEMU Developers
On Mon, 1 Jun 2020 at 14:01, Adam Lackorzynski <adam@l4re.org> wrote:
> Indeed that's another option. Besides that A15+GICv3 currently just
> works with this.
Not sure how...
> So I guess the alternative is to switch to 32bit from EL3 when using an A57?
If you're using KVM then you can use -cpu host,aarch64=off
thanks
-- PMM
^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2020-06-01 13:18 UTC | newest]
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2020-05-29 23:06 [PATCH] target/arm: Init GIC CPU IF regs for A15/A7 Adam Lackorzynski
2020-06-01 12:36 ` Peter Maydell
2020-06-01 13:01 ` Adam Lackorzynski
2020-06-01 13:17 ` Peter Maydell
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