* [PATCH v3 0/2] Aspeed I3C device model
@ 2022-01-11 8:45 Troy Lee
2022-01-11 8:45 ` [PATCH v3 1/2] Introduce a dummy AST2600 I3C model Troy Lee
` (4 more replies)
0 siblings, 5 replies; 12+ messages in thread
From: Troy Lee @ 2022-01-11 8:45 UTC (permalink / raw)
To: qemu-devel; +Cc: leetroy, hailin.wu
This series of patch introduce a dummy implemenation of aspeed i3c
model, and it provide just enough information for guest machine.
However, the driver probing is still failed, but it will not cause
kernel panic.
v3:
- Remove unused AspeedI3CClass
- Refine memory region
- Refine register reset
- Remove unrelated changes to SPI2 address
- Remove i3c controller irq line
v2:
- Split i3c model into i3c and i3c_device
- Create 6x i3c devices
- Using register fields macro
- Rebase to mainline QEMU
Troy Lee (2):
Introduce a dummy AST2600 I3C model.
This patch includes i3c instance in ast2600 soc.
hw/arm/aspeed_ast2600.c | 16 ++
hw/misc/aspeed_i3c.c | 381 +++++++++++++++++++++++++++++++++++
hw/misc/meson.build | 1 +
hw/misc/trace-events | 6 +
include/hw/arm/aspeed_soc.h | 3 +
include/hw/misc/aspeed_i3c.h | 48 +++++
6 files changed, 455 insertions(+)
create mode 100644 hw/misc/aspeed_i3c.c
create mode 100644 include/hw/misc/aspeed_i3c.h
--
2.25.1
^ permalink raw reply [flat|nested] 12+ messages in thread* [PATCH v3 1/2] Introduce a dummy AST2600 I3C model. 2022-01-11 8:45 [PATCH v3 0/2] Aspeed I3C device model Troy Lee @ 2022-01-11 8:45 ` Troy Lee 2022-01-11 9:05 ` Cédric Le Goater 2022-01-11 8:45 ` [PATCH v3 2/2] This patch includes i3c instance in ast2600 soc Troy Lee ` (3 subsequent siblings) 4 siblings, 1 reply; 12+ messages in thread From: Troy Lee @ 2022-01-11 8:45 UTC (permalink / raw) To: qemu-devel Cc: Peter Maydell, Andrew Jeffery, hailin.wu, leetroy, open list:ASPEED BMCs, Cédric Le Goater, Joel Stanley Aspeed 2600 SDK enables I3C support by default. The I3C driver will try to reset the device controller and setup through device address table register. This dummy model response these register with default value listed on ast2600v10 datasheet chapter 54.2. If the device address table register doesn't set correctly, it will cause guest machine kernel panic due to reference to invalid address. v3: - Remove unused AspeedI3CClass - Refine memory region - Refine register reset v2: - Split i3c model into i3c and i3c_device - Create 6x i3c devices - Using register fields macro Signed-off-by: Troy Lee <troy_lee@aspeedtech.com> --- hw/misc/aspeed_i3c.c | 381 +++++++++++++++++++++++++++++++++++ hw/misc/meson.build | 1 + hw/misc/trace-events | 6 + include/hw/misc/aspeed_i3c.h | 48 +++++ 4 files changed, 436 insertions(+) create mode 100644 hw/misc/aspeed_i3c.c create mode 100644 include/hw/misc/aspeed_i3c.h diff --git a/hw/misc/aspeed_i3c.c b/hw/misc/aspeed_i3c.c new file mode 100644 index 0000000000..43771d768a --- /dev/null +++ b/hw/misc/aspeed_i3c.c @@ -0,0 +1,381 @@ +/* + * ASPEED I3C Controller + * + * Copyright (C) 2021 ASPEED Technology Inc. + * + * This code is licensed under the GPL version 2 or later. See + * the COPYING file in the top-level directory. + */ + +#include "qemu/osdep.h" +#include "qemu/log.h" +#include "qemu/error-report.h" +#include "hw/misc/aspeed_i3c.h" +#include "hw/registerfields.h" +#include "hw/qdev-properties.h" +#include "qapi/error.h" +#include "migration/vmstate.h" +#include "trace.h" + +/* I3C Controller Registers */ +REG32(I3C1_REG0, 0x10) +REG32(I3C1_REG1, 0x14) + FIELD(I3C1_REG1, I2C_MODE, 0, 1) + FIELD(I3C1_REG1, SA_EN, 15, 1) +REG32(I3C2_REG0, 0x20) +REG32(I3C2_REG1, 0x24) + FIELD(I3C2_REG1, I2C_MODE, 0, 1) + FIELD(I3C2_REG1, SA_EN, 15, 1) +REG32(I3C3_REG0, 0x30) +REG32(I3C3_REG1, 0x34) + FIELD(I3C3_REG1, I2C_MODE, 0, 1) + FIELD(I3C3_REG1, SA_EN, 15, 1) +REG32(I3C4_REG0, 0x40) +REG32(I3C4_REG1, 0x44) + FIELD(I3C4_REG1, I2C_MODE, 0, 1) + FIELD(I3C4_REG1, SA_EN, 15, 1) +REG32(I3C5_REG0, 0x50) +REG32(I3C5_REG1, 0x54) + FIELD(I3C5_REG1, I2C_MODE, 0, 1) + FIELD(I3C5_REG1, SA_EN, 15, 1) +REG32(I3C6_REG0, 0x60) +REG32(I3C6_REG1, 0x64) + FIELD(I3C6_REG1, I2C_MODE, 0, 1) + FIELD(I3C6_REG1, SA_EN, 15, 1) + +/* I3C Device Registers */ +REG32(DEVICE_CTRL, 0x00) +REG32(DEVICE_ADDR, 0x04) +REG32(HW_CAPABILITY, 0x08) +REG32(COMMAND_QUEUE_PORT, 0x0c) +REG32(RESPONSE_QUEUE_PORT, 0x10) +REG32(RX_TX_DATA_PORT, 0x14) +REG32(IBI_QUEUE_STATUS, 0x18) +REG32(IBI_QUEUE_DATA, 0x18) +REG32(QUEUE_THLD_CTRL, 0x1c) +REG32(DATA_BUFFER_THLD_CTRL, 0x20) +REG32(IBI_QUEUE_CTRL, 0x24) +REG32(IBI_MR_REQ_REJECT, 0x2c) +REG32(IBI_SIR_REQ_REJECT, 0x30) +REG32(RESET_CTRL, 0x34) +REG32(SLV_EVENT_CTRL, 0x38) +REG32(INTR_STATUS, 0x3c) +REG32(INTR_STATUS_EN, 0x40) +REG32(INTR_SIGNAL_EN, 0x44) +REG32(INTR_FORCE, 0x48) +REG32(QUEUE_STATUS_LEVEL, 0x4c) +REG32(DATA_BUFFER_STATUS_LEVEL, 0x50) +REG32(PRESENT_STATE, 0x54) +REG32(CCC_DEVICE_STATUS, 0x58) +REG32(DEVICE_ADDR_TABLE_POINTER, 0x5c) + FIELD(DEVICE_ADDR_TABLE_POINTER, DEPTH, 16, 16) + FIELD(DEVICE_ADDR_TABLE_POINTER, ADDR, 0, 16) +REG32(DEV_CHAR_TABLE_POINTER, 0x60) +REG32(VENDOR_SPECIFIC_REG_POINTER, 0x6c) +REG32(SLV_MIPI_PID_VALUE, 0x70) +REG32(SLV_PID_VALUE, 0x74) +REG32(SLV_CHAR_CTRL, 0x78) +REG32(SLV_MAX_LEN, 0x7c) +REG32(MAX_READ_TURNAROUND, 0x80) +REG32(MAX_DATA_SPEED, 0x84) +REG32(SLV_DEBUG_STATUS, 0x88) +REG32(SLV_INTR_REQ, 0x8c) +REG32(DEVICE_CTRL_EXTENDED, 0xb0) +REG32(SCL_I3C_OD_TIMING, 0xb4) +REG32(SCL_I3C_PP_TIMING, 0xb8) +REG32(SCL_I2C_FM_TIMING, 0xbc) +REG32(SCL_I2C_FMP_TIMING, 0xc0) +REG32(SCL_EXT_LCNT_TIMING, 0xc8) +REG32(SCL_EXT_TERMN_LCNT_TIMING, 0xcc) +REG32(BUS_FREE_TIMING, 0xd4) +REG32(BUS_IDLE_TIMING, 0xd8) +REG32(I3C_VER_ID, 0xe0) +REG32(I3C_VER_TYPE, 0xe4) +REG32(EXTENDED_CAPABILITY, 0xe8) +REG32(SLAVE_CONFIG, 0xec) + +static const uint32_t ast2600_i3c_device_resets[ASPEED_I3C_DEVICE_NR_REGS] = { + [R_HW_CAPABILITY] = 0x000e00bf, + [R_QUEUE_THLD_CTRL] = 0x01000101, + [R_I3C_VER_ID] = 0x3130302a, + [R_I3C_VER_TYPE] = 0x6c633033, + [R_DEVICE_ADDR_TABLE_POINTER] = 0x00080280, + [R_DEV_CHAR_TABLE_POINTER] = 0x00020200, + [A_VENDOR_SPECIFIC_REG_POINTER] = 0x000000b0, + [R_SLV_MAX_LEN] = 0x00ff00ff, +}; + +static uint64_t aspeed_i3c_device_read(void *opaque, hwaddr offset, + unsigned size) +{ + AspeedI3CDevice *s = ASPEED_I3C_DEVICE(opaque); + uint32_t addr = offset >> 2; + uint64_t value; + + switch (addr) { + case R_COMMAND_QUEUE_PORT: + value = 0; + break; + default: + value = s->regs[addr]; + break; + } + + trace_aspeed_i3c_device_read(s->id, offset, value); + + return value; +} + +static void aspeed_i3c_device_write(void *opaque, hwaddr offset, + uint64_t value, unsigned size) +{ + AspeedI3CDevice *s = ASPEED_I3C_DEVICE(opaque); + uint32_t addr = offset >> 2; + + trace_aspeed_i3c_device_write(s->id, offset, value); + + switch (addr) { + case R_HW_CAPABILITY: + case R_RESPONSE_QUEUE_PORT: + case R_IBI_QUEUE_DATA: + case R_QUEUE_STATUS_LEVEL: + case R_PRESENT_STATE: + case R_CCC_DEVICE_STATUS: + case R_DEVICE_ADDR_TABLE_POINTER: + case R_VENDOR_SPECIFIC_REG_POINTER: + case R_SLV_CHAR_CTRL: + case R_SLV_MAX_LEN: + case R_MAX_READ_TURNAROUND: + case R_I3C_VER_ID: + case R_I3C_VER_TYPE: + case R_EXTENDED_CAPABILITY: + qemu_log_mask(LOG_GUEST_ERROR, + "%s: write to readonly register[%02lx] = %08lx\n", + __func__, offset, value); + break; + case R_RX_TX_DATA_PORT: + break; + case R_RESET_CTRL: + break; + default: + s->regs[addr] = value; + break; + } +} + +static const VMStateDescription aspeed_i3c_device_vmstate = { + .name = TYPE_ASPEED_I3C, + .version_id = 1, + .minimum_version_id = 1, + .fields = (VMStateField[]){ + VMSTATE_UINT32_ARRAY(regs, AspeedI3CDevice, ASPEED_I3C_DEVICE_NR_REGS), + VMSTATE_END_OF_LIST(), + } +}; + +static const MemoryRegionOps aspeed_i3c_device_ops = { + .read = aspeed_i3c_device_read, + .write = aspeed_i3c_device_write, + .endianness = DEVICE_LITTLE_ENDIAN, +}; + +static void aspeed_i3c_device_reset(DeviceState *dev) +{ + AspeedI3CDevice *s = ASPEED_I3C_DEVICE(dev); + + memcpy(s->regs, ast2600_i3c_device_resets, sizeof(s->regs)); +} + +static void aspeed_i3c_device_realize(DeviceState *dev, Error **errp) +{ + AspeedI3CDevice *s = ASPEED_I3C_DEVICE(dev); + g_autofree char *name = g_strdup_printf(TYPE_ASPEED_I3C_DEVICE ".%d", + s->id); + + sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq); + + memory_region_init_io(&s->mr, OBJECT(s), &aspeed_i3c_device_ops, + s, name, ASPEED_I3C_DEVICE_NR_REGS << 2); +} + +static uint64_t aspeed_i3c_read(void *opaque, hwaddr addr, unsigned int size) +{ + AspeedI3CState *s = ASPEED_I3C(opaque); + uint64_t val = 0; + + val = s->regs[addr >> 2]; + + trace_aspeed_i3c_read(addr, val); + + return val; +} + +static void aspeed_i3c_write(void *opaque, + hwaddr addr, + uint64_t data, + unsigned int size) +{ + AspeedI3CState *s = ASPEED_I3C(opaque); + + trace_aspeed_i3c_write(addr, data); + + addr >>= 2; + + /* I3C controller register */ + switch (addr) { + case R_I3C1_REG1: + case R_I3C2_REG1: + case R_I3C3_REG1: + case R_I3C4_REG1: + case R_I3C5_REG1: + case R_I3C6_REG1: + if (data & R_I3C1_REG1_I2C_MODE_MASK) { + qemu_log_mask(LOG_UNIMP, + "%s: Not support I2C mode [%08lx]=%08lx", + __func__, addr << 2, data); + break; + } + if (data & R_I3C1_REG1_SA_EN_MASK) { + qemu_log_mask(LOG_UNIMP, + "%s: Not support slave mode [%08lx]=%08lx", + __func__, addr << 2, data); + break; + } + s->regs[addr] = data; + break; + default: + s->regs[addr] = data; + break; + } +} + +static const MemoryRegionOps aspeed_i3c_ops = { + .read = aspeed_i3c_read, + .write = aspeed_i3c_write, + .endianness = DEVICE_LITTLE_ENDIAN, + .valid = { + .min_access_size = 1, + .max_access_size = 4, + } +}; + +static void aspeed_i3c_reset(DeviceState *dev) +{ + AspeedI3CState *s = ASPEED_I3C(dev); + memset(s->regs, 0, sizeof(s->regs)); +} + +static void aspeed_i3c_instance_init(Object *obj) +{ + AspeedI3CState *s = ASPEED_I3C(obj); + int i; + + for (i = 0; i < ASPEED_I3C_NR_DEVICES; ++i) { + object_initialize_child(obj, "device[*]", &s->devices[i], + TYPE_ASPEED_I3C_DEVICE); + } +} + +static void aspeed_i3c_realize(DeviceState *dev, Error **errp) +{ + int i; + AspeedI3CState *s = ASPEED_I3C(dev); + SysBusDevice *sbd = SYS_BUS_DEVICE(dev); + + memory_region_init(&s->iomem_container, OBJECT(s), + TYPE_ASPEED_I3C ".container", 0x8000); + + sysbus_init_mmio(sbd, &s->iomem_container); + + memory_region_init_io(&s->iomem, OBJECT(s), &aspeed_i3c_ops, s, + TYPE_ASPEED_I3C ".regs", ASPEED_I3C_NR_REGS << 2); + + memory_region_add_subregion(&s->iomem_container, 0x0, &s->iomem); + + for (i = 0; i < ASPEED_I3C_NR_DEVICES; ++i) { + Object *dev = OBJECT(&s->devices[i]); + + if (!object_property_set_uint(dev, "device-id", i, errp)) { + return; + } + + if (!sysbus_realize(SYS_BUS_DEVICE(dev), errp)) { + return; + } + + /* + * Register Address of I3CX Device = + * (Base Address of Global Register) + (Offset of I3CX) + Offset + * X = 0, 1, 2, 3, 4, 5 + * Offset of I3C0 = 0x2000 + * Offset of I3C1 = 0x3000 + * Offset of I3C2 = 0x4000 + * Offset of I3C3 = 0x5000 + * Offset of I3C4 = 0x6000 + * Offset of I3C5 = 0x7000 + */ + memory_region_add_subregion(&s->iomem_container, + 0x2000 + i * 0x1000, &s->devices[i].mr); + } + +} + +static Property aspeed_i3c_device_properties[] = { + DEFINE_PROP_UINT8("device-id", AspeedI3CDevice, id, 0), + DEFINE_PROP_END_OF_LIST(), +}; + +static void aspeed_i3c_device_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->desc = "Aspeed I3C Device"; + dc->realize = aspeed_i3c_device_realize; + dc->reset = aspeed_i3c_device_reset; + device_class_set_props(dc, aspeed_i3c_device_properties); +} + +static const TypeInfo aspeed_i3c_device_info = { + .name = TYPE_ASPEED_I3C_DEVICE, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(AspeedI3CDevice), + .class_init = aspeed_i3c_device_class_init, +}; + +static const VMStateDescription vmstate_aspeed_i3c = { + .name = TYPE_ASPEED_I3C, + .version_id = 1, + .minimum_version_id = 1, + .fields = (VMStateField[]) { + VMSTATE_UINT32_ARRAY(regs, AspeedI3CState, ASPEED_I3C_NR_REGS), + VMSTATE_STRUCT_ARRAY(devices, AspeedI3CState, ASPEED_I3C_NR_DEVICES, 1, + aspeed_i3c_device_vmstate, AspeedI3CDevice), + VMSTATE_END_OF_LIST(), + } +}; + +static void aspeed_i3c_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->realize = aspeed_i3c_realize; + dc->reset = aspeed_i3c_reset; + dc->desc = "Aspeed I3C Controller"; + dc->vmsd = &vmstate_aspeed_i3c; +} + +static const TypeInfo aspeed_i3c_info = { + .name = TYPE_ASPEED_I3C, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_init = aspeed_i3c_instance_init, + .instance_size = sizeof(AspeedI3CState), + .class_init = aspeed_i3c_class_init, +}; + +static void aspeed_i3c_register_types(void) +{ + type_register_static(&aspeed_i3c_device_info); + type_register_static(&aspeed_i3c_info); +} + +type_init(aspeed_i3c_register_types); diff --git a/hw/misc/meson.build b/hw/misc/meson.build index 3f41a3a5b2..d1a1169108 100644 --- a/hw/misc/meson.build +++ b/hw/misc/meson.build @@ -105,6 +105,7 @@ softmmu_ss.add(when: 'CONFIG_PVPANIC_PCI', if_true: files('pvpanic-pci.c')) softmmu_ss.add(when: 'CONFIG_AUX', if_true: files('auxbus.c')) softmmu_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files( 'aspeed_hace.c', + 'aspeed_i3c.c', 'aspeed_lpc.c', 'aspeed_scu.c', 'aspeed_sdmc.c', diff --git a/hw/misc/trace-events b/hw/misc/trace-events index 2da96d167a..1c373dd0a4 100644 --- a/hw/misc/trace-events +++ b/hw/misc/trace-events @@ -199,6 +199,12 @@ armsse_mhu_write(uint64_t offset, uint64_t data, unsigned size) "SSE-200 MHU wri # aspeed_xdma.c aspeed_xdma_write(uint64_t offset, uint64_t data) "XDMA write: offset 0x%" PRIx64 " data 0x%" PRIx64 +# aspeed_i3c.c +aspeed_i3c_read(uint64_t offset, uint64_t data) "I3C read: offset 0x%" PRIx64 " data 0x%" PRIx64 +aspeed_i3c_write(uint64_t offset, uint64_t data) "I3C write: offset 0x%" PRIx64 " data 0x%" PRIx64 +aspeed_i3c_device_read(uint32_t deviceid, uint64_t offset, uint64_t data) "I3C Dev[%u] read: offset 0x%" PRIx64 " data 0x%" PRIx64 +aspeed_i3c_device_write(uint32_t deviceid, uint64_t offset, uint64_t data) "I3C Dev[%u] write: offset 0x%" PRIx64 " data 0x%" PRIx64 + # bcm2835_property.c bcm2835_mbox_property(uint32_t tag, uint32_t bufsize, size_t resplen) "mbox property tag:0x%08x in_sz:%u out_sz:%zu" diff --git a/include/hw/misc/aspeed_i3c.h b/include/hw/misc/aspeed_i3c.h new file mode 100644 index 0000000000..39679dfa1a --- /dev/null +++ b/include/hw/misc/aspeed_i3c.h @@ -0,0 +1,48 @@ +/* + * ASPEED I3C Controller + * + * Copyright (C) 2021 ASPEED Technology Inc. + * + * This code is licensed under the GPL version 2 or later. See + * the COPYING file in the top-level directory. + */ + +#ifndef ASPEED_I3C_H +#define ASPEED_I3C_H + +#include "hw/sysbus.h" + +#define TYPE_ASPEED_I3C "aspeed.i3c" +#define TYPE_ASPEED_I3C_DEVICE "aspeed.i3c.device" +OBJECT_DECLARE_TYPE(AspeedI3CState, AspeedI3CClass, ASPEED_I3C) + +#define ASPEED_I3C_NR_REGS (0x70 >> 2) +#define ASPEED_I3C_DEVICE_NR_REGS (0x300 >> 2) +#define ASPEED_I3C_NR_DEVICES 6 + +OBJECT_DECLARE_SIMPLE_TYPE(AspeedI3CDevice, ASPEED_I3C_DEVICE) +typedef struct AspeedI3CDevice { + /* <private> */ + SysBusDevice parent; + + /* <public> */ + MemoryRegion mr; + qemu_irq irq; + + uint8_t id; + uint32_t regs[ASPEED_I3C_DEVICE_NR_REGS]; +} AspeedI3CDevice; + +typedef struct AspeedI3CState { + /* <private> */ + SysBusDevice parent; + + /* <public> */ + MemoryRegion iomem; + MemoryRegion iomem_container; + qemu_irq irq; + + uint32_t regs[ASPEED_I3C_NR_REGS]; + AspeedI3CDevice devices[ASPEED_I3C_NR_DEVICES]; +} AspeedI3CState; +#endif /* ASPEED_I3C_H */ -- 2.25.1 ^ permalink raw reply related [flat|nested] 12+ messages in thread
* Re: [PATCH v3 1/2] Introduce a dummy AST2600 I3C model. 2022-01-11 8:45 ` [PATCH v3 1/2] Introduce a dummy AST2600 I3C model Troy Lee @ 2022-01-11 9:05 ` Cédric Le Goater 0 siblings, 0 replies; 12+ messages in thread From: Cédric Le Goater @ 2022-01-11 9:05 UTC (permalink / raw) To: Troy Lee, qemu-devel Cc: Peter Maydell, Andrew Jeffery, hailin.wu, leetroy, open list:ASPEED BMCs, Joel Stanley On 1/11/22 09:45, Troy Lee wrote: > Aspeed 2600 SDK enables I3C support by default. The I3C driver will try > to reset the device controller and setup through device address table > register. This dummy model response these register with default value > listed on ast2600v10 datasheet chapter 54.2. If the device address > table register doesn't set correctly, it will cause guest machine kernel > panic due to reference to invalid address. > > v3: > - Remove unused AspeedI3CClass > - Refine memory region > - Refine register reset > > v2: > - Split i3c model into i3c and i3c_device > - Create 6x i3c devices > - Using register fields macro > > Signed-off-by: Troy Lee <troy_lee@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Thanks, C. > --- > hw/misc/aspeed_i3c.c | 381 +++++++++++++++++++++++++++++++++++ > hw/misc/meson.build | 1 + > hw/misc/trace-events | 6 + > include/hw/misc/aspeed_i3c.h | 48 +++++ > 4 files changed, 436 insertions(+) > create mode 100644 hw/misc/aspeed_i3c.c > create mode 100644 include/hw/misc/aspeed_i3c.h > > diff --git a/hw/misc/aspeed_i3c.c b/hw/misc/aspeed_i3c.c > new file mode 100644 > index 0000000000..43771d768a > --- /dev/null > +++ b/hw/misc/aspeed_i3c.c > @@ -0,0 +1,381 @@ > +/* > + * ASPEED I3C Controller > + * > + * Copyright (C) 2021 ASPEED Technology Inc. > + * > + * This code is licensed under the GPL version 2 or later. See > + * the COPYING file in the top-level directory. > + */ > + > +#include "qemu/osdep.h" > +#include "qemu/log.h" > +#include "qemu/error-report.h" > +#include "hw/misc/aspeed_i3c.h" > +#include "hw/registerfields.h" > +#include "hw/qdev-properties.h" > +#include "qapi/error.h" > +#include "migration/vmstate.h" > +#include "trace.h" > + > +/* I3C Controller Registers */ > +REG32(I3C1_REG0, 0x10) > +REG32(I3C1_REG1, 0x14) > + FIELD(I3C1_REG1, I2C_MODE, 0, 1) > + FIELD(I3C1_REG1, SA_EN, 15, 1) > +REG32(I3C2_REG0, 0x20) > +REG32(I3C2_REG1, 0x24) > + FIELD(I3C2_REG1, I2C_MODE, 0, 1) > + FIELD(I3C2_REG1, SA_EN, 15, 1) > +REG32(I3C3_REG0, 0x30) > +REG32(I3C3_REG1, 0x34) > + FIELD(I3C3_REG1, I2C_MODE, 0, 1) > + FIELD(I3C3_REG1, SA_EN, 15, 1) > +REG32(I3C4_REG0, 0x40) > +REG32(I3C4_REG1, 0x44) > + FIELD(I3C4_REG1, I2C_MODE, 0, 1) > + FIELD(I3C4_REG1, SA_EN, 15, 1) > +REG32(I3C5_REG0, 0x50) > +REG32(I3C5_REG1, 0x54) > + FIELD(I3C5_REG1, I2C_MODE, 0, 1) > + FIELD(I3C5_REG1, SA_EN, 15, 1) > +REG32(I3C6_REG0, 0x60) > +REG32(I3C6_REG1, 0x64) > + FIELD(I3C6_REG1, I2C_MODE, 0, 1) > + FIELD(I3C6_REG1, SA_EN, 15, 1) > + > +/* I3C Device Registers */ > +REG32(DEVICE_CTRL, 0x00) > +REG32(DEVICE_ADDR, 0x04) > +REG32(HW_CAPABILITY, 0x08) > +REG32(COMMAND_QUEUE_PORT, 0x0c) > +REG32(RESPONSE_QUEUE_PORT, 0x10) > +REG32(RX_TX_DATA_PORT, 0x14) > +REG32(IBI_QUEUE_STATUS, 0x18) > +REG32(IBI_QUEUE_DATA, 0x18) > +REG32(QUEUE_THLD_CTRL, 0x1c) > +REG32(DATA_BUFFER_THLD_CTRL, 0x20) > +REG32(IBI_QUEUE_CTRL, 0x24) > +REG32(IBI_MR_REQ_REJECT, 0x2c) > +REG32(IBI_SIR_REQ_REJECT, 0x30) > +REG32(RESET_CTRL, 0x34) > +REG32(SLV_EVENT_CTRL, 0x38) > +REG32(INTR_STATUS, 0x3c) > +REG32(INTR_STATUS_EN, 0x40) > +REG32(INTR_SIGNAL_EN, 0x44) > +REG32(INTR_FORCE, 0x48) > +REG32(QUEUE_STATUS_LEVEL, 0x4c) > +REG32(DATA_BUFFER_STATUS_LEVEL, 0x50) > +REG32(PRESENT_STATE, 0x54) > +REG32(CCC_DEVICE_STATUS, 0x58) > +REG32(DEVICE_ADDR_TABLE_POINTER, 0x5c) > + FIELD(DEVICE_ADDR_TABLE_POINTER, DEPTH, 16, 16) > + FIELD(DEVICE_ADDR_TABLE_POINTER, ADDR, 0, 16) > +REG32(DEV_CHAR_TABLE_POINTER, 0x60) > +REG32(VENDOR_SPECIFIC_REG_POINTER, 0x6c) > +REG32(SLV_MIPI_PID_VALUE, 0x70) > +REG32(SLV_PID_VALUE, 0x74) > +REG32(SLV_CHAR_CTRL, 0x78) > +REG32(SLV_MAX_LEN, 0x7c) > +REG32(MAX_READ_TURNAROUND, 0x80) > +REG32(MAX_DATA_SPEED, 0x84) > +REG32(SLV_DEBUG_STATUS, 0x88) > +REG32(SLV_INTR_REQ, 0x8c) > +REG32(DEVICE_CTRL_EXTENDED, 0xb0) > +REG32(SCL_I3C_OD_TIMING, 0xb4) > +REG32(SCL_I3C_PP_TIMING, 0xb8) > +REG32(SCL_I2C_FM_TIMING, 0xbc) > +REG32(SCL_I2C_FMP_TIMING, 0xc0) > +REG32(SCL_EXT_LCNT_TIMING, 0xc8) > +REG32(SCL_EXT_TERMN_LCNT_TIMING, 0xcc) > +REG32(BUS_FREE_TIMING, 0xd4) > +REG32(BUS_IDLE_TIMING, 0xd8) > +REG32(I3C_VER_ID, 0xe0) > +REG32(I3C_VER_TYPE, 0xe4) > +REG32(EXTENDED_CAPABILITY, 0xe8) > +REG32(SLAVE_CONFIG, 0xec) > + > +static const uint32_t ast2600_i3c_device_resets[ASPEED_I3C_DEVICE_NR_REGS] = { > + [R_HW_CAPABILITY] = 0x000e00bf, > + [R_QUEUE_THLD_CTRL] = 0x01000101, > + [R_I3C_VER_ID] = 0x3130302a, > + [R_I3C_VER_TYPE] = 0x6c633033, > + [R_DEVICE_ADDR_TABLE_POINTER] = 0x00080280, > + [R_DEV_CHAR_TABLE_POINTER] = 0x00020200, > + [A_VENDOR_SPECIFIC_REG_POINTER] = 0x000000b0, > + [R_SLV_MAX_LEN] = 0x00ff00ff, > +}; > + > +static uint64_t aspeed_i3c_device_read(void *opaque, hwaddr offset, > + unsigned size) > +{ > + AspeedI3CDevice *s = ASPEED_I3C_DEVICE(opaque); > + uint32_t addr = offset >> 2; > + uint64_t value; > + > + switch (addr) { > + case R_COMMAND_QUEUE_PORT: > + value = 0; > + break; > + default: > + value = s->regs[addr]; > + break; > + } > + > + trace_aspeed_i3c_device_read(s->id, offset, value); > + > + return value; > +} > + > +static void aspeed_i3c_device_write(void *opaque, hwaddr offset, > + uint64_t value, unsigned size) > +{ > + AspeedI3CDevice *s = ASPEED_I3C_DEVICE(opaque); > + uint32_t addr = offset >> 2; > + > + trace_aspeed_i3c_device_write(s->id, offset, value); > + > + switch (addr) { > + case R_HW_CAPABILITY: > + case R_RESPONSE_QUEUE_PORT: > + case R_IBI_QUEUE_DATA: > + case R_QUEUE_STATUS_LEVEL: > + case R_PRESENT_STATE: > + case R_CCC_DEVICE_STATUS: > + case R_DEVICE_ADDR_TABLE_POINTER: > + case R_VENDOR_SPECIFIC_REG_POINTER: > + case R_SLV_CHAR_CTRL: > + case R_SLV_MAX_LEN: > + case R_MAX_READ_TURNAROUND: > + case R_I3C_VER_ID: > + case R_I3C_VER_TYPE: > + case R_EXTENDED_CAPABILITY: > + qemu_log_mask(LOG_GUEST_ERROR, > + "%s: write to readonly register[%02lx] = %08lx\n", > + __func__, offset, value); > + break; > + case R_RX_TX_DATA_PORT: > + break; > + case R_RESET_CTRL: > + break; > + default: > + s->regs[addr] = value; > + break; > + } > +} > + > +static const VMStateDescription aspeed_i3c_device_vmstate = { > + .name = TYPE_ASPEED_I3C, > + .version_id = 1, > + .minimum_version_id = 1, > + .fields = (VMStateField[]){ > + VMSTATE_UINT32_ARRAY(regs, AspeedI3CDevice, ASPEED_I3C_DEVICE_NR_REGS), > + VMSTATE_END_OF_LIST(), > + } > +}; > + > +static const MemoryRegionOps aspeed_i3c_device_ops = { > + .read = aspeed_i3c_device_read, > + .write = aspeed_i3c_device_write, > + .endianness = DEVICE_LITTLE_ENDIAN, > +}; > + > +static void aspeed_i3c_device_reset(DeviceState *dev) > +{ > + AspeedI3CDevice *s = ASPEED_I3C_DEVICE(dev); > + > + memcpy(s->regs, ast2600_i3c_device_resets, sizeof(s->regs)); > +} > + > +static void aspeed_i3c_device_realize(DeviceState *dev, Error **errp) > +{ > + AspeedI3CDevice *s = ASPEED_I3C_DEVICE(dev); > + g_autofree char *name = g_strdup_printf(TYPE_ASPEED_I3C_DEVICE ".%d", > + s->id); > + > + sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq); > + > + memory_region_init_io(&s->mr, OBJECT(s), &aspeed_i3c_device_ops, > + s, name, ASPEED_I3C_DEVICE_NR_REGS << 2); > +} > + > +static uint64_t aspeed_i3c_read(void *opaque, hwaddr addr, unsigned int size) > +{ > + AspeedI3CState *s = ASPEED_I3C(opaque); > + uint64_t val = 0; > + > + val = s->regs[addr >> 2]; > + > + trace_aspeed_i3c_read(addr, val); > + > + return val; > +} > + > +static void aspeed_i3c_write(void *opaque, > + hwaddr addr, > + uint64_t data, > + unsigned int size) > +{ > + AspeedI3CState *s = ASPEED_I3C(opaque); > + > + trace_aspeed_i3c_write(addr, data); > + > + addr >>= 2; > + > + /* I3C controller register */ > + switch (addr) { > + case R_I3C1_REG1: > + case R_I3C2_REG1: > + case R_I3C3_REG1: > + case R_I3C4_REG1: > + case R_I3C5_REG1: > + case R_I3C6_REG1: > + if (data & R_I3C1_REG1_I2C_MODE_MASK) { > + qemu_log_mask(LOG_UNIMP, > + "%s: Not support I2C mode [%08lx]=%08lx", > + __func__, addr << 2, data); > + break; > + } > + if (data & R_I3C1_REG1_SA_EN_MASK) { > + qemu_log_mask(LOG_UNIMP, > + "%s: Not support slave mode [%08lx]=%08lx", > + __func__, addr << 2, data); > + break; > + } > + s->regs[addr] = data; > + break; > + default: > + s->regs[addr] = data; > + break; > + } > +} > + > +static const MemoryRegionOps aspeed_i3c_ops = { > + .read = aspeed_i3c_read, > + .write = aspeed_i3c_write, > + .endianness = DEVICE_LITTLE_ENDIAN, > + .valid = { > + .min_access_size = 1, > + .max_access_size = 4, > + } > +}; > + > +static void aspeed_i3c_reset(DeviceState *dev) > +{ > + AspeedI3CState *s = ASPEED_I3C(dev); > + memset(s->regs, 0, sizeof(s->regs)); > +} > + > +static void aspeed_i3c_instance_init(Object *obj) > +{ > + AspeedI3CState *s = ASPEED_I3C(obj); > + int i; > + > + for (i = 0; i < ASPEED_I3C_NR_DEVICES; ++i) { > + object_initialize_child(obj, "device[*]", &s->devices[i], > + TYPE_ASPEED_I3C_DEVICE); > + } > +} > + > +static void aspeed_i3c_realize(DeviceState *dev, Error **errp) > +{ > + int i; > + AspeedI3CState *s = ASPEED_I3C(dev); > + SysBusDevice *sbd = SYS_BUS_DEVICE(dev); > + > + memory_region_init(&s->iomem_container, OBJECT(s), > + TYPE_ASPEED_I3C ".container", 0x8000); > + > + sysbus_init_mmio(sbd, &s->iomem_container); > + > + memory_region_init_io(&s->iomem, OBJECT(s), &aspeed_i3c_ops, s, > + TYPE_ASPEED_I3C ".regs", ASPEED_I3C_NR_REGS << 2); > + > + memory_region_add_subregion(&s->iomem_container, 0x0, &s->iomem); > + > + for (i = 0; i < ASPEED_I3C_NR_DEVICES; ++i) { > + Object *dev = OBJECT(&s->devices[i]); > + > + if (!object_property_set_uint(dev, "device-id", i, errp)) { > + return; > + } > + > + if (!sysbus_realize(SYS_BUS_DEVICE(dev), errp)) { > + return; > + } > + > + /* > + * Register Address of I3CX Device = > + * (Base Address of Global Register) + (Offset of I3CX) + Offset > + * X = 0, 1, 2, 3, 4, 5 > + * Offset of I3C0 = 0x2000 > + * Offset of I3C1 = 0x3000 > + * Offset of I3C2 = 0x4000 > + * Offset of I3C3 = 0x5000 > + * Offset of I3C4 = 0x6000 > + * Offset of I3C5 = 0x7000 > + */ > + memory_region_add_subregion(&s->iomem_container, > + 0x2000 + i * 0x1000, &s->devices[i].mr); > + } > + > +} > + > +static Property aspeed_i3c_device_properties[] = { > + DEFINE_PROP_UINT8("device-id", AspeedI3CDevice, id, 0), > + DEFINE_PROP_END_OF_LIST(), > +}; > + > +static void aspeed_i3c_device_class_init(ObjectClass *klass, void *data) > +{ > + DeviceClass *dc = DEVICE_CLASS(klass); > + > + dc->desc = "Aspeed I3C Device"; > + dc->realize = aspeed_i3c_device_realize; > + dc->reset = aspeed_i3c_device_reset; > + device_class_set_props(dc, aspeed_i3c_device_properties); > +} > + > +static const TypeInfo aspeed_i3c_device_info = { > + .name = TYPE_ASPEED_I3C_DEVICE, > + .parent = TYPE_SYS_BUS_DEVICE, > + .instance_size = sizeof(AspeedI3CDevice), > + .class_init = aspeed_i3c_device_class_init, > +}; > + > +static const VMStateDescription vmstate_aspeed_i3c = { > + .name = TYPE_ASPEED_I3C, > + .version_id = 1, > + .minimum_version_id = 1, > + .fields = (VMStateField[]) { > + VMSTATE_UINT32_ARRAY(regs, AspeedI3CState, ASPEED_I3C_NR_REGS), > + VMSTATE_STRUCT_ARRAY(devices, AspeedI3CState, ASPEED_I3C_NR_DEVICES, 1, > + aspeed_i3c_device_vmstate, AspeedI3CDevice), > + VMSTATE_END_OF_LIST(), > + } > +}; > + > +static void aspeed_i3c_class_init(ObjectClass *klass, void *data) > +{ > + DeviceClass *dc = DEVICE_CLASS(klass); > + > + dc->realize = aspeed_i3c_realize; > + dc->reset = aspeed_i3c_reset; > + dc->desc = "Aspeed I3C Controller"; > + dc->vmsd = &vmstate_aspeed_i3c; > +} > + > +static const TypeInfo aspeed_i3c_info = { > + .name = TYPE_ASPEED_I3C, > + .parent = TYPE_SYS_BUS_DEVICE, > + .instance_init = aspeed_i3c_instance_init, > + .instance_size = sizeof(AspeedI3CState), > + .class_init = aspeed_i3c_class_init, > +}; > + > +static void aspeed_i3c_register_types(void) > +{ > + type_register_static(&aspeed_i3c_device_info); > + type_register_static(&aspeed_i3c_info); > +} > + > +type_init(aspeed_i3c_register_types); > diff --git a/hw/misc/meson.build b/hw/misc/meson.build > index 3f41a3a5b2..d1a1169108 100644 > --- a/hw/misc/meson.build > +++ b/hw/misc/meson.build > @@ -105,6 +105,7 @@ softmmu_ss.add(when: 'CONFIG_PVPANIC_PCI', if_true: files('pvpanic-pci.c')) > softmmu_ss.add(when: 'CONFIG_AUX', if_true: files('auxbus.c')) > softmmu_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files( > 'aspeed_hace.c', > + 'aspeed_i3c.c', > 'aspeed_lpc.c', > 'aspeed_scu.c', > 'aspeed_sdmc.c', > diff --git a/hw/misc/trace-events b/hw/misc/trace-events > index 2da96d167a..1c373dd0a4 100644 > --- a/hw/misc/trace-events > +++ b/hw/misc/trace-events > @@ -199,6 +199,12 @@ armsse_mhu_write(uint64_t offset, uint64_t data, unsigned size) "SSE-200 MHU wri > # aspeed_xdma.c > aspeed_xdma_write(uint64_t offset, uint64_t data) "XDMA write: offset 0x%" PRIx64 " data 0x%" PRIx64 > > +# aspeed_i3c.c > +aspeed_i3c_read(uint64_t offset, uint64_t data) "I3C read: offset 0x%" PRIx64 " data 0x%" PRIx64 > +aspeed_i3c_write(uint64_t offset, uint64_t data) "I3C write: offset 0x%" PRIx64 " data 0x%" PRIx64 > +aspeed_i3c_device_read(uint32_t deviceid, uint64_t offset, uint64_t data) "I3C Dev[%u] read: offset 0x%" PRIx64 " data 0x%" PRIx64 > +aspeed_i3c_device_write(uint32_t deviceid, uint64_t offset, uint64_t data) "I3C Dev[%u] write: offset 0x%" PRIx64 " data 0x%" PRIx64 > + > # bcm2835_property.c > bcm2835_mbox_property(uint32_t tag, uint32_t bufsize, size_t resplen) "mbox property tag:0x%08x in_sz:%u out_sz:%zu" > > diff --git a/include/hw/misc/aspeed_i3c.h b/include/hw/misc/aspeed_i3c.h > new file mode 100644 > index 0000000000..39679dfa1a > --- /dev/null > +++ b/include/hw/misc/aspeed_i3c.h > @@ -0,0 +1,48 @@ > +/* > + * ASPEED I3C Controller > + * > + * Copyright (C) 2021 ASPEED Technology Inc. > + * > + * This code is licensed under the GPL version 2 or later. See > + * the COPYING file in the top-level directory. > + */ > + > +#ifndef ASPEED_I3C_H > +#define ASPEED_I3C_H > + > +#include "hw/sysbus.h" > + > +#define TYPE_ASPEED_I3C "aspeed.i3c" > +#define TYPE_ASPEED_I3C_DEVICE "aspeed.i3c.device" > +OBJECT_DECLARE_TYPE(AspeedI3CState, AspeedI3CClass, ASPEED_I3C) > + > +#define ASPEED_I3C_NR_REGS (0x70 >> 2) > +#define ASPEED_I3C_DEVICE_NR_REGS (0x300 >> 2) > +#define ASPEED_I3C_NR_DEVICES 6 > + > +OBJECT_DECLARE_SIMPLE_TYPE(AspeedI3CDevice, ASPEED_I3C_DEVICE) > +typedef struct AspeedI3CDevice { > + /* <private> */ > + SysBusDevice parent; > + > + /* <public> */ > + MemoryRegion mr; > + qemu_irq irq; > + > + uint8_t id; > + uint32_t regs[ASPEED_I3C_DEVICE_NR_REGS]; > +} AspeedI3CDevice; > + > +typedef struct AspeedI3CState { > + /* <private> */ > + SysBusDevice parent; > + > + /* <public> */ > + MemoryRegion iomem; > + MemoryRegion iomem_container; > + qemu_irq irq; > + > + uint32_t regs[ASPEED_I3C_NR_REGS]; > + AspeedI3CDevice devices[ASPEED_I3C_NR_DEVICES]; > +} AspeedI3CState; > +#endif /* ASPEED_I3C_H */ > ^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH v3 2/2] This patch includes i3c instance in ast2600 soc. 2022-01-11 8:45 [PATCH v3 0/2] Aspeed I3C device model Troy Lee 2022-01-11 8:45 ` [PATCH v3 1/2] Introduce a dummy AST2600 I3C model Troy Lee @ 2022-01-11 8:45 ` Troy Lee 2022-01-11 9:12 ` Cédric Le Goater 2022-01-20 16:01 ` Peter Maydell 2022-01-11 9:21 ` [PATCH v3 0/2] Aspeed I3C device model Cédric Le Goater ` (2 subsequent siblings) 4 siblings, 2 replies; 12+ messages in thread From: Troy Lee @ 2022-01-11 8:45 UTC (permalink / raw) To: qemu-devel Cc: Peter Maydell, Andrew Jeffery, hailin.wu, leetroy, open list:ASPEED BMCs, Cédric Le Goater, Joel Stanley v3: - Remove unrelated changes to SPI2 address - Remove controller irq line v2: Rebase to mainline QEMU Signed-off-by: Troy Lee <troy_lee@aspeedtech.com> --- hw/arm/aspeed_ast2600.c | 16 ++++++++++++++++ include/hw/arm/aspeed_soc.h | 3 +++ 2 files changed, 19 insertions(+) diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c index e33483fb5d..8f37bdb1d8 100644 --- a/hw/arm/aspeed_ast2600.c +++ b/hw/arm/aspeed_ast2600.c @@ -61,6 +61,7 @@ static const hwaddr aspeed_soc_ast2600_memmap[] = { [ASPEED_DEV_UART1] = 0x1E783000, [ASPEED_DEV_UART5] = 0x1E784000, [ASPEED_DEV_VUART] = 0x1E787000, + [ASPEED_DEV_I3C] = 0x1E7A0000, [ASPEED_DEV_SDRAM] = 0x80000000, }; @@ -108,6 +109,7 @@ static const int aspeed_soc_ast2600_irqmap[] = { [ASPEED_DEV_ETH4] = 33, [ASPEED_DEV_KCS] = 138, /* 138 -> 142 */ [ASPEED_DEV_DP] = 62, + [ASPEED_DEV_I3C] = 102, /* 102 -> 107 */ }; static qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int ctrl) @@ -223,6 +225,8 @@ static void aspeed_soc_ast2600_init(Object *obj) snprintf(typename, sizeof(typename), "aspeed.hace-%s", socname); object_initialize_child(obj, "hace", &s->hace, typename); + + object_initialize_child(obj, "i3c", &s->i3c, TYPE_ASPEED_I3C); } /* @@ -523,6 +527,18 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp) sysbus_mmio_map(SYS_BUS_DEVICE(&s->hace), 0, sc->memmap[ASPEED_DEV_HACE]); sysbus_connect_irq(SYS_BUS_DEVICE(&s->hace), 0, aspeed_soc_get_irq(s, ASPEED_DEV_HACE)); + + /* I3C */ + if (!sysbus_realize(SYS_BUS_DEVICE(&s->i3c), errp)) { + return; + } + sysbus_mmio_map(SYS_BUS_DEVICE(&s->i3c), 0, sc->memmap[ASPEED_DEV_I3C]); + for (i = 0; i < ASPEED_I3C_NR_DEVICES; i++) { + qemu_irq irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), + sc->irqmap[ASPEED_DEV_I3C] + i); + /* The AST2600 I3C controller has one IRQ per bus. */ + sysbus_connect_irq(SYS_BUS_DEVICE(&s->i3c.devices[i]), 0, irq); + } } static void aspeed_soc_ast2600_class_init(ObjectClass *oc, void *data) diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h index 18fb7eed46..cae9906684 100644 --- a/include/hw/arm/aspeed_soc.h +++ b/include/hw/arm/aspeed_soc.h @@ -21,6 +21,7 @@ #include "hw/timer/aspeed_timer.h" #include "hw/rtc/aspeed_rtc.h" #include "hw/i2c/aspeed_i2c.h" +#include "hw/misc/aspeed_i3c.h" #include "hw/ssi/aspeed_smc.h" #include "hw/misc/aspeed_hace.h" #include "hw/watchdog/wdt_aspeed.h" @@ -51,6 +52,7 @@ struct AspeedSoCState { AspeedRtcState rtc; AspeedTimerCtrlState timerctrl; AspeedI2CState i2c; + AspeedI3CState i3c; AspeedSCUState scu; AspeedHACEState hace; AspeedXDMAState xdma; @@ -141,6 +143,7 @@ enum { ASPEED_DEV_HACE, ASPEED_DEV_DPMCU, ASPEED_DEV_DP, + ASPEED_DEV_I3C, }; #endif /* ASPEED_SOC_H */ -- 2.25.1 ^ permalink raw reply related [flat|nested] 12+ messages in thread
* Re: [PATCH v3 2/2] This patch includes i3c instance in ast2600 soc. 2022-01-11 8:45 ` [PATCH v3 2/2] This patch includes i3c instance in ast2600 soc Troy Lee @ 2022-01-11 9:12 ` Cédric Le Goater 2022-01-20 16:01 ` Peter Maydell 1 sibling, 0 replies; 12+ messages in thread From: Cédric Le Goater @ 2022-01-11 9:12 UTC (permalink / raw) To: Troy Lee, qemu-devel Cc: Peter Maydell, Andrew Jeffery, hailin.wu, leetroy, open list:ASPEED BMCs, Joel Stanley On 1/11/22 09:45, Troy Lee wrote: > v3: > - Remove unrelated changes to SPI2 address > - Remove controller irq line > > v2: Rebase to mainline QEMU > > Signed-off-by: Troy Lee <troy_lee@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> You should consider updating the documentation : https://qemu.readthedocs.io/en/latest/system/arm/aspeed.html Thanks, C. > --- > hw/arm/aspeed_ast2600.c | 16 ++++++++++++++++ > include/hw/arm/aspeed_soc.h | 3 +++ > 2 files changed, 19 insertions(+) > > diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c > index e33483fb5d..8f37bdb1d8 100644 > --- a/hw/arm/aspeed_ast2600.c > +++ b/hw/arm/aspeed_ast2600.c > @@ -61,6 +61,7 @@ static const hwaddr aspeed_soc_ast2600_memmap[] = { > [ASPEED_DEV_UART1] = 0x1E783000, > [ASPEED_DEV_UART5] = 0x1E784000, > [ASPEED_DEV_VUART] = 0x1E787000, > + [ASPEED_DEV_I3C] = 0x1E7A0000, > [ASPEED_DEV_SDRAM] = 0x80000000, > }; > > @@ -108,6 +109,7 @@ static const int aspeed_soc_ast2600_irqmap[] = { > [ASPEED_DEV_ETH4] = 33, > [ASPEED_DEV_KCS] = 138, /* 138 -> 142 */ > [ASPEED_DEV_DP] = 62, > + [ASPEED_DEV_I3C] = 102, /* 102 -> 107 */ > }; > > static qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int ctrl) > @@ -223,6 +225,8 @@ static void aspeed_soc_ast2600_init(Object *obj) > > snprintf(typename, sizeof(typename), "aspeed.hace-%s", socname); > object_initialize_child(obj, "hace", &s->hace, typename); > + > + object_initialize_child(obj, "i3c", &s->i3c, TYPE_ASPEED_I3C); > } > > /* > @@ -523,6 +527,18 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp) > sysbus_mmio_map(SYS_BUS_DEVICE(&s->hace), 0, sc->memmap[ASPEED_DEV_HACE]); > sysbus_connect_irq(SYS_BUS_DEVICE(&s->hace), 0, > aspeed_soc_get_irq(s, ASPEED_DEV_HACE)); > + > + /* I3C */ > + if (!sysbus_realize(SYS_BUS_DEVICE(&s->i3c), errp)) { > + return; > + } > + sysbus_mmio_map(SYS_BUS_DEVICE(&s->i3c), 0, sc->memmap[ASPEED_DEV_I3C]); > + for (i = 0; i < ASPEED_I3C_NR_DEVICES; i++) { > + qemu_irq irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), > + sc->irqmap[ASPEED_DEV_I3C] + i); > + /* The AST2600 I3C controller has one IRQ per bus. */ > + sysbus_connect_irq(SYS_BUS_DEVICE(&s->i3c.devices[i]), 0, irq); > + } > } > > static void aspeed_soc_ast2600_class_init(ObjectClass *oc, void *data) > diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h > index 18fb7eed46..cae9906684 100644 > --- a/include/hw/arm/aspeed_soc.h > +++ b/include/hw/arm/aspeed_soc.h > @@ -21,6 +21,7 @@ > #include "hw/timer/aspeed_timer.h" > #include "hw/rtc/aspeed_rtc.h" > #include "hw/i2c/aspeed_i2c.h" > +#include "hw/misc/aspeed_i3c.h" > #include "hw/ssi/aspeed_smc.h" > #include "hw/misc/aspeed_hace.h" > #include "hw/watchdog/wdt_aspeed.h" > @@ -51,6 +52,7 @@ struct AspeedSoCState { > AspeedRtcState rtc; > AspeedTimerCtrlState timerctrl; > AspeedI2CState i2c; > + AspeedI3CState i3c; > AspeedSCUState scu; > AspeedHACEState hace; > AspeedXDMAState xdma; > @@ -141,6 +143,7 @@ enum { > ASPEED_DEV_HACE, > ASPEED_DEV_DPMCU, > ASPEED_DEV_DP, > + ASPEED_DEV_I3C, > }; > > #endif /* ASPEED_SOC_H */ > ^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH v3 2/2] This patch includes i3c instance in ast2600 soc. 2022-01-11 8:45 ` [PATCH v3 2/2] This patch includes i3c instance in ast2600 soc Troy Lee 2022-01-11 9:12 ` Cédric Le Goater @ 2022-01-20 16:01 ` Peter Maydell 1 sibling, 0 replies; 12+ messages in thread From: Peter Maydell @ 2022-01-20 16:01 UTC (permalink / raw) To: Troy Lee Cc: Andrew Jeffery, qemu-devel, hailin.wu, leetroy, open list:ASPEED BMCs, Joel Stanley, Cédric Le Goater On Tue, 11 Jan 2022 at 08:46, Troy Lee <troy_lee@aspeedtech.com> wrote: > > v3: > - Remove unrelated changes to SPI2 address > - Remove controller irq line > > v2: Rebase to mainline QEMU > > Signed-off-by: Troy Lee <troy_lee@aspeedtech.com> This turns out not to build on macOS or on 32-bit hosts because of format string issues -- you can't portably use %lx to print uint64_t or hwaddr types. I have folded in the following fix: diff --git a/hw/misc/aspeed_i3c.c b/hw/misc/aspeed_i3c.c index 43771d768ad..f54f5da522b 100644 --- a/hw/misc/aspeed_i3c.c +++ b/hw/misc/aspeed_i3c.c @@ -150,7 +150,8 @@ static void aspeed_i3c_device_write(void *opaque, hwaddr offset, case R_I3C_VER_TYPE: case R_EXTENDED_CAPABILITY: qemu_log_mask(LOG_GUEST_ERROR, - "%s: write to readonly register[%02lx] = %08lx\n", + "%s: write to readonly register[0x%02" HWADDR_PRIx + "] = 0x%08" PRIx64 "\n", __func__, offset, value); break; case R_RX_TX_DATA_PORT: @@ -231,13 +232,15 @@ static void aspeed_i3c_write(void *opaque, case R_I3C6_REG1: if (data & R_I3C1_REG1_I2C_MODE_MASK) { qemu_log_mask(LOG_UNIMP, - "%s: Not support I2C mode [%08lx]=%08lx", + "%s: Unsupported I2C mode [0x%08" HWADDR_PRIx + "]=%08" PRIx64 "\n", __func__, addr << 2, data); break; } if (data & R_I3C1_REG1_SA_EN_MASK) { qemu_log_mask(LOG_UNIMP, - "%s: Not support slave mode [%08lx]=%08lx", + "%s: Unsupported slave mode [%08" HWADDR_PRIx + "]=0x%08" PRIx64 "\n", __func__, addr << 2, data); break; } which also includes a small grammar fix, adds the missing trailing newlines, and includes the "0x" prefix to make it clearer to the user that the values printed are hex. thanks -- PMM ^ permalink raw reply related [flat|nested] 12+ messages in thread
* Re: [PATCH v3 0/2] Aspeed I3C device model 2022-01-11 8:45 [PATCH v3 0/2] Aspeed I3C device model Troy Lee 2022-01-11 8:45 ` [PATCH v3 1/2] Introduce a dummy AST2600 I3C model Troy Lee 2022-01-11 8:45 ` [PATCH v3 2/2] This patch includes i3c instance in ast2600 soc Troy Lee @ 2022-01-11 9:21 ` Cédric Le Goater 2022-01-12 10:57 ` Graeme Gregory 2022-01-18 17:40 ` Peter Maydell 4 siblings, 0 replies; 12+ messages in thread From: Cédric Le Goater @ 2022-01-11 9:21 UTC (permalink / raw) To: qemu-devel On 1/11/22 09:45, Troy Lee wrote: > This series of patch introduce a dummy implemenation of aspeed i3c > model, and it provide just enough information for guest machine. > However, the driver probing is still failed, but it will not cause > kernel panic. > > v3: > - Remove unused AspeedI3CClass > - Refine memory region > - Refine register reset > - Remove unrelated changes to SPI2 address > - Remove i3c controller irq line > > v2: > - Split i3c model into i3c and i3c_device > - Create 6x i3c devices > - Using register fields macro > - Rebase to mainline QEMU > > Troy Lee (2): > Introduce a dummy AST2600 I3C model. > This patch includes i3c instance in ast2600 soc. It's nice to add a "hw/arm/aspeed: " prefix to the Subject, or "aspeed: " at least. In case you resend, keep my "Reviewed-by". You can grab the patches on : http://patchwork.ozlabs.org/project/qemu-devel/list/?series=280442 with : pwclient get 1578334 1578335 Thanks, C. ^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH v3 0/2] Aspeed I3C device model 2022-01-11 8:45 [PATCH v3 0/2] Aspeed I3C device model Troy Lee ` (2 preceding siblings ...) 2022-01-11 9:21 ` [PATCH v3 0/2] Aspeed I3C device model Cédric Le Goater @ 2022-01-12 10:57 ` Graeme Gregory 2022-01-12 12:45 ` Cédric Le Goater 2022-01-12 13:50 ` Troy Lee 2022-01-18 17:40 ` Peter Maydell 4 siblings, 2 replies; 12+ messages in thread From: Graeme Gregory @ 2022-01-12 10:57 UTC (permalink / raw) To: Troy Lee; +Cc: leetroy, qemu-devel, hailin.wu On Tue, Jan 11, 2022 at 04:45:44PM +0800, Troy Lee wrote: > This series of patch introduce a dummy implemenation of aspeed i3c > model, and it provide just enough information for guest machine. > However, the driver probing is still failed, but it will not cause > kernel panic. > These patches arrived just in time for our i3c testing. This stops our CI halting due to kernel panic on i3c probing. Reviewed-by: Graeme Gregory <quic_ggregory@quicinc.com> Tested-by: Graeme Gregory <quic_ggregory@quicinc.com> > v3: > - Remove unused AspeedI3CClass > - Refine memory region > - Refine register reset > - Remove unrelated changes to SPI2 address > - Remove i3c controller irq line > > v2: > - Split i3c model into i3c and i3c_device > - Create 6x i3c devices > - Using register fields macro > - Rebase to mainline QEMU > > Troy Lee (2): > Introduce a dummy AST2600 I3C model. > This patch includes i3c instance in ast2600 soc. > > hw/arm/aspeed_ast2600.c | 16 ++ > hw/misc/aspeed_i3c.c | 381 +++++++++++++++++++++++++++++++++++ > hw/misc/meson.build | 1 + > hw/misc/trace-events | 6 + > include/hw/arm/aspeed_soc.h | 3 + > include/hw/misc/aspeed_i3c.h | 48 +++++ > 6 files changed, 455 insertions(+) > create mode 100644 hw/misc/aspeed_i3c.c > create mode 100644 include/hw/misc/aspeed_i3c.h > > -- > 2.25.1 > > ^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH v3 0/2] Aspeed I3C device model 2022-01-12 10:57 ` Graeme Gregory @ 2022-01-12 12:45 ` Cédric Le Goater 2022-01-12 15:54 ` Graeme Gregory 2022-01-12 13:50 ` Troy Lee 1 sibling, 1 reply; 12+ messages in thread From: Cédric Le Goater @ 2022-01-12 12:45 UTC (permalink / raw) To: Graeme Gregory, Troy Lee; +Cc: leetroy, qemu-devel, hailin.wu Hello Gregory, On 1/12/22 11:57, Graeme Gregory wrote: > On Tue, Jan 11, 2022 at 04:45:44PM +0800, Troy Lee wrote: >> This series of patch introduce a dummy implemenation of aspeed i3c >> model, and it provide just enough information for guest machine. >> However, the driver probing is still failed, but it will not cause >> kernel panic. >> > > These patches arrived just in time for our i3c testing. This stops > our CI halting due to kernel panic on i3c probing. > > Reviewed-by: Graeme Gregory <quic_ggregory@quicinc.com> > Tested-by: Graeme Gregory <quic_ggregory@quicinc.com> Excellent ! Are you using the Aspeed image from : https://github.com/AspeedTech-BMC/openbmc/releases/tag/v07.02 or your custom ones ? Thanks, C. ^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH v3 0/2] Aspeed I3C device model 2022-01-12 12:45 ` Cédric Le Goater @ 2022-01-12 15:54 ` Graeme Gregory 0 siblings, 0 replies; 12+ messages in thread From: Graeme Gregory @ 2022-01-12 15:54 UTC (permalink / raw) To: Cédric Le Goater; +Cc: leetroy, Troy Lee, qemu-devel, hailin.wu On Wed, Jan 12, 2022 at 01:45:05PM +0100, Cédric Le Goater wrote: > Hello Gregory, > > On 1/12/22 11:57, Graeme Gregory wrote: > > On Tue, Jan 11, 2022 at 04:45:44PM +0800, Troy Lee wrote: > > > This series of patch introduce a dummy implemenation of aspeed i3c > > > model, and it provide just enough information for guest machine. > > > However, the driver probing is still failed, but it will not cause > > > kernel panic. > > > > > > > These patches arrived just in time for our i3c testing. This stops > > our CI halting due to kernel panic on i3c probing. > > > > Reviewed-by: Graeme Gregory <quic_ggregory@quicinc.com> > > Tested-by: Graeme Gregory <quic_ggregory@quicinc.com> > > Excellent ! > > Are you using the Aspeed image from : > > https://github.com/AspeedTech-BMC/openbmc/releases/tag/v07.02 > > or your custom ones ? > We are using the drivers from the v5.4 based SDK currently. Hacked into the v5.15 kernel of openbmc upstream! We needed something quick to test a new PCB. Graeme ^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH v3 0/2] Aspeed I3C device model 2022-01-12 10:57 ` Graeme Gregory 2022-01-12 12:45 ` Cédric Le Goater @ 2022-01-12 13:50 ` Troy Lee 1 sibling, 0 replies; 12+ messages in thread From: Troy Lee @ 2022-01-12 13:50 UTC (permalink / raw) To: Graeme Gregory; +Cc: Troy Lee, qemu-devel, hailin.wu On Wed, Jan 12, 2022 at 6:57 PM Graeme Gregory <quic_ggregory@quicinc.com> wrote: > > On Tue, Jan 11, 2022 at 04:45:44PM +0800, Troy Lee wrote: > > This series of patch introduce a dummy implemenation of aspeed i3c > > model, and it provide just enough information for guest machine. > > However, the driver probing is still failed, but it will not cause > > kernel panic. > > > > These patches arrived just in time for our i3c testing. This stops > our CI halting due to kernel panic on i3c probing. > > Reviewed-by: Graeme Gregory <quic_ggregory@quicinc.com> > Tested-by: Graeme Gregory <quic_ggregory@quicinc.com> > I'm glad it was able to help. Thanks, Troy Lee > > v3: > > - Remove unused AspeedI3CClass > > - Refine memory region > > - Refine register reset > > - Remove unrelated changes to SPI2 address > > - Remove i3c controller irq line > > > > v2: > > - Split i3c model into i3c and i3c_device > > - Create 6x i3c devices > > - Using register fields macro > > - Rebase to mainline QEMU > > > > Troy Lee (2): > > Introduce a dummy AST2600 I3C model. > > This patch includes i3c instance in ast2600 soc. > > > > hw/arm/aspeed_ast2600.c | 16 ++ > > hw/misc/aspeed_i3c.c | 381 +++++++++++++++++++++++++++++++++++ > > hw/misc/meson.build | 1 + > > hw/misc/trace-events | 6 + > > include/hw/arm/aspeed_soc.h | 3 + > > include/hw/misc/aspeed_i3c.h | 48 +++++ > > 6 files changed, 455 insertions(+) > > create mode 100644 hw/misc/aspeed_i3c.c > > create mode 100644 include/hw/misc/aspeed_i3c.h > > > > -- > > 2.25.1 > > > > ^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH v3 0/2] Aspeed I3C device model 2022-01-11 8:45 [PATCH v3 0/2] Aspeed I3C device model Troy Lee ` (3 preceding siblings ...) 2022-01-12 10:57 ` Graeme Gregory @ 2022-01-18 17:40 ` Peter Maydell 4 siblings, 0 replies; 12+ messages in thread From: Peter Maydell @ 2022-01-18 17:40 UTC (permalink / raw) To: Troy Lee; +Cc: leetroy, qemu-devel, hailin.wu, Cédric Le Goater On Tue, 11 Jan 2022 at 08:48, Troy Lee <troy_lee@aspeedtech.com> wrote: > > This series of patch introduce a dummy implemenation of aspeed i3c > model, and it provide just enough information for guest machine. > However, the driver probing is still failed, but it will not cause > kernel panic. > > v3: > - Remove unused AspeedI3CClass > - Refine memory region > - Refine register reset > - Remove unrelated changes to SPI2 address > - Remove i3c controller irq line > > v2: > - Split i3c model into i3c and i3c_device > - Create 6x i3c devices > - Using register fields macro > - Rebase to mainline QEMU > > Troy Lee (2): > Introduce a dummy AST2600 I3C model. > This patch includes i3c instance in ast2600 soc. Applied to target-arm.next, thanks. I have tidied up the commit messages a bit (removing the v2/v3 changes information, for instance). I would echo Cédric's suggestion that you send a patch that updates the documentation to note that this device is now partially implemented. -- PMM ^ permalink raw reply [flat|nested] 12+ messages in thread
end of thread, other threads:[~2022-01-20 22:37 UTC | newest] Thread overview: 12+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2022-01-11 8:45 [PATCH v3 0/2] Aspeed I3C device model Troy Lee 2022-01-11 8:45 ` [PATCH v3 1/2] Introduce a dummy AST2600 I3C model Troy Lee 2022-01-11 9:05 ` Cédric Le Goater 2022-01-11 8:45 ` [PATCH v3 2/2] This patch includes i3c instance in ast2600 soc Troy Lee 2022-01-11 9:12 ` Cédric Le Goater 2022-01-20 16:01 ` Peter Maydell 2022-01-11 9:21 ` [PATCH v3 0/2] Aspeed I3C device model Cédric Le Goater 2022-01-12 10:57 ` Graeme Gregory 2022-01-12 12:45 ` Cédric Le Goater 2022-01-12 15:54 ` Graeme Gregory 2022-01-12 13:50 ` Troy Lee 2022-01-18 17:40 ` Peter Maydell
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