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From: Peter Maydell <peter.maydell@linaro.org>
To: Alvise Rigo <a.rigo@virtualopensystems.com>
Cc: "tech@virtualopensystems.com" <tech@virtualopensystems.com>,
	QEMU Developers <qemu-devel@nongnu.org>
Subject: Re: [Qemu-devel] [RFC 3/4] Add l2ctlr cp register to CPUARMState
Date: Tue, 25 Feb 2014 18:22:14 +0000	[thread overview]
Message-ID: <CAFEAcA_q0ch8RVdSO_mJvhVcMZANvTvUBNev+SxuiP7aK+X=dA@mail.gmail.com> (raw)
In-Reply-To: <1393347170-28502-4-git-send-email-a.rigo@virtualopensystems.com>

On 25 February 2014 16:52, Alvise Rigo <a.rigo@virtualopensystems.com> wrote:
> Since the irq bit seems to not be updated, exclude it from the check done
> while copying data during migration.
>
> Signed-off-by: Alvise Rigo <a.rigo@virtualopensystems.com>
> ---
>  target-arm/cpu.c | 22 ++++++++++++++++++----
>  1 file changed, 18 insertions(+), 4 deletions(-)
>
> diff --git a/target-arm/cpu.c b/target-arm/cpu.c
> index 6e7ce89..e8db00e 100644
> --- a/target-arm/cpu.c
> +++ b/target-arm/cpu.c
> @@ -681,20 +681,34 @@ static void cortex_a9_initfn(Object *obj)
>  }
>
>  #ifndef CONFIG_USER_ONLY
> -static uint64_t a15_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri)
> +static void a15_l2ctlr_reset(CPUARMState *env, const ARMCPRegInfo *opaque)
>  {
>      /* Linux wants the number of processors from here.
>       * Might as well set the interrupt-controller bit too.
>       */
> -    return ((smp_cpus - 1) << 24) | (1 << 23);
> +    env->cp15.c9_l2ctlr = ((smp_cpus - 1) << 24) | (1 << 23);
> +}
> +
> +static void a15_l2ctlr_write(CPUARMState *env, const ARMCPRegInfo *ri,
> +                           uint64_t value)
> +{
> +    int smp_cpus_new = ((value >> 24) & 3);
> +    int smp_cpus_old = ((env->cp15.c9_l2ctlr >> 24) & 3);
> +
> +    if (smp_cpus_new != smp_cpus_old) {
> +        return;
> +    }
> +
> +    env->cp15.c9_l2ctlr = value;
>  }
>  #endif
>
>  static const ARMCPRegInfo cortexa15_cp_reginfo[] = {
>  #ifndef CONFIG_USER_ONLY
>      { .name = "L2CTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2,
> -      .access = PL1_RW, .resetvalue = 0, .readfn = a15_l2ctlr_read,
> -      .writefn = arm_cp_write_ignore, },
> +      .access = PL1_RW, .resetvalue = 0,
> +      .resetfn = a15_l2ctlr_reset, .writefn = a15_l2ctlr_write,
> +      .fieldoffset = offsetof(CPUARMState, cp15.c9_l2ctlr) },
>  #endif

Why are you changing the behaviour of this register from
read-only/writes-ignored to permitting writes? This looks
wrong.

thanks
-- PMM

  reply	other threads:[~2014-02-25 18:22 UTC|newest]

Thread overview: 23+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2014-02-25 16:52 [Qemu-devel] [RFC 0/4] target-arm: KVM to TCG migration Alvise Rigo
2014-02-25 16:52 ` [Qemu-devel] [RFC 1/4] Fix issue affecting get_int32_le() in vmstate.c Alvise Rigo
2014-02-25 18:11   ` Eduardo Habkost
2014-02-25 18:16   ` Peter Maydell
2014-02-25 18:52   ` Juan Quintela
2014-02-25 18:55     ` Peter Maydell
2014-02-25 16:52 ` [Qemu-devel] [RFC 2/4] Added flag in ARMCPU to track last execution mode Alvise Rigo
2014-02-25 18:19   ` Peter Maydell
2014-02-26  9:16     ` alvise rigo
2014-02-26  9:56       ` Peter Maydell
2014-02-25 16:52 ` [Qemu-devel] [RFC 3/4] Add l2ctlr cp register to CPUARMState Alvise Rigo
2014-02-25 18:22   ` Peter Maydell [this message]
2014-02-26  9:17     ` alvise rigo
2014-02-26 10:07       ` Peter Maydell
2014-02-25 16:52 ` [Qemu-devel] [RFC 4/4] Relevant changes to enable KVM to TCG migration Alvise Rigo
2014-02-25 18:25   ` Peter Maydell
2014-02-26 10:02     ` alvise rigo
2014-02-26 10:04       ` Peter Maydell
2014-02-26 10:27         ` alvise rigo
2014-02-26 10:33           ` Peter Maydell
2014-03-03 21:39       ` Peter Maydell
2014-03-05 15:01         ` alvise rigo
2014-03-05 17:11           ` Peter Maydell

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