From: Peter Maydell <peter.maydell@linaro.org>
To: "Cédric Le Goater" <clg@kaod.org>
Cc: QEMU Developers <qemu-devel@nongnu.org>,
qemu-arm <qemu-arm@nongnu.org>, Joel Stanley <joel@jms.id.au>,
Andrew Jeffery <andrew@aj.id.au>,
Jason Wang <jasowang@redhat.com>
Subject: Re: [Qemu-devel] [PATCH] ftgmac100: implement the new MDIO interface on Aspeed SoC
Date: Thu, 17 Jan 2019 18:44:42 +0000 [thread overview]
Message-ID: <CAFEAcA_x+4ReaCrW5CYmYqyJkbW72J-t7svthGKt325A1PGL=A@mail.gmail.com> (raw)
In-Reply-To: <20190111125759.31577-1-clg@kaod.org>
On Fri, 11 Jan 2019 at 12:58, Cédric Le Goater <clg@kaod.org> wrote:
>
> The PHY behind the MAC of an Aspeed SoC can be controlled using two
> different MDC/MDIO interfaces. The same registers PHYCR (MAC60) and
> PHYDATA (MAC64) are involved but they have a different layout.
>
> BIT31 of the Feature Register (MAC40) controls which MDC/MDIO
> interface is active.
>
> Signed-off-by: Cédric Le Goater <clg@kaod.org>
> ---
Applied to target-arm.next, thanks.
-- PMM
prev parent reply other threads:[~2019-01-17 18:44 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-01-11 12:57 [Qemu-devel] [PATCH] ftgmac100: implement the new MDIO interface on Aspeed SoC Cédric Le Goater
2019-01-13 22:52 ` Andrew Jeffery
2019-01-14 3:29 ` Joel Stanley
2019-01-14 7:32 ` Cédric Le Goater
2019-01-17 18:44 ` Peter Maydell [this message]
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