Re: [PATCH 0/4] Add support for Fujitsu A64FX processor

Re: [PATCH 0/4] Add support for Fujitsu A64FX processor

[Peter Maydell]

On Fri, 16 Jul 2021 at 06:27, Shuuichirou Ishii
<ishii.shuuichir@fujitsu.com> wrote:
>
> Hello, everyone.

Hi; it looks like something with your outgoing email setup still disagrees
with QEMU's mailing list server :-(  As far as I can tell these emails didn't
make it to the list, so only people on the direct-cc list will have
seen them :-(

> These are a series of patches to enable the Fujitsu A64FX processor[1] in "machine virt".
>
> [1]
> https://github.com/fujitsu/A64FX/blob/master/doc/A64FX_Microarchitecture_Manual_en_1.4.pdf
>
>
> The motivation for creating these patches was previously discussed in the following RFC.
>
> https://lore.kernel.org/qemu-devel/a56283b3-3bb2-d9a3-9a6e-8175cc17b376@linaro.org/
>
> This patch series is a fix to enable the A64FX processor by specifying "-cpu a64fx" in "-M virt".
> In the future, we plan to implement the implementation defined register group of the HPC
> (High Performance Computing) function[2] which is implemented specific to the A64FX processor,
> but since the A64FX-related functions are not implemented in QEMU at present,
> we will first implement the minimum necessary functions.
> However, since the A64FX-related functions are currently not implemented in QEMU,
> we will first implement the minimum necessary functions.
>
> [2]
> https://github.com/fujitsu/A64FX/blob/master/doc/A64FX_Specification_HPC_Extension_v1_EN.pdf
>
> Since this is the first time for us to contribute patches to qemu,
> we are sure that there will be some incompetence,
> but if there are any problems, we would appreciate your comments.
>
> Best regards
>
> Shuuichirou Ishii (4):
>   target-arm: Introduce ARM_FEATURE_A64FX
>   target-arm: cpu64: Add support for Fujitsu A64FX
>   tests/arm-cpu-features: Add A64FX processor related tests
>   docs/system: Add a64fx(Fujitsu A64FX processor) to supported guest CPU
>     type
>
>  docs/system/arm/virt.rst       |  1 +
>  hw/arm/virt.c                  |  1 +
>  target/arm/cpu.h               |  1 +
>  target/arm/cpu64.c             | 49 ++++++++++++++++++++++++++++++++++++++++++
>  tests/qtest/arm-cpu-features.c |  3 +++
>  5 files changed, 55 insertions(+)

thanks
-- PMM

RE: [PATCH 0/4] Add support for Fujitsu A64FX processor

[ishii.shuuichir]

Hi, peter
Thank you for your comment.

> Hi; it looks like something with your outgoing email setup still disagrees
> with QEMU's mailing list server :-(  As far as I can tell these emails didn't
> make it to the list, so only people on the direct-cc list will have
> seen them :-(

As you said, it seems that I am not listed in the mail server again.
When I contacted the server administrator before, 
the server administrator took care of it so that my e-mail address would not be judged as spam mail, 
but I am in the process of contacting the server administrator again.

If the mail server is able to list it correctly,
should we resubmit the V1 patch series to list it properly?
Or, since there are patches that have already been commented on,
should I post them as a V2 patch series that reflects those comments?

Best regards.

> -----Original Message-----
> From: Peter Maydell <peter.maydell@linaro.org>
> Sent: Monday, July 19, 2021 9:49 PM
> To: Ishii, Shuuichirou/石井 周一郎 <ishii.shuuichir@fujitsu.com>
> Cc: Thomas Huth <thuth@redhat.com>; Laurent Vivier <lvivier@redhat.com>;
> Paolo Bonzini <pbonzini@redhat.com>; qemu-arm <qemu-arm@nongnu.org>;
> QEMU Developers <qemu-devel@nongnu.org>
> Subject: Re: [PATCH 0/4] Add support for Fujitsu A64FX processor
> 
> On Fri, 16 Jul 2021 at 06:27, Shuuichirou Ishii
> <ishii.shuuichir@fujitsu.com> wrote:
> >
> > Hello, everyone.
> 
> Hi; it looks like something with your outgoing email setup still disagrees
> with QEMU's mailing list server :-(  As far as I can tell these emails didn't
> make it to the list, so only people on the direct-cc list will have
> seen them :-(
> 
> > These are a series of patches to enable the Fujitsu A64FX processor[1] in
> "machine virt".
> >
> > [1]
> >
> https://github.com/fujitsu/A64FX/blob/master/doc/A64FX_Microarchitecture_
> Manual_en_1.4.pdf
> >
> >
> > The motivation for creating these patches was previously discussed in the
> following RFC.
> >
> >
> https://lore.kernel.org/qemu-devel/a56283b3-3bb2-d9a3-9a6e-8175cc17b376
> @linaro.org/
> >
> > This patch series is a fix to enable the A64FX processor by specifying "-cpu
> a64fx" in "-M virt".
> > In the future, we plan to implement the implementation defined register group of
> the HPC
> > (High Performance Computing) function[2] which is implemented specific to the
> A64FX processor,
> > but since the A64FX-related functions are not implemented in QEMU at present,
> > we will first implement the minimum necessary functions.
> > However, since the A64FX-related functions are currently not implemented in
> QEMU,
> > we will first implement the minimum necessary functions.
> >
> > [2]
> >
> https://github.com/fujitsu/A64FX/blob/master/doc/A64FX_Specification_HPC_
> Extension_v1_EN.pdf
> >
> > Since this is the first time for us to contribute patches to qemu,
> > we are sure that there will be some incompetence,
> > but if there are any problems, we would appreciate your comments.
> >
> > Best regards
> >
> > Shuuichirou Ishii (4):
> >   target-arm: Introduce ARM_FEATURE_A64FX
> >   target-arm: cpu64: Add support for Fujitsu A64FX
> >   tests/arm-cpu-features: Add A64FX processor related tests
> >   docs/system: Add a64fx(Fujitsu A64FX processor) to supported guest CPU
> >     type
> >
> >  docs/system/arm/virt.rst       |  1 +
> >  hw/arm/virt.c                  |  1 +
> >  target/arm/cpu.h               |  1 +
> >  target/arm/cpu64.c             | 49
> ++++++++++++++++++++++++++++++++++++++++++
> >  tests/qtest/arm-cpu-features.c |  3 +++
> >  5 files changed, 55 insertions(+)
> 
> thanks
> -- PMM

Re: [PATCH 0/4] Add support for Fujitsu A64FX processor

[Peter Maydell]

On Tue, 20 Jul 2021 at 08:35, ishii.shuuichir@fujitsu.com
<ishii.shuuichir@fujitsu.com> wrote:
>
> Hi, peter
> Thank you for your comment.
>
> > Hi; it looks like something with your outgoing email setup still disagrees
> > with QEMU's mailing list server :-(  As far as I can tell these emails didn't
> > make it to the list, so only people on the direct-cc list will have
> > seen them :-(
>
> As you said, it seems that I am not listed in the mail server again.
> When I contacted the server administrator before,
> the server administrator took care of it so that my e-mail address would not be judged as spam mail,
> but I am in the process of contacting the server administrator again.
>
> If the mail server is able to list it correctly,
> should we resubmit the V1 patch series to list it properly?
> Or, since there are patches that have already been commented on,
> should I post them as a V2 patch series that reflects those comments?

Once you've got the mail issues sorted, if you have a v2 ready to
go at that point, you might as well just post the v2. Otherwise
you can repost the v1.

thanks
-- PMM

Re: [PATCH 0/4] Add support for Fujitsu A64FX processor

[Philippe Mathieu-Daudé]

Hi Ishii,

On 7/20/21 9:34 AM, ishii.shuuichir@fujitsu.com wrote:
> Hi, peter
> Thank you for your comment.
> 
>> Hi; it looks like something with your outgoing email setup still disagrees
>> with QEMU's mailing list server :-(  As far as I can tell these emails didn't
>> make it to the list, so only people on the direct-cc list will have
>> seen them :-(
> 
> As you said, it seems that I am not listed in the mail server again.
> When I contacted the server administrator before, 
> the server administrator took care of it so that my e-mail address would not be judged as spam mail, 
> but I am in the process of contacting the server administrator again.

Meanwhile you can send your series via sourcehut: https://sr.ht/

> If the mail server is able to list it correctly,
> should we resubmit the V1 patch series to list it properly?
> Or, since there are patches that have already been commented on,
> should I post them as a V2 patch series that reflects those comments?
> 
> Best regards.
> 
>> -----Original Message-----
>> From: Peter Maydell <peter.maydell@linaro.org>
>> Sent: Monday, July 19, 2021 9:49 PM
>> To: Ishii, Shuuichirou/石井 周一郎 <ishii.shuuichir@fujitsu.com>
>> Cc: Thomas Huth <thuth@redhat.com>; Laurent Vivier <lvivier@redhat.com>;
>> Paolo Bonzini <pbonzini@redhat.com>; qemu-arm <qemu-arm@nongnu.org>;
>> QEMU Developers <qemu-devel@nongnu.org>
>> Subject: Re: [PATCH 0/4] Add support for Fujitsu A64FX processor
>>
>> On Fri, 16 Jul 2021 at 06:27, Shuuichirou Ishii
>> <ishii.shuuichir@fujitsu.com> wrote:
>>>
>>> Hello, everyone.
>>
>> Hi; it looks like something with your outgoing email setup still disagrees
>> with QEMU's mailing list server :-(  As far as I can tell these emails didn't
>> make it to the list, so only people on the direct-cc list will have
>> seen them :-(
>>
>> thanks
>> -- PMM

RE: [PATCH 0/4] Add support for Fujitsu A64FX processor

[ishii.shuuichir]

Hi, Philippe.

> Meanwhile you can send your series via sourcehut: https://sr.ht/

Thank you for providing useful information.
We will use the above sites as needed.

Best regards.

> -----Original Message-----
> From: Philippe Mathieu-Daudé <philmd@redhat.com>
> Sent: Tuesday, July 20, 2021 8:25 PM
> To: Ishii, Shuuichirou/石井 周一郎 <ishii.shuuichir@fujitsu.com>; 'Peter Maydell'
> <peter.maydell@linaro.org>
> Cc: Laurent Vivier <lvivier@redhat.com>; Thomas Huth <thuth@redhat.com>;
> QEMU Developers <qemu-devel@nongnu.org>; qemu-arm
> <qemu-arm@nongnu.org>; Paolo Bonzini <pbonzini@redhat.com>
> Subject: Re: [PATCH 0/4] Add support for Fujitsu A64FX processor
> 
> Hi Ishii,
> 
> On 7/20/21 9:34 AM, ishii.shuuichir@fujitsu.com wrote:
> > Hi, peter
> > Thank you for your comment.
> >
> >> Hi; it looks like something with your outgoing email setup still
> >> disagrees with QEMU's mailing list server :-(  As far as I can tell
> >> these emails didn't make it to the list, so only people on the
> >> direct-cc list will have seen them :-(
> >
> > As you said, it seems that I am not listed in the mail server again.
> > When I contacted the server administrator before, the server
> > administrator took care of it so that my e-mail address would not be
> > judged as spam mail, but I am in the process of contacting the server
> administrator again.
> 
> Meanwhile you can send your series via sourcehut: https://sr.ht/
> 
> > If the mail server is able to list it correctly, should we resubmit
> > the V1 patch series to list it properly?
> > Or, since there are patches that have already been commented on,
> > should I post them as a V2 patch series that reflects those comments?
> >
> > Best regards.
> >
> >> -----Original Message-----
> >> From: Peter Maydell <peter.maydell@linaro.org>
> >> Sent: Monday, July 19, 2021 9:49 PM
> >> To: Ishii, Shuuichirou/石井 周一郎 <ishii.shuuichir@fujitsu.com>
> >> Cc: Thomas Huth <thuth@redhat.com>; Laurent Vivier
> >> <lvivier@redhat.com>; Paolo Bonzini <pbonzini@redhat.com>; qemu-arm
> >> <qemu-arm@nongnu.org>; QEMU Developers <qemu-devel@nongnu.org>
> >> Subject: Re: [PATCH 0/4] Add support for Fujitsu A64FX processor
> >>
> >> On Fri, 16 Jul 2021 at 06:27, Shuuichirou Ishii
> >> <ishii.shuuichir@fujitsu.com> wrote:
> >>>
> >>> Hello, everyone.
> >>
> >> Hi; it looks like something with your outgoing email setup still
> >> disagrees with QEMU's mailing list server :-(  As far as I can tell
> >> these emails didn't make it to the list, so only people on the
> >> direct-cc list will have seen them :-(
> >>
> >> thanks
> >> -- PMM

Re: [PATCH 1/4] target-arm: Introduce ARM_FEATURE_A64FX

[Peter Maydell]

On Fri, 16 Jul 2021 at 06:27, Shuuichirou Ishii
<ishii.shuuichir@fujitsu.com> wrote:
>
> This function is used to distinguish HPC extensions in the Fujitsu A64FX processor.
>
> HPC (High Performance Computing) extensions are A64FX processor-specific features
> that are implemented to improve application performance for HPC.
>
> Signed-off-by: Shuuichirou Ishii <ishii.shuuichir@fujitsu.com>
> ---
>  target/arm/cpu.h | 1 +
>  1 file changed, 1 insertion(+)
>
> diff --git a/target/arm/cpu.h b/target/arm/cpu.h
> index be9a4dc..e5c8645 100644
> --- a/target/arm/cpu.h
> +++ b/target/arm/cpu.h
> @@ -2140,6 +2140,7 @@ enum arm_features {
>      ARM_FEATURE_M_SECURITY, /* M profile Security Extension */
>      ARM_FEATURE_M_MAIN, /* M profile Main Extension */
>      ARM_FEATURE_V8_1M, /* M profile extras only in v8.1M and later */
> +    ARM_FEATURE_A64FX, /* Fujitsu A64FX processor HPC extensions support */
>  };

Hi; as far as I can see there's nothing in your patchset that ever
tests this feature bit and behaves differently as a result. We
shouldn't add the feature flag until we have something we want to
control with it.

thanks
-- PMM

Re: [PATCH 2/4] target-arm: cpu64: Add support for Fujitsu A64FX

[Peter Maydell]

On Fri, 16 Jul 2021 at 06:27, Shuuichirou Ishii
<ishii.shuuichir@fujitsu.com> wrote:
>
> Add a definition for the Fujitsu A64FX processor.
>
> The A64FX processor does not implement the AArch32 Execution state,
> so there are no associated AArch32 Identification registers.
>
> Signed-off-by: Shuuichirou Ishii <ishii.shuuichir@fujitsu.com>
> ---
>  hw/arm/virt.c      |  1 +
>  target/arm/cpu64.c | 49 +++++++++++++++++++++++++++++++++++++++++++++++++
>  2 files changed, 50 insertions(+)
>
> diff --git a/hw/arm/virt.c b/hw/arm/virt.c
> index 93ab9d2..2e91991 100644
> --- a/hw/arm/virt.c
> +++ b/hw/arm/virt.c
> @@ -202,6 +202,7 @@ static const char *valid_cpus[] = {
>      ARM_CPU_TYPE_NAME("cortex-a72"),
>      ARM_CPU_TYPE_NAME("host"),
>      ARM_CPU_TYPE_NAME("max"),
> +    ARM_CPU_TYPE_NAME("a64fx"),
>  };
>
>  static bool cpu_type_valid(const char *cpu)
> diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
> index c7a1626..a2c22a2 100644
> --- a/target/arm/cpu64.c
> +++ b/target/arm/cpu64.c
> @@ -787,11 +787,60 @@ static void aarch64_max_initfn(Object *obj)
>                          cpu_max_set_sve_max_vq, NULL, NULL);
>  }
>
> +static const ARMCPRegInfo a64fx_cp_reginfo[] = {
> +    /* TODO  Add A64FX specific HPC extensinos registers */

"extension".

Rather than defining a reginfo array with no contents, just put
the TODO comment into the initfn. We can add the array and the
call to define_arm_cp_regs() when we actually add the first
a64fx-specific register.

> +    REGINFO_SENTINEL
> +};
> +static void aarch64_a64fx_initfn(Object *obj)
> +{
> +    ARMCPU *cpu = ARM_CPU(obj);
> +
> +    cpu->dtb_compatible = "arm,a64fx";
> +    set_feature(&cpu->env, ARM_FEATURE_A64FX);
> +    set_feature(&cpu->env, ARM_FEATURE_V8);
> +    set_feature(&cpu->env, ARM_FEATURE_NEON);
> +    set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
> +    set_feature(&cpu->env, ARM_FEATURE_AARCH64);
> +    set_feature(&cpu->env, ARM_FEATURE_EL2);
> +    set_feature(&cpu->env, ARM_FEATURE_EL3);
> +    set_feature(&cpu->env, ARM_FEATURE_PMU);
> +    cpu->midr = 0x461f0010;
> +    cpu->revidr = 0x00000000;
> +    cpu->ctr = 86668006;
> +    cpu->reset_sctlr = 0x30000180;
> +    cpu->isar.id_aa64pfr0 =   0x0000000101111111; /* No RAS Extensions */
> +    cpu->isar.id_aa64pfr1 = 0x0000000000000000;
> +    cpu->isar.id_aa64dfr0 = 0x0000000010305408;
> +    cpu->isar.id_aa64dfr1 = 0x0000000000000000;
> +    cpu->id_aa64afr0 = 0x0000000000000000;
> +    cpu->id_aa64afr1 = 0x0000000000000000;
> +    cpu->isar.id_aa64mmfr0 = 0x0000000000001122;
> +    cpu->isar.id_aa64mmfr1 = 0x0000000011212100;
> +    cpu->isar.id_aa64mmfr2 = 0x0000000000001011;
> +    cpu->isar.id_aa64isar0 = 0x0000000010211120;
> +    cpu->isar.id_aa64isar1 = 0x0000000000010001;
> +    cpu->isar.id_aa64zfr0 = 0x0000000000000000;
> +    cpu->clidr = 0x0000000080000023;
> +    cpu->ccsidr[0] = 0x7007e01c; /* 64KB L1 dcache */
> +    cpu->ccsidr[1] = 0x2007e01c; /* 64KB L1 icache */
> +    cpu->ccsidr[2] = 0x70ffe07c; /* 8MB L2 cache */
> +    cpu->dcz_blocksize = 6; /* 256 bytes */
> +    cpu->gic_num_lrs = 4;
> +    cpu->gic_vpribits = 5;
> +    cpu->gic_vprebits = 5;
> +    define_arm_cp_regs(cpu, a64fx_cp_reginfo);
> +
> +    aarch64_add_sve_properties(obj);
> +    object_property_add(obj, "sve-max-vq", "uint32", cpu_max_get_sve_max_vq,
> +                        cpu_max_set_sve_max_vq, NULL, NULL);
> +}
> +
>  static const ARMCPUInfo aarch64_cpus[] = {
>      { .name = "cortex-a57",         .initfn = aarch64_a57_initfn },
>      { .name = "cortex-a53",         .initfn = aarch64_a53_initfn },
>      { .name = "cortex-a72",         .initfn = aarch64_a72_initfn },
>      { .name = "max",                .initfn = aarch64_max_initfn },
> +    { .name = "a64fx",              .initfn = aarch64_a64fx_initfn },

Leave "max" at the end of the list, please.

>  };
>
>  static bool aarch64_cpu_get_aarch64(Object *obj, Error **errp)

Otherwise this patch looks good to me.

thanks
-- PMM

Re: [PATCH 4/4] docs/system: Add a64fx(Fujitsu A64FX processor) to supported guest CPU type

[Peter Maydell]

On Fri, 16 Jul 2021 at 06:27, Shuuichirou Ishii
<ishii.shuuichir@fujitsu.com> wrote:
>
> Signed-off-by: Shuuichirou Ishii <ishii.shuuichir@fujitsu.com>
> ---
>  docs/system/arm/virt.rst | 1 +
>  1 file changed, 1 insertion(+)
>
> diff --git a/docs/system/arm/virt.rst b/docs/system/arm/virt.rst
> index 27652ad..5329e95 100644
> --- a/docs/system/arm/virt.rst
> +++ b/docs/system/arm/virt.rst
> @@ -55,6 +55,7 @@ Supported guest CPU types:
>  - ``cortex-a53`` (64-bit)
>  - ``cortex-a57`` (64-bit)
>  - ``cortex-a72`` (64-bit)
> +- ``a64fx`` (64-bit)
>  - ``host`` (with KVM only)
>  - ``max`` (same as ``host`` for KVM; best possible emulation with TCG)

This adds a64fx to the list of CPUs we support in the 'virt' board,
but it hasn't changed the valid_cpus[] array in hw/arm/virt.c, so
trying to actually use -cpu a64fx with -machine virt will fail.

thanks
-- PMM

RE: [PATCH 4/4] docs/system: Add a64fx(Fujitsu A64FX processor) to supported guest CPU type

[ishii.shuuichir]

Hi, Peter.

> This adds a64fx to the list of CPUs we support in the 'virt' board, but it hasn't
> changed the valid_cpus[] array in hw/arm/virt.c, so trying to actually use -cpu
> a64fx with -machine virt will fail.

I'm sorry, but just to be sure, let me check.

Is it correct to understand that the above comment means that we need to add
the following fixes included in "[PATCH 2/4] target-arm: cpu64: Add support for Fujitsu A64FX" patch
within this patch to make it a meaningful fix within one patch?

> diff --git a/hw/arm/virt.c b/hw/arm/virt.c
> index 93ab9d2..2e91991 100644
> --- a/hw/arm/virt.c
> +++ b/hw/arm/virt.c
> @@ -202,6 +202,7 @@ static const char *valid_cpus[] = {
> ARM_CPU_TYPE_NAME("cortex-a72"),
> ARM_CPU_TYPE_NAME("host"),
> ARM_CPU_TYPE_NAME("max"),
> + ARM_CPU_TYPE_NAME("a64fx"),
> };

Best regards.

> -----Original Message-----
> From: Peter Maydell <peter.maydell@linaro.org>
> Sent: Monday, July 19, 2021 9:56 PM
> To: ishii.shuuichir@fujitsu.com
> Cc: Thomas Huth <thuth@redhat.com>; Laurent Vivier <lvivier@redhat.com>;
> Paolo Bonzini <pbonzini@redhat.com>; qemu-arm <qemu-arm@nongnu.org>;
> QEMU Developers <qemu-devel@nongnu.org>
> Subject: Re: [PATCH 4/4] docs/system: Add a64fx(Fujitsu A64FX processor) to
> supported guest CPU type
> 
> On Fri, 16 Jul 2021 at 06:27, Shuuichirou Ishii <ishii.shuuichir@fujitsu.com>
> wrote:
> >
> > Signed-off-by: Shuuichirou Ishii <ishii.shuuichir@fujitsu.com>
> > ---
> >  docs/system/arm/virt.rst | 1 +
> >  1 file changed, 1 insertion(+)
> >
> > diff --git a/docs/system/arm/virt.rst b/docs/system/arm/virt.rst index
> > 27652ad..5329e95 100644
> > --- a/docs/system/arm/virt.rst
> > +++ b/docs/system/arm/virt.rst
> > @@ -55,6 +55,7 @@ Supported guest CPU types:
> >  - ``cortex-a53`` (64-bit)
> >  - ``cortex-a57`` (64-bit)
> >  - ``cortex-a72`` (64-bit)
> > +- ``a64fx`` (64-bit)
> >  - ``host`` (with KVM only)
> >  - ``max`` (same as ``host`` for KVM; best possible emulation with
> > TCG)
> 
> This adds a64fx to the list of CPUs we support in the 'virt' board, but it hasn't
> changed the valid_cpus[] array in hw/arm/virt.c, so trying to actually use -cpu
> a64fx with -machine virt will fail.
> 
> thanks
> -- PMM

Re: [PATCH 4/4] docs/system: Add a64fx(Fujitsu A64FX processor) to supported guest CPU type

[Peter Maydell]

On Thu, 29 Jul 2021 at 08:31, ishii.shuuichir@fujitsu.com
<ishii.shuuichir@fujitsu.com> wrote:
>
> Hi, Peter.
>
> > This adds a64fx to the list of CPUs we support in the 'virt' board, but it hasn't
> > changed the valid_cpus[] array in hw/arm/virt.c, so trying to actually use -cpu
> > a64fx with -machine virt will fail.
>
> I'm sorry, but just to be sure, let me check.
>
> Is it correct to understand that the above comment means that we need to add
> the following fixes included in "[PATCH 2/4] target-arm: cpu64: Add support for Fujitsu A64FX" patch
> within this patch to make it a meaningful fix within one patch?
>
> > diff --git a/hw/arm/virt.c b/hw/arm/virt.c
> > index 93ab9d2..2e91991 100644
> > --- a/hw/arm/virt.c
> > +++ b/hw/arm/virt.c
> > @@ -202,6 +202,7 @@ static const char *valid_cpus[] = {
> > ARM_CPU_TYPE_NAME("cortex-a72"),
> > ARM_CPU_TYPE_NAME("host"),
> > ARM_CPU_TYPE_NAME("max"),
> > + ARM_CPU_TYPE_NAME("a64fx"),
> > };

If you want this CPU to work with the virt board, then yes.
You should put it above 'host' and 'max' (because those are
not-real-cpu special cases, so it makes more sense for them to be last
in the list).

More generally: how are you testing this patchset? To test it
you should have at least one board that lets you use the new
CPU type so you can boot some guest with it. So if that's not
"virt" then what is it?

-- PMM

RE: [PATCH 4/4] docs/system: Add a64fx(Fujitsu A64FX processor) to supported guest CPU type

[ishii.shuuichir]

> If you want this CPU to work with the virt board, then yes.
> You should put it above 'host' and 'max' (because those are
> not-real-cpu special cases, so it makes more sense for them to be last
> in the list).
> 
> More generally: how are you testing this patchset? To test it
> you should have at least one board that lets you use the new
> CPU type so you can boot some guest with it. So if that's not
> "virt" then what is it?

We are testing it on the virt board.
Therefore, we will fix it as you suggested.

Best regards.

> -----Original Message-----
> From: Peter Maydell <peter.maydell@linaro.org>
> Sent: Thursday, July 29, 2021 6:43 PM
> To: Ishii, Shuuichirou/石井 周一郎 <ishii.shuuichir@fujitsu.com>
> Cc: Thomas Huth <thuth@redhat.com>; Laurent Vivier <lvivier@redhat.com>;
> Paolo Bonzini <pbonzini@redhat.com>; qemu-arm <qemu-arm@nongnu.org>;
> QEMU Developers <qemu-devel@nongnu.org>
> Subject: Re: [PATCH 4/4] docs/system: Add a64fx(Fujitsu A64FX processor) to
> supported guest CPU type
> 
> On Thu, 29 Jul 2021 at 08:31, ishii.shuuichir@fujitsu.com
> <ishii.shuuichir@fujitsu.com> wrote:
> >
> > Hi, Peter.
> >
> > > This adds a64fx to the list of CPUs we support in the 'virt' board, but it hasn't
> > > changed the valid_cpus[] array in hw/arm/virt.c, so trying to actually use -cpu
> > > a64fx with -machine virt will fail.
> >
> > I'm sorry, but just to be sure, let me check.
> >
> > Is it correct to understand that the above comment means that we need to add
> > the following fixes included in "[PATCH 2/4] target-arm: cpu64: Add support for
> Fujitsu A64FX" patch
> > within this patch to make it a meaningful fix within one patch?
> >
> > > diff --git a/hw/arm/virt.c b/hw/arm/virt.c
> > > index 93ab9d2..2e91991 100644
> > > --- a/hw/arm/virt.c
> > > +++ b/hw/arm/virt.c
> > > @@ -202,6 +202,7 @@ static const char *valid_cpus[] = {
> > > ARM_CPU_TYPE_NAME("cortex-a72"),
> > > ARM_CPU_TYPE_NAME("host"),
> > > ARM_CPU_TYPE_NAME("max"),
> > > + ARM_CPU_TYPE_NAME("a64fx"),
> > > };
> 
> If you want this CPU to work with the virt board, then yes.
> You should put it above 'host' and 'max' (because those are
> not-real-cpu special cases, so it makes more sense for them to be last
> in the list).
> 
> More generally: how are you testing this patchset? To test it
> you should have at least one board that lets you use the new
> CPU type so you can boot some guest with it. So if that's not
> "virt" then what is it?
> 
> -- PMM

Re: [PATCH 3/4] tests/arm-cpu-features: Add A64FX processor related tests

[Peter Maydell]

On Fri, 16 Jul 2021 at 06:27, Shuuichirou Ishii
<ishii.shuuichir@fujitsu.com> wrote:
>
> Signed-off-by: Shuuichirou Ishii <ishii.shuuichir@fujitsu.com>
> ---
>  tests/qtest/arm-cpu-features.c | 3 +++
>  1 file changed, 3 insertions(+)
>
> diff --git a/tests/qtest/arm-cpu-features.c b/tests/qtest/arm-cpu-features.c
> index 8252b85..979c6f8 100644
> --- a/tests/qtest/arm-cpu-features.c
> +++ b/tests/qtest/arm-cpu-features.c
> @@ -472,6 +472,9 @@ static void test_query_cpu_model_expansion(const void *data)
>          assert_has_feature_enabled(qts, "max", "sve128");
>          assert_has_feature_enabled(qts, "cortex-a57", "pmu");
>          assert_has_feature_enabled(qts, "cortex-a57", "aarch64");
> +        assert_has_feature_enabled(qts, "a64fx", "pmu");
> +        assert_has_feature_enabled(qts, "a64fx", "aarch64");
> +        assert_has_feature_enabled(qts, "a64fx", "sve");
>
>          sve_tests_default(qts, "max");
>          pauth_tests_default(qts, "max");
> --
> 1.8.3.1

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>

thanks
-- PMM