* [PATCH] ALSA: x86: Ensure VLV bitwise operations are SOC specific
@ 2017-02-10 3:33 Ian W MORRISON
2017-02-10 22:54 ` Pierre-Louis Bossart
0 siblings, 1 reply; 3+ messages in thread
From: Ian W MORRISON @ 2017-02-10 3:33 UTC (permalink / raw)
To: Takashi Iwai; +Cc: alsa-devel, Pierre-Louis Bossart, Jerome Anand
The function vlv_display_irq_postinstall is used by both valleyview
and cherryview irq handling. I915_LPE_PIPE_C_INTERRUPT is specific
to cherryview so should be excluded from any valleyview associated
bitwise operations.
Signed-off-by: Ian W Morrison <linuxium@linuxium.com.au>
---
drivers/gpu/drm/i915/i915_irq.c | 7 ++++---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c
b/drivers/gpu/drm/i915/i915_irq.c
index f0880af..ee61808 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2940,9 +2940,10 @@ static void vlv_display_irq_postinstall(struct
drm_i915_private *dev_priv)
WARN_ON(dev_priv->irq_mask != ~0);
- val = (I915_LPE_PIPE_A_INTERRUPT |
- I915_LPE_PIPE_B_INTERRUPT |
- I915_LPE_PIPE_C_INTERRUPT);
+ val = I915_LPE_PIPE_A_INTERRUPT |
+ I915_LPE_PIPE_B_INTERRUPT;
+ if (IS_CHERRYVIEW(dev_priv))
+ val |= I915_LPE_PIPE_C_INTERRUPT;
enable_mask |= val;
--
1.9.1
^ permalink raw reply related [flat|nested] 3+ messages in thread
* Re: [PATCH] ALSA: x86: Ensure VLV bitwise operations are SOC specific
2017-02-10 3:33 [PATCH] ALSA: x86: Ensure VLV bitwise operations are SOC specific Ian W MORRISON
@ 2017-02-10 22:54 ` Pierre-Louis Bossart
2017-02-10 23:49 ` Ian W MORRISON
0 siblings, 1 reply; 3+ messages in thread
From: Pierre-Louis Bossart @ 2017-02-10 22:54 UTC (permalink / raw)
To: Ian W MORRISON, Takashi Iwai; +Cc: alsa-devel, Jerome Anand
On 2/9/17 9:33 PM, Ian W MORRISON wrote:
> The function vlv_display_irq_postinstall is used by both valleyview
> and cherryview irq handling. I915_LPE_PIPE_C_INTERRUPT is specific
> to cherryview so should be excluded from any valleyview associated
> bitwise operations.
it's a write indeed to a field that isn't defined but there is no
matching read or action taken as a result of a write of that field. Does
this solve a real problem or is this more to make the code more consistent?
>
> Signed-off-by: Ian W Morrison <linuxium@linuxium.com.au
> <mailto:linuxium@linuxium.com.au>>
> ---
> drivers/gpu/drm/i915/i915_irq.c | 7 ++++---
> 1 file changed, 4 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_irq.c
> b/drivers/gpu/drm/i915/i915_irq.c
> index f0880af..ee61808 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -2940,9 +2940,10 @@ static void vlv_display_irq_postinstall(struct
> drm_i915_private *dev_priv)
>
> WARN_ON(dev_priv->irq_mask != ~0);
>
> - val = (I915_LPE_PIPE_A_INTERRUPT |
> - I915_LPE_PIPE_B_INTERRUPT |
> - I915_LPE_PIPE_C_INTERRUPT);
> + val = I915_LPE_PIPE_A_INTERRUPT |
> + I915_LPE_PIPE_B_INTERRUPT;
> + if (IS_CHERRYVIEW(dev_priv))
> + val |= I915_LPE_PIPE_C_INTERRUPT;
>
> enable_mask |= val;
>
> --
> 1.9.1
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH] ALSA: x86: Ensure VLV bitwise operations are SOC specific
2017-02-10 22:54 ` Pierre-Louis Bossart
@ 2017-02-10 23:49 ` Ian W MORRISON
0 siblings, 0 replies; 3+ messages in thread
From: Ian W MORRISON @ 2017-02-10 23:49 UTC (permalink / raw)
To: Pierre-Louis Bossart; +Cc: Takashi Iwai, alsa-devel, Jerome Anand
On 11 February 2017 at 09:54, Pierre-Louis Bossart <
pierre-louis.bossart@linux.intel.com> wrote:
> On 2/9/17 9:33 PM, Ian W MORRISON wrote:
>
>> The function vlv_display_irq_postinstall is used by both valleyview
>> and cherryview irq handling. I915_LPE_PIPE_C_INTERRUPT is specific
>> to cherryview so should be excluded from any valleyview associated
>> bitwise operations.
>>
>
> it's a write indeed to a field that isn't defined but there is no matching
> read or action taken as a result of a write of that field. Does this solve
> a real problem or is this more to make the code more consistent?
>
>
Certainly the later and only to the point of removing any opportunities for
problems to exist for the former. In trying to diagnose the '*ERROR* Atomic
update failure on pipe X' messages in 'dmesg' it was more of a straw grasp.
>
>> Signed-off-by: Ian W Morrison <linuxium@linuxium.com.au
>> <mailto:linuxium@linuxium.com.au>>
>> ---
>> drivers/gpu/drm/i915/i915_irq.c | 7 ++++---
>> 1 file changed, 4 insertions(+), 3 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_irq.c
>> b/drivers/gpu/drm/i915/i915_irq.c
>> index f0880af..ee61808 100644
>> --- a/drivers/gpu/drm/i915/i915_irq.c
>> +++ b/drivers/gpu/drm/i915/i915_irq.c
>> @@ -2940,9 +2940,10 @@ static void vlv_display_irq_postinstall(struct
>> drm_i915_private *dev_priv)
>>
>> WARN_ON(dev_priv->irq_mask != ~0);
>>
>> - val = (I915_LPE_PIPE_A_INTERRUPT |
>> - I915_LPE_PIPE_B_INTERRUPT |
>> - I915_LPE_PIPE_C_INTERRUPT);
>> + val = I915_LPE_PIPE_A_INTERRUPT |
>> + I915_LPE_PIPE_B_INTERRUPT;
>> + if (IS_CHERRYVIEW(dev_priv))
>> + val |= I915_LPE_PIPE_C_INTERRUPT;
>>
>> enable_mask |= val;
>>
>> --
>> 1.9.1
>>
>
>
^ permalink raw reply [flat|nested] 3+ messages in thread
end of thread, other threads:[~2017-02-10 23:49 UTC | newest]
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2017-02-10 3:33 [PATCH] ALSA: x86: Ensure VLV bitwise operations are SOC specific Ian W MORRISON
2017-02-10 22:54 ` Pierre-Louis Bossart
2017-02-10 23:49 ` Ian W MORRISON
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