From: Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in> To: "Z.q. Hou" <zhiqiang.hou@nxp.com> Cc: Bjorn Helgaas <helgaas@kernel.org>, "linux-pci@vger.kernel.org" <linux-pci@vger.kernel.org>, "linux-arm-kernel@lists.infradead.org" <linux-arm-kernel@lists.infradead.org>, "devicetree@vger.kernel.org" <devicetree@vger.kernel.org>, "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>, "robh+dt@kernel.org" <robh+dt@kernel.org>, "mark.rutland@arm.com" <mark.rutland@arm.com>, "shawnguo@kernel.org" <shawnguo@kernel.org>, Leo Li <leoyang.li@nxp.com>, "lorenzo.pieralisi@arm.com" <lorenzo.pieralisi@arm.com>, "catalin.marinas@arm.com" <catalin.marinas@arm.com>, "will.deacon@arm.com" <will.deacon@arm.com>, Mingkai Hu <mingkai.hu@nxp.com>, "M.h. Lian" <minghuan.lian@nxp.com>, Xiaowei Bao <xiaowei.bao@nxp.com> Subject: Re: [PATCHv4 11/28] PCI: mobiveil: only fix up the Class Code field Date: Wed, 13 Mar 2019 16:29:18 +0530 [thread overview] Message-ID: <CAFZiPx1+SDPLZ3CAAhSxbTUWdKrnx3UkF99nTxwqoNx3mdXDcA@mail.gmail.com> (raw) In-Reply-To: <AM6PR04MB5781498315C6B69EB2586B9D84490@AM6PR04MB5781.eurprd04.prod.outlook.com> Bjorn/ZQ, On Tue, Mar 12, 2019 at 2:48 PM Z.q. Hou <zhiqiang.hou@nxp.com> wrote: > > Hi Bjorn, > > Thanks a lot for your comments! > > > -----Original Message----- > > From: Bjorn Helgaas [mailto:helgaas@kernel.org] > > Sent: 2019年3月11日 22:14 > > To: Z.q. Hou <zhiqiang.hou@nxp.com> > > Cc: linux-pci@vger.kernel.org; linux-arm-kernel@lists.infradead.org; > > devicetree@vger.kernel.org; linux-kernel@vger.kernel.org; > > robh+dt@kernel.org; mark.rutland@arm.com; l.subrahmanya@mobiveil.co.in; > > shawnguo@kernel.org; Leo Li <leoyang.li@nxp.com>; > > lorenzo.pieralisi@arm.com; catalin.marinas@arm.com; > > will.deacon@arm.com; Mingkai Hu <mingkai.hu@nxp.com>; M.h. Lian > > <minghuan.lian@nxp.com>; Xiaowei Bao <xiaowei.bao@nxp.com> > > Subject: Re: [PATCHv4 11/28] PCI: mobiveil: only fix up the Class Code field > > > > On Mon, Mar 11, 2019 at 09:31:23AM +0000, Z.q. Hou wrote: > > > From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> > > > > > > Fix up the Class Code to PCI bridge, do not change the Revision ID. > > > And move the fixup to mobiveil_host_init function. > > > > Add parens after function name. > > > > Please explain why this change is needed. Does it fix a bug? > > > > Does this fix the problem that the PCI core didn't correctly identify the device > > as a bridge because it identified bridges by class code instead of header type? > > > > That problem *should* be fixed by b2fb5cc57469 ("PCI: Rely on config space > > header type, not class code"), which is now upstream. > > > > You might still want this class code change so that lspci shows the correct > > thing. That's fine, but the changelog should say why we're doing it. > > > > Subrahmanya's original patch is to fixup 'Class Code' field, but it also fixed the 'Revision ID' field. This patch is patch is to remove the fixup of 'Revision ID' field. it was introduced during the test with 4.9 and 4.15 linux version, without this fix driver was not getting loaded. I belive it should be sufficient to mention in code comment: "Fixing the class code as hardware is not reflecting the correct class code", And the changelog for this patch mentioning "avoid changing the revision ID during the class code fix". Is that OK? Thanks, > > > > Fixes: 9af6bcb11e12 ("PCI: mobiveil: Add Mobiveil PCIe Host Bridge IP > > > driver") > > > > Make this "Fixes:" line a single line again. > > > > > Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> > > > Reviewed-by: Minghuan Lian <Minghuan.Lian@nxp.com> > > > Reviewed-by: Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in> > > > --- > > > V4: > > > - no change > > > > > > drivers/pci/controller/pcie-mobiveil.c | 9 ++++++--- > > > 1 file changed, 6 insertions(+), 3 deletions(-) > > > > > > diff --git a/drivers/pci/controller/pcie-mobiveil.c > > > b/drivers/pci/controller/pcie-mobiveil.c > > > index 78e575e71f4d..8eee1ab7ee24 100644 > > > --- a/drivers/pci/controller/pcie-mobiveil.c > > > +++ b/drivers/pci/controller/pcie-mobiveil.c > > > @@ -653,6 +653,12 @@ static int mobiveil_host_init(struct mobiveil_pcie > > *pcie) > > > type, resource_size(win->res)); > > > } > > > > > > + /* fixup for PCIe class register */ > > > + value = csr_readl(pcie, PAB_INTP_AXI_PIO_CLASS); > > > + value &= 0xff; > > > + value |= (PCI_CLASS_BRIDGE_PCI << 16); > > > + csr_writel(pcie, value, PAB_INTP_AXI_PIO_CLASS); > > > + > > > /* setup MSI hardware registers */ > > > mobiveil_pcie_enable_msi(pcie); > > > > > > @@ -896,9 +902,6 @@ static int mobiveil_pcie_probe(struct > > platform_device *pdev) > > > goto error; > > > } > > > > > > - /* fixup for PCIe class register */ > > > - csr_writel(pcie, 0x060402ab, PAB_INTP_AXI_PIO_CLASS); > > > - > > > /* initialize the IRQ domains */ > > > ret = mobiveil_pcie_init_irq_domain(pcie); > > > if (ret) { > > > -- > > > 2.17.1 > > > > > Thanks, > Zhiqiang
WARNING: multiple messages have this Message-ID (diff)
From: Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in> To: "Z.q. Hou" <zhiqiang.hou@nxp.com> Cc: "mark.rutland@arm.com" <mark.rutland@arm.com>, "devicetree@vger.kernel.org" <devicetree@vger.kernel.org>, "lorenzo.pieralisi@arm.com" <lorenzo.pieralisi@arm.com>, Xiaowei Bao <xiaowei.bao@nxp.com>, "linux-pci@vger.kernel.org" <linux-pci@vger.kernel.org>, "will.deacon@arm.com" <will.deacon@arm.com>, "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>, Leo Li <leoyang.li@nxp.com>, "M.h. Lian" <minghuan.lian@nxp.com>, "robh+dt@kernel.org" <robh+dt@kernel.org>, Bjorn Helgaas <helgaas@kernel.org>, Mingkai Hu <mingkai.hu@nxp.com>, "catalin.marinas@arm.com" <catalin.marinas@arm.com>, "shawnguo@kernel.org" <shawnguo@kernel.org>, "linux-arm-kernel@lists.infradead.org" <linux-arm-kernel@lists.infradead.org> Subject: Re: [PATCHv4 11/28] PCI: mobiveil: only fix up the Class Code field Date: Wed, 13 Mar 2019 16:29:18 +0530 [thread overview] Message-ID: <CAFZiPx1+SDPLZ3CAAhSxbTUWdKrnx3UkF99nTxwqoNx3mdXDcA@mail.gmail.com> (raw) In-Reply-To: <AM6PR04MB5781498315C6B69EB2586B9D84490@AM6PR04MB5781.eurprd04.prod.outlook.com> Bjorn/ZQ, On Tue, Mar 12, 2019 at 2:48 PM Z.q. Hou <zhiqiang.hou@nxp.com> wrote: > > Hi Bjorn, > > Thanks a lot for your comments! > > > -----Original Message----- > > From: Bjorn Helgaas [mailto:helgaas@kernel.org] > > Sent: 2019年3月11日 22:14 > > To: Z.q. Hou <zhiqiang.hou@nxp.com> > > Cc: linux-pci@vger.kernel.org; linux-arm-kernel@lists.infradead.org; > > devicetree@vger.kernel.org; linux-kernel@vger.kernel.org; > > robh+dt@kernel.org; mark.rutland@arm.com; l.subrahmanya@mobiveil.co.in; > > shawnguo@kernel.org; Leo Li <leoyang.li@nxp.com>; > > lorenzo.pieralisi@arm.com; catalin.marinas@arm.com; > > will.deacon@arm.com; Mingkai Hu <mingkai.hu@nxp.com>; M.h. Lian > > <minghuan.lian@nxp.com>; Xiaowei Bao <xiaowei.bao@nxp.com> > > Subject: Re: [PATCHv4 11/28] PCI: mobiveil: only fix up the Class Code field > > > > On Mon, Mar 11, 2019 at 09:31:23AM +0000, Z.q. Hou wrote: > > > From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> > > > > > > Fix up the Class Code to PCI bridge, do not change the Revision ID. > > > And move the fixup to mobiveil_host_init function. > > > > Add parens after function name. > > > > Please explain why this change is needed. Does it fix a bug? > > > > Does this fix the problem that the PCI core didn't correctly identify the device > > as a bridge because it identified bridges by class code instead of header type? > > > > That problem *should* be fixed by b2fb5cc57469 ("PCI: Rely on config space > > header type, not class code"), which is now upstream. > > > > You might still want this class code change so that lspci shows the correct > > thing. That's fine, but the changelog should say why we're doing it. > > > > Subrahmanya's original patch is to fixup 'Class Code' field, but it also fixed the 'Revision ID' field. This patch is patch is to remove the fixup of 'Revision ID' field. it was introduced during the test with 4.9 and 4.15 linux version, without this fix driver was not getting loaded. I belive it should be sufficient to mention in code comment: "Fixing the class code as hardware is not reflecting the correct class code", And the changelog for this patch mentioning "avoid changing the revision ID during the class code fix". Is that OK? Thanks, > > > > Fixes: 9af6bcb11e12 ("PCI: mobiveil: Add Mobiveil PCIe Host Bridge IP > > > driver") > > > > Make this "Fixes:" line a single line again. > > > > > Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> > > > Reviewed-by: Minghuan Lian <Minghuan.Lian@nxp.com> > > > Reviewed-by: Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in> > > > --- > > > V4: > > > - no change > > > > > > drivers/pci/controller/pcie-mobiveil.c | 9 ++++++--- > > > 1 file changed, 6 insertions(+), 3 deletions(-) > > > > > > diff --git a/drivers/pci/controller/pcie-mobiveil.c > > > b/drivers/pci/controller/pcie-mobiveil.c > > > index 78e575e71f4d..8eee1ab7ee24 100644 > > > --- a/drivers/pci/controller/pcie-mobiveil.c > > > +++ b/drivers/pci/controller/pcie-mobiveil.c > > > @@ -653,6 +653,12 @@ static int mobiveil_host_init(struct mobiveil_pcie > > *pcie) > > > type, resource_size(win->res)); > > > } > > > > > > + /* fixup for PCIe class register */ > > > + value = csr_readl(pcie, PAB_INTP_AXI_PIO_CLASS); > > > + value &= 0xff; > > > + value |= (PCI_CLASS_BRIDGE_PCI << 16); > > > + csr_writel(pcie, value, PAB_INTP_AXI_PIO_CLASS); > > > + > > > /* setup MSI hardware registers */ > > > mobiveil_pcie_enable_msi(pcie); > > > > > > @@ -896,9 +902,6 @@ static int mobiveil_pcie_probe(struct > > platform_device *pdev) > > > goto error; > > > } > > > > > > - /* fixup for PCIe class register */ > > > - csr_writel(pcie, 0x060402ab, PAB_INTP_AXI_PIO_CLASS); > > > - > > > /* initialize the IRQ domains */ > > > ret = mobiveil_pcie_init_irq_domain(pcie); > > > if (ret) { > > > -- > > > 2.17.1 > > > > > Thanks, > Zhiqiang _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2019-03-13 10:59 UTC|newest] Thread overview: 158+ messages / expand[flat|nested] mbox.gz Atom feed top 2019-03-11 9:29 [PATCHv4 00/28] PCI: refactor Mobiveil driver and add PCIe Gen4 driver for NXP Layerscape SoCs Z.q. Hou 2019-03-11 9:29 ` Z.q. Hou 2019-03-11 9:29 ` Z.q. Hou 2019-03-11 9:30 ` [PATCHv4 01/28] PCI: mobiveil: uniform the register accessors Z.q. Hou 2019-03-11 9:30 ` Z.q. Hou 2019-03-11 9:30 ` Z.q. Hou 2019-03-11 9:30 ` [PATCHv4 02/28] PCI: mobiveil: format the code without function change Z.q. Hou 2019-03-11 9:30 ` Z.q. Hou 2019-03-11 9:30 ` Z.q. Hou 2019-03-11 9:30 ` [PATCHv4 03/28] PCI: mobiveil: correct the returned error number Z.q. Hou 2019-03-11 9:30 ` Z.q. Hou 2019-03-11 9:30 ` Z.q. Hou 2019-03-11 9:30 ` [PATCHv4 04/28] PCI: mobiveil: remove flag MSI_FLAG_MULTI_PCI_MSI Z.q. Hou 2019-03-11 9:30 ` Z.q. Hou 2019-03-11 9:30 ` Z.q. Hou 2019-03-11 9:30 ` [PATCHv4 05/28] PCI: mobiveil: correct PCI base address in MEM/IO outbound windows Z.q. Hou 2019-03-11 9:30 ` Z.q. Hou 2019-03-11 9:30 ` Z.q. Hou 2019-03-11 9:30 ` [PATCHv4 06/28] PCI: mobiveil: replace the resource list iteration function Z.q. Hou 2019-03-11 9:30 ` Z.q. Hou 2019-03-11 9:30 ` Z.q. Hou 2019-03-11 9:30 ` [PATCHv4 07/28] PCI: mobiveil: use WIN_NUM_0 explicitly for CFG outbound window Z.q. Hou 2019-03-11 9:30 ` Z.q. Hou 2019-03-11 9:30 ` Z.q. Hou 2019-03-11 9:31 ` [PATCHv4 08/28] PCI: mobiveil: use the 1st inbound window for MEM inbound transactions Z.q. Hou 2019-03-11 9:31 ` Z.q. Hou 2019-03-11 9:31 ` Z.q. Hou 2019-03-11 9:31 ` [PATCHv4 09/28] PCI: mobiveil: correct inbound/outbound window setup routines Z.q. Hou 2019-03-11 9:31 ` Z.q. Hou 2019-03-11 9:31 ` Z.q. Hou 2019-03-11 9:31 ` [PATCHv4 10/28] PCI: mobiveil: fix the INTx process error Z.q. Hou 2019-03-11 9:31 ` Z.q. Hou 2019-03-11 9:31 ` Z.q. Hou 2019-03-11 14:08 ` Bjorn Helgaas 2019-03-11 14:08 ` Bjorn Helgaas 2019-03-11 14:08 ` Bjorn Helgaas 2019-03-12 4:42 ` Z.q. Hou 2019-03-12 4:42 ` Z.q. Hou 2019-03-12 4:42 ` Z.q. Hou 2019-03-11 9:31 ` [PATCHv4 11/28] PCI: mobiveil: only fix up the Class Code field Z.q. Hou 2019-03-11 9:31 ` Z.q. Hou 2019-03-11 9:31 ` Z.q. Hou 2019-03-11 14:14 ` Bjorn Helgaas 2019-03-11 14:14 ` Bjorn Helgaas 2019-03-11 14:14 ` Bjorn Helgaas 2019-03-12 9:17 ` Z.q. Hou 2019-03-12 9:17 ` Z.q. Hou 2019-03-12 9:17 ` Z.q. Hou 2019-03-13 10:59 ` Subrahmanya Lingappa [this message] 2019-03-13 10:59 ` Subrahmanya Lingappa 2019-03-13 10:59 ` Subrahmanya Lingappa 2019-03-11 9:31 ` [PATCHv4 12/28] PCI: mobiveil: move out the link up waiting from mobiveil_host_init Z.q. Hou 2019-03-11 9:31 ` Z.q. Hou 2019-03-11 9:31 ` Z.q. Hou 2019-03-11 9:31 ` [PATCHv4 13/28] PCI: mobiveil: move irq chained handler setup out of DT parse Z.q. Hou 2019-03-11 9:31 ` Z.q. Hou 2019-03-11 9:31 ` Z.q. Hou 2019-03-11 9:31 ` [PATCHv4 14/28] PCI: mobiveil: initialize Primary/Secondary/Subordinate bus number Z.q. Hou 2019-03-11 9:31 ` Z.q. Hou 2019-03-11 9:31 ` Z.q. Hou 2019-03-11 9:31 ` [PATCHv4 15/28] dt-bindings: pci: mobiveil: change gpio_slave and apb_csr to optional Z.q. Hou 2019-03-11 9:31 ` Z.q. Hou 2019-03-11 9:31 ` Z.q. Hou 2019-03-11 9:32 ` [PATCHv4 16/28] PCI: mobiveil: refactor Mobiveil PCIe Host Bridge IP driver Z.q. Hou 2019-03-11 9:32 ` Z.q. Hou 2019-03-11 9:32 ` Z.q. Hou 2019-03-26 17:34 ` Lorenzo Pieralisi 2019-03-26 17:34 ` Lorenzo Pieralisi 2019-03-26 17:34 ` Lorenzo Pieralisi 2019-03-27 2:04 ` Z.q. Hou 2019-03-27 2:04 ` Z.q. Hou 2019-03-27 17:39 ` Lorenzo Pieralisi 2019-03-27 17:39 ` Lorenzo Pieralisi 2019-03-27 17:39 ` Lorenzo Pieralisi 2019-03-28 2:09 ` Z.q. Hou 2019-03-28 2:09 ` Z.q. Hou 2019-03-28 16:09 ` Lorenzo Pieralisi 2019-03-28 16:09 ` Lorenzo Pieralisi 2019-03-28 16:09 ` Lorenzo Pieralisi 2019-03-29 6:07 ` Z.q. Hou 2019-03-29 6:07 ` Z.q. Hou 2019-03-11 9:32 ` [PATCHv4 17/28] PCI: mobiveil: fix the checking of valid device Z.q. Hou 2019-03-11 9:32 ` Z.q. Hou 2019-03-11 9:32 ` Z.q. Hou 2019-03-11 9:32 ` [PATCHv4 18/28] PCI: mobiveil: add link up condition check Z.q. Hou 2019-03-11 9:32 ` Z.q. Hou 2019-03-11 9:32 ` Z.q. Hou 2019-03-11 9:32 ` [PATCHv4 19/28] PCI: mobiveil: continue to initialize the host upon no PCIe link Z.q. Hou 2019-03-11 9:32 ` Z.q. Hou 2019-03-11 9:32 ` Z.q. Hou 2019-03-11 9:32 ` [PATCHv4 20/28] PCI: mobiveil: disabled IB and OB windows set by bootloader Z.q. Hou 2019-03-11 9:32 ` Z.q. Hou 2019-03-11 9:32 ` Z.q. Hou 2019-03-11 9:32 ` [PATCHv4 21/28] PCI: mobiveil: add Byte and Half-Word width register accessors Z.q. Hou 2019-03-11 9:32 ` Z.q. Hou 2019-03-11 9:32 ` Z.q. Hou 2019-03-11 9:32 ` [PATCHv4 22/28] PCI: mobiveil: make mobiveil_host_init can be used to re-init host Z.q. Hou 2019-03-11 9:32 ` Z.q. Hou 2019-03-11 9:32 ` Z.q. Hou 2019-03-11 9:33 ` [PATCHv4 23/28] dt-bindings: pci: Add NXP Layerscape SoCs PCIe Gen4 controller Z.q. Hou 2019-03-11 9:33 ` Z.q. Hou 2019-03-11 9:33 ` Z.q. Hou 2019-03-11 22:11 ` Rob Herring 2019-03-11 22:11 ` Rob Herring 2019-03-11 22:11 ` Rob Herring 2019-03-12 3:17 ` Z.q. Hou 2019-03-12 3:17 ` Z.q. Hou 2019-03-12 3:17 ` Z.q. Hou 2019-03-12 9:42 ` Z.q. Hou 2019-03-12 9:42 ` Z.q. Hou 2019-03-11 9:33 ` [PATCHv4 24/28] PCI: mobiveil: add PCIe Gen4 RC driver for NXP Layerscape SoCs Z.q. Hou 2019-03-11 9:33 ` Z.q. Hou 2019-03-11 9:33 ` Z.q. Hou 2019-03-11 14:01 ` Bjorn Helgaas 2019-03-11 14:01 ` Bjorn Helgaas 2019-03-11 14:01 ` Bjorn Helgaas 2019-03-12 4:40 ` Z.q. Hou 2019-03-12 4:40 ` Z.q. Hou 2019-03-11 9:33 ` [PATCHv4 25/28] PCI: mobiveil: ls_pcie_g4: add Workaround for A-011577 Z.q. Hou 2019-03-11 9:33 ` Z.q. Hou 2019-03-11 9:33 ` Z.q. Hou 2019-03-13 14:51 ` Z.q. Hou 2019-03-13 14:51 ` Z.q. Hou 2019-03-13 14:51 ` Z.q. Hou 2019-03-11 9:33 ` [PATCHv4 26/28] PCI: mobiveil: ls_pcie_g4: add Workaround for A-011451 Z.q. Hou 2019-03-11 9:33 ` Z.q. Hou 2019-03-11 9:33 ` Z.q. Hou 2019-03-11 17:34 ` Bjorn Helgaas 2019-03-11 17:34 ` Bjorn Helgaas 2019-03-11 17:34 ` Bjorn Helgaas 2019-03-12 9:34 ` Z.q. Hou 2019-03-12 9:34 ` Z.q. Hou 2019-03-12 9:34 ` Z.q. Hou 2019-03-12 13:34 ` Bjorn Helgaas 2019-03-12 13:34 ` Bjorn Helgaas 2019-03-12 13:34 ` Bjorn Helgaas 2019-03-13 14:49 ` Z.q. Hou 2019-03-13 14:49 ` Z.q. Hou 2019-03-13 14:49 ` Z.q. Hou 2019-03-13 14:51 ` Z.q. Hou 2019-03-13 14:51 ` Z.q. Hou 2019-03-11 9:33 ` [PATCHv4 27/28] arm64: dts: freescale: lx2160a: add pcie DT nodes Z.q. Hou 2019-03-11 9:33 ` Z.q. Hou 2019-03-11 9:33 ` Z.q. Hou 2019-03-11 9:33 ` [PATCHv4 28/28] arm64: defconfig: Enable CONFIG_PCI_LAYERSCAPE_GEN4 Z.q. Hou 2019-03-11 9:33 ` Z.q. Hou 2019-03-11 9:33 ` Z.q. Hou 2019-03-11 13:33 ` [PATCHv4 00/28] PCI: refactor Mobiveil driver and add PCIe Gen4 driver for NXP Layerscape SoCs Bjorn Helgaas 2019-03-11 13:33 ` Bjorn Helgaas 2019-03-11 13:33 ` Bjorn Helgaas 2019-03-12 4:18 ` Z.q. Hou 2019-03-12 4:18 ` Z.q. Hou 2019-03-26 17:37 ` Lorenzo Pieralisi 2019-03-26 17:37 ` Lorenzo Pieralisi 2019-03-26 17:37 ` Lorenzo Pieralisi 2019-03-27 2:11 ` Z.q. Hou 2019-03-27 2:11 ` Z.q. Hou 2019-03-27 2:11 ` Z.q. Hou
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