[U-Boot] [PATCH v1 05/16] arm: socfpga: misc: Add CONFIG_SYS_L2_PL310 switch

[U-Boot] [PATCH v1 05/16] arm: socfpga: misc: Add CONFIG_SYS_L2_PL310 switch

[Marek Vasut]

On 04/19/2018 11:50 AM, Ley Foon Tan wrote:
> Add CONFIG_SYS_L2_PL310 conditional build.

Why ?

> Signed-off-by: Chin Liang See <chin.liang.see@intel.com>
> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
> ---
>  arch/arm/mach-socfpga/misc.c |    4 ++++
>  1 files changed, 4 insertions(+), 0 deletions(-)
> 
> diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c
> index 692466c..01f824c 100644
> --- a/arch/arm/mach-socfpga/misc.c
> +++ b/arch/arm/mach-socfpga/misc.c
> @@ -23,8 +23,10 @@
>  
>  DECLARE_GLOBAL_DATA_PTR;
>  
> +#ifdef CONFIG_SYS_L2_PL310
>  static const struct pl310_regs *const pl310 =
>  	(struct pl310_regs *)CONFIG_SYS_PL310_BASE;
> +#endif
>  
>  struct bsel bsel_str[] = {
>  	{ "rsvd", "Reserved", },
> @@ -53,6 +55,7 @@ void enable_caches(void)
>  #endif
>  }
>  
> +#ifdef CONFIG_SYS_L2_PL310
>  void v7_outer_cache_enable(void)
>  {
>  	/* Disable the L2 cache */
> @@ -73,6 +76,7 @@ void v7_outer_cache_disable(void)
>  	/* Disable the L2 cache */
>  	clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
>  }
> +#endif
>  
>  #if defined(CONFIG_SYS_CONSOLE_IS_IN_ENV) && \
>  defined(CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE)
> 


-- 
Best regards,
Marek Vasut

[U-Boot] [PATCH v1 06/16] arm: socfpga: misc: Move eth reset to common misc driver

[Marek Vasut]

On 04/19/2018 11:50 AM, Ley Foon Tan wrote:
> Move eth reset to common misc driver so can used by other device families.
> 
> Signed-off-by: Chin Liang See <chin.liang.see@intel.com>
> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>

Shouldn't this use the reset framework instead ?

-- 
Best regards,
Marek Vasut

[U-Boot] [PATCH v1 07/16] arm: socfpga: stratix10: Add misc support for Stratix10 SoC

[Marek Vasut]

On 04/19/2018 11:50 AM, Ley Foon Tan wrote:
> Add misc support such as EMAC and cpu info printout for Stratix SoC
> 
> Signed-off-by: Chin Liang See <chin.liang.see@intel.com>
> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
> ---
>  arch/arm/mach-socfpga/Makefile   |    1 +
>  arch/arm/mach-socfpga/misc_s10.c |  103 ++++++++++++++++++++++++++++++++++++++
>  2 files changed, 104 insertions(+), 0 deletions(-)
>  create mode 100644 arch/arm/mach-socfpga/misc_s10.c
> 
> diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
> index 910eb6f..b253914 100644
> --- a/arch/arm/mach-socfpga/Makefile
> +++ b/arch/arm/mach-socfpga/Makefile
> @@ -32,6 +32,7 @@ endif
>  
>  ifdef CONFIG_TARGET_SOCFPGA_STRATIX10
>  obj-y	+= clock_manager_s10.o
> +obj-y	+= misc_s10.o
>  obj-y	+= reset_manager_s10.o
>  obj-y	+= system_manager_s10.o
>  obj-y	+= wrap_pinmux_config_s10.o
> diff --git a/arch/arm/mach-socfpga/misc_s10.c b/arch/arm/mach-socfpga/misc_s10.c
> new file mode 100644
> index 0000000..b1cc6ca
> --- /dev/null
> +++ b/arch/arm/mach-socfpga/misc_s10.c
> @@ -0,0 +1,103 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (C) 2016-2018 Intel Corporation <www.intel.com>
> + *
> + */
> +
> +#include <altera.h>
> +#include <common.h>
> +#include <errno.h>
> +#include <fdtdec.h>
> +#include <miiphy.h>
> +#include <netdev.h>
> +#include <watchdog.h>
> +#include <asm/io.h>
> +#include <asm/arch/reset_manager.h>
> +#include <asm/arch/system_manager.h>
> +#include <asm/arch/misc.h>
> +#include <asm/pl310.h>
> +#include <linux/libfdt.h>
> +
> +#include <dt-bindings/reset/altr,rst-mgr-s10.h>
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +static struct socfpga_system_manager *sysmgr_regs =
> +	(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
> +
> +/*
> + * DesignWare Ethernet initialization
> + */
> +#ifdef CONFIG_ETH_DESIGNWARE

Use the reset framework ? Talk to Dinh if in doubt

> +void dwmac_deassert_reset(const unsigned int of_reset_id,
> +			  const u32 phymode)
> +{
> +	/* Put the emac we're using into reset.
> +	 * This is required before configuring the PHY interface
> +	 */
> +	socfpga_emac_manage_reset(of_reset_id, 1);
> +
> +	clrsetbits_le32(&sysmgr_regs->emac0 + (of_reset_id - EMAC0_RESET),
> +			SYSMGR_EMACGRP_CTRL_PHYSEL_MASK,
> +			phymode);
> +
> +	socfpga_emac_manage_reset(of_reset_id, 0);
> +}
> +#endif
> +
> +/*
> + * Print CPU information
> + */
> +#if defined(CONFIG_DISPLAY_CPUINFO)
> +int print_cpuinfo(void)
> +{
> +	puts("CPU:   Intel FPGA SoCFPGA Platform\n");
> +	puts("FPGA:  Intel FPGA Stratix 10\n");

This can well come from DT.

> +	return 0;
> +}
> +#endif
> +
> +#ifdef CONFIG_ARCH_MISC_INIT
> +int arch_misc_init(void)
> +{
> +	char qspi_string[13];
> +
> +	sprintf(qspi_string, "<0x%08x>", cm_get_qspi_controller_clk_hz());
> +	env_set("qspi_clock", qspi_string);
> +
> +	return socfpga_eth_reset();
> +}
> +#endif
> +
> +int arch_early_init_r(void)
> +{
> +	return 0;

Needed ?

> +}
> +
> +int do_bridge(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
> +{
> +	if (argc != 2)
> +		return CMD_RET_USAGE;
> +
> +	argv++;
> +
> +	switch (*argv[0]) {
> +	case 'e':	/* Enable */
> +		socfpga_bridges_reset(1);
> +		break;
> +	case 'd':	/* Disable */
> +		socfpga_bridges_reset(0);
> +		break;

Do you really need to duplicate this command ?

> +	default:
> +		return CMD_RET_USAGE;
> +	}
> +
> +	return 0;
> +}
> +
> +U_BOOT_CMD(bridge, 2, 1, do_bridge,
> +	   "SoCFPGA HPS FPGA bridge control",
> +	   "enable  - Enable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA bridges\n"
> +	   "bridge disable - Disable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA bridges\n"
> +	   ""
> +);
> 


-- 
Best regards,
Marek Vasut

[U-Boot] [PATCH v1 08/16] arm: socfpga: stratix10: Add mailbox support for Stratix10 SoC

[Marek Vasut]

On 04/19/2018 11:50 AM, Ley Foon Tan wrote:
> Add mailbox support for Stratix SoC
> 
> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
> Signed-off-by: Chin Liang See <chin.liang.see@intel.com>
> ---
>  arch/arm/mach-socfpga/Makefile                   |    1 +
>  arch/arm/mach-socfpga/include/mach/mailbox_s10.h |  155 +++++++++
>  arch/arm/mach-socfpga/mailbox_s10.c              |  378 ++++++++++++++++++++++
>  3 files changed, 534 insertions(+), 0 deletions(-)
>  create mode 100644 arch/arm/mach-socfpga/include/mach/mailbox_s10.h
>  create mode 100644 arch/arm/mach-socfpga/mailbox_s10.c
> 
> diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
> index b253914..43e18d2 100644
> --- a/arch/arm/mach-socfpga/Makefile
> +++ b/arch/arm/mach-socfpga/Makefile
> @@ -32,6 +32,7 @@ endif
>  
>  ifdef CONFIG_TARGET_SOCFPGA_STRATIX10
>  obj-y	+= clock_manager_s10.o
> +obj-y	+= mailbox_s10.o
>  obj-y	+= misc_s10.o
>  obj-y	+= reset_manager_s10.o
>  obj-y	+= system_manager_s10.o
> diff --git a/arch/arm/mach-socfpga/include/mach/mailbox_s10.h b/arch/arm/mach-socfpga/include/mach/mailbox_s10.h
> new file mode 100644
> index 0000000..85e7f84
> --- /dev/null
> +++ b/arch/arm/mach-socfpga/include/mach/mailbox_s10.h
> @@ -0,0 +1,155 @@
> +/* SPDX-License-Identifier: GPL-2.0
> + *
> + * Copyright (C) 2017-2018 Intel Corporation <www.intel.com>
> + *
> + */
> +
> +#ifndef _MAILBOX_S10_H_
> +#define _MAILBOX_S10_H_
> +
> +/* user define Uboot ID */
> +#define MBOX_CLIENT_ID_UBOOT	0xB
> +#define MBOX_ID_UBOOT		0x1
> +
> +#define MBOX_CMD_DIRECT	0
> +#define MBOX_CMD_INDIRECT	1
> +
> +#define MBOX_MAX_CMD_INDEX	2047
> +#define MBOX_CMD_BUFFER_SIZE	32
> +#define MBOX_RESP_BUFFER_SIZE	16
> +
> +#define MBOX_HDR_CMD_LSB	0
> +#define MBOX_HDR_CMD_MSK	(BIT(11) - 1)
> +#define MBOX_HDR_I_LSB		11
> +#define MBOX_HDR_I_MSK		BIT(11)
> +#define MBOX_HDR_LEN_LSB	12
> +#define MBOX_HDR_LEN_MSK	0x007FF000
> +#define MBOX_HDR_ID_LSB		24
> +#define MBOX_HDR_ID_MSK		0x0F000000
> +#define MBOX_HDR_CLIENT_LSB	28
> +#define MBOX_HDR_CLIENT_MSK	0xF0000000
> +
> +/* Interrupt flags */
> +#define MBOX_FLAGS_INT_COE	BIT(0)	/* COUT update interrupt enable */
> +#define MBOX_FLAGS_INT_RIE	BIT(1)	/* RIN update interrupt enable */
> +#define MBOX_FLAGS_INT_UAE	BIT(8)	/* Urgent ACK interrupt enable */
> +#define MBOX_ALL_INTRS		(MBOX_FLAGS_INT_COE | \
> +				 MBOX_FLAGS_INT_RIE | \
> +				 MBOX_FLAGS_INT_UAE)
> +
> +/* Status */
> +#define MBOX_STATUS_UA_MSK	BIT(8)
> +
> +#define MBOX_CMD_HEADER(client, id, len, indirect, cmd)     \
> +	((((cmd) << MBOX_HDR_CMD_LSB) & MBOX_HDR_CMD_MSK) | \
> +	(((indirect) << MBOX_HDR_I_LSB) & MBOX_HDR_I_MSK) | \
> +	(((len) << MBOX_HDR_LEN_LSB) & MBOX_HDR_LEN_MSK)  | \
> +	(((id) << MBOX_HDR_ID_LSB) & MBOX_HDR_ID_MSK)     | \
> +	(((client) << MBOX_HDR_CLIENT_LSB) & MBOX_HDR_CLIENT_MSK))
> +
> +#define MBOX_RESP_ERR_GET(resp)				\
> +	(((resp) & MBOX_HDR_CMD_MSK) >> MBOX_HDR_CMD_LSB)
> +#define MBOX_RESP_LEN_GET(resp)			\
> +	(((resp) & MBOX_HDR_LEN_MSK) >> MBOX_HDR_LEN_LSB)
> +#define MBOX_RESP_ID_GET(resp)				\
> +	(((resp) & MBOX_HDR_ID_MSK) >> MBOX_HDR_ID_LSB)
> +#define MBOX_RESP_CLIENT_GET(resp)			\
> +	(((resp) & MBOX_HDR_CLIENT_MSK) >> MBOX_HDR_CLIENT_LSB)
> +
> +/* Response error list */
> +enum ALT_SDM_MBOX_RESP_CODE {
> +	/* CMD completed successfully, but check resp ARGS for any errors */
> +	MBOX_RESP_STATOK = 0,
> +	/* CMD is incorrectly formatted in some way */
> +	MBOX_RESP_INVALID_COMMAND = 1,
> +	/* BootROM Command code not undesrtood */
> +	MBOX_RESP_UNKNOWN_BR = 2,
> +	/* CMD code not recognized by firmware */
> +	MBOX_RESP_UNKNOWN = 3,
> +	/* Indicates that the device is not configured */
> +	MBOX_RESP_NOT_CONFIGURED = 256,
> +	/* Indicates that the device is busy */
> +	MBOX_RESP_DEVICE_BUSY = 0x1FF,
> +	/* Indicates that there is no valid response available */
> +	MBOX_RESP_NO_VALID_RESP_AVAILABLE = 0x2FF,
> +	/* General Error */
> +	MBOX_RESP_ERROR = 0x3FF,
> +};
> +
> +/* Mailbox command list */
> +#define MBOX_RESTART		2
> +#define MBOX_CONFIG_STATUS	4
> +#define MBOX_RECONFIG		6
> +#define MBOX_RECONFIG_MSEL	7
> +#define MBOX_RECONFIG_DATA	8
> +#define MBOX_RECONFIG_STATUS	9
> +#define MBOX_QSPI_OPEN		50
> +#define MBOX_QSPI_CLOSE		51
> +#define MBOX_QSPI_DIRECT	59
> +#define MBOX_REBOOT_HPS		71
> +
> +struct socfpga_mailbox {

We should probably just use register offset macros in new code, this
struct {} stuff often doesn't work too well and the limitations are showing.

> +	u32 cin;		/* command valid offset */
> +	u32 rout;		/* response output offset */
> +	u32 urg;		/* urgent command */
> +	u32 flags;		/* interrupt enables */
> +	u32 pad_0x10_0x1f[4];	/* 0x10 - 0x1F reserved */
> +	u32 cout;		/* command free offset */
> +	u32 rin;		/* respond valid offset */
> +	u32 pad_0x28;		/* 0x28 reserved */
> +	u32 status;		/* mailbox status */
> +	u32 pad_0x30_0x3f[4];	/* 0x30 - 0x3F reserved */
> +	u32 cmd_buf[MBOX_CMD_BUFFER_SIZE];	/* 0x40 - 0xBC circular command
> +						 * buffer to SDM
> +						 */
> +	u32 resp_buf[MBOX_RESP_BUFFER_SIZE];	/* 0xC0 - 0xFF circular
> +						 * response buffer
> +						 */
> +};
> +
> +/* Use define other than put into struct socfpga_mailbox to save spaces */
> +#define MBOX_DOORBELL_TO_SDM_REG	(SOCFPGA_MAILBOX_ADDRESS + 0x400)
> +#define MBOX_DOORBELL_FROM_SDM_REG	(SOCFPGA_MAILBOX_ADDRESS + 0x480)
> +
> +/******** Status and bit information returned by RECONFIG_STATUS ********/
> +#define RECONFIG_STATUS_RESPONSE_LEN			6
> +#define RECONFIG_STATUS_STATE				0
> +#define RECONFIG_STATUS_PIN_STATUS			2
> +#define RECONFIG_STATUS_SOFTFUNC_STATUS			3
> +
> +#define MBOX_CFGSTAT_STATE_IDLE				0x00000000
> +#define MBOX_CFGSTAT_STATE_CONFIG			0x10000000
> +#define MBOX_CFGSTAT_STATE_FAILACK			0x08000000
> +#define MBOX_CFGSTAT_STATE_ERROR_INVALID		0xf0000001
> +#define MBOX_CFGSTAT_STATE_ERROR_CORRUPT		0xf0000002
> +#define MBOX_CFGSTAT_STATE_ERROR_AUTH			0xf0000003
> +#define MBOX_CFGSTAT_STATE_ERROR_CORE_IO		0xf0000004
> +#define MBOX_CFGSTAT_STATE_ERROR_HARDWARE		0xf0000005
> +#define MBOX_CFGSTAT_STATE_ERROR_FAKE			0xf0000006
> +#define MBOX_CFGSTAT_STATE_ERROR_BOOT_INFO		0xf0000007
> +#define MBOX_CFGSTAT_STATE_ERROR_QSPI_ERROR		0xf0000008
> +
> +#define RCF_SOFTFUNC_STATUS_CONF_DONE			BIT(0)
> +#define RCF_SOFTFUNC_STATUS_INIT_DONE			BIT(1)
> +#define RCF_SOFTFUNC_STATUS_SEU_ERROR			BIT(3)
> +#define RCF_PIN_STATUS_NSTATUS				BIT(31)
> +/************************************************************************/
> +
> +int mbox_send_cmd(u8 id, u32 cmd, u8 is_indirect, u32 len, u32 *arg, u8 urgent,
> +		  u32 *resp_buf_len, u32 *resp_buf);
> +int mbox_send_cmd_psci(u8 id, u32 cmd, u8 is_indirect, u32 len, u32 *arg,
> +		       u8 urgent, u32 *resp_buf_len, u32 *resp_buf);
> +int mbox_send_cmd_only(u8 id, u32 cmd, u8 is_indirect, u32 len, u32 *arg);
> +int mbox_send_cmd_only_psci(u8 id, u32 cmd, u8 is_indirect, u32 len, u32 *arg);
> +int mbox_rcv_resp(u32 *resp_buf, u32 resp_buf_max_len);
> +int mbox_rcv_resp_psci(u32 *resp_buf, u32 resp_buf_max_len);
> +int mbox_init(void);
> +
> +#ifdef CONFIG_CADENCE_QSPI
> +int mbox_qspi_close(void);
> +int mbox_qspi_open(void);
> +#endif
> +
> +int mbox_reset_cold(void);
> +
> +#endif /* _MAILBOX_S10_H_ */
> diff --git a/arch/arm/mach-socfpga/mailbox_s10.c b/arch/arm/mach-socfpga/mailbox_s10.c
> new file mode 100644
> index 0000000..ed713a9
> --- /dev/null
> +++ b/arch/arm/mach-socfpga/mailbox_s10.c
> @@ -0,0 +1,378 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (C) 2017-2018 Intel Corporation <www.intel.com>
> + *
> + */
> +
> +#include <common.h>
> +#include <wait_bit.h>
> +#include <asm/io.h>
> +#include <asm/arch/mailbox_s10.h>
> +#include <asm/arch/system_manager.h>
> +#include <asm/secure.h>
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +static __always_inline int mbox_polling_resp(u32 rout)
> +{
> +	static const struct socfpga_mailbox *mbox_base =
> +					(void *)SOCFPGA_MAILBOX_ADDRESS;
> +	u32 rin;
> +	unsigned long i = ~0;
> +
> +	while (i) {
> +		rin = readl(&mbox_base->rin);
> +		if (rout != rin)
> +			return 0;

This looks like include/wait_bit.h reimplementation

> +		i--;
> +	}
> +
> +	return -ETIMEDOUT;
> +}
> +
> +/* Check for available slot and write to circular buffer.
> + * It also update command valid offset (cin) register.
> + */
> +static __always_inline int mbox_fill_cmd_circular_buff(u32 header, u32 len,
> +						       u32 *arg)
> +{
> +	static const struct socfpga_mailbox *mbox_base =
> +					(void *)SOCFPGA_MAILBOX_ADDRESS;
> +	u32 cin;
> +	u32 cout;
> +	u32 i;
> +
> +	cin = readl(&mbox_base->cin) % MBOX_CMD_BUFFER_SIZE;
> +	cout = readl(&mbox_base->cout) % MBOX_CMD_BUFFER_SIZE;
> +
> +	/* if command buffer is full or not enough free space
> +	 * to fit the data
> +	 */
> +	if (((cin + 1) % MBOX_CMD_BUFFER_SIZE) == cout ||
> +	    ((MBOX_CMD_BUFFER_SIZE - cin + cout - 1) %
> +	     MBOX_CMD_BUFFER_SIZE) < len)
> +		return -ENOMEM;
> +
> +	/* write header to circular buffer */
> +	writel(header, &mbox_base->cmd_buf[cin++]);
> +	/* wrapping around when it reach the buffer size */
> +	cin %= MBOX_CMD_BUFFER_SIZE;
> +
> +	/* write arguments */
> +	for (i = 0; i < len; i++) {
> +		writel(arg[i], &mbox_base->cmd_buf[cin++]);
> +		/* wrapping around when it reach the buffer size */
> +		cin %= MBOX_CMD_BUFFER_SIZE;
> +	}
> +
> +	/* write command valid offset */
> +	writel(cin, &mbox_base->cin);
> +
> +	return 0;
> +}
> +
> +/* Check the command and fill it into circular buffer */
> +static __always_inline int mbox_prepare_cmd_only(u8 id, u32 cmd,
> +						 u8 is_indirect, u32 len,
> +						 u32 *arg)
> +{
> +	u32 header;
> +	int ret;
> +
> +	/* Total length is command + argument length */
> +	if ((len + 1) > MBOX_CMD_BUFFER_SIZE)
> +		return -EINVAL;
> +
> +	if (cmd > MBOX_MAX_CMD_INDEX)
> +		return -EINVAL;
> +
> +	header = MBOX_CMD_HEADER(MBOX_CLIENT_ID_UBOOT, id, len,
> +				 (is_indirect) ? 1 : 0, cmd);
> +
> +	ret = mbox_fill_cmd_circular_buff(header, len, arg);
> +
> +	return ret;
> +}
> +
> +/* Send command only without waiting for responses from SDM */
> +static __always_inline int __mbox_send_cmd_only(u8 id, u32 cmd,
> +						u8 is_indirect, u32 len,
> +						u32 *arg)
> +{
> +	int ret = mbox_prepare_cmd_only(id, cmd, is_indirect, len, arg);
> +	/* write doorbell */
> +	writel(1, MBOX_DOORBELL_TO_SDM_REG);
> +
> +	return ret;
> +}
> +
> +/* Return number of responses received in buffer */
> +static __always_inline int __mbox_rcv_resp(u32 *resp_buf, u32 resp_buf_max_len)

__always_inline is nonsense, drop it. Let the compiler do it's thing.

> +{
> +	static const struct socfpga_mailbox *mbox_base =
> +					(void *)SOCFPGA_MAILBOX_ADDRESS;
> +	u32 rin;
> +	u32 rout;
> +	u32 resp_len = 0;
> +
> +	/* clear doorbell from SDM if it was SET */
> +	if (readl((const u32 *)MBOX_DOORBELL_FROM_SDM_REG) & 1)
> +		writel(0, MBOX_DOORBELL_FROM_SDM_REG);
> +
> +	/* read current response offset */
> +	rout = readl(&mbox_base->rout);
> +	/* read response valid offset */
> +	rin = readl(&mbox_base->rin);
> +
> +	while (rin != rout && (resp_len < resp_buf_max_len)) {
> +		/* Response received */
> +		if (resp_buf)
> +			resp_buf[resp_len++] =
> +				readl(&mbox_base->resp_buf[rout]);
> +		rout++;
> +		/* wrapping around when it reach the buffer size */
> +		rout %= MBOX_RESP_BUFFER_SIZE;
> +		/* update next ROUT */
> +		writel(rout, &mbox_base->rout);
> +	}
> +
> +	return resp_len;
> +}
> +
> +/* Support one command and up to 31 words argument length only */
> +static __always_inline int __mbox_send_cmd(u8 id, u32 cmd, u8 is_indirect,
> +					   u32 len, u32 *arg, u8 urgent,
> +					   u32 *resp_buf_len, u32 *resp_buf)
> +{
> +	static const struct socfpga_mailbox *mbox_base =
> +					(void *)SOCFPGA_MAILBOX_ADDRESS;
> +
> +	u32 rin;
> +	u32 resp;
> +	u32 rout;
> +	u32 status;
> +	u32 resp_len;
> +	u32 buf_len;
> +	int ret;
> +
> +	ret = mbox_prepare_cmd_only(id, cmd, is_indirect, len, arg);
> +	if (ret)
> +		return ret;
> +
> +	if (urgent) {
> +		/* Read status because it is toggled */
> +		status = readl(&mbox_base->status) & MBOX_STATUS_UA_MSK;
> +		/* Send command as urgent command */
> +		writel(1, &mbox_base->urg);
> +	}
> +
> +	/* write doorbell */
> +	writel(1, MBOX_DOORBELL_TO_SDM_REG);
> +
> +	while (1) {
> +		ret = ~0;
> +
> +		/* Wait for doorbell from SDM */
> +		while (!readl(MBOX_DOORBELL_FROM_SDM_REG) && ret--)
> +			;
> +		if (!ret)
> +			return -ETIMEDOUT;

wait_for_bit...

> +		/* clear interrupt */
> +		writel(0, MBOX_DOORBELL_FROM_SDM_REG);
> +
> +		if (urgent) {
> +			u32 new_status = readl(&mbox_base->status);
> +			/* urgent command doesn't have response */
> +			writel(0, &mbox_base->urg);
> +			/* Urgent ACK is toggled */
> +			if ((new_status & MBOX_STATUS_UA_MSK) ^ status)
> +				return 0;
> +
> +			return -ECOMM;
> +		}
> +
> +		/* read current response offset */
> +		rout = readl(&mbox_base->rout);
> +
> +		/* read response valid offset */
> +		rin = readl(&mbox_base->rin);
> +
> +		if (rout != rin) {
> +			/* Response received */
> +			resp = readl(&mbox_base->resp_buf[rout]);
> +			rout++;
> +			/* wrapping around when it reach the buffer size */
> +			rout %= MBOX_RESP_BUFFER_SIZE;
> +			/* update next ROUT */
> +			writel(rout, &mbox_base->rout);
> +
> +			/* check client ID and ID */
> +			if ((MBOX_RESP_CLIENT_GET(resp) == MBOX_CLIENT_ID_UBOOT) &&
> +			    (MBOX_RESP_ID_GET(resp) == id)) {
> +				ret = MBOX_RESP_ERR_GET(resp);
> +				if (ret)
> +					return ret;
> +
> +				if (resp_buf_len) {
> +					buf_len = *resp_buf_len;
> +					*resp_buf_len = 0;
> +				} else {
> +					buf_len = 0;
> +				}
> +
> +				resp_len = MBOX_RESP_LEN_GET(resp);
> +				while (resp_len) {
> +					ret = mbox_polling_resp(rout);
> +					if (ret)
> +						return ret;
> +					/* we need to process response buffer
> +					 * even caller doesn't need it
> +					 */
> +					resp = readl(&mbox_base->resp_buf[rout]);
> +					rout++;
> +					resp_len--;
> +					rout %= MBOX_RESP_BUFFER_SIZE;
> +					writel(rout, &mbox_base->rout);
> +					if (buf_len) {
> +						/* copy response to buffer */
> +						resp_buf[*resp_buf_len] = resp;
> +						(*resp_buf_len)++;
> +						buf_len--;
> +					}
> +				}
> +				return ret;
> +			}
> +		}
> +	};
> +
> +	return -EIO;
> +}
> +
> +int mbox_init(void)
> +{
> +	static const struct socfpga_mailbox *mbox_base =
> +					(void *)SOCFPGA_MAILBOX_ADDRESS;
> +	int ret;
> +
> +	/* enable mailbox interrupts */
> +	writel(MBOX_ALL_INTRS, &mbox_base->flags);
> +
> +	/* Ensure urgent request is cleared */
> +	writel(0, &mbox_base->urg);
> +
> +	/* Ensure the Doorbell Interrupt is cleared */
> +	writel(0, MBOX_DOORBELL_FROM_SDM_REG);
> +
> +	ret = mbox_send_cmd(MBOX_ID_UBOOT, MBOX_RESTART, MBOX_CMD_DIRECT, 0,
> +			    NULL, 1, 0, NULL);
> +	if (ret)
> +		return ret;
> +
> +	/* Renable mailbox interrupts after MBOX_RESTART */
> +	writel(MBOX_ALL_INTRS, &mbox_base->flags);
> +
> +	return 0;
> +}
> +
> +#ifdef CONFIG_CADENCE_QSPI
> +int mbox_qspi_close(void)
> +{
> +	return mbox_send_cmd(MBOX_ID_UBOOT, MBOX_QSPI_CLOSE, MBOX_CMD_DIRECT,
> +			     0, NULL, 0, 0, NULL);
> +}
> +
> +int mbox_qspi_open(void)
> +{
> +	static const struct socfpga_system_manager *sysmgr_regs =
> +		(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
> +
> +	int ret;
> +	u32 resp_buf[1];
> +	u32 resp_buf_len;
> +
> +	ret = mbox_send_cmd(MBOX_ID_UBOOT, MBOX_QSPI_OPEN, MBOX_CMD_DIRECT,
> +			    0, NULL, 0, 0, NULL);
> +	if (ret) {
> +		/* retry again by closing and reopen the QSPI again */
> +		ret = mbox_qspi_close();
> +		if (ret)
> +			return ret;
> +
> +		ret = mbox_send_cmd(MBOX_ID_UBOOT, MBOX_QSPI_OPEN,
> +				    MBOX_CMD_DIRECT, 0, NULL, 0, 0, NULL);
> +		if (ret)
> +			return ret;
> +	}
> +
> +	/* HPS will directly control the QSPI controller, no longer mailbox */
> +	resp_buf_len = 1;
> +	ret = mbox_send_cmd(MBOX_ID_UBOOT, MBOX_QSPI_DIRECT, MBOX_CMD_DIRECT,
> +			    0, NULL, 0, (u32 *)&resp_buf_len,
> +			    (u32 *)&resp_buf);
> +	if (ret)
> +		goto error;
> +
> +	/* We are getting QSPI ref clock and set into sysmgr boot register */
> +	printf("QSPI: Reference clock at %d Hz\n", resp_buf[0]);

Certainly something I can get out of clock or clk command, drop the print.

> +	writel(resp_buf[0], &sysmgr_regs->boot_scratch_cold0);
> +
> +	return 0;
> +
> +error:
> +	mbox_qspi_close();
> +
> +	return ret;
> +}
> +#endif /* CONFIG_CADENCE_QSPI */
> +
> +int mbox_reset_cold(void)
> +{
> +	int ret;
> +
> +	ret = mbox_send_cmd(MBOX_ID_UBOOT, MBOX_REBOOT_HPS, MBOX_CMD_DIRECT,
> +			    0, NULL, 0, 0, NULL);
> +	if (ret) {
> +		/* mailbox sent failure, wait for watchdog to kick in */
> +		while (1)
> +			;

Is this supposed to be hang() ?

> +	}
> +	return 0;
> +}
> +
> +int mbox_send_cmd(u8 id, u32 cmd, u8 is_indirect, u32 len, u32 *arg,
> +		  u8 urgent, u32 *resp_buf_len, u32 *resp_buf)
> +{
> +	return __mbox_send_cmd(id, cmd, is_indirect, len, arg, urgent,
> +			       resp_buf_len, resp_buf);
> +}

__anything is reserved for compiler, drop the leading underscores
> 


-- 
Best regards,
Marek Vasut

[U-Boot] [PATCH v1 09/16] arm: socfpga: stratix10: Add MMU support for Stratix10 SoC

[Marek Vasut]

On 04/19/2018 11:50 AM, Ley Foon Tan wrote:
> Add MMU support for Stratix SoC

You could get more creative with the commit messages ;-)

> Signed-off-by: Chin Liang See <chin.liang.see@intel.com>
> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>

Acked-by: Marek Vasut <marex@denx.de>

> ---
>  arch/arm/mach-socfpga/Makefile        |    1 +
>  arch/arm/mach-socfpga/mmu-arm64_s10.c |   71 +++++++++++++++++++++++++++++++++
>  2 files changed, 72 insertions(+), 0 deletions(-)
>  create mode 100644 arch/arm/mach-socfpga/mmu-arm64_s10.c
> 
> diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
> index 43e18d2..098e5e9 100644
> --- a/arch/arm/mach-socfpga/Makefile
> +++ b/arch/arm/mach-socfpga/Makefile
> @@ -34,6 +34,7 @@ ifdef CONFIG_TARGET_SOCFPGA_STRATIX10
>  obj-y	+= clock_manager_s10.o
>  obj-y	+= mailbox_s10.o
>  obj-y	+= misc_s10.o
> +obj-y	+= mmu-arm64_s10.o
>  obj-y	+= reset_manager_s10.o
>  obj-y	+= system_manager_s10.o
>  obj-y	+= wrap_pinmux_config_s10.o
> diff --git a/arch/arm/mach-socfpga/mmu-arm64_s10.c b/arch/arm/mach-socfpga/mmu-arm64_s10.c
> new file mode 100644
> index 0000000..670ceb9
> --- /dev/null
> +++ b/arch/arm/mach-socfpga/mmu-arm64_s10.c
> @@ -0,0 +1,71 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (C) 2016-2018 Intel Corporation <www.intel.com>
> + *
> + */
> +
> +#include <common.h>
> +#include <asm/armv8/mmu.h>
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +static struct mm_region socfpga_stratix10_mem_map[] = {
> +	{
> +		/* MEM 2GB*/
> +		.virt	= 0x0UL,
> +		.phys	= 0x0UL,
> +		.size	= 0x80000000UL,
> +		.attrs	= PTE_BLOCK_MEMTYPE(MT_NORMAL) |
> +				PTE_BLOCK_INNER_SHARE,
> +	}, {
> +		/* FPGA 1.5GB */
> +		.virt	= 0x80000000UL,
> +		.phys	= 0x80000000UL,
> +		.size	= 0x60000000UL,
> +		.attrs	= PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
> +				PTE_BLOCK_NON_SHARE |
> +				PTE_BLOCK_PXN | PTE_BLOCK_UXN,
> +	}, {
> +		/* DEVICE 142MB */
> +		.virt	= 0xF7000000UL,
> +		.phys	= 0xF7000000UL,
> +		.size	= 0x08E00000UL,
> +		.attrs	= PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
> +				PTE_BLOCK_NON_SHARE |
> +				PTE_BLOCK_PXN | PTE_BLOCK_UXN,
> +	}, {
> +		/* OCRAM 1MB but available 256KB */
> +		.virt	= 0xFFE00000UL,
> +		.phys	= 0xFFE00000UL,
> +		.size	= 0x00100000UL,
> +		.attrs	= PTE_BLOCK_MEMTYPE(MT_NORMAL) |
> +				PTE_BLOCK_INNER_SHARE,
> +	}, {
> +		/* DEVICE 32KB */
> +		.virt	= 0xFFFC0000UL,
> +		.phys	= 0xFFFC0000UL,
> +		.size	= 0x00008000UL,
> +		.attrs	= PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
> +				PTE_BLOCK_NON_SHARE |
> +				PTE_BLOCK_PXN | PTE_BLOCK_UXN,
> +	}, {
> +		/* MEM 124GB */
> +		.virt	= 0x0100000000UL,
> +		.phys	= 0x0100000000UL,
> +		.size	= 0x1F00000000UL,
> +		.attrs	= PTE_BLOCK_MEMTYPE(MT_NORMAL) |
> +				PTE_BLOCK_INNER_SHARE,
> +	}, {
> +		/* DEVICE 4GB */
> +		.virt	= 0x2000000000UL,
> +		.phys	= 0x2000000000UL,
> +		.size	= 0x0100000000UL,
> +		.attrs	= PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
> +				PTE_BLOCK_NON_SHARE |
> +				PTE_BLOCK_PXN | PTE_BLOCK_UXN,
> +	}, {
> +		/* List terminator */
> +	},
> +};
> +
> +struct mm_region *mem_map = socfpga_stratix10_mem_map;
> 


-- 
Best regards,
Marek Vasut

[U-Boot] [PATCH v1 10/16] arm: dts: Add dts for Stratix10 SoC

[Marek Vasut]

On 04/19/2018 11:50 AM, Ley Foon Tan wrote:
> Device tree for Stratix10 SoC
> 
> Signed-off-by: Chin Liang See <chin.liang.see@intel.com>
> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>


Is this pulled from mainline Linux or not ?

-- 
Best regards,
Marek Vasut

[U-Boot] [PATCH v1 12/16] arm: socfpga: stratix10: Add SPL driver for Stratix10 SoC

[Marek Vasut]

On 04/19/2018 11:50 AM, Ley Foon Tan wrote:
> Add SPL driver support for Stratix SoC
> 
> Signed-off-by: Chin Liang See <chin.liang.see@intel.com>
> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
> ---
>  arch/arm/mach-socfpga/Makefile                    |    4 +
>  arch/arm/mach-socfpga/include/mach/firewall_s10.h |   84 +++++++++
>  arch/arm/mach-socfpga/spl_s10.c                   |  205 +++++++++++++++++++++
>  3 files changed, 293 insertions(+), 0 deletions(-)
>  create mode 100644 arch/arm/mach-socfpga/include/mach/firewall_s10.h
>  create mode 100644 arch/arm/mach-socfpga/spl_s10.c
> 
> diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
> index b669d43..35b124a 100644
> --- a/arch/arm/mach-socfpga/Makefile
> +++ b/arch/arm/mach-socfpga/Makefile
> @@ -40,6 +40,7 @@ obj-y	+= system_manager_s10.o
>  obj-y	+= wrap_pinmux_config_s10.o
>  obj-y	+= wrap_pll_config_s10.o
>  endif
> +
>  ifdef CONFIG_SPL_BUILD
>  ifdef CONFIG_TARGET_SOCFPGA_GEN5
>  obj-y	+= spl_gen5.o
> @@ -51,6 +52,9 @@ endif
>  ifdef CONFIG_TARGET_SOCFPGA_ARRIA10
>  obj-y	+= spl_a10.o
>  endif
> +ifdef CONFIG_TARGET_SOCFPGA_STRATIX10
> +obj-y	+= spl_s10.o
> +endif
>  endif
>  
>  ifdef CONFIG_TARGET_SOCFPGA_GEN5
> diff --git a/arch/arm/mach-socfpga/include/mach/firewall_s10.h b/arch/arm/mach-socfpga/include/mach/firewall_s10.h
> new file mode 100644
> index 0000000..70aa9a6
> --- /dev/null
> +++ b/arch/arm/mach-socfpga/include/mach/firewall_s10.h
> @@ -0,0 +1,84 @@
> +/* SPDX-License-Identifier: GPL-2.0
> + *
> + * Copyright (C) 2017-2018 Intel Corporation <www.intel.com>
> + *
> + */
> +
> +#ifndef	_FIREWALL_S10_
> +#define	_FIREWALL_S10_
> +
> +struct socfpga_firwall_l4_per {
> +	u32	nand;		/* 0x00 */
> +	u32	nand_data;
> +	u32	_pad_0x8;
> +	u32	usb0;
> +	u32	usb1;		/* 0x10 */
> +	u32	_pad_0x14;
> +	u32	_pad_0x18;
> +	u32	spim0;
> +	u32	spim1;		/* 0x20 */
> +	u32	spis0;
> +	u32	spis1;
> +	u32	emac0;
> +	u32	emac1;		/* 0x30 */
> +	u32	emac2;
> +	u32	_pad_0x38;
> +	u32	_pad_0x3c;
> +	u32	sdmmc;		/* 0x40 */
> +	u32	gpio0;
> +	u32	gpio1;
> +	u32	_pad_0x4c;
> +	u32	i2c0;		/* 0x50 */
> +	u32	i2c1;
> +	u32	i2c2;
> +	u32	i2c3;
> +	u32	i2c4;		/* 0x60 */
> +	u32	timer0;
> +	u32	timer1;
> +	u32	uart0;
> +	u32	uart1;		/* 0x70 */
> +};
> +
> +struct socfpga_firwall_l4_sys {
> +	u32	_pad_0x00;		/* 0x00 */
> +	u32	_pad_0x04;
> +	u32	dma_ecc;
> +	u32	emac0rx_ecc;
> +	u32	emac0tx_ecc;		/* 0x10 */
> +	u32	emac1rx_ecc;
> +	u32	emac1tx_ecc;
> +	u32	emac2rx_ecc;
> +	u32	emac2tx_ecc;		/* 0x20 */
> +	u32	_pad_0x24;
> +	u32	_pad_0x28;
> +	u32	nand_ecc;
> +	u32	nand_read_ecc;		/* 0x30 */
> +	u32	nand_write_ecc;
> +	u32	ocram_ecc;
> +	u32	_pad_0x3c;
> +	u32	sdmmc_ecc;		/* 0x40 */
> +	u32	usb0_ecc;
> +	u32	usb1_ecc;
> +	u32	clock_manager;
> +	u32	_pad_0x50;		/* 0x50 */
> +	u32	io_manager;
> +	u32	reset_manager;
> +	u32	system_manager;
> +	u32	osc0_timer;		/* 0x60 */
> +	u32	osc1_timer;
> +	u32	watchdog0;
> +	u32	watchdog1;
> +	u32	watchdog2;		/* 0x70 */
> +	u32	watchdog3;
> +};
> +
> +#define FIREWALL_L4_DISABLE_ALL		(BIT(0) | BIT(24) | BIT(16))
> +#define FIREWALL_BRIDGE_DISABLE_ALL	(~0)
> +
> +#define CCU_CPU0_MPRT_ADMASK_MEM_RAM0_ADDR	0xf7004688
> +#define CCU_IOM_MPRT_ADMASK_MEM_RAM0_ADDR	0xf7018628
> +
> +#define CCU_ADMASK_P_MASK			(BIT(0))
> +#define CCU_ADMASK_NS_MASK			(BIT(1))

Drop outer parenthesis

> +
> +#endif /* _FIREWALL_S10_ */
> diff --git a/arch/arm/mach-socfpga/spl_s10.c b/arch/arm/mach-socfpga/spl_s10.c
> new file mode 100644
> index 0000000..3b3833d
> --- /dev/null
> +++ b/arch/arm/mach-socfpga/spl_s10.c
> @@ -0,0 +1,205 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (C) 2016-2018 Intel Corporation <www.intel.com>
> + *
> + */
> +
> +#include <common.h>
> +#include <asm/io.h>
> +#include <asm/u-boot.h>
> +#include <asm/utils.h>
> +#include <image.h>
> +#include <asm/arch/reset_manager.h>
> +#include <spl.h>
> +#include <asm/arch/system_manager.h>
> +#include <asm/arch/clock_manager.h>
> +#include <asm/arch/sdram_s10.h>
> +#include <asm/arch/mailbox_s10.h>
> +#include <asm/arch/firewall_s10.h>
> +#include <watchdog.h>
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +static const struct socfpga_firwall_l4_per *firwall_l4_per_base =
> +	(struct socfpga_firwall_l4_per *)SOCFPGA_FIREWALL_L4_PER;
> +static const struct socfpga_firwall_l4_sys *firwall_l4_sys_base =
> +	(struct socfpga_firwall_l4_sys *)SOCFPGA_FIREWALL_L4_SYS;
> +static struct socfpga_system_manager *sysmgr_regs =
> +	(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
> +
> +u32 spl_boot_device(void)
> +{
> +	/* TODO: Get from SDM or handoff */
> +	return BOOT_DEVICE_MMC1;
> +}
> +
> +#ifdef CONFIG_SPL_MMC_SUPPORT
> +u32 spl_boot_mode(const u32 boot_device)
> +{
> +#if defined(CONFIG_SPL_FAT_SUPPORT) || defined(CONFIG_SPL_EXT_SUPPORT)
> +	return MMCSD_MODE_FS;
> +#else
> +	return MMCSD_MODE_RAW;
> +#endif
> +}
> +#endif
> +
> +void board_init_f(ulong dummy)
> +{
> +	const struct cm_config *cm_default_cfg = cm_get_default_config();
> +
> +#ifdef CONFIG_HW_WATCHDOG
> +	/* Ensure watchdog is paused when debugging is happening */
> +	writel(SYSMGR_WDDBG_PAUSE_ALL_CPU, &sysmgr_regs->wddbg);
> +
> +	/* Enable watchdog before initializing the HW */
> +	socfpga_per_reset(SOCFPGA_RESET(L4WD0), 1);
> +	socfpga_per_reset(SOCFPGA_RESET(L4WD0), 0);
> +	hw_watchdog_init();
> +#endif
> +
> +	/* ensure all processors are not released prior Linux boot */
> +	writeq(0, CPU_RELEASE_ADDR);
> +
> +	socfpga_per_reset(SOCFPGA_RESET(OSC1TIMER0), 0);
> +	timer_init();
> +
> +	populate_sysmgr_pinmux();
> +
> +	/* configuring the HPS clocks */
> +	cm_basic_init(cm_default_cfg);
> +
> +	/* enable console uart printing */
> +#if (CONFIG_SYS_NS16550_COM1 == SOCFPGA_UART0_ADDRESS)

Yoda notation, please fix. Also, shouldn't the reset controller handle
this ?

> +	socfpga_per_reset(SOCFPGA_RESET(UART0), 0);
> +	/* enables nonsecure access to UART0 */
> +	writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_per_base->uart0);
> +#elif (CONFIG_SYS_NS16550_COM1 == SOCFPGA_UART1_ADDRESS)
> +	socfpga_per_reset(SOCFPGA_RESET(UART1), 0);
> +	/* enables nonsecure access to UART1 */
> +	writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_per_base->uart1);
> +#endif
> +
> +	preloader_console_init();
> +	cm_print_clock_quick_summary();

This function doesn't fit on my pivoted 4k screen with small font, it is
clearly too long. Please split it.

> +	/* enable non-secure interface to DMA330 DMA and peripherals */
> +	writel(SYSMGR_DMA_IRQ_NS | SYSMGR_DMA_MGR_NS, &sysmgr_regs->dma);
> +	writel(SYSMGR_DMAPERIPH_ALL_NS, &sysmgr_regs->dma_periph);
> +	/* enable DMA330 DMA */
> +	socfpga_per_reset(SOCFPGA_RESET(DMA), 0);
> +
> +	/*
> +	 * The following lines of code will enable non-secure access
> +	 * to nand, usb, spi, emac, sdmmc, gpio, i2c, and timers. This
> +	 * is needed as most OS run in non-secure mode. Thus we need to
> +	 * enable non-secure access to these peripherals in order for the
> +	 * OS to use these peripherals.
> +	 */
> +	writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_per_base->nand);
> +	writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_per_base->nand_data);
> +	writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_per_base->usb0);
> +	writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_per_base->usb1);
> +	writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_per_base->spim0);
> +	writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_per_base->spim1);
> +	writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_per_base->emac0);
> +	writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_per_base->emac1);
> +	writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_per_base->emac2);
> +	writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_per_base->sdmmc);
> +	writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_sys_base->sdmmc_ecc);
> +	writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_per_base->gpio0);
> +	writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_per_base->gpio1);
> +	writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_per_base->i2c0);
> +	writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_per_base->i2c1);
> +	writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_per_base->i2c2);
> +	writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_per_base->i2c3);
> +	writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_per_base->i2c4);
> +	writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_per_base->timer0);
> +	writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_per_base->timer1);

Turn this into a table ?

> +	/* enables nonsecure access to clock mgr */
> +	writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_sys_base->clock_manager);
> +
> +	/* enables nonsecure access to reset mgr */
> +	writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_sys_base->reset_manager);
> +
> +	/* enables nonsecure access to system mgr */
> +	writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_sys_base->system_manager);
> +
> +	/* enables nonsecure access to OCRAM */
> +	writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_sys_base->ocram_ecc);
> +
> +	/* enables nonsecure access to all the emacs */
> +	writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_sys_base->emac0rx_ecc);
> +	writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_sys_base->emac0tx_ecc);
> +	writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_sys_base->emac1rx_ecc);
> +	writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_sys_base->emac1tx_ecc);
> +	writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_sys_base->emac2rx_ecc);
> +	writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_sys_base->emac2tx_ecc);
> +
> +	/* enables nonsecure access to SMMU */
> +	writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_sys_base->io_manager);
> +
> +	/* enables nonsecure access to watchdog */
> +	writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_sys_base->watchdog0);
> +	writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_sys_base->watchdog1);
> +	writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_sys_base->watchdog2);
> +	writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_sys_base->watchdog3);
> +
> +	/* enables SDMMC */
> +	socfpga_per_reset(SOCFPGA_RESET(SDMMC_OCP), 0);
> +	socfpga_per_reset(SOCFPGA_RESET(SDMMC), 0);
> +	/* enable usb0 and usb1 */
> +	socfpga_per_reset(SOCFPGA_RESET(USB0), 0);
> +	socfpga_per_reset(SOCFPGA_RESET(USB1), 0);
> +	socfpga_per_reset(SOCFPGA_RESET(USB0_OCP), 0);
> +	socfpga_per_reset(SOCFPGA_RESET(USB1_OCP), 0);
> +	/* enable SPIM1 */
> +	socfpga_per_reset(SOCFPGA_RESET(SPIM1), 0);

See below.

> +	/* disable lwsocf2fpga and soc2fpga bridge security */
> +	writel(FIREWALL_BRIDGE_DISABLE_ALL, SOCFPGA_FIREWALL_SOC2FPGA);
> +	writel(FIREWALL_BRIDGE_DISABLE_ALL, SOCFPGA_FIREWALL_LWSOC2FPGA);
> +
> +	/* disable SMMU security */
> +	writel(FIREWALL_L4_DISABLE_ALL, SOCFPGA_FIREWALL_TCU);
> +
> +	/* disable ocram security at CCU for non secure access */
> +	clrbits_le32(CCU_CPU0_MPRT_ADMASK_MEM_RAM0_ADDR,
> +		     CCU_ADMASK_P_MASK | CCU_ADMASK_NS_MASK);
> +	clrbits_le32(CCU_IOM_MPRT_ADMASK_MEM_RAM0_ADDR,
> +		     CCU_ADMASK_P_MASK | CCU_ADMASK_NS_MASK);
> +
> +	/* enable i2c1 */
> +	socfpga_per_reset(SOCFPGA_RESET(I2C1), 0);
> +
> +	/* Take GPIO0 & GPIO1 out of reset */
> +	socfpga_per_reset(SOCFPGA_RESET(GPIO0), 0);
> +	socfpga_per_reset(SOCFPGA_RESET(GPIO1), 0);

Shouldn't this be done by the reset framework ?

> +	/* enable SPIM0 and SPIM1 */
> +	socfpga_per_reset(SOCFPGA_RESET(SPIM0), 0);
> +	socfpga_per_reset(SOCFPGA_RESET(SPIM1), 0);

You ungated this SPI block already like 20 lines above.

> +	puts("DDR: Initializing Hard Memory Controller\n");
> +	if (sdram_mmr_init_full(0)) {
> +		puts("DDR: Initialization failed.\n");
> +		hang();
> +	}
> +
> +	gd->ram_size = sdram_calculate_size();
> +	printf("DDR: %d MiB\n", (int)(gd->ram_size >> 20));
> +
> +	/* Sanity check ensure correct SDRAM size specified */
> +	puts("DDR: Running SDRAM size sanity check\n");
> +	if (get_ram_size(0, gd->ram_size) != gd->ram_size) {
> +		puts("DDR: SDRAM size check failed!\n");
> +		hang();
> +	}
> +	puts("DDR: SDRAM size check passed!\n");

You can probably turn most of those ad-hoc prints into debug()s.

> +
> +#ifdef CONFIG_CADENCE_QSPI
> +	mbox_init();
> +	mbox_qspi_open();
> +#endif
> +}
> 


-- 
Best regards,
Marek Vasut

[U-Boot] [PATCH v1 13/16] arm: socfpga: stratix10: Add timer support for Stratix10 SoC

[Marek Vasut]

On 04/19/2018 11:50 AM, Ley Foon Tan wrote:
> Add timer support for Stratix SoC

Is this really custom timer or is that some armv8 thing you're adding
here ? Don't we already have a generic implementation for that ? If not,
that's what we should do here.

> Signed-off-by: Chin Liang See <chin.liang.see@intel.com>
> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
> ---
>  arch/arm/mach-socfpga/timer.c |   17 ++++++++++++++++-
>  1 files changed, 16 insertions(+), 1 deletions(-)
> 
> diff --git a/arch/arm/mach-socfpga/timer.c b/arch/arm/mach-socfpga/timer.c
> index 253cde3..4c90b57 100644
> --- a/arch/arm/mach-socfpga/timer.c
> +++ b/arch/arm/mach-socfpga/timer.c
> @@ -1,5 +1,6 @@
>  /*
> - *  Copyright (C) 2012 Altera Corporation <www.altera.com>
> + * Copyright (C) 2016-2018 Intel Corporation <www.intel.com>
> + * Copyright (C) 2012-2016 Altera Corporation <www.altera.com>
>   *
>   * SPDX-License-Identifier:	GPL-2.0+
>   */
> @@ -10,15 +11,29 @@
>  
>  #define TIMER_LOAD_VAL		0xFFFFFFFF
>  
> +#if !defined(CONFIG_TARGET_SOCFPGA_STRATIX10)
>  static const struct socfpga_timer *timer_base = (void *)CONFIG_SYS_TIMERBASE;
> +#endif
>  
>  /*
>   * Timer initialization
>   */
>  int timer_init(void)
>  {
> +#if defined(CONFIG_TARGET_SOCFPGA_STRATIX10)
> +	int enable = 0x3;	/* timer enable + output signal masked */
> +	int loadval = ~0;
> +
> +	/* enable system counter */
> +	writel(enable, SOCFPGA_GTIMER_SEC_ADDRESS);
> +	/* enable processor pysical counter */
> +	asm volatile("msr cntp_ctl_el0, %0" : : "r" (enable));
> +	asm volatile("msr cntp_tval_el0, %0" : : "r" (loadval));
> +
> +#else
>  	writel(TIMER_LOAD_VAL, &timer_base->load_val);
>  	writel(TIMER_LOAD_VAL, &timer_base->curr_val);
>  	writel(readl(&timer_base->ctrl) | 0x3, &timer_base->ctrl);
> +#endif
>  	return 0;
>  }
> 


-- 
Best regards,
Marek Vasut

[U-Boot] [PATCH v1 14/16] ddr: altera: stratix10: Add DDR support for Stratix10 SoC

[Marek Vasut]

On 04/19/2018 11:50 AM, Ley Foon Tan wrote:
> Add DDR support for Stratix SoC

OT: How very different is the DDR controller on Stratix 10 and Arria 10?

> Signed-off-by: Chin Liang See <chin.liang.see@intel.com>
> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
> ---
>  arch/arm/mach-socfpga/include/mach/sdram_s10.h |  340 ++++++++++++++++++++

If this is used only be the driver, no point having it in mach/

>  drivers/ddr/altera/Makefile                    |    1 +
>  drivers/ddr/altera/sdram_s10.c                 |  392 ++++++++++++++++++++++++
>  3 files changed, 733 insertions(+), 0 deletions(-)
>  create mode 100644 arch/arm/mach-socfpga/include/mach/sdram_s10.h
>  create mode 100644 drivers/ddr/altera/sdram_s10.c
[...]

> +
> +union caltiming9_reg {
> +	struct {
> +		u32 cfg_4_act_to_act:8;
> +		u32 reserved:24;
> +	};
> +	u32 word;
> +};

I wonder if this struct stuff is really a good idea.

> +#define DDR_SCHED_DDRTIMING_ACTTOACT_OFFSET	0
> +#define DDR_SCHED_DDRTIMING_RDTOMISS_OFFSET	6
> +#define DDR_SCHED_DDRTIMING_WRTOMISS_OFFSET	12
> +#define DDR_SCHED_DDRTIMING_BURSTLEN_OFFSET	18
> +#define DDR_SCHED_DDRTIMING_RDTOWR_OFFSET	21
> +#define DDR_SCHED_DDRTIMING_WRTORD_OFFSET	26
> +#define DDR_SCHED_DDRTIMING_BWRATIO_OFFSET	31
> +#define DDR_SCHED_DDRMOD_BWRATIOEXTENDED_OFFSET	1
> +#define DDR_SCHED_ACTIVATE_RRD_OFFSET		0
> +#define DDR_SCHED_ACTIVATE_FAW_OFFSET		4
> +#define DDR_SCHED_ACTIVATE_FAWBANK_OFFSET	10
> +#define DDR_SCHED_DEVTODEV_BUSRDTORD_OFFSET	0
> +#define DDR_SCHED_DEVTODEV_BUSRDTOWR_OFFSET	2
> +#define DDR_SCHED_DEVTODEV_BUSWRTORD_OFFSET	4
> +#define DDR_HMC_DDRIOCTRL_IOSIZE_MSK		0x00000003
> +#define DDR_HMC_DDRCALSTAT_CAL_MSK		0x00000001
> +#define DDR_HMC_ECCCTL_AWB_CNT_RST_SET_MSK	0x00010000
> +#define DDR_HMC_ECCCTL_CNT_RST_SET_MSK		0x00000100
> +#define DDR_HMC_ECCCTL_ECC_EN_SET_MSK		0x00000001
> +#define DDR_HMC_ECCCTL2_RMW_EN_SET_MSK		0x00000100
> +#define DDR_HMC_ECCCTL2_AWB_EN_SET_MSK		0x00000001
> +#define DDR_HMC_ECC_DIAGON_ECCDIAGON_EN_SET_MSK	0x00010000
> +#define DDR_HMC_ECC_DIAGON_WRDIAGON_EN_SET_MSK	0x00000001
> +#define DDR_HMC_ERRINTEN_SERRINTEN_EN_SET_MSK	0x00000001
> +#define DDR_HMC_ERRINTEN_DERRINTEN_EN_SET_MSK	0x00000002
> +#define DDR_HMC_INTSTAT_SERRPENA_SET_MSK	0x00000001
> +#define DDR_HMC_INTSTAT_DERRPENA_SET_MSK	0x00000002
> +#define DDR_HMC_INTSTAT_ADDRMTCFLG_SET_MSK	0x00010000
> +#define DDR_HMC_INTMODE_INTMODE_SET_MSK		0x00000001
> +#define DDR_HMC_RSTHANDSHAKE_MASK		0x000000ff
> +#define DDR_HMC_CORE2SEQ_INT_REQ		0xF
> +#define DDR_HMC_SEQ2CORE_INT_RESP_MASK		0x8
> +#define DDR_HMC_HPSINTFCSEL_ENABLE_MASK		0x001f1f1f
> +
> +#define CCU_CPU0_MPRT_ADBASE_DDRREG_ADDR	0xf7004400
> +#define CCU_CPU0_MPRT_ADBASE_MEMSPACE0_ADDR	0xf70045c0
> +#define CCU_CPU0_MPRT_ADBASE_MEMSPACE1A_ADDR	0xf70045e0
> +#define CCU_CPU0_MPRT_ADBASE_MEMSPACE1B_ADDR	0xf7004600
> +#define CCU_CPU0_MPRT_ADBASE_MEMSPACE1C_ADDR	0xf7004620
> +#define CCU_CPU0_MPRT_ADBASE_MEMSPACE1D_ADDR	0xf7004640
> +#define CCU_CPU0_MPRT_ADBASE_MEMSPACE1E_ADDR	0xf7004660

Can all this come from DT, maybe except for the offsets ?

> +#define CCU_IOM_MPRT_ADBASE_MEMSPACE0_ADDR	0xf7018560
> +#define CCU_IOM_MPRT_ADBASE_MEMSPACE1A_ADDR	0xf7018580
> +#define CCU_IOM_MPRT_ADBASE_MEMSPACE1B_ADDR	0xf70185a0
> +#define CCU_IOM_MPRT_ADBASE_MEMSPACE1C_ADDR	0xf70185c0
> +#define CCU_IOM_MPRT_ADBASE_MEMSPACE1D_ADDR	0xf70185e0
> +#define CCU_IOM_MPRT_ADBASE_MEMSPACE1E_ADDR	0xf7018600
> +
> +#define CCU_ADBASE_DI_MASK			0x00000010

[...]

> +#define DDR_CONFIG(A, B, C, R)	((A << 24) | (B << 16) | (C << 8) | R)

You need parenthesis around A, B, C, R in the macro.

> +/* The followring are the supported configurations */
> +u32 ddr_config[] = {
> +	/* DDR_CONFIG(Address order,Bank,Column,Row) */
> +	/* List for DDR3 or LPDDR3 (pinout order > chip, row, bank, column) */
> +	DDR_CONFIG(0, 3, 10, 12),
> +	DDR_CONFIG(0, 3,  9, 13),
> +	DDR_CONFIG(0, 3, 10, 13),
> +	DDR_CONFIG(0, 3,  9, 14),
> +	DDR_CONFIG(0, 3, 10, 14),
> +	DDR_CONFIG(0, 3, 10, 15),
> +	DDR_CONFIG(0, 3, 11, 14),
> +	DDR_CONFIG(0, 3, 11, 15),
> +	DDR_CONFIG(0, 3, 10, 16),
> +	DDR_CONFIG(0, 3, 11, 16),
> +	DDR_CONFIG(0, 3, 12, 15),	/* 0xa */
> +	/* List for DDR4 only (pinout order > chip, bank, row, column) */
> +	DDR_CONFIG(1, 3, 10, 14),
> +	DDR_CONFIG(1, 4, 10, 14),
> +	DDR_CONFIG(1, 3, 10, 15),
> +	DDR_CONFIG(1, 4, 10, 15),
> +	DDR_CONFIG(1, 3, 10, 16),
> +	DDR_CONFIG(1, 4, 10, 16),
> +	DDR_CONFIG(1, 3, 10, 17),
> +	DDR_CONFIG(1, 4, 10, 17),
> +};
> +
> +#define DDR_CONFIG_ELEMENTS	(sizeof(ddr_config) / sizeof(u32))

Is that ARRAY_SIZE() ?

> +int match_ddr_conf(u32 ddr_conf)
> +{
> +	int i;
> +
> +	for (i = 0; i < DDR_CONFIG_ELEMENTS; i++) {
> +		if (ddr_conf == ddr_config[i])
> +			return i;
> +	}
> +	return 0;
> +}
> +
> +static int emif_clear(void)
> +{
> +	u32 s2c, i;
> +
> +	writel(0, &socfpga_ecc_hmc_base->rsthandshakectrl);
> +	s2c = readl(&socfpga_ecc_hmc_base->rsthandshakestat) &
> +	      DDR_HMC_RSTHANDSHAKE_MASK;
> +
> +	for (i = 1000; (i > 0) && s2c; i--) {
> +		WATCHDOG_RESET();
> +		mdelay(1);
> +		s2c = readl(&socfpga_ecc_hmc_base->rsthandshakestat) &
> +		      DDR_HMC_RSTHANDSHAKE_MASK;

wait_for_bit() ?

> +	}
> +	return !s2c;
> +}
> +
> +static int emif_reset(void)
> +{
> +	u32 c2s, s2c, i;
> +
> +	c2s = readl(&socfpga_ecc_hmc_base->rsthandshakectrl) &
> +	      DDR_HMC_RSTHANDSHAKE_MASK;
> +	s2c = readl(&socfpga_ecc_hmc_base->rsthandshakestat) &
> +	      DDR_HMC_RSTHANDSHAKE_MASK;
> +
> +	debug("DDR: c2s=%08x s2c=%08x nr0=%08x nr1=%08x nr2=%08x dst=%08x\n",
> +	      c2s, s2c, readl(&socfpga_io48_mmr_base->niosreserve0),
> +	      readl(&socfpga_io48_mmr_base->niosreserve1),
> +	      readl(&socfpga_io48_mmr_base->niosreserve2),
> +	      readl(&socfpga_io48_mmr_base->dramsts));
> +
> +	if (s2c && emif_clear()) {
> +		printf("DDR: emif_clear() failed\n");
> +		return -1;
> +	}
> +
> +	puts("DDR: Triggerring emif reset\n");
> +	writel(DDR_HMC_CORE2SEQ_INT_REQ,
> +	       &socfpga_ecc_hmc_base->rsthandshakectrl);
> +
> +	for (i = 1000; i > 0; i--) {
> +		/* if seq2core[3] = 0, we are good */
> +		if (!(readl(&socfpga_ecc_hmc_base->rsthandshakestat) &
> +		    DDR_HMC_SEQ2CORE_INT_RESP_MASK))
> +			break;
> +		WATCHDOG_RESET();
> +		mdelay(1);

Another wait_for_bit() ?

> +	}
> +
> +	if (!i) {
> +		printf("DDR: failed to get ack from EMIF\n");
> +		return -2;
> +	}
> +
> +	if (emif_clear()) {
> +		printf("DDR: emif_clear() failed\n");
> +		return -3;
> +	}
> +
> +	printf("DDR: %s triggered successly\n", __func__);

debug() ?

> +	return 0;
> +}
Comb through this and fix the things mentioned above globally.

-- 
Best regards,
Marek Vasut

[U-Boot] [PATCH v1 01/16] arm: socfpga: stratix10: Add base address map for Statix10 SoC

[Marek Vasut]

On 04/19/2018 11:50 AM, Ley Foon Tan wrote:
> Add the base address map for Statix10 SoC
> 
> Signed-off-by: Chin Liang See <chin.liang.see@intel.com>
> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
> ---
>  arch/arm/mach-socfpga/include/mach/base_addr_s10.h |   38 ++++++++++++++++++++
>  1 files changed, 38 insertions(+), 0 deletions(-)
>  create mode 100644 arch/arm/mach-socfpga/include/mach/base_addr_s10.h
> 
> diff --git a/arch/arm/mach-socfpga/include/mach/base_addr_s10.h b/arch/arm/mach-socfpga/include/mach/base_addr_s10.h
> new file mode 100644
> index 0000000..e18d2bf
> --- /dev/null
> +++ b/arch/arm/mach-socfpga/include/mach/base_addr_s10.h
> @@ -0,0 +1,38 @@
> +/* SPDX-License-Identifier: GPL-2.0
> + *
> + * Copyright (C) 2016-2018 Intel Corporation <www.intel.com>
> + *
> + */
> +
> +#ifndef _SOCFPGA_S10_BASE_HARDWARE_H_
> +#define _SOCFPGA_S10_BASE_HARDWARE_H_
> +
> +#define SOCFPGA_SDR_SCHEDULER_ADDRESS		0xf8000400
> +#define SOCFPGA_HMC_MMR_IO48_ADDRESS		0xf8010000
> +#define SOCFPGA_SDR_ADDRESS			0xf8011000
> +#define SOCFPGA_SMMU_ADDRESS			0xfa000000
> +#define SOCFPGA_MAILBOX_ADDRESS			0xffA30000
> +#define SOCFPGA_UART0_ADDRESS			0xffc02000
> +#define SOCFPGA_UART1_ADDRESS			0xffc02100
> +#define SOCFPGA_L4WD0_ADDRESS			0xffd00200
> +#define SOCFPGA_L4WD1_ADDRESS			0xffd00300
> +#define SOCFPGA_L4WD2_ADDRESS			0xffd00400
> +#define SOCFPGA_L4WD3_ADDRESS			0xffd00500
> +#define SOCFPGA_GTIMER_SEC_ADDRESS		0xffd01000
> +#define SOCFPGA_GTIMER_NSEC_ADDRESS		0xffd02000
> +#define SOCFPGA_CLKMGR_ADDRESS			0xffd10000
> +#define SOCFPGA_RSTMGR_ADDRESS			0xffd11000
> +#define SOCFPGA_SYSMGR_ADDRESS			0xffd12000
> +#define SOCFPGA_PINMUX_DEDICATED_IO_ADDRESS	0xffd13000
> +#define SOCFPGA_FIREWALL_L4_PER			0xffd21000
> +#define SOCFPGA_FIREWALL_L4_SYS			0xffd21100
> +#define SOCFPGA_FIREWALL_SOC2FPGA		0xffd21200
> +#define SOCFPGA_FIREWALL_LWSOC2FPGA		0xffd21300
> +#define SOCFPGA_FIREWALL_TCU			0xffd21400
> +#define SOCFPGA_DMANONSECURE_ADDRESS		0xffda0000
> +#define SOCFPGA_DMASECURE_ADDRESS		0xffda1000
> +#define SOCFPGA_OCRAM_ADDRESS			0xffe00000
> +#define GICD_BASE				0xfffc1000
> +#define GICC_BASE				0xfffc2000

How much of this can come from DT ?

> +#endif /* _SOCFPGA_S10_BASE_HARDWARE_H_ */
> 


-- 
Best regards,
Marek Vasut

[U-Boot] [PATCH v1 06/16] arm: socfpga: misc: Move eth reset to common misc driver

[Ley Foon Tan]

On Thu, Apr 19, 2018 at 10:47 AM, Marek Vasut <marex@denx.de> wrote:
> On 04/19/2018 11:50 AM, Ley Foon Tan wrote:
>> Move eth reset to common misc driver so can used by other device families.
>>
>> Signed-off-by: Chin Liang See <chin.liang.see@intel.com>
>> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
>
> Shouldn't this use the reset framework instead ?
>
What reset framework you refer to? drivers/reset?

[U-Boot] [PATCH v1 05/16] arm: socfpga: misc: Add CONFIG_SYS_L2_PL310 switch

[See, Chin Liang]

On Thu, 2018-04-19 at 04:47 +0200, Marek Vasut wrote:
> On 04/19/2018 11:50 AM, Ley Foon Tan wrote:
> > 
> > Add CONFIG_SYS_L2_PL310 conditional build.
> Why ?
> 

In ARM64, L2 cache controller is accessed through processor registers.
Hence we shall make this conditional in order this file can be shared
across SOCFPGAs.

Thanks
Chin Liang

[U-Boot] [PATCH v1 13/16] arm: socfpga: stratix10: Add timer support for Stratix10 SoC

[See, Chin Liang]

On Thu, 2018-04-19 at 04:59 +0200, Marek Vasut wrote:
> On 04/19/2018 11:50 AM, Ley Foon Tan wrote:
> > 
> > Add timer support for Stratix SoC
> Is this really custom timer or is that some armv8 thing you're adding
> here ? Don't we already have a generic implementation for that ? If
> not,
> that's what we should do here.

Yes but not the init function. It's left with platform specific code to
init it.

Thanks
Chin Liang

[U-Boot] [PATCH v1 05/16] arm: socfpga: misc: Add CONFIG_SYS_L2_PL310 switch

[Marek Vasut]

On 04/19/2018 07:15 AM, See, Chin Liang wrote:
> On Thu, 2018-04-19 at 04:47 +0200, Marek Vasut wrote:
>> On 04/19/2018 11:50 AM, Ley Foon Tan wrote:
>>>
>>> Add CONFIG_SYS_L2_PL310 conditional build.
>> Why ?
>>
> 
> In ARM64, L2 cache controller is accessed through processor registers.
> Hence we shall make this conditional in order this file can be shared
> across SOCFPGAs.

That should be in the patch description .
Do you ever add the PL310 register access on S10 later in the set?

-- 
Best regards,
Marek Vasut

[U-Boot] [PATCH v1 06/16] arm: socfpga: misc: Move eth reset to common misc driver

[Marek Vasut]

On 04/19/2018 05:13 AM, Ley Foon Tan wrote:
> On Thu, Apr 19, 2018 at 10:47 AM, Marek Vasut <marex@denx.de> wrote:
>> On 04/19/2018 11:50 AM, Ley Foon Tan wrote:
>>> Move eth reset to common misc driver so can used by other device families.
>>>
>>> Signed-off-by: Chin Liang See <chin.liang.see@intel.com>
>>> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
>>
>> Shouldn't this use the reset framework instead ?
>>
> What reset framework you refer to? drivers/reset?

I think so, there were patches from Dinh earlier this month
 2ac718821a   | Dinh Nguyen  | reset: socfpga: add reset driver for
SoCFPGA platform

-- 
Best regards,
Marek Vasut

[U-Boot] [PATCH v1 13/16] arm: socfpga: stratix10: Add timer support for Stratix10 SoC

[Marek Vasut]

On 04/19/2018 07:26 AM, See, Chin Liang wrote:
> On Thu, 2018-04-19 at 04:59 +0200, Marek Vasut wrote:
>> On 04/19/2018 11:50 AM, Ley Foon Tan wrote:
>>>
>>> Add timer support for Stratix SoC
>> Is this really custom timer or is that some armv8 thing you're adding
>> here ? Don't we already have a generic implementation for that ? If
>> not,
>> that's what we should do here.
> 
> Yes but not the init function. It's left with platform specific code to
> init it.

Where is the common part ?

-- 
Best regards,
Marek Vasut

[U-Boot] [PATCH v1 00/16] Add Intel Stratix 10 SoC support

[Ley Foon Tan]

This patchset adds Intel Stratix 10 SoC support.

Regards
Ley Foon

Ley Foon Tan (16):
  arm: socfpga: stratix10: Add base address map for Statix10 SoC
  arm: socfpga: stratix10: Add clock manager driver for Stratix10 SoC
  arm: socfpga: stratix10: Add reset manager driver for Stratix10 SoC
  arm: socfpga: stratix10: Add pinmux support for Stratix10 SoC
  arm: socfpga: misc: Add CONFIG_SYS_L2_PL310 switch
  arm: socfpga: misc: Move eth reset to common misc driver
  arm: socfpga: stratix10: Add misc support for Stratix10 SoC
  arm: socfpga: stratix10: Add mailbox support for Stratix10 SoC
  arm: socfpga: stratix10: Add MMU support for Stratix10 SoC
  arm: dts: Add dts for Stratix10 SoC
  arm: socfpga: Restructure the SPL file
  arm: socfpga: stratix10: Add SPL driver for Stratix10 SoC
  arm: socfpga: stratix10: Add timer support for Stratix10 SoC
  ddr: altera: stratix10: Add DDR support for Stratix10 SoC
  board: altera: stratix10: Add socdk board support for Stratix10 SoC
  arm: socfpga: stratix10: Enable Stratix10 SoC build

 arch/arm/Kconfig                                   |    9 +-
 arch/arm/dts/Makefile                              |    3 +-
 arch/arm/dts/socfpga_stratix10_socdk.dts           |  282 ++++++++++++++
 arch/arm/mach-socfpga/Kconfig                      |   13 +
 arch/arm/mach-socfpga/Makefile                     |   19 +-
 arch/arm/mach-socfpga/clock_manager.c              |    4 +-
 arch/arm/mach-socfpga/clock_manager_s10.c          |  380 +++++++++++++++++++
 arch/arm/mach-socfpga/include/mach/base_addr_s10.h |   38 ++
 arch/arm/mach-socfpga/include/mach/clock_manager.h |    2 +
 .../mach-socfpga/include/mach/clock_manager_s10.h  |  210 +++++++++++
 arch/arm/mach-socfpga/include/mach/firewall_s10.h  |   84 +++++
 arch/arm/mach-socfpga/include/mach/handoff_s10.h   |   32 ++
 arch/arm/mach-socfpga/include/mach/mailbox_s10.h   |  155 ++++++++
 arch/arm/mach-socfpga/include/mach/misc.h          |    1 +
 arch/arm/mach-socfpga/include/mach/reset_manager.h |    2 +
 .../mach-socfpga/include/mach/reset_manager_s10.h  |  116 ++++++
 arch/arm/mach-socfpga/include/mach/sdram_s10.h     |  340 +++++++++++++++++
 .../arm/mach-socfpga/include/mach/system_manager.h |    5 +-
 .../mach-socfpga/include/mach/system_manager_s10.h |  176 +++++++++
 arch/arm/mach-socfpga/mailbox_s10.c                |  378 +++++++++++++++++++
 arch/arm/mach-socfpga/misc.c                       |   73 ++++
 arch/arm/mach-socfpga/misc_gen5.c                  |   74 +----
 arch/arm/mach-socfpga/misc_s10.c                   |  103 +++++
 arch/arm/mach-socfpga/mmu-arm64_s10.c              |   71 ++++
 arch/arm/mach-socfpga/reset_manager.c              |   11 +
 arch/arm/mach-socfpga/reset_manager_s10.c          |  140 +++++++
 arch/arm/mach-socfpga/spl_a10.c                    |  105 ++++++
 arch/arm/mach-socfpga/{spl.c => spl_gen5.c}        |   57 +---
 arch/arm/mach-socfpga/spl_s10.c                    |  205 ++++++++++
 arch/arm/mach-socfpga/system_manager_s10.c         |   91 +++++
 arch/arm/mach-socfpga/timer.c                      |   17 +-
 arch/arm/mach-socfpga/wrap_pinmux_config_s10.c     |   56 +++
 arch/arm/mach-socfpga/wrap_pll_config_s10.c        |   59 +++
 board/altera/stratix10-socdk/MAINTAINERS           |    7 +
 board/altera/stratix10-socdk/Makefile              |    7 +
 board/altera/stratix10-socdk/socfpga.c             |    7 +
 configs/socfpga_stratix10_defconfig                |   52 +++
 drivers/ddr/altera/Makefile                        |    1 +
 drivers/ddr/altera/sdram_s10.c                     |  392 ++++++++++++++++++++
 include/configs/socfpga_stratix10_socdk.h          |  234 ++++++++++++
 include/dt-bindings/reset/altr,rst-mgr-s10.h       |   96 +++++
 41 files changed, 3979 insertions(+), 128 deletions(-)
 create mode 100644 arch/arm/dts/socfpga_stratix10_socdk.dts
 create mode 100644 arch/arm/mach-socfpga/clock_manager_s10.c
 create mode 100644 arch/arm/mach-socfpga/include/mach/base_addr_s10.h
 create mode 100644 arch/arm/mach-socfpga/include/mach/clock_manager_s10.h
 create mode 100644 arch/arm/mach-socfpga/include/mach/firewall_s10.h
 create mode 100644 arch/arm/mach-socfpga/include/mach/handoff_s10.h
 create mode 100644 arch/arm/mach-socfpga/include/mach/mailbox_s10.h
 create mode 100644 arch/arm/mach-socfpga/include/mach/reset_manager_s10.h
 create mode 100644 arch/arm/mach-socfpga/include/mach/sdram_s10.h
 create mode 100644 arch/arm/mach-socfpga/include/mach/system_manager_s10.h
 create mode 100644 arch/arm/mach-socfpga/mailbox_s10.c
 create mode 100644 arch/arm/mach-socfpga/misc_s10.c
 create mode 100644 arch/arm/mach-socfpga/mmu-arm64_s10.c
 create mode 100644 arch/arm/mach-socfpga/reset_manager_s10.c
 create mode 100644 arch/arm/mach-socfpga/spl_a10.c
 rename arch/arm/mach-socfpga/{spl.c => spl_gen5.c} (82%)
 create mode 100644 arch/arm/mach-socfpga/spl_s10.c
 create mode 100644 arch/arm/mach-socfpga/system_manager_s10.c
 create mode 100644 arch/arm/mach-socfpga/wrap_pinmux_config_s10.c
 create mode 100644 arch/arm/mach-socfpga/wrap_pll_config_s10.c
 create mode 100644 board/altera/stratix10-socdk/MAINTAINERS
 create mode 100644 board/altera/stratix10-socdk/Makefile
 create mode 100644 board/altera/stratix10-socdk/socfpga.c
 create mode 100644 configs/socfpga_stratix10_defconfig
 create mode 100644 drivers/ddr/altera/sdram_s10.c
 create mode 100644 include/configs/socfpga_stratix10_socdk.h
 create mode 100644 include/dt-bindings/reset/altr,rst-mgr-s10.h

[U-Boot] [PATCH v1 01/16] arm: socfpga: stratix10: Add base address map for Statix10 SoC

[Ley Foon Tan]

Add the base address map for Statix10 SoC

Signed-off-by: Chin Liang See <chin.liang.see@intel.com>
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
---
 arch/arm/mach-socfpga/include/mach/base_addr_s10.h |   38 ++++++++++++++++++++
 1 files changed, 38 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/mach-socfpga/include/mach/base_addr_s10.h

diff --git a/arch/arm/mach-socfpga/include/mach/base_addr_s10.h b/arch/arm/mach-socfpga/include/mach/base_addr_s10.h
new file mode 100644
index 0000000..e18d2bf
--- /dev/null
+++ b/arch/arm/mach-socfpga/include/mach/base_addr_s10.h
@@ -0,0 +1,38 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright (C) 2016-2018 Intel Corporation <www.intel.com>
+ *
+ */
+
+#ifndef _SOCFPGA_S10_BASE_HARDWARE_H_
+#define _SOCFPGA_S10_BASE_HARDWARE_H_
+
+#define SOCFPGA_SDR_SCHEDULER_ADDRESS		0xf8000400
+#define SOCFPGA_HMC_MMR_IO48_ADDRESS		0xf8010000
+#define SOCFPGA_SDR_ADDRESS			0xf8011000
+#define SOCFPGA_SMMU_ADDRESS			0xfa000000
+#define SOCFPGA_MAILBOX_ADDRESS			0xffA30000
+#define SOCFPGA_UART0_ADDRESS			0xffc02000
+#define SOCFPGA_UART1_ADDRESS			0xffc02100
+#define SOCFPGA_L4WD0_ADDRESS			0xffd00200
+#define SOCFPGA_L4WD1_ADDRESS			0xffd00300
+#define SOCFPGA_L4WD2_ADDRESS			0xffd00400
+#define SOCFPGA_L4WD3_ADDRESS			0xffd00500
+#define SOCFPGA_GTIMER_SEC_ADDRESS		0xffd01000
+#define SOCFPGA_GTIMER_NSEC_ADDRESS		0xffd02000
+#define SOCFPGA_CLKMGR_ADDRESS			0xffd10000
+#define SOCFPGA_RSTMGR_ADDRESS			0xffd11000
+#define SOCFPGA_SYSMGR_ADDRESS			0xffd12000
+#define SOCFPGA_PINMUX_DEDICATED_IO_ADDRESS	0xffd13000
+#define SOCFPGA_FIREWALL_L4_PER			0xffd21000
+#define SOCFPGA_FIREWALL_L4_SYS			0xffd21100
+#define SOCFPGA_FIREWALL_SOC2FPGA		0xffd21200
+#define SOCFPGA_FIREWALL_LWSOC2FPGA		0xffd21300
+#define SOCFPGA_FIREWALL_TCU			0xffd21400
+#define SOCFPGA_DMANONSECURE_ADDRESS		0xffda0000
+#define SOCFPGA_DMASECURE_ADDRESS		0xffda1000
+#define SOCFPGA_OCRAM_ADDRESS			0xffe00000
+#define GICD_BASE				0xfffc1000
+#define GICC_BASE				0xfffc2000
+
+#endif /* _SOCFPGA_S10_BASE_HARDWARE_H_ */
-- 
1.7.1

[U-Boot] [PATCH v1 02/16] arm: socfpga: stratix10: Add clock manager driver for Stratix10 SoC

[Ley Foon Tan]

Add Clock Manager driver support for Stratix SoC

Signed-off-by: Chin Liang See <chin.liang.see@intel.com>
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
---
 arch/arm/mach-socfpga/Makefile                     |    4 +
 arch/arm/mach-socfpga/clock_manager.c              |    4 +-
 arch/arm/mach-socfpga/clock_manager_s10.c          |  380 ++++++++++++++++++++
 arch/arm/mach-socfpga/include/mach/clock_manager.h |    2 +
 .../mach-socfpga/include/mach/clock_manager_s10.h  |  210 +++++++++++
 arch/arm/mach-socfpga/include/mach/handoff_s10.h   |   32 ++
 arch/arm/mach-socfpga/wrap_pll_config_s10.c        |   59 +++
 7 files changed, 689 insertions(+), 2 deletions(-)
 create mode 100644 arch/arm/mach-socfpga/clock_manager_s10.c
 create mode 100644 arch/arm/mach-socfpga/include/mach/clock_manager_s10.h
 create mode 100644 arch/arm/mach-socfpga/include/mach/handoff_s10.h
 create mode 100644 arch/arm/mach-socfpga/wrap_pll_config_s10.c

diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index 286bfef..e5f9dd7 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -30,6 +30,10 @@ obj-y	+= pinmux_arria10.o
 obj-y	+= reset_manager_arria10.o
 endif
 
+ifdef CONFIG_TARGET_SOCFPGA_STRATIX10
+obj-y	+= clock_manager_s10.o
+obj-y	+= wrap_pll_config_s10.o
+endif
 ifdef CONFIG_SPL_BUILD
 obj-y	+= spl.o
 ifdef CONFIG_TARGET_SOCFPGA_GEN5
diff --git a/arch/arm/mach-socfpga/clock_manager.c b/arch/arm/mach-socfpga/clock_manager.c
index 43e72a8..924b3c7 100644
--- a/arch/arm/mach-socfpga/clock_manager.c
+++ b/arch/arm/mach-socfpga/clock_manager.c
@@ -21,7 +21,7 @@ void cm_wait_for_lock(u32 mask)
 	do {
 #if defined(CONFIG_TARGET_SOCFPGA_GEN5)
 		inter_val = readl(&clock_manager_base->inter) & mask;
-#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+#else
 		inter_val = readl(&clock_manager_base->stat) & mask;
 #endif
 		/* Wait for stable lock */
@@ -52,7 +52,7 @@ int set_cpu_clk_info(void)
 
 #if defined(CONFIG_TARGET_SOCFPGA_GEN5)
 	gd->bd->bi_ddr_freq = cm_get_sdram_clk_hz() / 1000000;
-#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+#else
 	gd->bd->bi_ddr_freq = 0;
 #endif
 
diff --git a/arch/arm/mach-socfpga/clock_manager_s10.c b/arch/arm/mach-socfpga/clock_manager_s10.c
new file mode 100644
index 0000000..3ba2a00
--- /dev/null
+++ b/arch/arm/mach-socfpga/clock_manager_s10.c
@@ -0,0 +1,380 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2016-2018 Intel Corporation <www.intel.com>
+ *
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/clock_manager.h>
+#include <asm/arch/handoff_s10.h>
+#include <asm/arch/system_manager.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static const struct socfpga_clock_manager *clock_manager_base =
+	(struct socfpga_clock_manager *)SOCFPGA_CLKMGR_ADDRESS;
+static const struct socfpga_system_manager *sysmgr_regs =
+		(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
+
+/*
+ * function to write the bypass register which requires a poll of the
+ * busy bit
+ */
+static void cm_write_bypass_mainpll(u32 val)
+{
+	writel(val, &clock_manager_base->main_pll.bypass);
+	cm_wait_for_fsm();
+}
+
+static void cm_write_bypass_perpll(u32 val)
+{
+	writel(val, &clock_manager_base->per_pll.bypass);
+	cm_wait_for_fsm();
+}
+
+/* function to write the ctrl register which requires a poll of the busy bit */
+static void cm_write_ctrl(u32 val)
+{
+	writel(val, &clock_manager_base->ctrl);
+	cm_wait_for_fsm();
+}
+
+/*
+ * Setup clocks while making no assumptions about previous state of the clocks.
+ */
+void cm_basic_init(const struct cm_config * const cfg)
+{
+	u32 mdiv, refclkdiv, mscnt, hscnt, vcocalib;
+
+	if (cfg == 0)
+		return;
+
+	/* Put all plls in bypass */
+	cm_write_bypass_mainpll(CLKMGR_BYPASS_MAINPLL_ALL);
+	cm_write_bypass_perpll(CLKMGR_BYPASS_PERPLL_ALL);
+
+	/* setup main PLL dividers where calculate the vcocalib value */
+	mdiv = (cfg->main_pll_fdbck >> CLKMGR_FDBCK_MDIV_OFFSET) &
+		CLKMGR_FDBCK_MDIV_MASK;
+	refclkdiv = (cfg->main_pll_pllglob >> CLKMGR_PLLGLOB_REFCLKDIV_OFFSET) &
+		     CLKMGR_PLLGLOB_REFCLKDIV_MASK;
+	mscnt = CLKMGR_MSCNT_CONST / (CLKMGR_MDIV_CONST + mdiv) / refclkdiv;
+	hscnt = (mdiv + CLKMGR_MDIV_CONST) * mscnt / refclkdiv -
+		CLKMGR_HSCNT_CONST;
+	vcocalib = (hscnt & CLKMGR_VCOCALIB_HSCNT_MASK) |
+		   ((mscnt & CLKMGR_VCOCALIB_MSCNT_MASK) <<
+		   CLKMGR_VCOCALIB_MSCNT_OFFSET);
+
+	writel((cfg->main_pll_pllglob & ~CLKMGR_PLLGLOB_PD_MASK &
+		~CLKMGR_PLLGLOB_RST_MASK),
+		&clock_manager_base->main_pll.pllglob);
+	writel(cfg->main_pll_fdbck, &clock_manager_base->main_pll.fdbck);
+	writel(vcocalib, &clock_manager_base->main_pll.vcocalib);
+	writel(cfg->main_pll_pllc0, &clock_manager_base->main_pll.pllc0);
+	writel(cfg->main_pll_pllc1, &clock_manager_base->main_pll.pllc1);
+	writel(cfg->main_pll_nocdiv, &clock_manager_base->main_pll.nocdiv);
+
+	/* setup peripheral PLL dividers */
+	/* calculate the vcocalib value */
+	mdiv = (cfg->per_pll_fdbck >> CLKMGR_FDBCK_MDIV_OFFSET) &
+		CLKMGR_FDBCK_MDIV_MASK;
+	refclkdiv = (cfg->per_pll_pllglob >> CLKMGR_PLLGLOB_REFCLKDIV_OFFSET) &
+		     CLKMGR_PLLGLOB_REFCLKDIV_MASK;
+	mscnt = CLKMGR_MSCNT_CONST / (CLKMGR_MDIV_CONST + mdiv) / refclkdiv;
+	hscnt = (mdiv + CLKMGR_MDIV_CONST) * mscnt / refclkdiv -
+		CLKMGR_HSCNT_CONST;
+	vcocalib = (hscnt & CLKMGR_VCOCALIB_HSCNT_MASK) |
+		   ((mscnt & CLKMGR_VCOCALIB_MSCNT_MASK) <<
+		   CLKMGR_VCOCALIB_MSCNT_OFFSET);
+
+	writel((cfg->per_pll_pllglob & ~CLKMGR_PLLGLOB_PD_MASK &
+		~CLKMGR_PLLGLOB_RST_MASK),
+		&clock_manager_base->per_pll.pllglob);
+	writel(cfg->per_pll_fdbck, &clock_manager_base->per_pll.fdbck);
+	writel(vcocalib, &clock_manager_base->per_pll.vcocalib);
+	writel(cfg->per_pll_pllc0, &clock_manager_base->per_pll.pllc0);
+	writel(cfg->per_pll_pllc1, &clock_manager_base->per_pll.pllc1);
+	writel(cfg->per_pll_emacctl, &clock_manager_base->per_pll.emacctl);
+	writel(cfg->per_pll_gpiodiv, &clock_manager_base->per_pll.gpiodiv);
+
+	/* Take both PLL out of reset and power up */
+	setbits_le32(&clock_manager_base->main_pll.pllglob,
+		     CLKMGR_PLLGLOB_PD_MASK | CLKMGR_PLLGLOB_RST_MASK);
+	setbits_le32(&clock_manager_base->per_pll.pllglob,
+		     CLKMGR_PLLGLOB_PD_MASK | CLKMGR_PLLGLOB_RST_MASK);
+
+#define LOCKED_MASK \
+	(CLKMGR_STAT_MAINPLL_LOCKED | \
+	CLKMGR_STAT_PERPLL_LOCKED)
+
+	cm_wait_for_lock(LOCKED_MASK);
+
+	/*
+	 * Dividers for C2 to C9 only init after PLLs are lock. As dividers
+	 * only take effect upon value change, we shall set a maximum value as
+	 * default value.
+	 */
+	writel(0xff, &clock_manager_base->main_pll.mpuclk);
+	writel(0xff, &clock_manager_base->main_pll.nocclk);
+	writel(0xff, &clock_manager_base->main_pll.cntr2clk);
+	writel(0xff, &clock_manager_base->main_pll.cntr3clk);
+	writel(0xff, &clock_manager_base->main_pll.cntr4clk);
+	writel(0xff, &clock_manager_base->main_pll.cntr5clk);
+	writel(0xff, &clock_manager_base->main_pll.cntr6clk);
+	writel(0xff, &clock_manager_base->main_pll.cntr7clk);
+	writel(0xff, &clock_manager_base->main_pll.cntr8clk);
+	writel(0xff, &clock_manager_base->main_pll.cntr9clk);
+	writel(0xff, &clock_manager_base->per_pll.cntr2clk);
+	writel(0xff, &clock_manager_base->per_pll.cntr3clk);
+	writel(0xff, &clock_manager_base->per_pll.cntr4clk);
+	writel(0xff, &clock_manager_base->per_pll.cntr5clk);
+	writel(0xff, &clock_manager_base->per_pll.cntr6clk);
+	writel(0xff, &clock_manager_base->per_pll.cntr7clk);
+	writel(0xff, &clock_manager_base->per_pll.cntr8clk);
+	writel(0xff, &clock_manager_base->per_pll.cntr9clk);
+
+	writel(cfg->main_pll_mpuclk, &clock_manager_base->main_pll.mpuclk);
+	writel(cfg->main_pll_nocclk, &clock_manager_base->main_pll.nocclk);
+	writel(cfg->main_pll_cntr2clk, &clock_manager_base->main_pll.cntr2clk);
+	writel(cfg->main_pll_cntr3clk, &clock_manager_base->main_pll.cntr3clk);
+	writel(cfg->main_pll_cntr4clk, &clock_manager_base->main_pll.cntr4clk);
+	writel(cfg->main_pll_cntr5clk, &clock_manager_base->main_pll.cntr5clk);
+	writel(cfg->main_pll_cntr6clk, &clock_manager_base->main_pll.cntr6clk);
+	writel(cfg->main_pll_cntr7clk, &clock_manager_base->main_pll.cntr7clk);
+	writel(cfg->main_pll_cntr8clk, &clock_manager_base->main_pll.cntr8clk);
+	writel(cfg->main_pll_cntr9clk, &clock_manager_base->main_pll.cntr9clk);
+	writel(cfg->per_pll_cntr2clk, &clock_manager_base->per_pll.cntr2clk);
+	writel(cfg->per_pll_cntr3clk, &clock_manager_base->per_pll.cntr3clk);
+	writel(cfg->per_pll_cntr4clk, &clock_manager_base->per_pll.cntr4clk);
+	writel(cfg->per_pll_cntr5clk, &clock_manager_base->per_pll.cntr5clk);
+	writel(cfg->per_pll_cntr6clk, &clock_manager_base->per_pll.cntr6clk);
+	writel(cfg->per_pll_cntr7clk, &clock_manager_base->per_pll.cntr7clk);
+	writel(cfg->per_pll_cntr8clk, &clock_manager_base->per_pll.cntr8clk);
+	writel(cfg->per_pll_cntr9clk, &clock_manager_base->per_pll.cntr9clk);
+
+	/* Take all PLLs out of bypass */
+	cm_write_bypass_mainpll(0);
+	cm_write_bypass_perpll(0);
+
+	/* clear safe mode / out of boot mode */
+	cm_write_ctrl(readl(&clock_manager_base->ctrl)
+			& ~(CLKMGR_CTRL_SAFEMODE));
+
+	/* Now ungate non-hw-managed clocks */
+	writel(~0, &clock_manager_base->main_pll.en);
+	writel(~0, &clock_manager_base->per_pll.en);
+
+	/* Clear the loss of lock bits (write 1 to clear) */
+	writel(CLKMGR_INTER_PERPLLLOST_MASK | CLKMGR_INTER_MAINPLLLOST_MASK,
+	       &clock_manager_base->intrclr);
+}
+
+static unsigned long cm_get_main_vco_clk_hz(void)
+{
+	 unsigned long fref, refdiv, mdiv, reg, vco;
+
+	reg = readl(&clock_manager_base->main_pll.pllglob);
+
+	fref = (reg >> CLKMGR_PLLGLOB_VCO_PSRC_OFFSET) &
+		CLKMGR_PLLGLOB_VCO_PSRC_MASK;
+	switch (fref) {
+	case CLKMGR_VCO_PSRC_EOSC1:
+		fref = cm_get_osc_clk_hz();
+		break;
+	case CLKMGR_VCO_PSRC_INTOSC:
+		fref = cm_get_intosc_clk_hz();
+		break;
+	case CLKMGR_VCO_PSRC_F2S:
+		fref = cm_get_fpga_clk_hz();
+		break;
+	}
+
+	refdiv = (reg >> CLKMGR_PLLGLOB_REFCLKDIV_OFFSET) &
+		  CLKMGR_PLLGLOB_REFCLKDIV_MASK;
+
+	reg = readl(&clock_manager_base->main_pll.fdbck);
+	mdiv = (reg >> CLKMGR_FDBCK_MDIV_OFFSET) & CLKMGR_FDBCK_MDIV_MASK;
+
+	vco = fref / refdiv;
+	vco = vco * (CLKMGR_MDIV_CONST + mdiv);
+	return vco;
+}
+
+static unsigned long cm_get_per_vco_clk_hz(void)
+{
+	unsigned long fref, refdiv, mdiv, reg, vco;
+
+	reg = readl(&clock_manager_base->per_pll.pllglob);
+
+	fref = (reg >> CLKMGR_PLLGLOB_VCO_PSRC_OFFSET) &
+		CLKMGR_PLLGLOB_VCO_PSRC_MASK;
+	switch (fref) {
+	case CLKMGR_VCO_PSRC_EOSC1:
+		fref = cm_get_osc_clk_hz();
+		break;
+	case CLKMGR_VCO_PSRC_INTOSC:
+		fref = cm_get_intosc_clk_hz();
+		break;
+	case CLKMGR_VCO_PSRC_F2S:
+		fref = cm_get_fpga_clk_hz();
+		break;
+	}
+
+	refdiv = (reg >> CLKMGR_PLLGLOB_REFCLKDIV_OFFSET) &
+		  CLKMGR_PLLGLOB_REFCLKDIV_MASK;
+
+	reg = readl(&clock_manager_base->per_pll.fdbck);
+	mdiv = (reg >> CLKMGR_FDBCK_MDIV_OFFSET) & CLKMGR_FDBCK_MDIV_MASK;
+
+	vco = fref / refdiv;
+	vco = vco * (CLKMGR_MDIV_CONST + mdiv);
+	return vco;
+}
+
+unsigned long cm_get_mpu_clk_hz(void)
+{
+	unsigned long clock = readl(&clock_manager_base->main_pll.mpuclk);
+
+	clock = (clock >> CLKMGR_CLKSRC_OFFSET) & CLKMGR_CLKSRC_MASK;
+
+	switch (clock) {
+	case CLKMGR_CLKSRC_MAIN:
+		clock = cm_get_main_vco_clk_hz();
+		clock /= (readl(&clock_manager_base->main_pll.pllc0) &
+			  CLKMGR_PLLC0_DIV_MASK);
+		break;
+
+	case CLKMGR_CLKSRC_PER:
+		clock = cm_get_per_vco_clk_hz();
+		clock /= (readl(&clock_manager_base->per_pll.pllc0) &
+			  CLKMGR_CLKCNT_MSK);
+		break;
+
+	case CLKMGR_CLKSRC_OSC1:
+		clock = cm_get_osc_clk_hz();
+		break;
+
+	case CLKMGR_CLKSRC_INTOSC:
+		clock = cm_get_intosc_clk_hz();
+		break;
+
+	case CLKMGR_CLKSRC_FPGA:
+		clock = cm_get_fpga_clk_hz();
+		break;
+	}
+
+	clock /= 1 + (readl(&clock_manager_base->main_pll.mpuclk) &
+		CLKMGR_CLKCNT_MSK);
+	return clock;
+}
+
+unsigned int cm_get_l3_main_clk_hz(void)
+{
+	u32 clock = readl(&clock_manager_base->main_pll.nocclk);
+
+	clock = (clock >> CLKMGR_CLKSRC_OFFSET) & CLKMGR_CLKSRC_MASK;
+
+	switch (clock) {
+	case CLKMGR_CLKSRC_MAIN:
+		clock = cm_get_main_vco_clk_hz();
+		clock /= (readl(&clock_manager_base->main_pll.pllc1) &
+			  CLKMGR_PLLC0_DIV_MASK);
+		break;
+
+	case CLKMGR_CLKSRC_PER:
+		clock = cm_get_per_vco_clk_hz();
+		clock /= (readl(&clock_manager_base->per_pll.pllc1) &
+			  CLKMGR_CLKCNT_MSK);
+		break;
+
+	case CLKMGR_CLKSRC_OSC1:
+		clock = cm_get_osc_clk_hz();
+		break;
+
+	case CLKMGR_CLKSRC_INTOSC:
+		clock = cm_get_intosc_clk_hz();
+		break;
+
+	case CLKMGR_CLKSRC_FPGA:
+		clock = cm_get_fpga_clk_hz();
+		break;
+	}
+
+	clock /= 1 + (readl(&clock_manager_base->main_pll.nocclk) &
+		CLKMGR_CLKCNT_MSK);
+	return clock;
+}
+
+unsigned int cm_get_mmc_controller_clk_hz(void)
+{
+	u32 clock = readl(&clock_manager_base->per_pll.cntr6clk);
+
+	clock = (clock >> CLKMGR_CLKSRC_OFFSET) & CLKMGR_CLKSRC_MASK;
+
+	switch (clock) {
+	case CLKMGR_CLKSRC_MAIN:
+		clock = cm_get_l3_main_clk_hz();
+		clock /= 1 + (readl(&clock_manager_base->main_pll.cntr6clk) &
+			CLKMGR_CLKCNT_MSK);
+		break;
+
+	case CLKMGR_CLKSRC_PER:
+		clock = cm_get_l3_main_clk_hz();
+		clock /= 1 + (readl(&clock_manager_base->per_pll.cntr6clk) &
+			CLKMGR_CLKCNT_MSK);
+		break;
+
+	case CLKMGR_CLKSRC_OSC1:
+		clock = cm_get_osc_clk_hz();
+		break;
+
+	case CLKMGR_CLKSRC_INTOSC:
+		clock = cm_get_intosc_clk_hz();
+		break;
+
+	case CLKMGR_CLKSRC_FPGA:
+		clock = cm_get_fpga_clk_hz();
+		break;
+	}
+	return clock / 4;
+}
+
+unsigned int cm_get_l4_sp_clk_hz(void)
+{
+	u32 clock = cm_get_l3_main_clk_hz();
+
+	clock /= (1 << ((readl(&clock_manager_base->main_pll.nocdiv) >>
+		  CLKMGR_NOCDIV_L4SPCLK_OFFSET) & CLKMGR_CLKCNT_MSK));
+	return clock;
+}
+
+unsigned int cm_get_qspi_controller_clk_hz(void)
+{
+	return readl(&sysmgr_regs->boot_scratch_cold0);
+}
+
+unsigned int cm_get_spi_controller_clk_hz(void)
+{
+	u32 clock = cm_get_l3_main_clk_hz();
+
+	clock /= (1 << ((readl(&clock_manager_base->main_pll.nocdiv) >>
+		  CLKMGR_NOCDIV_L4MAIN_OFFSET) & CLKMGR_CLKCNT_MSK));
+	return clock;
+}
+
+unsigned int cm_get_l4_sys_free_clk_hz(void)
+{
+	return cm_get_l3_main_clk_hz() / 4;
+}
+
+void cm_print_clock_quick_summary(void)
+{
+	printf("MPU         %d kHz\n", (u32)(cm_get_mpu_clk_hz() / 1000));
+	printf("L3 main     %d kHz\n", cm_get_l3_main_clk_hz() / 1000);
+	printf("Main VCO    %d kHz\n", (u32)(cm_get_main_vco_clk_hz() / 1000));
+	printf("Per VCO     %d kHz\n", (u32)(cm_get_per_vco_clk_hz() / 1000));
+	printf("EOSC1       %d kHz\n", cm_get_osc_clk_hz() / 1000);
+	printf("HPS MMC     %d kHz\n", cm_get_mmc_controller_clk_hz() / 1000);
+	printf("UART        %d kHz\n", cm_get_l4_sp_clk_hz() / 1000);
+}
diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager.h b/arch/arm/mach-socfpga/include/mach/clock_manager.h
index 4c6b1f8..ddf814f 100644
--- a/arch/arm/mach-socfpga/include/mach/clock_manager.h
+++ b/arch/arm/mach-socfpga/include/mach/clock_manager.h
@@ -17,6 +17,8 @@ void cm_print_clock_quick_summary(void);
 #include <asm/arch/clock_manager_gen5.h>
 #elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
 #include <asm/arch/clock_manager_arria10.h>
+#elif defined(CONFIG_TARGET_SOCFPGA_STRATIX10)
+#include <asm/arch/clock_manager_s10.h>
 #endif
 
 #endif /* _CLOCK_MANAGER_H_ */
diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h b/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h
new file mode 100644
index 0000000..24b20de
--- /dev/null
+++ b/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h
@@ -0,0 +1,210 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright (C) 2016-2018 Intel Corporation <www.intel.com>
+ *
+ */
+
+#ifndef	_CLOCK_MANAGER_S10_
+#define	_CLOCK_MANAGER_S10_
+
+/* Clock speed accessors */
+unsigned long cm_get_mpu_clk_hz(void);
+unsigned long cm_get_sdram_clk_hz(void);
+unsigned int cm_get_l4_sp_clk_hz(void);
+unsigned int cm_get_mmc_controller_clk_hz(void);
+unsigned int cm_get_qspi_controller_clk_hz(void);
+unsigned int cm_get_spi_controller_clk_hz(void);
+const unsigned int cm_get_osc_clk_hz(void);
+const unsigned int cm_get_f2s_per_ref_clk_hz(void);
+const unsigned int cm_get_f2s_sdr_ref_clk_hz(void);
+const unsigned int cm_get_intosc_clk_hz(void);
+const unsigned int cm_get_fpga_clk_hz(void);
+
+#define CLKMGR_EOSC1_HZ		25000000
+#define CLKMGR_INTOSC_HZ	460000000
+#define CLKMGR_FPGA_CLK_HZ	50000000
+
+/* Clock configuration accessors */
+const struct cm_config * const cm_get_default_config(void);
+
+struct cm_config {
+	/* main group */
+	u32 main_pll_mpuclk;
+	u32 main_pll_nocclk;
+	u32 main_pll_cntr2clk;
+	u32 main_pll_cntr3clk;
+	u32 main_pll_cntr4clk;
+	u32 main_pll_cntr5clk;
+	u32 main_pll_cntr6clk;
+	u32 main_pll_cntr7clk;
+	u32 main_pll_cntr8clk;
+	u32 main_pll_cntr9clk;
+	u32 main_pll_nocdiv;
+	u32 main_pll_pllglob;
+	u32 main_pll_fdbck;
+	u32 main_pll_pllc0;
+	u32 main_pll_pllc1;
+	u32 spare;
+
+	/* peripheral group */
+	u32 per_pll_cntr2clk;
+	u32 per_pll_cntr3clk;
+	u32 per_pll_cntr4clk;
+	u32 per_pll_cntr5clk;
+	u32 per_pll_cntr6clk;
+	u32 per_pll_cntr7clk;
+	u32 per_pll_cntr8clk;
+	u32 per_pll_cntr9clk;
+	u32 per_pll_emacctl;
+	u32 per_pll_gpiodiv;
+	u32 per_pll_pllglob;
+	u32 per_pll_fdbck;
+	u32 per_pll_pllc0;
+	u32 per_pll_pllc1;
+
+	/* incoming clock */
+	u32 hps_osc_clk_hz;
+	u32 fpga_clk_hz;
+};
+
+void cm_basic_init(const struct cm_config * const cfg);
+
+struct socfpga_clock_manager_main_pll {
+	u32	en;
+	u32	ens;
+	u32	enr;
+	u32	bypass;
+	u32	bypasss;
+	u32	bypassr;
+	u32	mpuclk;
+	u32	nocclk;
+	u32	cntr2clk;
+	u32	cntr3clk;
+	u32	cntr4clk;
+	u32	cntr5clk;
+	u32	cntr6clk;
+	u32	cntr7clk;
+	u32	cntr8clk;
+	u32	cntr9clk;
+	u32	nocdiv;
+	u32	pllglob;
+	u32	fdbck;
+	u32	mem;
+	u32	memstat;
+	u32	pllc0;
+	u32	pllc1;
+	u32	vcocalib;
+	u32	_pad_0x90_0xA0[5];
+};
+
+struct socfpga_clock_manager_per_pll {
+	u32	en;
+	u32	ens;
+	u32	enr;
+	u32	bypass;
+	u32	bypasss;
+	u32	bypassr;
+	u32	cntr2clk;
+	u32	cntr3clk;
+	u32	cntr4clk;
+	u32	cntr5clk;
+	u32	cntr6clk;
+	u32	cntr7clk;
+	u32	cntr8clk;
+	u32	cntr9clk;
+	u32	emacctl;
+	u32	gpiodiv;
+	u32	pllglob;
+	u32	fdbck;
+	u32	mem;
+	u32	memstat;
+	u32	pllc0;
+	u32	pllc1;
+	u32	vcocalib;
+	u32	_pad_0x100_0x124[10];
+};
+
+struct socfpga_clock_manager {
+	u32	ctrl;
+	u32	stat;
+	u32	testioctrl;
+	u32	intrgen;
+	u32	intrmsk;
+	u32	intrclr;
+	u32	intrsts;
+	u32	intrstk;
+	u32	intrraw;
+	u32	_pad_0x24_0x2c[3];
+	struct socfpga_clock_manager_main_pll main_pll;
+	struct socfpga_clock_manager_per_pll per_pll;
+};
+
+#define CLKMGR_CTRL_SAFEMODE				BIT(0)
+#define CLKMGR_BYPASS_MAINPLL_ALL			0x00000007
+#define CLKMGR_BYPASS_PERPLL_ALL			0x0000007f
+
+#define CLKMGR_INTER_MAINPLLLOCKED_MASK			0x00000001
+#define CLKMGR_INTER_PERPLLLOCKED_MASK			0x00000002
+#define CLKMGR_INTER_MAINPLLLOST_MASK			0x00000004
+#define CLKMGR_INTER_PERPLLLOST_MASK			0x00000008
+#define CLKMGR_STAT_BUSY				BIT(0)
+#define CLKMGR_STAT_MAINPLL_LOCKED			BIT(8)
+#define CLKMGR_STAT_PERPLL_LOCKED			BIT(9)
+
+#define CLKMGR_PLLGLOB_PD_MASK				0x00000001
+#define CLKMGR_PLLGLOB_RST_MASK				0x00000002
+#define CLKMGR_PLLGLOB_VCO_PSRC_MASK			0X3
+#define CLKMGR_PLLGLOB_VCO_PSRC_OFFSET			16
+#define CLKMGR_VCO_PSRC_EOSC1				0
+#define CLKMGR_VCO_PSRC_INTOSC				1
+#define CLKMGR_VCO_PSRC_F2S				2
+#define CLKMGR_PLLGLOB_REFCLKDIV_MASK			0X3f
+#define CLKMGR_PLLGLOB_REFCLKDIV_OFFSET			8
+
+#define CLKMGR_CLKSRC_MASK				0x7
+#define CLKMGR_CLKSRC_OFFSET				16
+#define CLKMGR_CLKSRC_MAIN				0
+#define CLKMGR_CLKSRC_PER				1
+#define CLKMGR_CLKSRC_OSC1				2
+#define CLKMGR_CLKSRC_INTOSC				3
+#define CLKMGR_CLKSRC_FPGA				4
+#define CLKMGR_CLKCNT_MSK				0x7ff
+
+#define CLKMGR_FDBCK_MDIV_MASK				0xff
+#define CLKMGR_FDBCK_MDIV_OFFSET			24
+
+#define CLKMGR_PLLC0_DIV_MASK				0xff
+#define CLKMGR_PLLC1_DIV_MASK				0xff
+#define CLKMGR_PLLC0_EN_OFFSET				27
+#define CLKMGR_PLLC1_EN_OFFSET				24
+
+#define CLKMGR_NOCDIV_L4MAIN_OFFSET			0
+#define CLKMGR_NOCDIV_L4MPCLK_OFFSET			8
+#define CLKMGR_NOCDIV_L4SPCLK_OFFSET			16
+#define CLKMGR_NOCDIV_CSATCLK_OFFSET			24
+#define CLKMGR_NOCDIV_CSTRACECLK_OFFSET			26
+#define CLKMGR_NOCDIV_CSPDBGCLK_OFFSET			28
+
+#define CLKMGR_NOCDIV_L4SPCLK_MASK			0X3
+#define CLKMGR_NOCDIV_DIV1				0
+#define CLKMGR_NOCDIV_DIV2				1
+#define CLKMGR_NOCDIV_DIV4				2
+#define CLKMGR_NOCDIV_DIV8				3
+#define CLKMGR_CSPDBGCLK_DIV1				0
+#define CLKMGR_CSPDBGCLK_DIV4				1
+
+#define CLKMGR_MSCNT_CONST				200
+#define CLKMGR_MDIV_CONST				6
+#define CLKMGR_HSCNT_CONST				9
+
+#define CLKMGR_VCOCALIB_MSCNT_MASK			0xff
+#define CLKMGR_VCOCALIB_MSCNT_OFFSET			9
+#define CLKMGR_VCOCALIB_HSCNT_MASK			0xff
+
+#define CLKMGR_EMACCTL_EMAC0SEL_OFFSET			26
+#define CLKMGR_EMACCTL_EMAC1SEL_OFFSET			27
+#define CLKMGR_EMACCTL_EMAC2SEL_OFFSET			28
+
+#define CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK		0x00000020
+
+#endif /* _CLOCK_MANAGER_S10_ */
diff --git a/arch/arm/mach-socfpga/include/mach/handoff_s10.h b/arch/arm/mach-socfpga/include/mach/handoff_s10.h
new file mode 100644
index 0000000..c32b431
--- /dev/null
+++ b/arch/arm/mach-socfpga/include/mach/handoff_s10.h
@@ -0,0 +1,32 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright (C) 2016-2018 Intel Corporation <www.intel.com>
+ *
+ */
+
+#ifndef _HANDOFF_S10_H_
+#define _HANDOFF_S10_H_
+
+/*
+ * Offset for HW handoff from Quartus tools
+ */
+#define CONFIG_HANDOFF_BASE		0xFFE3F000
+#define CONFIG_HANDOFF_MUX		(CONFIG_HANDOFF_BASE + 0x10)
+#define CONFIG_HANDOFF_IOCTL		(CONFIG_HANDOFF_BASE + 0x1A0)
+#define CONFIG_HANDOFF_FPGA		(CONFIG_HANDOFF_BASE + 0x330)
+#define CONFIG_HANODFF_DELAY		(CONFIG_HANDOFF_BASE + 0x3F0)
+#define CONFIG_HANDOFF_CLOCK		(CONFIG_HANDOFF_BASE + 0x580)
+#define CONFIG_HANDOFF_MISC		(CONFIG_HANDOFF_BASE + 0x610)
+#define CONFIG_HANDOFF_MAGIC_MUX	0x504D5558
+#define CONFIG_HANDOFF_MAGIC_IOCTL	0x494F4354
+#define CONFIG_HANDOFF_MAGIC_FPGA	0x46504741
+#define CONFIG_HANDOFF_MAGIC_DELAY	0x444C4159
+#define CONFIG_HANDOFF_MAGIC_CLOCK	0x434C4B53
+#define CONFIG_HANDOFF_MAGIC_MISC	0x4D495343
+#define CONFIG_HANDOFF_OFFSET_LENGTH	0x4
+#define CONFIG_HANDOFF_OFFSET_DATA	0x10
+
+#define CONFIG_HANDOFF_CLOCK_OSC	(CONFIG_HANDOFF_BASE + 0x608)
+#define CONFIG_HANDOFF_CLOCK_FPGA	(CONFIG_HANDOFF_BASE + 0x60C)
+
+#endif /* _HANDOFF_S10_H_ */
diff --git a/arch/arm/mach-socfpga/wrap_pll_config_s10.c b/arch/arm/mach-socfpga/wrap_pll_config_s10.c
new file mode 100644
index 0000000..c68b239
--- /dev/null
+++ b/arch/arm/mach-socfpga/wrap_pll_config_s10.c
@@ -0,0 +1,59 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2016-2018 Intel Corporation <www.intel.com>
+ *
+ */
+
+#include <common.h>
+#include <asm/arch/clock_manager.h>
+#include <asm/io.h>
+#include <asm/arch/handoff_s10.h>
+#include <asm/arch/system_manager.h>
+
+static const struct socfpga_system_manager *sysmgr_regs =
+	(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
+
+const struct cm_config * const cm_get_default_config(void)
+{
+	struct cm_config *cm_handoff_cfg = (struct cm_config *)
+		(CONFIG_HANDOFF_CLOCK + CONFIG_HANDOFF_OFFSET_DATA);
+	u32 *conversion = (u32 *)cm_handoff_cfg;
+	u32 i;
+	u32 handoff_clk = readl(CONFIG_HANDOFF_CLOCK);
+
+	if (swab32(handoff_clk) == CONFIG_HANDOFF_MAGIC_CLOCK) {
+		writel(swab32(handoff_clk), CONFIG_HANDOFF_CLOCK);
+		for (i = 0; i < (sizeof(*cm_handoff_cfg) / sizeof(u32)); i++)
+			conversion[i] = swab32(conversion[i]);
+		return cm_handoff_cfg;
+	} else if (handoff_clk == CONFIG_HANDOFF_MAGIC_CLOCK) {
+		return cm_handoff_cfg;
+	}
+
+	return NULL;
+}
+
+const unsigned int cm_get_osc_clk_hz(void)
+{
+#ifdef CONFIG_SPL_BUILD
+	u32 clock = readl(CONFIG_HANDOFF_CLOCK_OSC);
+
+	writel(clock, &sysmgr_regs->boot_scratch_cold1);
+#endif
+	return readl(&sysmgr_regs->boot_scratch_cold1);
+}
+
+const unsigned int cm_get_intosc_clk_hz(void)
+{
+	return CLKMGR_INTOSC_HZ;
+}
+
+const unsigned int cm_get_fpga_clk_hz(void)
+{
+#ifdef CONFIG_SPL_BUILD
+	u32 clock = readl(CONFIG_HANDOFF_CLOCK_FPGA);
+
+	writel(clock, &sysmgr_regs->boot_scratch_cold2);
+#endif
+	return readl(&sysmgr_regs->boot_scratch_cold2);
+}
-- 
1.7.1

[U-Boot] [PATCH v1 03/16] arm: socfpga: stratix10: Add reset manager driver for Stratix10 SoC

[Ley Foon Tan]

Add Reset Manager driver support for Stratix SoC

Signed-off-by: Chin Liang See <chin.liang.see@intel.com>
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
---
 arch/arm/mach-socfpga/Makefile                     |    1 +
 arch/arm/mach-socfpga/include/mach/reset_manager.h |    2 +
 .../mach-socfpga/include/mach/reset_manager_s10.h  |  116 ++++++++++++++++
 arch/arm/mach-socfpga/reset_manager.c              |   11 ++
 arch/arm/mach-socfpga/reset_manager_s10.c          |  140 ++++++++++++++++++++
 include/dt-bindings/reset/altr,rst-mgr-s10.h       |   96 +++++++++++++
 6 files changed, 366 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/mach-socfpga/include/mach/reset_manager_s10.h
 create mode 100644 arch/arm/mach-socfpga/reset_manager_s10.c
 create mode 100644 include/dt-bindings/reset/altr,rst-mgr-s10.h

diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index e5f9dd7..f10b05c 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -32,6 +32,7 @@ endif
 
 ifdef CONFIG_TARGET_SOCFPGA_STRATIX10
 obj-y	+= clock_manager_s10.o
+obj-y	+= reset_manager_s10.o
 obj-y	+= wrap_pll_config_s10.o
 endif
 ifdef CONFIG_SPL_BUILD
diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager.h b/arch/arm/mach-socfpga/include/mach/reset_manager.h
index 6591745..577fcce 100644
--- a/arch/arm/mach-socfpga/include/mach/reset_manager.h
+++ b/arch/arm/mach-socfpga/include/mach/reset_manager.h
@@ -45,6 +45,8 @@ void socfpga_per_reset_all(void);
 #include <asm/arch/reset_manager_gen5.h>
 #elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
 #include <asm/arch/reset_manager_arria10.h>
+#elif defined(CONFIG_TARGET_SOCFPGA_STRATIX10)
+#include <asm/arch/reset_manager_s10.h>
 #endif
 
 #endif /* _RESET_MANAGER_H_ */
diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager_s10.h b/arch/arm/mach-socfpga/include/mach/reset_manager_s10.h
new file mode 100644
index 0000000..6182d5f
--- /dev/null
+++ b/arch/arm/mach-socfpga/include/mach/reset_manager_s10.h
@@ -0,0 +1,116 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright (C) 2016-2018 Intel Corporation <www.intel.com>
+ *
+ */
+
+#ifndef	_RESET_MANAGER_S10_
+#define	_RESET_MANAGER_S10_
+
+void reset_cpu(ulong addr);
+void reset_deassert_peripherals_handoff(void);
+
+void socfpga_bridges_reset(int enable);
+
+void socfpga_per_reset(u32 reset, int set);
+void socfpga_per_reset_all(void);
+
+struct socfpga_reset_manager {
+	u32	status;
+	u32	mpu_rst_stat;
+	u32	misc_stat;
+	u32	padding1;
+	u32	hdsk_en;
+	u32	hdsk_req;
+	u32	hdsk_ack;
+	u32	hdsk_stall;
+	u32	mpumodrst;
+	u32	per0modrst;
+	u32	per1modrst;
+	u32	brgmodrst;
+	u32	padding2;
+	u32     cold_mod_reset;
+	u32	padding3;
+	u32     dbg_mod_reset;
+	u32     tap_mod_reset;
+	u32	padding4;
+	u32	padding5;
+	u32     brg_warm_mask;
+	u32	padding6[3];
+	u32     tst_stat;
+	u32	padding7;
+	u32     hdsk_timeout;
+	u32     mpul2flushtimeout;
+	u32     dbghdsktimeout;
+};
+
+#define RSTMGR_MPUMODRST_CORE0		0
+#define RSTMGR_PER0MODRST_OCP_MASK	0x0020bf00
+#define RSTMGR_BRGMODRST_DDRSCH_MASK	0X00000040
+
+/*
+ * Define a reset identifier, from which a permodrst bank ID
+ * and reset ID can be extracted using the subsequent macros
+ * RSTMGR_RESET() and RSTMGR_BANK().
+ */
+#define RSTMGR_BANK_OFFSET	8
+#define RSTMGR_BANK_MASK	0x7
+#define RSTMGR_RESET_OFFSET	0
+#define RSTMGR_RESET_MASK	0x1f
+#define RSTMGR_DEFINE(_bank, _offset)		\
+	((_bank) << RSTMGR_BANK_OFFSET) | ((_offset) << RSTMGR_RESET_OFFSET)
+
+/* Extract reset ID from the reset identifier. */
+#define RSTMGR_RESET(_reset)			\
+	(((_reset) >> RSTMGR_RESET_OFFSET) & RSTMGR_RESET_MASK)
+
+/* Extract bank ID from the reset identifier. */
+#define RSTMGR_BANK(_reset)			\
+	(((_reset) >> RSTMGR_BANK_OFFSET) & RSTMGR_BANK_MASK)
+
+/*
+ * SocFPGA Stratix10 reset IDs, bank mapping is as follows:
+ * 0 ... mpumodrst
+ * 1 ... per0modrst
+ * 2 ... per1modrst
+ * 3 ... brgmodrst
+ */
+#define RSTMGR_EMAC0		RSTMGR_DEFINE(1, 0)
+#define RSTMGR_EMAC1		RSTMGR_DEFINE(1, 1)
+#define RSTMGR_EMAC2		RSTMGR_DEFINE(1, 2)
+#define RSTMGR_USB0		RSTMGR_DEFINE(1, 3)
+#define RSTMGR_USB1		RSTMGR_DEFINE(1, 4)
+#define RSTMGR_NAND		RSTMGR_DEFINE(1, 5)
+#define RSTMGR_SDMMC		RSTMGR_DEFINE(1, 7)
+#define RSTMGR_EMAC0_OCP	RSTMGR_DEFINE(1, 8)
+#define RSTMGR_EMAC1_OCP	RSTMGR_DEFINE(1, 9)
+#define RSTMGR_EMAC2_OCP	RSTMGR_DEFINE(1, 10)
+#define RSTMGR_USB0_OCP		RSTMGR_DEFINE(1, 11)
+#define RSTMGR_USB1_OCP		RSTMGR_DEFINE(1, 12)
+#define RSTMGR_NAND_OCP		RSTMGR_DEFINE(1, 13)
+#define RSTMGR_SDMMC_OCP	RSTMGR_DEFINE(1, 15)
+#define RSTMGR_DMA		RSTMGR_DEFINE(1, 16)
+#define RSTMGR_SPIM0		RSTMGR_DEFINE(1, 17)
+#define RSTMGR_SPIM1		RSTMGR_DEFINE(1, 18)
+#define RSTMGR_L4WD0		RSTMGR_DEFINE(2, 0)
+#define RSTMGR_L4WD1		RSTMGR_DEFINE(2, 1)
+#define RSTMGR_L4WD2		RSTMGR_DEFINE(2, 2)
+#define RSTMGR_L4WD3		RSTMGR_DEFINE(2, 3)
+#define RSTMGR_OSC1TIMER0	RSTMGR_DEFINE(2, 4)
+#define RSTMGR_I2C0		RSTMGR_DEFINE(2, 8)
+#define RSTMGR_I2C1		RSTMGR_DEFINE(2, 9)
+#define RSTMGR_I2C2		RSTMGR_DEFINE(2, 10)
+#define RSTMGR_I2C3		RSTMGR_DEFINE(2, 11)
+#define RSTMGR_I2C4		RSTMGR_DEFINE(2, 12)
+#define RSTMGR_UART0		RSTMGR_DEFINE(2, 16)
+#define RSTMGR_UART1		RSTMGR_DEFINE(2, 17)
+#define RSTMGR_GPIO0		RSTMGR_DEFINE(2, 24)
+#define RSTMGR_GPIO1		RSTMGR_DEFINE(2, 25)
+#define RSTMGR_SDR		RSTMGR_DEFINE(3, 6)
+
+void socfpga_emac_manage_reset(const unsigned int of_reset_id, u32 state);
+
+/* Create a human-readable reference to SoCFPGA reset. */
+#define SOCFPGA_RESET(_name)	RSTMGR_##_name
+
+#endif /* _RESET_MANAGER_S10_ */
diff --git a/arch/arm/mach-socfpga/reset_manager.c b/arch/arm/mach-socfpga/reset_manager.c
index 29438ed..06cd020 100644
--- a/arch/arm/mach-socfpga/reset_manager.c
+++ b/arch/arm/mach-socfpga/reset_manager.c
@@ -9,10 +9,16 @@
 #include <asm/io.h>
 #include <asm/arch/reset_manager.h>
 
+#if defined(CONFIG_TARGET_SOCFPGA_STRATIX10)
+#include <asm/arch/mailbox_s10.h>
+#endif
+
 DECLARE_GLOBAL_DATA_PTR;
 
+#if !defined(CONFIG_TARGET_SOCFPGA_STRATIX10)
 static const struct socfpga_reset_manager *reset_manager_base =
 		(void *)SOCFPGA_RSTMGR_ADDRESS;
+#endif
 
 /*
  * Write the reset manager register to cause reset
@@ -20,8 +26,13 @@ static const struct socfpga_reset_manager *reset_manager_base =
 void reset_cpu(ulong addr)
 {
 	/* request a warm reset */
+#if defined(CONFIG_TARGET_SOCFPGA_STRATIX10)
+	puts("Mailbox: Issuing mailbox cmd REBOOT_HPS\n");
+	mbox_reset_cold();
+#else
 	writel(1 << RSTMGR_CTRL_SWWARMRSTREQ_LSB,
 	       &reset_manager_base->ctrl);
+#endif
 	/*
 	 * infinite loop here as watchdog will trigger and reset
 	 * the processor
diff --git a/arch/arm/mach-socfpga/reset_manager_s10.c b/arch/arm/mach-socfpga/reset_manager_s10.c
new file mode 100644
index 0000000..5cc8336
--- /dev/null
+++ b/arch/arm/mach-socfpga/reset_manager_s10.c
@@ -0,0 +1,140 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2016-2018 Intel Corporation <www.intel.com>
+ *
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/reset_manager.h>
+#include <asm/arch/system_manager.h>
+#include <dt-bindings/reset/altr,rst-mgr-s10.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static const struct socfpga_reset_manager *reset_manager_base =
+		(void *)SOCFPGA_RSTMGR_ADDRESS;
+static const struct socfpga_system_manager *system_manager_base =
+		(void *)SOCFPGA_SYSMGR_ADDRESS;
+
+/* Assert or de-assert SoCFPGA reset manager reset. */
+void socfpga_per_reset(u32 reset, int set)
+{
+	const void *reg;
+
+	if (RSTMGR_BANK(reset) == 0)
+		reg = &reset_manager_base->mpumodrst;
+	else if (RSTMGR_BANK(reset) == 1)
+		reg = &reset_manager_base->per0modrst;
+	else if (RSTMGR_BANK(reset) == 2)
+		reg = &reset_manager_base->per1modrst;
+	else if (RSTMGR_BANK(reset) == 3)
+		reg = &reset_manager_base->brgmodrst;
+	else	/* Invalid reset register, do nothing */
+		return;
+
+	if (set)
+		setbits_le32(reg, 1 << RSTMGR_RESET(reset));
+	else
+		clrbits_le32(reg, 1 << RSTMGR_RESET(reset));
+}
+
+/*
+ * Assert reset on every peripheral but L4WD0.
+ * Watchdog must be kept intact to prevent glitches
+ * and/or hangs.
+ */
+void socfpga_per_reset_all(void)
+{
+	const u32 l4wd0 = 1 << RSTMGR_RESET(SOCFPGA_RESET(L4WD0));
+
+	/* disable all except OCP and l4wd0. OCP disable later */
+	writel(~(l4wd0 | RSTMGR_PER0MODRST_OCP_MASK),
+	       &reset_manager_base->per0modrst);
+	writel(~l4wd0, &reset_manager_base->per0modrst);
+	writel(0xffffffff, &reset_manager_base->per1modrst);
+}
+
+void socfpga_bridges_reset(int enable)
+{
+	if (enable) {
+		/* clear idle request to all bridges */
+		setbits_le32(&system_manager_base->noc_idlereq_clr, ~0);
+
+		/* Release bridges from reset state per handoff value */
+		clrbits_le32(&reset_manager_base->brgmodrst, ~0);
+
+		/* Poll until all idleack to 0 */
+		while (readl(&system_manager_base->noc_idleack))
+			;
+	} else {
+		/* set idle request to all bridges */
+		writel(~0, &system_manager_base->noc_idlereq_set);
+
+		/* Enable the NOC timeout */
+		writel(1, &system_manager_base->noc_timeout);
+
+		/* Poll until all idleack to 1 */
+		while ((readl(&system_manager_base->noc_idleack) ^
+			(SYSMGR_NOC_H2F_MSK | SYSMGR_NOC_LWH2F_MSK)))
+			;
+
+		/* Poll until all idlestatus to 1 */
+		while ((readl(&system_manager_base->noc_idlestatus) ^
+			(SYSMGR_NOC_H2F_MSK | SYSMGR_NOC_LWH2F_MSK)))
+			;
+
+		/* Put all bridges (except NOR DDR scheduler) into reset */
+		setbits_le32(&reset_manager_base->brgmodrst,
+			     ~RSTMGR_BRGMODRST_DDRSCH_MASK);
+
+		/* Disable NOC timeout */
+		writel(0, &system_manager_base->noc_timeout);
+	}
+}
+
+/* of_reset_id: emac reset id
+ * state: 0 - disable reset, !0 - enable reset
+ */
+void socfpga_emac_manage_reset(const unsigned int of_reset_id, u32 state)
+{
+	u32 reset_emac;
+	u32 reset_emacocp;
+
+	/* hardcode this now */
+	switch (of_reset_id) {
+	case EMAC0_RESET:
+		reset_emac = SOCFPGA_RESET(EMAC0);
+		reset_emacocp = SOCFPGA_RESET(EMAC0_OCP);
+		break;
+	case EMAC1_RESET:
+		reset_emac = SOCFPGA_RESET(EMAC1);
+		reset_emacocp = SOCFPGA_RESET(EMAC1_OCP);
+		break;
+	case EMAC2_RESET:
+		reset_emac = SOCFPGA_RESET(EMAC2);
+		reset_emacocp = SOCFPGA_RESET(EMAC2_OCP);
+		break;
+	default:
+		printf("GMAC: Invalid reset ID (%i)!\n", of_reset_id);
+		hang();
+		break;
+	}
+
+	/* Reset ECC OCP first */
+	socfpga_per_reset(reset_emacocp, state);
+
+	/* Release the EMAC controller from reset */
+	socfpga_per_reset(reset_emac, state);
+}
+
+/*
+ * Release peripherals from reset based on handoff
+ */
+void reset_deassert_peripherals_handoff(void)
+{
+	writel(0, &reset_manager_base->per1modrst);
+	/* Enable OCP first */
+	writel(~RSTMGR_PER0MODRST_OCP_MASK, &reset_manager_base->per0modrst);
+	writel(0, &reset_manager_base->per0modrst);
+}
diff --git a/include/dt-bindings/reset/altr,rst-mgr-s10.h b/include/dt-bindings/reset/altr,rst-mgr-s10.h
new file mode 100644
index 0000000..b018d70
--- /dev/null
+++ b/include/dt-bindings/reset/altr,rst-mgr-s10.h
@@ -0,0 +1,96 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright (C) 2016-2018 Intel Corporation <www.intel.com>
+ *
+ */
+
+#ifndef _DT_BINDINGS_RESET_ALTR_RST_MGR_S10_H
+#define _DT_BINDINGS_RESET_ALTR_RST_MGR_S10_H
+
+/* MPUMODRST */
+#define CPU0_RESET		0
+#define CPU1_RESET		1
+#define CPU2_RESET		2
+#define CPU3_RESET		3
+
+/* PER0MODRST */
+#define EMAC0_RESET		32
+#define EMAC1_RESET		33
+#define EMAC2_RESET		34
+#define USB0_RESET		35
+#define USB1_RESET		36
+#define NAND_RESET		37
+/* 38 is empty*/
+#define SDMMC_RESET		39
+#define EMAC0OCP_RESET		40
+#define EMAC1OCP_RESET		41
+#define EMAC2OCP_RESET		42
+#define USB0OCP_RESET		43
+#define USB1OCP_RESET		44
+#define NANDOCP_RESET		45
+/* 46 is empty*/
+#define SDMMCOCP_RESET		47
+#define DMA_RESET		48
+#define SPIM0_RESET		49
+#define SPIM1_RESET		50
+#define SPIS0_RESET		51
+#define SPIS1_RESET		52
+#define DMAOCP_RESET		53
+#define EMACPTP_RESET		54
+/* 55 is empty*/
+#define DMAIF0_RESET		56
+#define DMAIF1_RESET		57
+#define DMAIF2_RESET		58
+#define DMAIF3_RESET		59
+#define DMAIF4_RESET		60
+#define DMAIF5_RESET		61
+#define DMAIF6_RESET		62
+#define DMAIF7_RESET		63
+
+/* PER1MODRST */
+#define L4WD0_RESET		64
+#define L4WD1_RESET		65
+#define L4WD2_RESET		66
+#define L4WD3_RESET		67
+#define L4SYSTIMER0_RESET	68
+#define L4SYSTIMER1_RESET	69
+#define SPTIMER0_RESET		70
+#define SPTIMER1_RESET		71
+#define I2C0_RESET		72
+#define I2C1_RESET		73
+#define I2C2_RESET		74
+#define I2C3_RESET		75
+#define I2C4_RESET		76
+/* 77-79 is reserved */
+#define UART0_RESET		80
+#define UART1_RESET		81
+/* 82-87 is reserved */
+#define GPIO0_RESET		88
+#define GPIO1_RESET		89
+
+/* BRGMODRST */
+#define HPS2FPGA_RESET		96
+#define LWHPS2FPGA_RESET	97
+#define FPGA2HPS_RESET		98
+#define F2SSDRAM0_RESET		99
+#define F2SSDRAM1_RESET		100
+#define F2SSDRAM2_RESET		101
+#define DDRSCH_RESET		102
+
+/* 128-159 is reserved */
+
+/* COLDMODRST */
+#define CPUPOR0_RESET		160
+#define CPUPOR1_RESET		161
+#define CPUPOR2_RESET		162
+#define CPUPOR3_RESET		163
+/* 164-167 is reserved */
+#define L2_RESET		168
+
+/* 192-223 is reserved */
+
+/* DBGMODRST */
+#define DBG_RESET		224
+#define CSDAP_RESET		225
+
+#endif
-- 
1.7.1

[U-Boot] [PATCH v1 04/16] arm: socfpga: stratix10: Add pinmux support for Stratix10 SoC

[Ley Foon Tan]

Add pinmux driver support for Stratix SoC

Signed-off-by: Chin Liang See <chin.liang.see@intel.com>
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
---
 arch/arm/mach-socfpga/Makefile                     |    2 +
 .../arm/mach-socfpga/include/mach/system_manager.h |    5 +-
 .../mach-socfpga/include/mach/system_manager_s10.h |  176 ++++++++++++++++++++
 arch/arm/mach-socfpga/system_manager_s10.c         |   91 ++++++++++
 arch/arm/mach-socfpga/wrap_pinmux_config_s10.c     |   56 ++++++
 5 files changed, 329 insertions(+), 1 deletions(-)
 create mode 100644 arch/arm/mach-socfpga/include/mach/system_manager_s10.h
 create mode 100644 arch/arm/mach-socfpga/system_manager_s10.c
 create mode 100644 arch/arm/mach-socfpga/wrap_pinmux_config_s10.c

diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index f10b05c..910eb6f 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -33,6 +33,8 @@ endif
 ifdef CONFIG_TARGET_SOCFPGA_STRATIX10
 obj-y	+= clock_manager_s10.o
 obj-y	+= reset_manager_s10.o
+obj-y	+= system_manager_s10.o
+obj-y	+= wrap_pinmux_config_s10.o
 obj-y	+= wrap_pll_config_s10.o
 endif
 ifdef CONFIG_SPL_BUILD
diff --git a/arch/arm/mach-socfpga/include/mach/system_manager.h b/arch/arm/mach-socfpga/include/mach/system_manager.h
index e6d4280..80c7d0b 100644
--- a/arch/arm/mach-socfpga/include/mach/system_manager.h
+++ b/arch/arm/mach-socfpga/include/mach/system_manager.h
@@ -7,6 +7,9 @@
 #ifndef _SYSTEM_MANAGER_H_
 #define _SYSTEM_MANAGER_H_
 
+#if defined(CONFIG_TARGET_SOCFPGA_STRATIX10)
+#include <asm/arch/system_manager_s10.h>
+#else
 #define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGPINMUX	BIT(0)
 #define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGIO	BIT(1)
 #define SYSMGR_ECC_OCRAM_EN	BIT(0)
@@ -89,5 +92,5 @@
 
 #define SYSMGR_GET_BOOTINFO_BSEL(bsel)		\
 		(((bsel) >> SYSMGR_BOOTINFO_BSEL_SHIFT) & 7)
-
+#endif
 #endif /* _SYSTEM_MANAGER_H_ */
diff --git a/arch/arm/mach-socfpga/include/mach/system_manager_s10.h b/arch/arm/mach-socfpga/include/mach/system_manager_s10.h
new file mode 100644
index 0000000..813dff2
--- /dev/null
+++ b/arch/arm/mach-socfpga/include/mach/system_manager_s10.h
@@ -0,0 +1,176 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright (C) 2016-2018 Intel Corporation <www.intel.com>
+ *
+ */
+
+#ifndef	_SYSTEM_MANAGER_S10_
+#define	_SYSTEM_MANAGER_S10_
+
+void sysmgr_pinmux_init(void);
+void populate_sysmgr_fpgaintf_module(void);
+void populate_sysmgr_pinmux(void);
+void sysmgr_pinmux_table_sel(const u32 **table, unsigned int *table_len);
+void sysmgr_pinmux_table_ctrl(const u32 **table, unsigned int *table_len);
+void sysmgr_pinmux_table_fpga(const u32 **table, unsigned int *table_len);
+void sysmgr_pinmux_table_delay(const u32 **table, unsigned int *table_len);
+
+struct socfpga_system_manager {
+	/* System Manager Module */
+	u32	siliconid1;			/* 0x00 */
+	u32	siliconid2;
+	u32	wddbg;
+	u32	_pad_0xc;
+	u32	mpu_status;			/* 0x10 */
+	u32	mpu_ace;
+	u32	_pad_0x18_0x1c[2];
+	u32	dma;				/* 0x20 */
+	u32	dma_periph;
+	/* SDMMC Controller Group */
+	u32	sdmmcgrp_ctrl;
+	u32	sdmmcgrp_l3master;
+	/* NAND Flash Controller Register Group */
+	u32	nandgrp_bootstrap;		/* 0x30 */
+	u32	nandgrp_l3master;
+	/* USB Controller Group */
+	u32	usb0_l3master;
+	u32	usb1_l3master;
+	/* EMAC Group */
+	u32	emac_gbl;			/* 0x40 */
+	u32	emac0;
+	u32	emac1;
+	u32	emac2;
+	u32	emac0_ace;			/* 0x50 */
+	u32	emac1_ace;
+	u32	emac2_ace;
+	u32	nand_axuser;
+	u32	_pad_0x60_0x64[2];		/* 0x60 */
+	/* FPGA interface Group */
+	u32	fpgaintf_en_1;
+	u32	fpgaintf_en_2;
+	u32	fpgaintf_en_3;			/* 0x70 */
+	u32	dma_l3master;
+	u32	etr_l3master;
+	u32	_pad_0x7c;
+	u32	sec_ctrl_slt;			/* 0x80 */
+	u32	osc_trim;
+	u32	_pad_0x88_0x8c[2];
+	/* ECC Group */
+	u32	ecc_intmask_value;		/* 0x90 */
+	u32	ecc_intmask_set;
+	u32	ecc_intmask_clr;
+	u32	ecc_intstatus_serr;
+	u32	ecc_intstatus_derr;		/* 0xa0 */
+	u32	_pad_0xa4_0xac[3];
+	u32	noc_addr_remap;			/* 0xb0 */
+	u32	hmc_clk;
+	u32	io_pa_ctrl;
+	u32	_pad_0xbc;
+	/* NOC Group */
+	u32	noc_timeout;			/* 0xc0 */
+	u32	noc_idlereq_set;
+	u32	noc_idlereq_clr;
+	u32	noc_idlereq_value;
+	u32	noc_idleack;			/* 0xd0 */
+	u32	noc_idlestatus;
+	u32	fpga2soc_ctrl;
+	u32	fpga_config;
+	u32	iocsrclk_gate;			/* 0xe0 */
+	u32	gpo;
+	u32	gpi;
+	u32	_pad_0xec;
+	u32	mpu;				/* 0xf0 */
+	u32	sdm_hps_spare;
+	u32	hps_sdm_spare;
+	u32	_pad_0xfc_0x1fc[65];
+	/* Boot scratch register group */
+	u32	boot_scratch_cold0;		/* 0x200 */
+	u32	boot_scratch_cold1;
+	u32	boot_scratch_cold2;
+	u32	boot_scratch_cold3;
+	u32	boot_scratch_cold4;		/* 0x210 */
+	u32	boot_scratch_cold5;
+	u32	boot_scratch_cold6;
+	u32	boot_scratch_cold7;
+	u32	boot_scratch_cold8;		/* 0x220 */
+	u32	boot_scratch_cold9;
+	u32	_pad_0x228_0xffc[886];
+	/* Pin select and pin control group */
+	u32	pinsel0[40];			/* 0x1000 */
+	u32	_pad_0x10a0_0x10fc[24];
+	u32	pinsel40[8];
+	u32	_pad_0x1120_0x112c[4];
+	u32	ioctrl0[28];
+	u32	_pad_0x11a0_0x11fc[24];
+	u32	ioctrl28[20];
+	u32	_pad_0x1250_0x12fc[44];
+	/* Use FPGA mux */
+	u32	rgmii0usefpga;			/* 0x1300 */
+	u32	rgmii1usefpga;
+	u32	rgmii2usefpga;
+	u32	i2c0usefpga;
+	u32	i2c1usefpga;
+	u32	i2c_emac0_usefpga;
+	u32	i2c_emac1_usefpga;
+	u32	i2c_emac2_usefpga;
+	u32	nandusefpga;
+	u32	_pad_0x1324;
+	u32	spim0usefpga;
+	u32	spim1usefpga;
+	u32	spis0usefpga;
+	u32	spis1usefpga;
+	u32	uart0usefpga;
+	u32	uart1usefpga;
+	u32	mdio0usefpga;
+	u32	mdio1usefpga;
+	u32	mdio2usefpga;
+	u32	_pad_0x134c;
+	u32	jtagusefpga;
+	u32	sdmmcusefpga;
+	u32	hps_osc_clk;
+	u32	_pad_0x135c_0x13fc[41];
+	u32	iodelay0[40];
+	u32	_pad_0x14a0_0x14fc[24];
+	u32	iodelay40[8];
+
+};
+
+#define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGPINMUX	BIT(0)
+#define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGIO	BIT(1)
+#define SYSMGR_ECC_OCRAM_EN	BIT(0)
+#define SYSMGR_ECC_OCRAM_SERR	BIT(3)
+#define SYSMGR_ECC_OCRAM_DERR	BIT(4)
+#define SYSMGR_FPGAINTF_USEFPGA	0x1
+
+#define SYSMGR_FPGAINTF_NAND	BIT(4)
+#define SYSMGR_FPGAINTF_SDMMC	BIT(8)
+#define SYSMGR_FPGAINTF_SPIM0	BIT(16)
+#define SYSMGR_FPGAINTF_SPIM1	BIT(24)
+#define SYSMGR_FPGAINTF_EMAC0	(0x11 << 0)
+#define SYSMGR_FPGAINTF_EMAC1	(0x11 << 8)
+#define SYSMGR_FPGAINTF_EMAC2	(0x11 << 16)
+
+#define SYSMGR_SDMMC_SMPLSEL_SHIFT	4
+#define SYSMGR_SDMMC_DRVSEL_SHIFT	0
+
+/* EMAC Group Bit definitions */
+#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII	0x0
+#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII		0x1
+#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII		0x2
+
+#define SYSMGR_EMACGRP_CTRL_PHYSEL0_LSB			0
+#define SYSMGR_EMACGRP_CTRL_PHYSEL1_LSB			2
+#define SYSMGR_EMACGRP_CTRL_PHYSEL_MASK			0x3
+
+#define SYSMGR_NOC_H2F_MSK		0x00000001
+#define SYSMGR_NOC_LWH2F_MSK		0x00000010
+#define SYSMGR_HMC_CLK_STATUS_MSK	0x00000001
+
+#define SYSMGR_DMA_IRQ_NS		0xFF000000
+#define SYSMGR_DMA_MGR_NS		0x00010000
+
+#define SYSMGR_DMAPERIPH_ALL_NS		0xFFFFFFFF
+
+#define SYSMGR_WDDBG_PAUSE_ALL_CPU	0x0F0F0F0F
+
+#endif /* _SYSTEM_MANAGER_S10_ */
diff --git a/arch/arm/mach-socfpga/system_manager_s10.c b/arch/arm/mach-socfpga/system_manager_s10.c
new file mode 100644
index 0000000..122828c
--- /dev/null
+++ b/arch/arm/mach-socfpga/system_manager_s10.c
@@ -0,0 +1,91 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2016-2018 Intel Corporation <www.intel.com>
+ *
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/system_manager.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static struct socfpga_system_manager *sysmgr_regs =
+	(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
+
+/*
+ * Configure all the pin muxes
+ */
+void sysmgr_pinmux_init(void)
+{
+	populate_sysmgr_pinmux();
+	populate_sysmgr_fpgaintf_module();
+}
+
+/*
+ * Populate the value for SYSMGR.FPGAINTF.MODULE based on pinmux setting.
+ * The value is not wrote to SYSMGR.FPGAINTF.MODULE but
+ * CONFIG_SYSMGR_ISWGRP_HANDOFF.
+ */
+void populate_sysmgr_fpgaintf_module(void)
+{
+	u32 handoff_val = 0;
+
+	/* Enable the signal for those HPS peripherals that use FPGA. */
+	if (readl(&sysmgr_regs->nandusefpga) == SYSMGR_FPGAINTF_USEFPGA)
+		handoff_val |= SYSMGR_FPGAINTF_NAND;
+	if (readl(&sysmgr_regs->sdmmcusefpga) == SYSMGR_FPGAINTF_USEFPGA)
+		handoff_val |= SYSMGR_FPGAINTF_SDMMC;
+	if (readl(&sysmgr_regs->spim0usefpga) == SYSMGR_FPGAINTF_USEFPGA)
+		handoff_val |= SYSMGR_FPGAINTF_SPIM0;
+	if (readl(&sysmgr_regs->spim1usefpga) == SYSMGR_FPGAINTF_USEFPGA)
+		handoff_val |= SYSMGR_FPGAINTF_SPIM1;
+	writel(handoff_val, &sysmgr_regs->fpgaintf_en_2);
+
+	handoff_val = 0;
+	if (readl(&sysmgr_regs->rgmii0usefpga) == SYSMGR_FPGAINTF_USEFPGA)
+		handoff_val |= SYSMGR_FPGAINTF_EMAC0;
+	if (readl(&sysmgr_regs->rgmii1usefpga) == SYSMGR_FPGAINTF_USEFPGA)
+		handoff_val |= SYSMGR_FPGAINTF_EMAC1;
+	if (readl(&sysmgr_regs->rgmii2usefpga) == SYSMGR_FPGAINTF_USEFPGA)
+		handoff_val |= SYSMGR_FPGAINTF_EMAC2;
+	writel(handoff_val, &sysmgr_regs->fpgaintf_en_3);
+}
+
+/*
+ * Configure all the pin muxes
+ */
+void populate_sysmgr_pinmux(void)
+{
+	const u32 *sys_mgr_table_u32;
+	unsigned int len, i;
+
+	/* setup the pin sel */
+	sysmgr_pinmux_table_sel(&sys_mgr_table_u32, &len);
+	for (i = 0; i < len; i = i + 2) {
+		writel(sys_mgr_table_u32[i + 1],
+		       sys_mgr_table_u32[i] + (u8 *)&sysmgr_regs->pinsel0[0]);
+	}
+
+	/* setup the pin ctrl */
+	sysmgr_pinmux_table_ctrl(&sys_mgr_table_u32, &len);
+	for (i = 0; i < len; i = i + 2) {
+		writel(sys_mgr_table_u32[i + 1],
+		       sys_mgr_table_u32[i] + (u8 *)&sysmgr_regs->ioctrl0[0]);
+	}
+
+	/* setup the fpga use */
+	sysmgr_pinmux_table_fpga(&sys_mgr_table_u32, &len);
+	for (i = 0; i < len; i = i + 2) {
+		writel(sys_mgr_table_u32[i + 1],
+		       sys_mgr_table_u32[i] +
+		       (u8 *)&sysmgr_regs->rgmii0usefpga);
+	}
+
+	/* setup the IO delay */
+	sysmgr_pinmux_table_delay(&sys_mgr_table_u32, &len);
+	for (i = 0; i < len; i = i + 2) {
+		writel(sys_mgr_table_u32[i + 1],
+		       sys_mgr_table_u32[i] + (u8 *)&sysmgr_regs->iodelay0[0]);
+	}
+}
diff --git a/arch/arm/mach-socfpga/wrap_pinmux_config_s10.c b/arch/arm/mach-socfpga/wrap_pinmux_config_s10.c
new file mode 100644
index 0000000..89c3153
--- /dev/null
+++ b/arch/arm/mach-socfpga/wrap_pinmux_config_s10.c
@@ -0,0 +1,56 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2016-2018 Intel Corporation <www.intel.com>
+ *
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <asm/io.h>
+#include <asm/arch/handoff_s10.h>
+
+static void sysmgr_pinmux_handoff_read(void *handoff_address,
+				       const u32 **table,
+				       unsigned int *table_len)
+{
+	unsigned int handoff_entry = (swab32(readl(handoff_address +
+					CONFIG_HANDOFF_OFFSET_LENGTH)) -
+					CONFIG_HANDOFF_OFFSET_DATA) /
+					sizeof(unsigned int);
+	unsigned int handoff_chunk[handoff_entry], temp, i;
+
+	if (swab32(readl(CONFIG_HANDOFF_MUX)) == CONFIG_HANDOFF_MAGIC_MUX) {
+		/* using handoff from Quartus tools if exists */
+		for (i = 0; i < handoff_entry; i++) {
+			temp = readl(handoff_address +
+				     CONFIG_HANDOFF_OFFSET_DATA + (i * 4));
+			handoff_chunk[i] = swab32(temp);
+		}
+		*table = handoff_chunk;
+		*table_len = ARRAY_SIZE(handoff_chunk);
+	}
+}
+
+void sysmgr_pinmux_table_sel(const u32 **table, unsigned int *table_len)
+{
+	sysmgr_pinmux_handoff_read((void *)CONFIG_HANDOFF_MUX, table,
+				   table_len);
+}
+
+void sysmgr_pinmux_table_ctrl(const u32 **table, unsigned int *table_len)
+{
+	sysmgr_pinmux_handoff_read((void *)CONFIG_HANDOFF_IOCTL, table,
+				   table_len);
+}
+
+void sysmgr_pinmux_table_fpga(const u32 **table, unsigned int *table_len)
+{
+	sysmgr_pinmux_handoff_read((void *)CONFIG_HANDOFF_FPGA, table,
+				   table_len);
+}
+
+void sysmgr_pinmux_table_delay(const u32 **table, unsigned int *table_len)
+{
+	sysmgr_pinmux_handoff_read((void *)CONFIG_HANODFF_DELAY, table,
+				   table_len);
+}
-- 
1.7.1

[U-Boot] [PATCH v1 05/16] arm: socfpga: misc: Add CONFIG_SYS_L2_PL310 switch

[Ley Foon Tan]

Add CONFIG_SYS_L2_PL310 conditional build.

Signed-off-by: Chin Liang See <chin.liang.see@intel.com>
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
---
 arch/arm/mach-socfpga/misc.c |    4 ++++
 1 files changed, 4 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c
index 692466c..01f824c 100644
--- a/arch/arm/mach-socfpga/misc.c
+++ b/arch/arm/mach-socfpga/misc.c
@@ -23,8 +23,10 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+#ifdef CONFIG_SYS_L2_PL310
 static const struct pl310_regs *const pl310 =
 	(struct pl310_regs *)CONFIG_SYS_PL310_BASE;
+#endif
 
 struct bsel bsel_str[] = {
 	{ "rsvd", "Reserved", },
@@ -53,6 +55,7 @@ void enable_caches(void)
 #endif
 }
 
+#ifdef CONFIG_SYS_L2_PL310
 void v7_outer_cache_enable(void)
 {
 	/* Disable the L2 cache */
@@ -73,6 +76,7 @@ void v7_outer_cache_disable(void)
 	/* Disable the L2 cache */
 	clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
 }
+#endif
 
 #if defined(CONFIG_SYS_CONSOLE_IS_IN_ENV) && \
 defined(CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE)
-- 
1.7.1

[U-Boot] [PATCH v1 06/16] arm: socfpga: misc: Move eth reset to common misc driver

[Ley Foon Tan]

Move eth reset to common misc driver so can used by other device families.

Signed-off-by: Chin Liang See <chin.liang.see@intel.com>
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
---
 arch/arm/mach-socfpga/include/mach/misc.h |    1 +
 arch/arm/mach-socfpga/misc.c              |   69 +++++++++++++++++++++++++++
 arch/arm/mach-socfpga/misc_gen5.c         |   74 +----------------------------
 3 files changed, 72 insertions(+), 72 deletions(-)

diff --git a/arch/arm/mach-socfpga/include/mach/misc.h b/arch/arm/mach-socfpga/include/mach/misc.h
index 0b65783..8466023 100644
--- a/arch/arm/mach-socfpga/include/mach/misc.h
+++ b/arch/arm/mach-socfpga/include/mach/misc.h
@@ -8,6 +8,7 @@
 #define _MISC_H_
 
 void dwmac_deassert_reset(const unsigned int of_reset_id, const u32 phymode);
+int socfpga_eth_reset(void);
 
 struct bsel {
 	const char	*mode;
diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c
index 01f824c..d15cbc7 100644
--- a/arch/arm/mach-socfpga/misc.c
+++ b/arch/arm/mach-socfpga/misc.c
@@ -140,3 +140,72 @@ int arch_cpu_init(void)
 
 	return 0;
 }
+
+#ifdef CONFIG_ETH_DESIGNWARE
+static u32 dwmac_phymode_to_modereg(const char *phymode, u32 *modereg)
+{
+	if (!phymode)
+		return -EINVAL;
+
+	if (!strcmp(phymode, "mii") || !strcmp(phymode, "gmii")) {
+		*modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII;
+		return 0;
+	}
+
+	if (!strcmp(phymode, "rgmii")) {
+		*modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII;
+		return 0;
+	}
+
+	if (!strcmp(phymode, "rmii")) {
+		*modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII;
+		return 0;
+	}
+
+	return -EINVAL;
+}
+
+int socfpga_eth_reset(void)
+{
+	const void *fdt = gd->fdt_blob;
+	struct fdtdec_phandle_args args;
+	const char *phy_mode;
+	u32 phy_modereg;
+	int nodes[3];	/* Max. 3 GMACs */
+	int ret, count;
+	int i, node;
+
+	count = fdtdec_find_aliases_for_id(fdt, "ethernet",
+					   COMPAT_ALTERA_SOCFPGA_DWMAC,
+					   nodes, ARRAY_SIZE(nodes));
+	for (i = 0; i < count; i++) {
+		node = nodes[i];
+		if (node <= 0)
+			continue;
+
+		ret = fdtdec_parse_phandle_with_args(fdt, node, "resets",
+						     "#reset-cells", 1, 0,
+						     &args);
+		if (ret || args.args_count != 1) {
+			debug("GMAC%i: Failed to parse DT 'resets'!\n", i);
+			continue;
+		}
+
+		phy_mode = fdt_getprop(fdt, node, "phy-mode", NULL);
+		ret = dwmac_phymode_to_modereg(phy_mode, &phy_modereg);
+		if (ret) {
+			debug("GMAC%i: Failed to parse DT 'phy-mode'!\n", i);
+			continue;
+		}
+
+		dwmac_deassert_reset(args.args[0], phy_modereg);
+	}
+
+	return 0;
+}
+#else
+int socfpga_eth_reset(void)
+{
+	return 0;
+};
+#endif
diff --git a/arch/arm/mach-socfpga/misc_gen5.c b/arch/arm/mach-socfpga/misc_gen5.c
index 177b35f..f642524 100644
--- a/arch/arm/mach-socfpga/misc_gen5.c
+++ b/arch/arm/mach-socfpga/misc_gen5.c
@@ -63,84 +63,13 @@ void dwmac_deassert_reset(const unsigned int of_reset_id,
 	/* Release the EMAC controller from reset */
 	socfpga_per_reset(reset, 0);
 }
-
-static u32 dwmac_phymode_to_modereg(const char *phymode, u32 *modereg)
-{
-	if (!phymode)
-		return -EINVAL;
-
-	if (!strcmp(phymode, "mii") || !strcmp(phymode, "gmii")) {
-		*modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII;
-		return 0;
-	}
-
-	if (!strcmp(phymode, "rgmii")) {
-		*modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII;
-		return 0;
-	}
-
-	if (!strcmp(phymode, "rmii")) {
-		*modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII;
-		return 0;
-	}
-
-	return -EINVAL;
-}
-
-static int socfpga_eth_reset(void)
-{
-	const void *fdt = gd->fdt_blob;
-	struct fdtdec_phandle_args args;
-	const char *phy_mode;
-	u32 phy_modereg;
-	int nodes[2];	/* Max. two GMACs */
-	int ret, count;
-	int i, node;
-
-	/* Put both GMACs into RESET state. */
-	socfpga_per_reset(SOCFPGA_RESET(EMAC0), 1);
-	socfpga_per_reset(SOCFPGA_RESET(EMAC1), 1);
-
-	count = fdtdec_find_aliases_for_id(fdt, "ethernet",
-					   COMPAT_ALTERA_SOCFPGA_DWMAC,
-					   nodes, ARRAY_SIZE(nodes));
-	for (i = 0; i < count; i++) {
-		node = nodes[i];
-		if (node <= 0)
-			continue;
-
-		ret = fdtdec_parse_phandle_with_args(fdt, node, "resets",
-						     "#reset-cells", 1, 0,
-						     &args);
-		if (ret || (args.args_count != 1)) {
-			debug("GMAC%i: Failed to parse DT 'resets'!\n", i);
-			continue;
-		}
-
-		phy_mode = fdt_getprop(fdt, node, "phy-mode", NULL);
-		ret = dwmac_phymode_to_modereg(phy_mode, &phy_modereg);
-		if (ret) {
-			debug("GMAC%i: Failed to parse DT 'phy-mode'!\n", i);
-			continue;
-		}
-
-		dwmac_deassert_reset(args.args[0], phy_modereg);
-	}
-
-	return 0;
-}
-#else
-static int socfpga_eth_reset(void)
-{
-	return 0;
-};
 #endif
 
 static const struct {
 	const u16	pn;
 	const char	*name;
 	const char	*var;
-} socfpga_fpga_model[] = {
+} const socfpga_fpga_model[] = {
 	/* Cyclone V E */
 	{ 0x2b15, "Cyclone V, E/A2", "cv_e_a2" },
 	{ 0x2b05, "Cyclone V, E/A4", "cv_e_a4" },
@@ -218,6 +147,7 @@ int arch_misc_init(void)
 	env_set("bootmode", bsel_str[bsel].mode);
 	if (fpga_id >= 0)
 		env_set("fpgatype", socfpga_fpga_model[fpga_id].var);
+
 	return socfpga_eth_reset();
 }
 #endif
-- 
1.7.1

[U-Boot] [PATCH v1 07/16] arm: socfpga: stratix10: Add misc support for Stratix10 SoC

[Ley Foon Tan]

Add misc support such as EMAC and cpu info printout for Stratix SoC

Signed-off-by: Chin Liang See <chin.liang.see@intel.com>
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
---
 arch/arm/mach-socfpga/Makefile   |    1 +
 arch/arm/mach-socfpga/misc_s10.c |  103 ++++++++++++++++++++++++++++++++++++++
 2 files changed, 104 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/mach-socfpga/misc_s10.c

diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index 910eb6f..b253914 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -32,6 +32,7 @@ endif
 
 ifdef CONFIG_TARGET_SOCFPGA_STRATIX10
 obj-y	+= clock_manager_s10.o
+obj-y	+= misc_s10.o
 obj-y	+= reset_manager_s10.o
 obj-y	+= system_manager_s10.o
 obj-y	+= wrap_pinmux_config_s10.o
diff --git a/arch/arm/mach-socfpga/misc_s10.c b/arch/arm/mach-socfpga/misc_s10.c
new file mode 100644
index 0000000..b1cc6ca
--- /dev/null
+++ b/arch/arm/mach-socfpga/misc_s10.c
@@ -0,0 +1,103 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2016-2018 Intel Corporation <www.intel.com>
+ *
+ */
+
+#include <altera.h>
+#include <common.h>
+#include <errno.h>
+#include <fdtdec.h>
+#include <miiphy.h>
+#include <netdev.h>
+#include <watchdog.h>
+#include <asm/io.h>
+#include <asm/arch/reset_manager.h>
+#include <asm/arch/system_manager.h>
+#include <asm/arch/misc.h>
+#include <asm/pl310.h>
+#include <linux/libfdt.h>
+
+#include <dt-bindings/reset/altr,rst-mgr-s10.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static struct socfpga_system_manager *sysmgr_regs =
+	(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
+
+/*
+ * DesignWare Ethernet initialization
+ */
+#ifdef CONFIG_ETH_DESIGNWARE
+void dwmac_deassert_reset(const unsigned int of_reset_id,
+			  const u32 phymode)
+{
+	/* Put the emac we're using into reset.
+	 * This is required before configuring the PHY interface
+	 */
+	socfpga_emac_manage_reset(of_reset_id, 1);
+
+	clrsetbits_le32(&sysmgr_regs->emac0 + (of_reset_id - EMAC0_RESET),
+			SYSMGR_EMACGRP_CTRL_PHYSEL_MASK,
+			phymode);
+
+	socfpga_emac_manage_reset(of_reset_id, 0);
+}
+#endif
+
+/*
+ * Print CPU information
+ */
+#if defined(CONFIG_DISPLAY_CPUINFO)
+int print_cpuinfo(void)
+{
+	puts("CPU:   Intel FPGA SoCFPGA Platform\n");
+	puts("FPGA:  Intel FPGA Stratix 10\n");
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_ARCH_MISC_INIT
+int arch_misc_init(void)
+{
+	char qspi_string[13];
+
+	sprintf(qspi_string, "<0x%08x>", cm_get_qspi_controller_clk_hz());
+	env_set("qspi_clock", qspi_string);
+
+	return socfpga_eth_reset();
+}
+#endif
+
+int arch_early_init_r(void)
+{
+	return 0;
+}
+
+int do_bridge(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	if (argc != 2)
+		return CMD_RET_USAGE;
+
+	argv++;
+
+	switch (*argv[0]) {
+	case 'e':	/* Enable */
+		socfpga_bridges_reset(1);
+		break;
+	case 'd':	/* Disable */
+		socfpga_bridges_reset(0);
+		break;
+	default:
+		return CMD_RET_USAGE;
+	}
+
+	return 0;
+}
+
+U_BOOT_CMD(bridge, 2, 1, do_bridge,
+	   "SoCFPGA HPS FPGA bridge control",
+	   "enable  - Enable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA bridges\n"
+	   "bridge disable - Disable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA bridges\n"
+	   ""
+);
-- 
1.7.1

[U-Boot] [PATCH v1 08/16] arm: socfpga: stratix10: Add mailbox support for Stratix10 SoC

[Ley Foon Tan]

Add mailbox support for Stratix SoC

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Signed-off-by: Chin Liang See <chin.liang.see@intel.com>
---
 arch/arm/mach-socfpga/Makefile                   |    1 +
 arch/arm/mach-socfpga/include/mach/mailbox_s10.h |  155 +++++++++
 arch/arm/mach-socfpga/mailbox_s10.c              |  378 ++++++++++++++++++++++
 3 files changed, 534 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/mach-socfpga/include/mach/mailbox_s10.h
 create mode 100644 arch/arm/mach-socfpga/mailbox_s10.c

diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index b253914..43e18d2 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -32,6 +32,7 @@ endif
 
 ifdef CONFIG_TARGET_SOCFPGA_STRATIX10
 obj-y	+= clock_manager_s10.o
+obj-y	+= mailbox_s10.o
 obj-y	+= misc_s10.o
 obj-y	+= reset_manager_s10.o
 obj-y	+= system_manager_s10.o
diff --git a/arch/arm/mach-socfpga/include/mach/mailbox_s10.h b/arch/arm/mach-socfpga/include/mach/mailbox_s10.h
new file mode 100644
index 0000000..85e7f84
--- /dev/null
+++ b/arch/arm/mach-socfpga/include/mach/mailbox_s10.h
@@ -0,0 +1,155 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright (C) 2017-2018 Intel Corporation <www.intel.com>
+ *
+ */
+
+#ifndef _MAILBOX_S10_H_
+#define _MAILBOX_S10_H_
+
+/* user define Uboot ID */
+#define MBOX_CLIENT_ID_UBOOT	0xB
+#define MBOX_ID_UBOOT		0x1
+
+#define MBOX_CMD_DIRECT	0
+#define MBOX_CMD_INDIRECT	1
+
+#define MBOX_MAX_CMD_INDEX	2047
+#define MBOX_CMD_BUFFER_SIZE	32
+#define MBOX_RESP_BUFFER_SIZE	16
+
+#define MBOX_HDR_CMD_LSB	0
+#define MBOX_HDR_CMD_MSK	(BIT(11) - 1)
+#define MBOX_HDR_I_LSB		11
+#define MBOX_HDR_I_MSK		BIT(11)
+#define MBOX_HDR_LEN_LSB	12
+#define MBOX_HDR_LEN_MSK	0x007FF000
+#define MBOX_HDR_ID_LSB		24
+#define MBOX_HDR_ID_MSK		0x0F000000
+#define MBOX_HDR_CLIENT_LSB	28
+#define MBOX_HDR_CLIENT_MSK	0xF0000000
+
+/* Interrupt flags */
+#define MBOX_FLAGS_INT_COE	BIT(0)	/* COUT update interrupt enable */
+#define MBOX_FLAGS_INT_RIE	BIT(1)	/* RIN update interrupt enable */
+#define MBOX_FLAGS_INT_UAE	BIT(8)	/* Urgent ACK interrupt enable */
+#define MBOX_ALL_INTRS		(MBOX_FLAGS_INT_COE | \
+				 MBOX_FLAGS_INT_RIE | \
+				 MBOX_FLAGS_INT_UAE)
+
+/* Status */
+#define MBOX_STATUS_UA_MSK	BIT(8)
+
+#define MBOX_CMD_HEADER(client, id, len, indirect, cmd)     \
+	((((cmd) << MBOX_HDR_CMD_LSB) & MBOX_HDR_CMD_MSK) | \
+	(((indirect) << MBOX_HDR_I_LSB) & MBOX_HDR_I_MSK) | \
+	(((len) << MBOX_HDR_LEN_LSB) & MBOX_HDR_LEN_MSK)  | \
+	(((id) << MBOX_HDR_ID_LSB) & MBOX_HDR_ID_MSK)     | \
+	(((client) << MBOX_HDR_CLIENT_LSB) & MBOX_HDR_CLIENT_MSK))
+
+#define MBOX_RESP_ERR_GET(resp)				\
+	(((resp) & MBOX_HDR_CMD_MSK) >> MBOX_HDR_CMD_LSB)
+#define MBOX_RESP_LEN_GET(resp)			\
+	(((resp) & MBOX_HDR_LEN_MSK) >> MBOX_HDR_LEN_LSB)
+#define MBOX_RESP_ID_GET(resp)				\
+	(((resp) & MBOX_HDR_ID_MSK) >> MBOX_HDR_ID_LSB)
+#define MBOX_RESP_CLIENT_GET(resp)			\
+	(((resp) & MBOX_HDR_CLIENT_MSK) >> MBOX_HDR_CLIENT_LSB)
+
+/* Response error list */
+enum ALT_SDM_MBOX_RESP_CODE {
+	/* CMD completed successfully, but check resp ARGS for any errors */
+	MBOX_RESP_STATOK = 0,
+	/* CMD is incorrectly formatted in some way */
+	MBOX_RESP_INVALID_COMMAND = 1,
+	/* BootROM Command code not undesrtood */
+	MBOX_RESP_UNKNOWN_BR = 2,
+	/* CMD code not recognized by firmware */
+	MBOX_RESP_UNKNOWN = 3,
+	/* Indicates that the device is not configured */
+	MBOX_RESP_NOT_CONFIGURED = 256,
+	/* Indicates that the device is busy */
+	MBOX_RESP_DEVICE_BUSY = 0x1FF,
+	/* Indicates that there is no valid response available */
+	MBOX_RESP_NO_VALID_RESP_AVAILABLE = 0x2FF,
+	/* General Error */
+	MBOX_RESP_ERROR = 0x3FF,
+};
+
+/* Mailbox command list */
+#define MBOX_RESTART		2
+#define MBOX_CONFIG_STATUS	4
+#define MBOX_RECONFIG		6
+#define MBOX_RECONFIG_MSEL	7
+#define MBOX_RECONFIG_DATA	8
+#define MBOX_RECONFIG_STATUS	9
+#define MBOX_QSPI_OPEN		50
+#define MBOX_QSPI_CLOSE		51
+#define MBOX_QSPI_DIRECT	59
+#define MBOX_REBOOT_HPS		71
+
+struct socfpga_mailbox {
+	u32 cin;		/* command valid offset */
+	u32 rout;		/* response output offset */
+	u32 urg;		/* urgent command */
+	u32 flags;		/* interrupt enables */
+	u32 pad_0x10_0x1f[4];	/* 0x10 - 0x1F reserved */
+	u32 cout;		/* command free offset */
+	u32 rin;		/* respond valid offset */
+	u32 pad_0x28;		/* 0x28 reserved */
+	u32 status;		/* mailbox status */
+	u32 pad_0x30_0x3f[4];	/* 0x30 - 0x3F reserved */
+	u32 cmd_buf[MBOX_CMD_BUFFER_SIZE];	/* 0x40 - 0xBC circular command
+						 * buffer to SDM
+						 */
+	u32 resp_buf[MBOX_RESP_BUFFER_SIZE];	/* 0xC0 - 0xFF circular
+						 * response buffer
+						 */
+};
+
+/* Use define other than put into struct socfpga_mailbox to save spaces */
+#define MBOX_DOORBELL_TO_SDM_REG	(SOCFPGA_MAILBOX_ADDRESS + 0x400)
+#define MBOX_DOORBELL_FROM_SDM_REG	(SOCFPGA_MAILBOX_ADDRESS + 0x480)
+
+/******** Status and bit information returned by RECONFIG_STATUS ********/
+#define RECONFIG_STATUS_RESPONSE_LEN			6
+#define RECONFIG_STATUS_STATE				0
+#define RECONFIG_STATUS_PIN_STATUS			2
+#define RECONFIG_STATUS_SOFTFUNC_STATUS			3
+
+#define MBOX_CFGSTAT_STATE_IDLE				0x00000000
+#define MBOX_CFGSTAT_STATE_CONFIG			0x10000000
+#define MBOX_CFGSTAT_STATE_FAILACK			0x08000000
+#define MBOX_CFGSTAT_STATE_ERROR_INVALID		0xf0000001
+#define MBOX_CFGSTAT_STATE_ERROR_CORRUPT		0xf0000002
+#define MBOX_CFGSTAT_STATE_ERROR_AUTH			0xf0000003
+#define MBOX_CFGSTAT_STATE_ERROR_CORE_IO		0xf0000004
+#define MBOX_CFGSTAT_STATE_ERROR_HARDWARE		0xf0000005
+#define MBOX_CFGSTAT_STATE_ERROR_FAKE			0xf0000006
+#define MBOX_CFGSTAT_STATE_ERROR_BOOT_INFO		0xf0000007
+#define MBOX_CFGSTAT_STATE_ERROR_QSPI_ERROR		0xf0000008
+
+#define RCF_SOFTFUNC_STATUS_CONF_DONE			BIT(0)
+#define RCF_SOFTFUNC_STATUS_INIT_DONE			BIT(1)
+#define RCF_SOFTFUNC_STATUS_SEU_ERROR			BIT(3)
+#define RCF_PIN_STATUS_NSTATUS				BIT(31)
+/************************************************************************/
+
+int mbox_send_cmd(u8 id, u32 cmd, u8 is_indirect, u32 len, u32 *arg, u8 urgent,
+		  u32 *resp_buf_len, u32 *resp_buf);
+int mbox_send_cmd_psci(u8 id, u32 cmd, u8 is_indirect, u32 len, u32 *arg,
+		       u8 urgent, u32 *resp_buf_len, u32 *resp_buf);
+int mbox_send_cmd_only(u8 id, u32 cmd, u8 is_indirect, u32 len, u32 *arg);
+int mbox_send_cmd_only_psci(u8 id, u32 cmd, u8 is_indirect, u32 len, u32 *arg);
+int mbox_rcv_resp(u32 *resp_buf, u32 resp_buf_max_len);
+int mbox_rcv_resp_psci(u32 *resp_buf, u32 resp_buf_max_len);
+int mbox_init(void);
+
+#ifdef CONFIG_CADENCE_QSPI
+int mbox_qspi_close(void);
+int mbox_qspi_open(void);
+#endif
+
+int mbox_reset_cold(void);
+
+#endif /* _MAILBOX_S10_H_ */
diff --git a/arch/arm/mach-socfpga/mailbox_s10.c b/arch/arm/mach-socfpga/mailbox_s10.c
new file mode 100644
index 0000000..ed713a9
--- /dev/null
+++ b/arch/arm/mach-socfpga/mailbox_s10.c
@@ -0,0 +1,378 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2017-2018 Intel Corporation <www.intel.com>
+ *
+ */
+
+#include <common.h>
+#include <wait_bit.h>
+#include <asm/io.h>
+#include <asm/arch/mailbox_s10.h>
+#include <asm/arch/system_manager.h>
+#include <asm/secure.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static __always_inline int mbox_polling_resp(u32 rout)
+{
+	static const struct socfpga_mailbox *mbox_base =
+					(void *)SOCFPGA_MAILBOX_ADDRESS;
+	u32 rin;
+	unsigned long i = ~0;
+
+	while (i) {
+		rin = readl(&mbox_base->rin);
+		if (rout != rin)
+			return 0;
+
+		i--;
+	}
+
+	return -ETIMEDOUT;
+}
+
+/* Check for available slot and write to circular buffer.
+ * It also update command valid offset (cin) register.
+ */
+static __always_inline int mbox_fill_cmd_circular_buff(u32 header, u32 len,
+						       u32 *arg)
+{
+	static const struct socfpga_mailbox *mbox_base =
+					(void *)SOCFPGA_MAILBOX_ADDRESS;
+	u32 cin;
+	u32 cout;
+	u32 i;
+
+	cin = readl(&mbox_base->cin) % MBOX_CMD_BUFFER_SIZE;
+	cout = readl(&mbox_base->cout) % MBOX_CMD_BUFFER_SIZE;
+
+	/* if command buffer is full or not enough free space
+	 * to fit the data
+	 */
+	if (((cin + 1) % MBOX_CMD_BUFFER_SIZE) == cout ||
+	    ((MBOX_CMD_BUFFER_SIZE - cin + cout - 1) %
+	     MBOX_CMD_BUFFER_SIZE) < len)
+		return -ENOMEM;
+
+	/* write header to circular buffer */
+	writel(header, &mbox_base->cmd_buf[cin++]);
+	/* wrapping around when it reach the buffer size */
+	cin %= MBOX_CMD_BUFFER_SIZE;
+
+	/* write arguments */
+	for (i = 0; i < len; i++) {
+		writel(arg[i], &mbox_base->cmd_buf[cin++]);
+		/* wrapping around when it reach the buffer size */
+		cin %= MBOX_CMD_BUFFER_SIZE;
+	}
+
+	/* write command valid offset */
+	writel(cin, &mbox_base->cin);
+
+	return 0;
+}
+
+/* Check the command and fill it into circular buffer */
+static __always_inline int mbox_prepare_cmd_only(u8 id, u32 cmd,
+						 u8 is_indirect, u32 len,
+						 u32 *arg)
+{
+	u32 header;
+	int ret;
+
+	/* Total length is command + argument length */
+	if ((len + 1) > MBOX_CMD_BUFFER_SIZE)
+		return -EINVAL;
+
+	if (cmd > MBOX_MAX_CMD_INDEX)
+		return -EINVAL;
+
+	header = MBOX_CMD_HEADER(MBOX_CLIENT_ID_UBOOT, id, len,
+				 (is_indirect) ? 1 : 0, cmd);
+
+	ret = mbox_fill_cmd_circular_buff(header, len, arg);
+
+	return ret;
+}
+
+/* Send command only without waiting for responses from SDM */
+static __always_inline int __mbox_send_cmd_only(u8 id, u32 cmd,
+						u8 is_indirect, u32 len,
+						u32 *arg)
+{
+	int ret = mbox_prepare_cmd_only(id, cmd, is_indirect, len, arg);
+	/* write doorbell */
+	writel(1, MBOX_DOORBELL_TO_SDM_REG);
+
+	return ret;
+}
+
+/* Return number of responses received in buffer */
+static __always_inline int __mbox_rcv_resp(u32 *resp_buf, u32 resp_buf_max_len)
+{
+	static const struct socfpga_mailbox *mbox_base =
+					(void *)SOCFPGA_MAILBOX_ADDRESS;
+	u32 rin;
+	u32 rout;
+	u32 resp_len = 0;
+
+	/* clear doorbell from SDM if it was SET */
+	if (readl((const u32 *)MBOX_DOORBELL_FROM_SDM_REG) & 1)
+		writel(0, MBOX_DOORBELL_FROM_SDM_REG);
+
+	/* read current response offset */
+	rout = readl(&mbox_base->rout);
+	/* read response valid offset */
+	rin = readl(&mbox_base->rin);
+
+	while (rin != rout && (resp_len < resp_buf_max_len)) {
+		/* Response received */
+		if (resp_buf)
+			resp_buf[resp_len++] =
+				readl(&mbox_base->resp_buf[rout]);
+		rout++;
+		/* wrapping around when it reach the buffer size */
+		rout %= MBOX_RESP_BUFFER_SIZE;
+		/* update next ROUT */
+		writel(rout, &mbox_base->rout);
+	}
+
+	return resp_len;
+}
+
+/* Support one command and up to 31 words argument length only */
+static __always_inline int __mbox_send_cmd(u8 id, u32 cmd, u8 is_indirect,
+					   u32 len, u32 *arg, u8 urgent,
+					   u32 *resp_buf_len, u32 *resp_buf)
+{
+	static const struct socfpga_mailbox *mbox_base =
+					(void *)SOCFPGA_MAILBOX_ADDRESS;
+
+	u32 rin;
+	u32 resp;
+	u32 rout;
+	u32 status;
+	u32 resp_len;
+	u32 buf_len;
+	int ret;
+
+	ret = mbox_prepare_cmd_only(id, cmd, is_indirect, len, arg);
+	if (ret)
+		return ret;
+
+	if (urgent) {
+		/* Read status because it is toggled */
+		status = readl(&mbox_base->status) & MBOX_STATUS_UA_MSK;
+		/* Send command as urgent command */
+		writel(1, &mbox_base->urg);
+	}
+
+	/* write doorbell */
+	writel(1, MBOX_DOORBELL_TO_SDM_REG);
+
+	while (1) {
+		ret = ~0;
+
+		/* Wait for doorbell from SDM */
+		while (!readl(MBOX_DOORBELL_FROM_SDM_REG) && ret--)
+			;
+		if (!ret)
+			return -ETIMEDOUT;
+
+		/* clear interrupt */
+		writel(0, MBOX_DOORBELL_FROM_SDM_REG);
+
+		if (urgent) {
+			u32 new_status = readl(&mbox_base->status);
+			/* urgent command doesn't have response */
+			writel(0, &mbox_base->urg);
+			/* Urgent ACK is toggled */
+			if ((new_status & MBOX_STATUS_UA_MSK) ^ status)
+				return 0;
+
+			return -ECOMM;
+		}
+
+		/* read current response offset */
+		rout = readl(&mbox_base->rout);
+
+		/* read response valid offset */
+		rin = readl(&mbox_base->rin);
+
+		if (rout != rin) {
+			/* Response received */
+			resp = readl(&mbox_base->resp_buf[rout]);
+			rout++;
+			/* wrapping around when it reach the buffer size */
+			rout %= MBOX_RESP_BUFFER_SIZE;
+			/* update next ROUT */
+			writel(rout, &mbox_base->rout);
+
+			/* check client ID and ID */
+			if ((MBOX_RESP_CLIENT_GET(resp) == MBOX_CLIENT_ID_UBOOT) &&
+			    (MBOX_RESP_ID_GET(resp) == id)) {
+				ret = MBOX_RESP_ERR_GET(resp);
+				if (ret)
+					return ret;
+
+				if (resp_buf_len) {
+					buf_len = *resp_buf_len;
+					*resp_buf_len = 0;
+				} else {
+					buf_len = 0;
+				}
+
+				resp_len = MBOX_RESP_LEN_GET(resp);
+				while (resp_len) {
+					ret = mbox_polling_resp(rout);
+					if (ret)
+						return ret;
+					/* we need to process response buffer
+					 * even caller doesn't need it
+					 */
+					resp = readl(&mbox_base->resp_buf[rout]);
+					rout++;
+					resp_len--;
+					rout %= MBOX_RESP_BUFFER_SIZE;
+					writel(rout, &mbox_base->rout);
+					if (buf_len) {
+						/* copy response to buffer */
+						resp_buf[*resp_buf_len] = resp;
+						(*resp_buf_len)++;
+						buf_len--;
+					}
+				}
+				return ret;
+			}
+		}
+	};
+
+	return -EIO;
+}
+
+int mbox_init(void)
+{
+	static const struct socfpga_mailbox *mbox_base =
+					(void *)SOCFPGA_MAILBOX_ADDRESS;
+	int ret;
+
+	/* enable mailbox interrupts */
+	writel(MBOX_ALL_INTRS, &mbox_base->flags);
+
+	/* Ensure urgent request is cleared */
+	writel(0, &mbox_base->urg);
+
+	/* Ensure the Doorbell Interrupt is cleared */
+	writel(0, MBOX_DOORBELL_FROM_SDM_REG);
+
+	ret = mbox_send_cmd(MBOX_ID_UBOOT, MBOX_RESTART, MBOX_CMD_DIRECT, 0,
+			    NULL, 1, 0, NULL);
+	if (ret)
+		return ret;
+
+	/* Renable mailbox interrupts after MBOX_RESTART */
+	writel(MBOX_ALL_INTRS, &mbox_base->flags);
+
+	return 0;
+}
+
+#ifdef CONFIG_CADENCE_QSPI
+int mbox_qspi_close(void)
+{
+	return mbox_send_cmd(MBOX_ID_UBOOT, MBOX_QSPI_CLOSE, MBOX_CMD_DIRECT,
+			     0, NULL, 0, 0, NULL);
+}
+
+int mbox_qspi_open(void)
+{
+	static const struct socfpga_system_manager *sysmgr_regs =
+		(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
+
+	int ret;
+	u32 resp_buf[1];
+	u32 resp_buf_len;
+
+	ret = mbox_send_cmd(MBOX_ID_UBOOT, MBOX_QSPI_OPEN, MBOX_CMD_DIRECT,
+			    0, NULL, 0, 0, NULL);
+	if (ret) {
+		/* retry again by closing and reopen the QSPI again */
+		ret = mbox_qspi_close();
+		if (ret)
+			return ret;
+
+		ret = mbox_send_cmd(MBOX_ID_UBOOT, MBOX_QSPI_OPEN,
+				    MBOX_CMD_DIRECT, 0, NULL, 0, 0, NULL);
+		if (ret)
+			return ret;
+	}
+
+	/* HPS will directly control the QSPI controller, no longer mailbox */
+	resp_buf_len = 1;
+	ret = mbox_send_cmd(MBOX_ID_UBOOT, MBOX_QSPI_DIRECT, MBOX_CMD_DIRECT,
+			    0, NULL, 0, (u32 *)&resp_buf_len,
+			    (u32 *)&resp_buf);
+	if (ret)
+		goto error;
+
+	/* We are getting QSPI ref clock and set into sysmgr boot register */
+	printf("QSPI: Reference clock at %d Hz\n", resp_buf[0]);
+	writel(resp_buf[0], &sysmgr_regs->boot_scratch_cold0);
+
+	return 0;
+
+error:
+	mbox_qspi_close();
+
+	return ret;
+}
+#endif /* CONFIG_CADENCE_QSPI */
+
+int mbox_reset_cold(void)
+{
+	int ret;
+
+	ret = mbox_send_cmd(MBOX_ID_UBOOT, MBOX_REBOOT_HPS, MBOX_CMD_DIRECT,
+			    0, NULL, 0, 0, NULL);
+	if (ret) {
+		/* mailbox sent failure, wait for watchdog to kick in */
+		while (1)
+			;
+	}
+	return 0;
+}
+
+int mbox_send_cmd(u8 id, u32 cmd, u8 is_indirect, u32 len, u32 *arg,
+		  u8 urgent, u32 *resp_buf_len, u32 *resp_buf)
+{
+	return __mbox_send_cmd(id, cmd, is_indirect, len, arg, urgent,
+			       resp_buf_len, resp_buf);
+}
+
+int __secure mbox_send_cmd_psci(u8 id, u32 cmd, u8 is_indirect, u32 len,
+				u32 *arg, u8 urgent, u32 *resp_buf_len,
+				u32 *resp_buf)
+{
+	return __mbox_send_cmd(id, cmd, is_indirect, len, arg, urgent,
+			       resp_buf_len, resp_buf);
+}
+
+int mbox_send_cmd_only(u8 id, u32 cmd, u8 is_indirect, u32 len, u32 *arg)
+{
+	return __mbox_send_cmd_only(id, cmd, is_indirect, len, arg);
+}
+
+int __secure mbox_send_cmd_only_psci(u8 id, u32 cmd, u8 is_indirect, u32 len,
+				     u32 *arg)
+{
+	return __mbox_send_cmd_only(id, cmd, is_indirect, len, arg);
+}
+
+int mbox_rcv_resp(u32 *resp_buf, u32 resp_buf_max_len)
+{
+	return __mbox_rcv_resp(resp_buf, resp_buf_max_len);
+}
+
+int __secure mbox_rcv_resp_psci(u32 *resp_buf, u32 resp_buf_max_len)
+{
+	return __mbox_rcv_resp(resp_buf, resp_buf_max_len);
+}
-- 
1.7.1

[U-Boot] [PATCH v1 09/16] arm: socfpga: stratix10: Add MMU support for Stratix10 SoC

[Ley Foon Tan]

Add MMU support for Stratix SoC

Signed-off-by: Chin Liang See <chin.liang.see@intel.com>
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
---
 arch/arm/mach-socfpga/Makefile        |    1 +
 arch/arm/mach-socfpga/mmu-arm64_s10.c |   71 +++++++++++++++++++++++++++++++++
 2 files changed, 72 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/mach-socfpga/mmu-arm64_s10.c

diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index 43e18d2..098e5e9 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -34,6 +34,7 @@ ifdef CONFIG_TARGET_SOCFPGA_STRATIX10
 obj-y	+= clock_manager_s10.o
 obj-y	+= mailbox_s10.o
 obj-y	+= misc_s10.o
+obj-y	+= mmu-arm64_s10.o
 obj-y	+= reset_manager_s10.o
 obj-y	+= system_manager_s10.o
 obj-y	+= wrap_pinmux_config_s10.o
diff --git a/arch/arm/mach-socfpga/mmu-arm64_s10.c b/arch/arm/mach-socfpga/mmu-arm64_s10.c
new file mode 100644
index 0000000..670ceb9
--- /dev/null
+++ b/arch/arm/mach-socfpga/mmu-arm64_s10.c
@@ -0,0 +1,71 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2016-2018 Intel Corporation <www.intel.com>
+ *
+ */
+
+#include <common.h>
+#include <asm/armv8/mmu.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static struct mm_region socfpga_stratix10_mem_map[] = {
+	{
+		/* MEM 2GB*/
+		.virt	= 0x0UL,
+		.phys	= 0x0UL,
+		.size	= 0x80000000UL,
+		.attrs	= PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+				PTE_BLOCK_INNER_SHARE,
+	}, {
+		/* FPGA 1.5GB */
+		.virt	= 0x80000000UL,
+		.phys	= 0x80000000UL,
+		.size	= 0x60000000UL,
+		.attrs	= PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+				PTE_BLOCK_NON_SHARE |
+				PTE_BLOCK_PXN | PTE_BLOCK_UXN,
+	}, {
+		/* DEVICE 142MB */
+		.virt	= 0xF7000000UL,
+		.phys	= 0xF7000000UL,
+		.size	= 0x08E00000UL,
+		.attrs	= PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+				PTE_BLOCK_NON_SHARE |
+				PTE_BLOCK_PXN | PTE_BLOCK_UXN,
+	}, {
+		/* OCRAM 1MB but available 256KB */
+		.virt	= 0xFFE00000UL,
+		.phys	= 0xFFE00000UL,
+		.size	= 0x00100000UL,
+		.attrs	= PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+				PTE_BLOCK_INNER_SHARE,
+	}, {
+		/* DEVICE 32KB */
+		.virt	= 0xFFFC0000UL,
+		.phys	= 0xFFFC0000UL,
+		.size	= 0x00008000UL,
+		.attrs	= PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+				PTE_BLOCK_NON_SHARE |
+				PTE_BLOCK_PXN | PTE_BLOCK_UXN,
+	}, {
+		/* MEM 124GB */
+		.virt	= 0x0100000000UL,
+		.phys	= 0x0100000000UL,
+		.size	= 0x1F00000000UL,
+		.attrs	= PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+				PTE_BLOCK_INNER_SHARE,
+	}, {
+		/* DEVICE 4GB */
+		.virt	= 0x2000000000UL,
+		.phys	= 0x2000000000UL,
+		.size	= 0x0100000000UL,
+		.attrs	= PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+				PTE_BLOCK_NON_SHARE |
+				PTE_BLOCK_PXN | PTE_BLOCK_UXN,
+	}, {
+		/* List terminator */
+	},
+};
+
+struct mm_region *mem_map = socfpga_stratix10_mem_map;
-- 
1.7.1

[U-Boot] [PATCH v1 10/16] arm: dts: Add dts for Stratix10 SoC

[Ley Foon Tan]

Device tree for Stratix10 SoC

Signed-off-by: Chin Liang See <chin.liang.see@intel.com>
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
---
 arch/arm/dts/Makefile                    |    3 +-
 arch/arm/dts/socfpga_stratix10_socdk.dts |  282 ++++++++++++++++++++++++++++++
 2 files changed, 284 insertions(+), 1 deletions(-)
 create mode 100644 arch/arm/dts/socfpga_stratix10_socdk.dts

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 62fbf32..61df5af 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -193,7 +193,8 @@ dtb-$(CONFIG_ARCH_SOCFPGA) +=				\
 	socfpga_cyclone5_sockit.dtb			\
 	socfpga_cyclone5_socrates.dtb			\
 	socfpga_cyclone5_sr1500.dtb			\
-	socfpga_cyclone5_vining_fpga.dtb
+	socfpga_cyclone5_vining_fpga.dtb		\
+	socfpga_stratix10_socdk.dtb
 
 dtb-$(CONFIG_TARGET_DRA7XX_EVM) += dra72-evm.dtb dra7-evm.dtb	\
 	dra72-evm-revc.dtb dra71-evm.dtb dra76-evm.dtb
diff --git a/arch/arm/dts/socfpga_stratix10_socdk.dts b/arch/arm/dts/socfpga_stratix10_socdk.dts
new file mode 100644
index 0000000..bcd34ac
--- /dev/null
+++ b/arch/arm/dts/socfpga_stratix10_socdk.dts
@@ -0,0 +1,282 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2016-2018 Intel Corporation <www.intel.com>
+ *
+ */
+
+/dts-v1/;
+#include "skeleton.dtsi"
+#include <dt-bindings/reset/altr,rst-mgr-s10.h>
+
+/ {
+	model = "Intel SOCFPGA Stratix 10 SoC Development Kit";
+	compatible = "altr,socfpga-stratix10", "altr,socfpga";
+
+	#address-cells = <2>;
+	#size-cells = <1>;
+
+	chosen {
+		bootargs = "console=ttyS0,115200";
+	};
+
+	aliases {
+		ethernet0 = &gmac0;
+		spi0 = &qspi;
+		i2c0 = &i2c;
+		spi1 = &spim0;
+		spi2 = &spim1;
+	};
+
+	memory {
+		name = "memory";
+		device_type = "memory";
+		reg = <0x0 0x0 0x80000000>; /* 2GB */
+	};
+
+	regulator_3_3v: 3-3-v-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "3.3V";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu at 0 {
+			compatible = "arm,cortex-a53", "arm,armv8";
+			device_type = "cpu";
+			enable-method = "psci";
+			reg = <0x0>;
+		};
+
+		cpu at 1 {
+			compatible = "arm,cortex-a53", "arm,armv8";
+			device_type = "cpu";
+			enable-method = "psci";
+			reg = <0x1>;
+		};
+
+		cpu at 2 {
+			compatible = "arm,cortex-a53", "arm,armv8";
+			device_type = "cpu";
+			enable-method = "psci";
+			reg = <0x2>;
+		};
+
+		cpu at 3 {
+			compatible = "arm,cortex-a53", "arm,armv8";
+			device_type = "cpu";
+			enable-method = "psci";
+			reg = <0x3>;
+		};
+	};
+
+	intc: intc at fffc1000 {
+		compatible = "arm,gic-400", "arm,cortex-a15-gic";
+		#interrupt-cells = <3>;
+		interrupt-controller;
+		reg = <0x0 0xfffc1000 0x1000>,
+		      <0x0 0xfffc2000 0x2000>,
+		      <0x0 0xfffc4000 0x2000>,
+		      <0x0 0xfffc6000 0x2000>;
+	};
+
+	soc {
+		#address-cells = <2>;
+		#size-cells = <1>;
+		compatible = "simple-bus";
+		device_type = "soc";
+		ranges;
+		u-boot,dm-pre-reloc;
+
+		rst: rstmgr at ffd11000 {
+			#reset-cells = <1>;
+			compatible = "altr,rst-mgr";
+			reg = <0x0 0xffd11000 0x100>;
+			altr,modrst-offset = <0x20>;
+		};
+
+		gmac0: ethernet at ff800000 {
+			compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a",
+				     "snps,dwmac";
+			reg = <0x0 0xff800000 0x2000>;
+			interrupts = <0 90 4>;
+			interrupt-names = "macirq";
+			interrupt-parent = <&intc>;
+			mac-address = [00 00 00 00 00 00];
+			resets = <&rst EMAC0_RESET>;
+			reset-names = "stmmaceth";
+			phy-mode = "rgmii";
+			phy-addr = <0xffffffff>; /* probe for phy addr */
+			max-speed = <1000>;
+			txd0-skew-ps = <0>; /* -420ps */
+			txd1-skew-ps = <0>; /* -420ps */
+			txd2-skew-ps = <0>; /* -420ps */
+			txd3-skew-ps = <0>; /* -420ps */
+			rxd0-skew-ps = <420>; /* 0ps */
+			rxd1-skew-ps = <420>; /* 0ps */
+			rxd2-skew-ps = <420>; /* 0ps */
+			rxd3-skew-ps = <420>; /* 0ps */
+			txen-skew-ps = <0>; /* -420ps */
+			txc-skew-ps = <1860>; /* 960ps */
+			rxdv-skew-ps = <420>; /* 0ps */
+			rxc-skew-ps = <1680>; /* 780ps */
+			status = "okay";
+		};
+
+		mmc0: dwmmc0 at 0xff808000 {
+			compatible = "altr,socfpga-dw-mshc";
+			reg = <0x0 0xff808000 0x1000>;
+			interrupts = <0 96 4>;
+			interrupt-parent = <&intc>;
+			num-slots = <1>;
+			broken-cd;
+			bus-width = <4>;
+			fifo-depth = <0x400>;
+			cap-mmc-highspeed;
+			cap-sd-highspeed;
+			drvsel = <3>;
+			smplsel = <0>;
+			status = "okay";
+			u-boot,dm-pre-reloc;
+			vmmc-supply = <&regulator_3_3v>;
+			vqmmc-supply = <&regulator_3_3v>;
+		};
+
+		uart0: serial0 at ffc02000 {
+			compatible = "snps,dw-apb-uart";
+			reg = <0x0 0xffc02000 0x1000>;
+			interrupts = <0 108 4>;
+			interrupt-parent = <&intc>;
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			status = "okay";
+		};
+
+		usbphy0: usbphy at 0 {
+			#phy-cells = <0>;
+			compatible = "usb-nop-xceiv";
+			status = "okay";
+		};
+
+		usb0: usb at ffb00000 {
+			compatible = "snps,dwc2";
+			reg = <0x0 0xffb00000 0xffff>;
+			interrupts = <0 93 4>;
+			interrupt-parent = <&intc>;
+			phys = <&usbphy0>;
+			phy-names = "usb2-phy";
+			status = "okay";
+		};
+
+		qspi: spi at ff8d2000 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "cadence,qspi";
+			reg = <0x0 0xff8d2000 0x100>,
+				<0x0 0xff900000 0x100000>;
+			interrupts = <0 98 4>;
+			interrupt-parent = <&intc>;
+			sram-size = <1024>;
+			bus-num = <0>;
+			spi-max-frequency = <50000000>;
+			spi-tx-bus-width = <1>;
+			spi-rx-bus-width = <4>;
+			status = "okay";
+			u-boot,dm-pre-reloc;
+
+			flash0: n25q1024a at 0 {
+				u-boot,dm-pre-reloc;
+				compatible = "stmicro,n25q1024a";
+				reg = <0>;      /* chip select */
+				spi-max-frequency = <50000000>;
+				page-size = <256>;
+				block-size = <16>; /* 2^16, 64KB */
+				tshsl-ns = <50>;
+				tsd2d-ns = <50>;
+				tchsh-ns = <4>;
+				tslch-ns = <4>;
+			};
+		};
+
+		i2c: i2c at ffc02900 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "snps,designware-i2c";
+			reg = <0x0 0xffc02900 0x100>;
+			interrupts = <0 104 0x4>;
+			interrupt-parent = <&intc>;
+			status = "okay";
+		};
+
+		gpio0: gpio at ffc03200 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "snps,dw-apb-gpio";
+			reg = <0x0 0xffc03200 0x100>;
+			status = "disabled";
+
+			porta: gpio-controller at 0 {
+				compatible = "snps,dw-apb-gpio-port";
+				bank-name = "porta";
+				gpio-controller;
+				#gpio-cells = <2>;
+				snps,nr-gpios = <24>;
+				reg = <0>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+				interrupts = <0 110 4>;
+				interrupt-parent = <&intc>;
+			};
+		};
+
+		gpio1: gpio at ffc03300 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "snps,dw-apb-gpio";
+			reg = <0x0 0xffc03300 0x100>;
+			status = "okay";
+
+			portb: gpio-controller at 0 {
+				compatible = "snps,dw-apb-gpio-port";
+				bank-name = "portb";
+				gpio-controller;
+				#gpio-cells = <2>;
+				snps,nr-gpios = <24>;
+				reg = <0>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+				interrupts = <0 111 4>;
+				interrupt-parent = <&intc>;
+			};
+		};
+
+		spim0: spi at ffda4000 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "snps,dw-apb-ssi";
+			reg = <0x0 0xffda4000 0x1000>;
+			interrupts = <0 99 4>;
+			interrupt-parent = <&intc>;
+			num-cs = <1>;
+			bus-num = <0>;
+			spi-max-frequency = <25000000>;
+			status = "okay";
+		};
+
+		spim1: spi at ffda5000 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "snps,dw-apb-ssi";
+			reg = <0x0 0xffda5000 0x1000>;
+			interrupts = <0 100 4>;
+			interrupt-parent = <&intc>;
+			num-cs = <1>;
+			bus-num = <0>;
+			spi-max-frequency = <25000000>;
+			status = "disabled";
+		};
+	};
+};
-- 
1.7.1

[U-Boot] [PATCH v1 11/16] arm: socfpga: Restructure the SPL file

[Ley Foon Tan]

Restructure the SPL so each devices such as CV, A10 and S10
will have their own dedicated SPL file. SPL file determine
the HW initialization flow which is device specific

Signed-off-by: Chin Liang See <chin.liang.see@intel.com>
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
---
 arch/arm/mach-socfpga/Makefile              |    5 +-
 arch/arm/mach-socfpga/spl_a10.c             |  105 +++++++++++++++++++++++++++
 arch/arm/mach-socfpga/{spl.c => spl_gen5.c} |   57 +++------------
 3 files changed, 120 insertions(+), 47 deletions(-)
 create mode 100644 arch/arm/mach-socfpga/spl_a10.c
 rename arch/arm/mach-socfpga/{spl.c => spl_gen5.c} (82%)

diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index 098e5e9..b669d43 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -41,13 +41,16 @@ obj-y	+= wrap_pinmux_config_s10.o
 obj-y	+= wrap_pll_config_s10.o
 endif
 ifdef CONFIG_SPL_BUILD
-obj-y	+= spl.o
 ifdef CONFIG_TARGET_SOCFPGA_GEN5
+obj-y	+= spl_gen5.o
 obj-y	+= freeze_controller.o
 obj-y	+= wrap_iocsr_config.o
 obj-y	+= wrap_pinmux_config.o
 obj-y	+= wrap_sdram_config.o
 endif
+ifdef CONFIG_TARGET_SOCFPGA_ARRIA10
+obj-y	+= spl_a10.o
+endif
 endif
 
 ifdef CONFIG_TARGET_SOCFPGA_GEN5
diff --git a/arch/arm/mach-socfpga/spl_a10.c b/arch/arm/mach-socfpga/spl_a10.c
new file mode 100644
index 0000000..e6fc766
--- /dev/null
+++ b/arch/arm/mach-socfpga/spl_a10.c
@@ -0,0 +1,105 @@
+/*
+ *  Copyright (C) 2012 Altera Corporation <www.altera.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/pl310.h>
+#include <asm/u-boot.h>
+#include <asm/utils.h>
+#include <image.h>
+#include <asm/arch/reset_manager.h>
+#include <spl.h>
+#include <asm/arch/system_manager.h>
+#include <asm/arch/freeze_controller.h>
+#include <asm/arch/clock_manager.h>
+#include <asm/arch/scan_manager.h>
+#include <asm/arch/sdram.h>
+#include <asm/arch/scu.h>
+#include <asm/arch/nic301.h>
+#include <asm/sections.h>
+#include <fdtdec.h>
+#include <watchdog.h>
+#include <asm/arch/pinmux.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static const struct socfpga_system_manager *sysmgr_regs =
+	(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
+
+u32 spl_boot_device(void)
+{
+	const u32 bsel = readl(&sysmgr_regs->bootinfo);
+
+	switch (SYSMGR_GET_BOOTINFO_BSEL(bsel)) {
+	case 0x1:	/* FPGA (HPS2FPGA Bridge) */
+		return BOOT_DEVICE_RAM;
+	case 0x2:	/* NAND Flash (1.8V) */
+	case 0x3:	/* NAND Flash (3.0V) */
+		socfpga_per_reset(SOCFPGA_RESET(NAND), 0);
+		return BOOT_DEVICE_NAND;
+	case 0x4:	/* SD/MMC External Transceiver (1.8V) */
+	case 0x5:	/* SD/MMC Internal Transceiver (3.0V) */
+		socfpga_per_reset(SOCFPGA_RESET(SDMMC), 0);
+		socfpga_per_reset(SOCFPGA_RESET(DMA), 0);
+		return BOOT_DEVICE_MMC1;
+	case 0x6:	/* QSPI Flash (1.8V) */
+	case 0x7:	/* QSPI Flash (3.0V) */
+		socfpga_per_reset(SOCFPGA_RESET(QSPI), 0);
+		return BOOT_DEVICE_SPI;
+	default:
+		printf("Invalid boot device (bsel=%08x)!\n", bsel);
+		hang();
+	}
+}
+
+#ifdef CONFIG_SPL_MMC_SUPPORT
+u32 spl_boot_mode(const u32 boot_device)
+{
+#if defined(CONFIG_SPL_FAT_SUPPORT) || defined(CONFIG_SPL_EXT_SUPPORT)
+	return MMCSD_MODE_FS;
+#else
+	return MMCSD_MODE_RAW;
+#endif
+}
+#endif
+
+void spl_board_init(void)
+{
+	/* configuring the clock based on handoff */
+	cm_basic_init(gd->fdt_blob);
+	WATCHDOG_RESET();
+
+	config_dedicated_pins(gd->fdt_blob);
+	WATCHDOG_RESET();
+
+	/* Release UART from reset */
+	socfpga_reset_uart(0);
+
+	/* enable console uart printing */
+	preloader_console_init();
+}
+
+void board_init_f(ulong dummy)
+{
+	/*
+	 * Configure Clock Manager to use intosc clock instead external osc to
+	 * ensure success watchdog operation. We do it as early as possible.
+	 */
+	cm_use_intosc();
+
+	socfpga_watchdog_disable();
+
+	arch_early_init_r();
+
+#ifdef CONFIG_HW_WATCHDOG
+	/* release osc1 watchdog timer 0 from reset */
+	socfpga_reset_deassert_osc1wd0();
+
+	/* reconfigure and enable the watchdog */
+	hw_watchdog_init();
+	WATCHDOG_RESET();
+#endif /* CONFIG_HW_WATCHDOG */
+}
diff --git a/arch/arm/mach-socfpga/spl.c b/arch/arm/mach-socfpga/spl_gen5.c
similarity index 82%
rename from arch/arm/mach-socfpga/spl.c
rename to arch/arm/mach-socfpga/spl_gen5.c
index 9bf3b9a..9864082 100644
--- a/arch/arm/mach-socfpga/spl.c
+++ b/arch/arm/mach-socfpga/spl_gen5.c
@@ -22,21 +22,15 @@
 #include <asm/sections.h>
 #include <fdtdec.h>
 #include <watchdog.h>
-#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
-#include <asm/arch/pinmux.h>
-#endif
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
 static struct pl310_regs *const pl310 =
 	(struct pl310_regs *)CONFIG_SYS_PL310_BASE;
 static struct scu_registers *scu_regs =
 	(struct scu_registers *)SOCFPGA_MPUSCU_ADDRESS;
 static struct nic301_registers *nic301_regs =
 	(struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS;
-#endif
-
 static const struct socfpga_system_manager *sysmgr_regs =
 	(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
 
@@ -66,7 +60,17 @@ u32 spl_boot_device(void)
 	}
 }
 
-#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
+#ifdef CONFIG_SPL_MMC_SUPPORT
+u32 spl_boot_mode(const u32 boot_device)
+{
+#if defined(CONFIG_SPL_FAT_SUPPORT) || defined(CONFIG_SPL_EXT_SUPPORT)
+	return MMCSD_MODE_FS;
+#else
+	return MMCSD_MODE_RAW;
+#endif
+}
+#endif
+
 static void socfpga_nic301_slave_ns(void)
 {
 	writel(0x1, &nic301_regs->lwhps2fpgaregs);
@@ -182,42 +186,3 @@ void board_init_f(ulong dummy)
 	/* Configure simple malloc base pointer into RAM. */
 	gd->malloc_base = CONFIG_SYS_TEXT_BASE + (1024 * 1024);
 }
-#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
-void spl_board_init(void)
-{
-	/* configuring the clock based on handoff */
-	cm_basic_init(gd->fdt_blob);
-	WATCHDOG_RESET();
-
-	config_dedicated_pins(gd->fdt_blob);
-	WATCHDOG_RESET();
-
-	/* Release UART from reset */
-	socfpga_reset_uart(0);
-
-	/* enable console uart printing */
-	preloader_console_init();
-}
-
-void board_init_f(ulong dummy)
-{
-	/*
-	 * Configure Clock Manager to use intosc clock instead external osc to
-	 * ensure success watchdog operation. We do it as early as possible.
-	 */
-	cm_use_intosc();
-
-	socfpga_watchdog_disable();
-
-	arch_early_init_r();
-
-#ifdef CONFIG_HW_WATCHDOG
-	/* release osc1 watchdog timer 0 from reset */
-	socfpga_reset_deassert_osc1wd0();
-
-	/* reconfigure and enable the watchdog */
-	hw_watchdog_init();
-	WATCHDOG_RESET();
-#endif /* CONFIG_HW_WATCHDOG */
-}
-#endif
-- 
1.7.1

[U-Boot] [PATCH v1 12/16] arm: socfpga: stratix10: Add SPL driver for Stratix10 SoC

[Ley Foon Tan]

Add SPL driver support for Stratix SoC

Signed-off-by: Chin Liang See <chin.liang.see@intel.com>
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
---
 arch/arm/mach-socfpga/Makefile                    |    4 +
 arch/arm/mach-socfpga/include/mach/firewall_s10.h |   84 +++++++++
 arch/arm/mach-socfpga/spl_s10.c                   |  205 +++++++++++++++++++++
 3 files changed, 293 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/mach-socfpga/include/mach/firewall_s10.h
 create mode 100644 arch/arm/mach-socfpga/spl_s10.c

diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index b669d43..35b124a 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -40,6 +40,7 @@ obj-y	+= system_manager_s10.o
 obj-y	+= wrap_pinmux_config_s10.o
 obj-y	+= wrap_pll_config_s10.o
 endif
+
 ifdef CONFIG_SPL_BUILD
 ifdef CONFIG_TARGET_SOCFPGA_GEN5
 obj-y	+= spl_gen5.o
@@ -51,6 +52,9 @@ endif
 ifdef CONFIG_TARGET_SOCFPGA_ARRIA10
 obj-y	+= spl_a10.o
 endif
+ifdef CONFIG_TARGET_SOCFPGA_STRATIX10
+obj-y	+= spl_s10.o
+endif
 endif
 
 ifdef CONFIG_TARGET_SOCFPGA_GEN5
diff --git a/arch/arm/mach-socfpga/include/mach/firewall_s10.h b/arch/arm/mach-socfpga/include/mach/firewall_s10.h
new file mode 100644
index 0000000..70aa9a6
--- /dev/null
+++ b/arch/arm/mach-socfpga/include/mach/firewall_s10.h
@@ -0,0 +1,84 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright (C) 2017-2018 Intel Corporation <www.intel.com>
+ *
+ */
+
+#ifndef	_FIREWALL_S10_
+#define	_FIREWALL_S10_
+
+struct socfpga_firwall_l4_per {
+	u32	nand;		/* 0x00 */
+	u32	nand_data;
+	u32	_pad_0x8;
+	u32	usb0;
+	u32	usb1;		/* 0x10 */
+	u32	_pad_0x14;
+	u32	_pad_0x18;
+	u32	spim0;
+	u32	spim1;		/* 0x20 */
+	u32	spis0;
+	u32	spis1;
+	u32	emac0;
+	u32	emac1;		/* 0x30 */
+	u32	emac2;
+	u32	_pad_0x38;
+	u32	_pad_0x3c;
+	u32	sdmmc;		/* 0x40 */
+	u32	gpio0;
+	u32	gpio1;
+	u32	_pad_0x4c;
+	u32	i2c0;		/* 0x50 */
+	u32	i2c1;
+	u32	i2c2;
+	u32	i2c3;
+	u32	i2c4;		/* 0x60 */
+	u32	timer0;
+	u32	timer1;
+	u32	uart0;
+	u32	uart1;		/* 0x70 */
+};
+
+struct socfpga_firwall_l4_sys {
+	u32	_pad_0x00;		/* 0x00 */
+	u32	_pad_0x04;
+	u32	dma_ecc;
+	u32	emac0rx_ecc;
+	u32	emac0tx_ecc;		/* 0x10 */
+	u32	emac1rx_ecc;
+	u32	emac1tx_ecc;
+	u32	emac2rx_ecc;
+	u32	emac2tx_ecc;		/* 0x20 */
+	u32	_pad_0x24;
+	u32	_pad_0x28;
+	u32	nand_ecc;
+	u32	nand_read_ecc;		/* 0x30 */
+	u32	nand_write_ecc;
+	u32	ocram_ecc;
+	u32	_pad_0x3c;
+	u32	sdmmc_ecc;		/* 0x40 */
+	u32	usb0_ecc;
+	u32	usb1_ecc;
+	u32	clock_manager;
+	u32	_pad_0x50;		/* 0x50 */
+	u32	io_manager;
+	u32	reset_manager;
+	u32	system_manager;
+	u32	osc0_timer;		/* 0x60 */
+	u32	osc1_timer;
+	u32	watchdog0;
+	u32	watchdog1;
+	u32	watchdog2;		/* 0x70 */
+	u32	watchdog3;
+};
+
+#define FIREWALL_L4_DISABLE_ALL		(BIT(0) | BIT(24) | BIT(16))
+#define FIREWALL_BRIDGE_DISABLE_ALL	(~0)
+
+#define CCU_CPU0_MPRT_ADMASK_MEM_RAM0_ADDR	0xf7004688
+#define CCU_IOM_MPRT_ADMASK_MEM_RAM0_ADDR	0xf7018628
+
+#define CCU_ADMASK_P_MASK			(BIT(0))
+#define CCU_ADMASK_NS_MASK			(BIT(1))
+
+#endif /* _FIREWALL_S10_ */
diff --git a/arch/arm/mach-socfpga/spl_s10.c b/arch/arm/mach-socfpga/spl_s10.c
new file mode 100644
index 0000000..3b3833d
--- /dev/null
+++ b/arch/arm/mach-socfpga/spl_s10.c
@@ -0,0 +1,205 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2016-2018 Intel Corporation <www.intel.com>
+ *
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/u-boot.h>
+#include <asm/utils.h>
+#include <image.h>
+#include <asm/arch/reset_manager.h>
+#include <spl.h>
+#include <asm/arch/system_manager.h>
+#include <asm/arch/clock_manager.h>
+#include <asm/arch/sdram_s10.h>
+#include <asm/arch/mailbox_s10.h>
+#include <asm/arch/firewall_s10.h>
+#include <watchdog.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static const struct socfpga_firwall_l4_per *firwall_l4_per_base =
+	(struct socfpga_firwall_l4_per *)SOCFPGA_FIREWALL_L4_PER;
+static const struct socfpga_firwall_l4_sys *firwall_l4_sys_base =
+	(struct socfpga_firwall_l4_sys *)SOCFPGA_FIREWALL_L4_SYS;
+static struct socfpga_system_manager *sysmgr_regs =
+	(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
+
+u32 spl_boot_device(void)
+{
+	/* TODO: Get from SDM or handoff */
+	return BOOT_DEVICE_MMC1;
+}
+
+#ifdef CONFIG_SPL_MMC_SUPPORT
+u32 spl_boot_mode(const u32 boot_device)
+{
+#if defined(CONFIG_SPL_FAT_SUPPORT) || defined(CONFIG_SPL_EXT_SUPPORT)
+	return MMCSD_MODE_FS;
+#else
+	return MMCSD_MODE_RAW;
+#endif
+}
+#endif
+
+void board_init_f(ulong dummy)
+{
+	const struct cm_config *cm_default_cfg = cm_get_default_config();
+
+#ifdef CONFIG_HW_WATCHDOG
+	/* Ensure watchdog is paused when debugging is happening */
+	writel(SYSMGR_WDDBG_PAUSE_ALL_CPU, &sysmgr_regs->wddbg);
+
+	/* Enable watchdog before initializing the HW */
+	socfpga_per_reset(SOCFPGA_RESET(L4WD0), 1);
+	socfpga_per_reset(SOCFPGA_RESET(L4WD0), 0);
+	hw_watchdog_init();
+#endif
+
+	/* ensure all processors are not released prior Linux boot */
+	writeq(0, CPU_RELEASE_ADDR);
+
+	socfpga_per_reset(SOCFPGA_RESET(OSC1TIMER0), 0);
+	timer_init();
+
+	populate_sysmgr_pinmux();
+
+	/* configuring the HPS clocks */
+	cm_basic_init(cm_default_cfg);
+
+	/* enable console uart printing */
+#if (CONFIG_SYS_NS16550_COM1 == SOCFPGA_UART0_ADDRESS)
+	socfpga_per_reset(SOCFPGA_RESET(UART0), 0);
+	/* enables nonsecure access to UART0 */
+	writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_per_base->uart0);
+#elif (CONFIG_SYS_NS16550_COM1 == SOCFPGA_UART1_ADDRESS)
+	socfpga_per_reset(SOCFPGA_RESET(UART1), 0);
+	/* enables nonsecure access to UART1 */
+	writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_per_base->uart1);
+#endif
+
+	preloader_console_init();
+	cm_print_clock_quick_summary();
+
+	/* enable non-secure interface to DMA330 DMA and peripherals */
+	writel(SYSMGR_DMA_IRQ_NS | SYSMGR_DMA_MGR_NS, &sysmgr_regs->dma);
+	writel(SYSMGR_DMAPERIPH_ALL_NS, &sysmgr_regs->dma_periph);
+	/* enable DMA330 DMA */
+	socfpga_per_reset(SOCFPGA_RESET(DMA), 0);
+
+	/*
+	 * The following lines of code will enable non-secure access
+	 * to nand, usb, spi, emac, sdmmc, gpio, i2c, and timers. This
+	 * is needed as most OS run in non-secure mode. Thus we need to
+	 * enable non-secure access to these peripherals in order for the
+	 * OS to use these peripherals.
+	 */
+	writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_per_base->nand);
+	writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_per_base->nand_data);
+	writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_per_base->usb0);
+	writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_per_base->usb1);
+	writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_per_base->spim0);
+	writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_per_base->spim1);
+	writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_per_base->emac0);
+	writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_per_base->emac1);
+	writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_per_base->emac2);
+	writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_per_base->sdmmc);
+	writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_sys_base->sdmmc_ecc);
+	writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_per_base->gpio0);
+	writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_per_base->gpio1);
+	writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_per_base->i2c0);
+	writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_per_base->i2c1);
+	writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_per_base->i2c2);
+	writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_per_base->i2c3);
+	writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_per_base->i2c4);
+	writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_per_base->timer0);
+	writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_per_base->timer1);
+
+	/* enables nonsecure access to clock mgr */
+	writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_sys_base->clock_manager);
+
+	/* enables nonsecure access to reset mgr */
+	writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_sys_base->reset_manager);
+
+	/* enables nonsecure access to system mgr */
+	writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_sys_base->system_manager);
+
+	/* enables nonsecure access to OCRAM */
+	writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_sys_base->ocram_ecc);
+
+	/* enables nonsecure access to all the emacs */
+	writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_sys_base->emac0rx_ecc);
+	writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_sys_base->emac0tx_ecc);
+	writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_sys_base->emac1rx_ecc);
+	writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_sys_base->emac1tx_ecc);
+	writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_sys_base->emac2rx_ecc);
+	writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_sys_base->emac2tx_ecc);
+
+	/* enables nonsecure access to SMMU */
+	writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_sys_base->io_manager);
+
+	/* enables nonsecure access to watchdog */
+	writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_sys_base->watchdog0);
+	writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_sys_base->watchdog1);
+	writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_sys_base->watchdog2);
+	writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_sys_base->watchdog3);
+
+	/* enables SDMMC */
+	socfpga_per_reset(SOCFPGA_RESET(SDMMC_OCP), 0);
+	socfpga_per_reset(SOCFPGA_RESET(SDMMC), 0);
+	/* enable usb0 and usb1 */
+	socfpga_per_reset(SOCFPGA_RESET(USB0), 0);
+	socfpga_per_reset(SOCFPGA_RESET(USB1), 0);
+	socfpga_per_reset(SOCFPGA_RESET(USB0_OCP), 0);
+	socfpga_per_reset(SOCFPGA_RESET(USB1_OCP), 0);
+	/* enable SPIM1 */
+	socfpga_per_reset(SOCFPGA_RESET(SPIM1), 0);
+
+	/* disable lwsocf2fpga and soc2fpga bridge security */
+	writel(FIREWALL_BRIDGE_DISABLE_ALL, SOCFPGA_FIREWALL_SOC2FPGA);
+	writel(FIREWALL_BRIDGE_DISABLE_ALL, SOCFPGA_FIREWALL_LWSOC2FPGA);
+
+	/* disable SMMU security */
+	writel(FIREWALL_L4_DISABLE_ALL, SOCFPGA_FIREWALL_TCU);
+
+	/* disable ocram security at CCU for non secure access */
+	clrbits_le32(CCU_CPU0_MPRT_ADMASK_MEM_RAM0_ADDR,
+		     CCU_ADMASK_P_MASK | CCU_ADMASK_NS_MASK);
+	clrbits_le32(CCU_IOM_MPRT_ADMASK_MEM_RAM0_ADDR,
+		     CCU_ADMASK_P_MASK | CCU_ADMASK_NS_MASK);
+
+	/* enable i2c1 */
+	socfpga_per_reset(SOCFPGA_RESET(I2C1), 0);
+
+	/* Take GPIO0 & GPIO1 out of reset */
+	socfpga_per_reset(SOCFPGA_RESET(GPIO0), 0);
+	socfpga_per_reset(SOCFPGA_RESET(GPIO1), 0);
+
+	/* enable SPIM0 and SPIM1 */
+	socfpga_per_reset(SOCFPGA_RESET(SPIM0), 0);
+	socfpga_per_reset(SOCFPGA_RESET(SPIM1), 0);
+
+	puts("DDR: Initializing Hard Memory Controller\n");
+	if (sdram_mmr_init_full(0)) {
+		puts("DDR: Initialization failed.\n");
+		hang();
+	}
+
+	gd->ram_size = sdram_calculate_size();
+	printf("DDR: %d MiB\n", (int)(gd->ram_size >> 20));
+
+	/* Sanity check ensure correct SDRAM size specified */
+	puts("DDR: Running SDRAM size sanity check\n");
+	if (get_ram_size(0, gd->ram_size) != gd->ram_size) {
+		puts("DDR: SDRAM size check failed!\n");
+		hang();
+	}
+	puts("DDR: SDRAM size check passed!\n");
+
+#ifdef CONFIG_CADENCE_QSPI
+	mbox_init();
+	mbox_qspi_open();
+#endif
+}
-- 
1.7.1

[U-Boot] [PATCH v1 13/16] arm: socfpga: stratix10: Add timer support for Stratix10 SoC

[Ley Foon Tan]

Add timer support for Stratix SoC

Signed-off-by: Chin Liang See <chin.liang.see@intel.com>
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
---
 arch/arm/mach-socfpga/timer.c |   17 ++++++++++++++++-
 1 files changed, 16 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-socfpga/timer.c b/arch/arm/mach-socfpga/timer.c
index 253cde3..4c90b57 100644
--- a/arch/arm/mach-socfpga/timer.c
+++ b/arch/arm/mach-socfpga/timer.c
@@ -1,5 +1,6 @@
 /*
- *  Copyright (C) 2012 Altera Corporation <www.altera.com>
+ * Copyright (C) 2016-2018 Intel Corporation <www.intel.com>
+ * Copyright (C) 2012-2016 Altera Corporation <www.altera.com>
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
@@ -10,15 +11,29 @@
 
 #define TIMER_LOAD_VAL		0xFFFFFFFF
 
+#if !defined(CONFIG_TARGET_SOCFPGA_STRATIX10)
 static const struct socfpga_timer *timer_base = (void *)CONFIG_SYS_TIMERBASE;
+#endif
 
 /*
  * Timer initialization
  */
 int timer_init(void)
 {
+#if defined(CONFIG_TARGET_SOCFPGA_STRATIX10)
+	int enable = 0x3;	/* timer enable + output signal masked */
+	int loadval = ~0;
+
+	/* enable system counter */
+	writel(enable, SOCFPGA_GTIMER_SEC_ADDRESS);
+	/* enable processor pysical counter */
+	asm volatile("msr cntp_ctl_el0, %0" : : "r" (enable));
+	asm volatile("msr cntp_tval_el0, %0" : : "r" (loadval));
+
+#else
 	writel(TIMER_LOAD_VAL, &timer_base->load_val);
 	writel(TIMER_LOAD_VAL, &timer_base->curr_val);
 	writel(readl(&timer_base->ctrl) | 0x3, &timer_base->ctrl);
+#endif
 	return 0;
 }
-- 
1.7.1

[U-Boot] [PATCH v1 14/16] ddr: altera: stratix10: Add DDR support for Stratix10 SoC

[Ley Foon Tan]

Add DDR support for Stratix SoC

Signed-off-by: Chin Liang See <chin.liang.see@intel.com>
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
---
 arch/arm/mach-socfpga/include/mach/sdram_s10.h |  340 ++++++++++++++++++++
 drivers/ddr/altera/Makefile                    |    1 +
 drivers/ddr/altera/sdram_s10.c                 |  392 ++++++++++++++++++++++++
 3 files changed, 733 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/mach-socfpga/include/mach/sdram_s10.h
 create mode 100644 drivers/ddr/altera/sdram_s10.c

diff --git a/arch/arm/mach-socfpga/include/mach/sdram_s10.h b/arch/arm/mach-socfpga/include/mach/sdram_s10.h
new file mode 100644
index 0000000..6ce5180
--- /dev/null
+++ b/arch/arm/mach-socfpga/include/mach/sdram_s10.h
@@ -0,0 +1,340 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright (C) 2017-2018 Intel Corporation <www.intel.com>
+ *
+ */
+
+#ifndef	_SDRAM_S10_H_
+#define	_SDRAM_S10_H_
+
+unsigned long sdram_calculate_size(void);
+int sdram_mmr_init_full(unsigned int sdr_phy_reg);
+int sdram_calibration_full(void);
+
+#define DDR_TWR				15
+#define DDR_READ_LATENCY_DELAY		40
+#define DDR_ACTIVATE_FAWBANK		0x1
+
+struct socfpga_ecc_hmc {
+	u32 ip_rev_id;
+	u32 _pad_0x4_0x7;
+	u32 ddrioctrl;
+	u32 ddrcalstat;
+	u32 mpr_0beat1;
+	u32 mpr_1beat1;
+	u32 mpr_2beat1;
+	u32 mpr_3beat1;
+	u32 mpr_4beat1;
+	u32 mpr_5beat1;
+	u32 mpr_6beat1;
+	u32 mpr_7beat1;
+	u32 mpr_8beat1;
+	u32 mpr_0beat2;
+	u32 mpr_1beat2;
+	u32 mpr_2beat2;
+	u32 mpr_3beat2;
+	u32 mpr_4beat2;
+	u32 mpr_5beat2;
+	u32 mpr_6beat2;
+	u32 mpr_7beat2;
+	u32 mpr_8beat2;
+	u32 _pad_0x58_0x5f[2];
+	u32 auto_precharge;
+	u32 _pad_0x64_0xdf[31];
+	u32 dramaddrwidth;
+	u32 _pad_0xe4_0xff[7];
+	u32 eccctrl;
+	u32 eccctrl2;
+	u32 _pad_0x108_0x10f[2];
+	u32 errinten;
+	u32 errintens;
+	u32 errintenr;
+	u32 intmode;
+	u32 intstat;
+	u32 diaginttest;
+	u32 modstat;
+	u32 derraddra;
+	u32 serraddra;
+	u32 _pad_0x134_0x137;
+	u32 autowb_corraddr;
+	u32 serrcntreg;
+	u32 autowb_drop_cntreg;
+	u32 ecc_reg2wreccdatabus;
+	u32 ecc_rdeccdata2regbus;
+	u32 ecc_reg2rdeccdatabus;
+	u32 ecc_diagon;
+	u32 ecc_decstat;
+	u32 _pad_0x158_0x15f[2];
+	u32 ecc_errgenaddr_0;
+	u32 ecc_errgenaddr_1;
+	u32 ecc_errgenaddr_2;
+	u32 ecc_errgenaddr_3;
+	u32 ecc_ref2rddatabus_beat0;
+	u32 ecc_ref2rddatabus_beat1;
+	u32 ecc_ref2rddatabus_beat2;
+	u32 ecc_ref2rddatabus_beat3;
+	u32 ecc_errgenhaddr_0;
+	u32 ecc_errgenhaddr_1;
+	u32 ecc_errgenhaddr_2;
+	u32 ecc_errgenhaddr_3;
+	u32 ecc_rdeccdata2regbus_beat0;
+	u32 ecc_rdeccdata2regbus_beat1;
+	u32 ecc_rdeccdata2regbus_beat2;
+	u32 ecc_rdeccdata2regbus_beat3;
+	u32 _pad_0x1a0_0x1af[4];
+	u32 derrhaddr;
+	u32 serrhaddr;
+	u32 _pad_0x1b8_0x1bb;
+	u32 autowb_corrhaddr;
+	u32 _pad_0x1c0_0x20f[20];
+	u32 hpsintfcsel;
+	u32 rsthandshakectrl;
+	u32 rsthandshakestat;
+};
+
+struct socfpga_noc_ddr_scheduler {
+	u32 main_scheduler_id_coreid;
+	u32 main_scheduler_id_revisionid;
+	u32 main_scheduler_ddrconf;
+	u32 main_scheduler_ddrtiming;
+	u32 main_scheduler_ddrmode;
+	u32 main_scheduler_readlatency;
+	u32 _pad_0x18_0x37[8];
+	u32 main_scheduler_activate;
+	u32 main_scheduler_devtodev;
+	u32 main_scheduler_ddr4timing;
+};
+
+struct socfpga_io48_mmr {
+	u32 dbgcfg0;
+	u32 dbgcfg1;
+	u32 dbgcfg2;
+	u32 dbgcfg3;
+	u32 dbgcfg4;
+	u32 dbgcfg5;
+	u32 dbgcfg6;
+	u32 reserve0;
+	u32 reserve1;
+	u32 reserve2;
+	u32 ctrlcfg0;
+	u32 ctrlcfg1;
+	u32 ctrlcfg2;
+	u32 ctrlcfg3;
+	u32 ctrlcfg4;
+	u32 ctrlcfg5;
+	u32 ctrlcfg6;
+	u32 ctrlcfg7;
+	u32 ctrlcfg8;
+	u32 ctrlcfg9;
+	u32 dramtiming0;
+	u32 dramodt0;
+	u32 dramodt1;
+	u32 sbcfg0;
+	u32 sbcfg1;
+	u32 sbcfg2;
+	u32 sbcfg3;
+	u32 sbcfg4;
+	u32 sbcfg5;
+	u32 sbcfg6;
+	u32 sbcfg7;
+	u32 caltiming0;
+	u32 caltiming1;
+	u32 caltiming2;
+	u32 caltiming3;
+	u32 caltiming4;
+	u32 caltiming5;
+	u32 caltiming6;
+	u32 caltiming7;
+	u32 caltiming8;
+	u32 caltiming9;
+	u32 caltiming10;
+	u32 dramaddrw;
+	u32 sideband0;
+	u32 sideband1;
+	u32 sideband2;
+	u32 sideband3;
+	u32 sideband4;
+	u32 sideband5;
+	u32 sideband6;
+	u32 sideband7;
+	u32 sideband8;
+	u32 sideband9;
+	u32 sideband10;
+	u32 sideband11;
+	u32 sideband12;
+	u32 sideband13;
+	u32 sideband14;
+	u32 sideband15;
+	u32 dramsts;
+	u32 dbgdone;
+	u32 dbgsignals;
+	u32 dbgreset;
+	u32 dbgmatch;
+	u32 counter0mask;
+	u32 counter1mask;
+	u32 counter0match;
+	u32 counter1match;
+	u32 niosreserve0;
+	u32 niosreserve1;
+	u32 niosreserve2;
+};
+
+union dramaddrw_reg {
+	struct {
+		u32 cfg_col_addr_width:5;
+		u32 cfg_row_addr_width:5;
+		u32 cfg_bank_addr_width:4;
+		u32 cfg_bank_group_addr_width:2;
+		u32 cfg_cs_addr_width:3;
+		u32 reserved:13;
+	};
+	u32 word;
+};
+
+union ctrlcfg0_reg {
+	struct {
+		u32 cfg_mem_type:4;
+		u32 cfg_dimm_type:3;
+		u32 cfg_ac_pos:2;
+		u32 cfg_ctrl_burst_len:5;
+		u32 reserved:18;  /* Other fields unused */
+	};
+	u32 word;
+};
+
+union ctrlcfg1_reg {
+	struct {
+		u32 cfg_dbc3_burst_len:5;
+		u32 cfg_addr_order:2;
+		u32 cfg_ctrl_enable_ecc:1;
+		u32 reserved:24;  /* Other fields unused */
+	};
+	u32 word;
+};
+
+union dramtiming0_reg {
+	struct {
+		u32 cfg_tcl:6;
+		u32 reserved:8;  /* Other fields unused */
+	};
+	u32 word;
+};
+
+union caltiming0_reg {
+	struct {
+		u32 cfg_act_to_rdwr:6;
+		u32 cfg_act_to_pch:6;
+		u32 cfg_act_to_act:6;
+		u32 cfg_act_to_act_db:6;
+		u32 reserved:8;  /* Other fields unused */
+	};
+	u32 word;
+};
+
+union caltiming1_reg {
+	struct {
+		u32 cfg_rd_to_rd:6;
+		u32 cfg_rd_to_rd_dc:6;
+		u32 cfg_rd_to_rd_db:6;
+		u32 cfg_rd_to_wr:6;
+		u32 cfg_rd_to_wr_dc:6;
+		u32 reserved:2;
+	};
+	u32 word;
+};
+
+union caltiming2_reg {
+	struct {
+		u32 cfg_rd_to_wr_db:6;
+		u32 cfg_rd_to_pch:6;
+		u32 cfg_rd_ap_to_valid:6;
+		u32 cfg_wr_to_wr:6;
+		u32 cfg_wr_to_wr_dc:6;
+		u32 reserved:2;
+	};
+	u32 word;
+};
+
+union caltiming3_reg {
+	struct {
+		u32 cfg_wr_to_wr_db:6;
+		u32 cfg_wr_to_rd:6;
+		u32 cfg_wr_to_rd_dc:6;
+		u32 cfg_wr_to_rd_db:6;
+		u32 cfg_wr_to_pch:6;
+		u32 reserved:2;
+	};
+	u32 word;
+};
+
+union caltiming4_reg {
+	struct {
+		u32 cfg_wr_ap_to_valid:6;
+		u32 cfg_pch_to_valid:6;
+		u32 cfg_pch_all_to_valid:6;
+		u32 cfg_arf_to_valid:8;
+		u32 cfg_pdn_to_valid:6;
+	};
+	u32 word;
+};
+
+union caltiming9_reg {
+	struct {
+		u32 cfg_4_act_to_act:8;
+		u32 reserved:24;
+	};
+	u32 word;
+};
+
+#define DDR_SCHED_DDRTIMING_ACTTOACT_OFFSET	0
+#define DDR_SCHED_DDRTIMING_RDTOMISS_OFFSET	6
+#define DDR_SCHED_DDRTIMING_WRTOMISS_OFFSET	12
+#define DDR_SCHED_DDRTIMING_BURSTLEN_OFFSET	18
+#define DDR_SCHED_DDRTIMING_RDTOWR_OFFSET	21
+#define DDR_SCHED_DDRTIMING_WRTORD_OFFSET	26
+#define DDR_SCHED_DDRTIMING_BWRATIO_OFFSET	31
+#define DDR_SCHED_DDRMOD_BWRATIOEXTENDED_OFFSET	1
+#define DDR_SCHED_ACTIVATE_RRD_OFFSET		0
+#define DDR_SCHED_ACTIVATE_FAW_OFFSET		4
+#define DDR_SCHED_ACTIVATE_FAWBANK_OFFSET	10
+#define DDR_SCHED_DEVTODEV_BUSRDTORD_OFFSET	0
+#define DDR_SCHED_DEVTODEV_BUSRDTOWR_OFFSET	2
+#define DDR_SCHED_DEVTODEV_BUSWRTORD_OFFSET	4
+#define DDR_HMC_DDRIOCTRL_IOSIZE_MSK		0x00000003
+#define DDR_HMC_DDRCALSTAT_CAL_MSK		0x00000001
+#define DDR_HMC_ECCCTL_AWB_CNT_RST_SET_MSK	0x00010000
+#define DDR_HMC_ECCCTL_CNT_RST_SET_MSK		0x00000100
+#define DDR_HMC_ECCCTL_ECC_EN_SET_MSK		0x00000001
+#define DDR_HMC_ECCCTL2_RMW_EN_SET_MSK		0x00000100
+#define DDR_HMC_ECCCTL2_AWB_EN_SET_MSK		0x00000001
+#define DDR_HMC_ECC_DIAGON_ECCDIAGON_EN_SET_MSK	0x00010000
+#define DDR_HMC_ECC_DIAGON_WRDIAGON_EN_SET_MSK	0x00000001
+#define DDR_HMC_ERRINTEN_SERRINTEN_EN_SET_MSK	0x00000001
+#define DDR_HMC_ERRINTEN_DERRINTEN_EN_SET_MSK	0x00000002
+#define DDR_HMC_INTSTAT_SERRPENA_SET_MSK	0x00000001
+#define DDR_HMC_INTSTAT_DERRPENA_SET_MSK	0x00000002
+#define DDR_HMC_INTSTAT_ADDRMTCFLG_SET_MSK	0x00010000
+#define DDR_HMC_INTMODE_INTMODE_SET_MSK		0x00000001
+#define DDR_HMC_RSTHANDSHAKE_MASK		0x000000ff
+#define DDR_HMC_CORE2SEQ_INT_REQ		0xF
+#define DDR_HMC_SEQ2CORE_INT_RESP_MASK		0x8
+#define DDR_HMC_HPSINTFCSEL_ENABLE_MASK		0x001f1f1f
+
+#define CCU_CPU0_MPRT_ADBASE_DDRREG_ADDR	0xf7004400
+#define CCU_CPU0_MPRT_ADBASE_MEMSPACE0_ADDR	0xf70045c0
+#define CCU_CPU0_MPRT_ADBASE_MEMSPACE1A_ADDR	0xf70045e0
+#define CCU_CPU0_MPRT_ADBASE_MEMSPACE1B_ADDR	0xf7004600
+#define CCU_CPU0_MPRT_ADBASE_MEMSPACE1C_ADDR	0xf7004620
+#define CCU_CPU0_MPRT_ADBASE_MEMSPACE1D_ADDR	0xf7004640
+#define CCU_CPU0_MPRT_ADBASE_MEMSPACE1E_ADDR	0xf7004660
+
+#define CCU_IOM_MPRT_ADBASE_MEMSPACE0_ADDR	0xf7018560
+#define CCU_IOM_MPRT_ADBASE_MEMSPACE1A_ADDR	0xf7018580
+#define CCU_IOM_MPRT_ADBASE_MEMSPACE1B_ADDR	0xf70185a0
+#define CCU_IOM_MPRT_ADBASE_MEMSPACE1C_ADDR	0xf70185c0
+#define CCU_IOM_MPRT_ADBASE_MEMSPACE1D_ADDR	0xf70185e0
+#define CCU_IOM_MPRT_ADBASE_MEMSPACE1E_ADDR	0xf7018600
+
+#define CCU_ADBASE_DI_MASK			0x00000010
+
+#endif /* _SDRAM_S10_H_ */
diff --git a/drivers/ddr/altera/Makefile b/drivers/ddr/altera/Makefile
index bdd2872..943b6cd 100644
--- a/drivers/ddr/altera/Makefile
+++ b/drivers/ddr/altera/Makefile
@@ -10,4 +10,5 @@
 
 ifdef CONFIG_ALTERA_SDRAM
 obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += sdram.o sequencer.o
+obj-$(CONFIG_TARGET_SOCFPGA_STRATIX10) += sdram_s10.o
 endif
diff --git a/drivers/ddr/altera/sdram_s10.c b/drivers/ddr/altera/sdram_s10.c
new file mode 100644
index 0000000..4c9cd34
--- /dev/null
+++ b/drivers/ddr/altera/sdram_s10.c
@@ -0,0 +1,392 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2016-2018 Intel Corporation <www.intel.com>
+ *
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <div64.h>
+#include <asm/io.h>
+#include <watchdog.h>
+#include <asm/arch/sdram_s10.h>
+#include <asm/arch/system_manager.h>
+#include <asm/arch/reset_manager.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static const struct socfpga_ecc_hmc *socfpga_ecc_hmc_base =
+		(void *)SOCFPGA_SDR_ADDRESS;
+static const struct socfpga_noc_ddr_scheduler *socfpga_noc_ddr_scheduler_base =
+		(void *)SOCFPGA_SDR_SCHEDULER_ADDRESS;
+static const struct socfpga_io48_mmr *socfpga_io48_mmr_base =
+		(void *)SOCFPGA_HMC_MMR_IO48_ADDRESS;
+static const struct socfpga_system_manager *sysmgr_regs =
+		(void *)SOCFPGA_SYSMGR_ADDRESS;
+
+#define DDR_CONFIG(A, B, C, R)	((A << 24) | (B << 16) | (C << 8) | R)
+
+/* The followring are the supported configurations */
+u32 ddr_config[] = {
+	/* DDR_CONFIG(Address order,Bank,Column,Row) */
+	/* List for DDR3 or LPDDR3 (pinout order > chip, row, bank, column) */
+	DDR_CONFIG(0, 3, 10, 12),
+	DDR_CONFIG(0, 3,  9, 13),
+	DDR_CONFIG(0, 3, 10, 13),
+	DDR_CONFIG(0, 3,  9, 14),
+	DDR_CONFIG(0, 3, 10, 14),
+	DDR_CONFIG(0, 3, 10, 15),
+	DDR_CONFIG(0, 3, 11, 14),
+	DDR_CONFIG(0, 3, 11, 15),
+	DDR_CONFIG(0, 3, 10, 16),
+	DDR_CONFIG(0, 3, 11, 16),
+	DDR_CONFIG(0, 3, 12, 15),	/* 0xa */
+	/* List for DDR4 only (pinout order > chip, bank, row, column) */
+	DDR_CONFIG(1, 3, 10, 14),
+	DDR_CONFIG(1, 4, 10, 14),
+	DDR_CONFIG(1, 3, 10, 15),
+	DDR_CONFIG(1, 4, 10, 15),
+	DDR_CONFIG(1, 3, 10, 16),
+	DDR_CONFIG(1, 4, 10, 16),
+	DDR_CONFIG(1, 3, 10, 17),
+	DDR_CONFIG(1, 4, 10, 17),
+};
+
+#define DDR_CONFIG_ELEMENTS	(sizeof(ddr_config) / sizeof(u32))
+
+int match_ddr_conf(u32 ddr_conf)
+{
+	int i;
+
+	for (i = 0; i < DDR_CONFIG_ELEMENTS; i++) {
+		if (ddr_conf == ddr_config[i])
+			return i;
+	}
+	return 0;
+}
+
+static int emif_clear(void)
+{
+	u32 s2c, i;
+
+	writel(0, &socfpga_ecc_hmc_base->rsthandshakectrl);
+	s2c = readl(&socfpga_ecc_hmc_base->rsthandshakestat) &
+	      DDR_HMC_RSTHANDSHAKE_MASK;
+
+	for (i = 1000; (i > 0) && s2c; i--) {
+		WATCHDOG_RESET();
+		mdelay(1);
+		s2c = readl(&socfpga_ecc_hmc_base->rsthandshakestat) &
+		      DDR_HMC_RSTHANDSHAKE_MASK;
+	}
+	return !s2c;
+}
+
+static int emif_reset(void)
+{
+	u32 c2s, s2c, i;
+
+	c2s = readl(&socfpga_ecc_hmc_base->rsthandshakectrl) &
+	      DDR_HMC_RSTHANDSHAKE_MASK;
+	s2c = readl(&socfpga_ecc_hmc_base->rsthandshakestat) &
+	      DDR_HMC_RSTHANDSHAKE_MASK;
+
+	debug("DDR: c2s=%08x s2c=%08x nr0=%08x nr1=%08x nr2=%08x dst=%08x\n",
+	      c2s, s2c, readl(&socfpga_io48_mmr_base->niosreserve0),
+	      readl(&socfpga_io48_mmr_base->niosreserve1),
+	      readl(&socfpga_io48_mmr_base->niosreserve2),
+	      readl(&socfpga_io48_mmr_base->dramsts));
+
+	if (s2c && emif_clear()) {
+		printf("DDR: emif_clear() failed\n");
+		return -1;
+	}
+
+	puts("DDR: Triggerring emif reset\n");
+	writel(DDR_HMC_CORE2SEQ_INT_REQ,
+	       &socfpga_ecc_hmc_base->rsthandshakectrl);
+
+	for (i = 1000; i > 0; i--) {
+		/* if seq2core[3] = 0, we are good */
+		if (!(readl(&socfpga_ecc_hmc_base->rsthandshakestat) &
+		    DDR_HMC_SEQ2CORE_INT_RESP_MASK))
+			break;
+		WATCHDOG_RESET();
+		mdelay(1);
+	}
+
+	if (!i) {
+		printf("DDR: failed to get ack from EMIF\n");
+		return -2;
+	}
+
+	if (emif_clear()) {
+		printf("DDR: emif_clear() failed\n");
+		return -3;
+	}
+
+	printf("DDR: %s triggered successly\n", __func__);
+	return 0;
+}
+
+static int poll_hmc_clock_status(void)
+{
+	u32 status, i;
+
+	for (i = 1000; i > 0; i--) {
+		status = readl(&sysmgr_regs->hmc_clk) &
+			 SYSMGR_HMC_CLK_STATUS_MSK;
+		udelay(1);
+		if (status)
+			break;
+		WATCHDOG_RESET();
+	}
+	return status;
+}
+
+/**
+ * sdram_mmr_init_full() - Function to initialize SDRAM MMR
+ *
+ * Initialize the SDRAM MMR.
+ */
+int sdram_mmr_init_full(unsigned int unused)
+{
+	u32 update_value, io48_value, ddrioctl;
+	u32 i, j, cal_success;
+
+	/* Enable access to DDR from CPU master */
+	clrbits_le32(CCU_CPU0_MPRT_ADBASE_DDRREG_ADDR, CCU_ADBASE_DI_MASK);
+	clrbits_le32(CCU_CPU0_MPRT_ADBASE_MEMSPACE0_ADDR, CCU_ADBASE_DI_MASK);
+	clrbits_le32(CCU_CPU0_MPRT_ADBASE_MEMSPACE1A_ADDR, CCU_ADBASE_DI_MASK);
+	clrbits_le32(CCU_CPU0_MPRT_ADBASE_MEMSPACE1B_ADDR, CCU_ADBASE_DI_MASK);
+	clrbits_le32(CCU_CPU0_MPRT_ADBASE_MEMSPACE1C_ADDR, CCU_ADBASE_DI_MASK);
+	clrbits_le32(CCU_CPU0_MPRT_ADBASE_MEMSPACE1D_ADDR, CCU_ADBASE_DI_MASK);
+	clrbits_le32(CCU_CPU0_MPRT_ADBASE_MEMSPACE1E_ADDR, CCU_ADBASE_DI_MASK);
+
+	/* Enable access to DDR from IO master */
+	clrbits_le32(CCU_IOM_MPRT_ADBASE_MEMSPACE0_ADDR, CCU_ADBASE_DI_MASK);
+	clrbits_le32(CCU_IOM_MPRT_ADBASE_MEMSPACE1A_ADDR, CCU_ADBASE_DI_MASK);
+	clrbits_le32(CCU_IOM_MPRT_ADBASE_MEMSPACE1B_ADDR, CCU_ADBASE_DI_MASK);
+	clrbits_le32(CCU_IOM_MPRT_ADBASE_MEMSPACE1C_ADDR, CCU_ADBASE_DI_MASK);
+	clrbits_le32(CCU_IOM_MPRT_ADBASE_MEMSPACE1D_ADDR, CCU_ADBASE_DI_MASK);
+	clrbits_le32(CCU_IOM_MPRT_ADBASE_MEMSPACE1E_ADDR, CCU_ADBASE_DI_MASK);
+
+	/* this enables nonsecure access to DDR */
+	/* mpuregion0addr_limit */
+	writel(0xFFFF0000, 0xF8020118);
+	writel(0x1F, 0xF802011c);
+
+	/* nonmpuregion0addr_limit */
+	writel(0xFFFF0000, 0xF8020198);
+	writel(0x1F, 0xF802019C);
+
+	/* Enable mpuregion0enable and nonmpuregion0enable */
+	writel(BIT(0) | BIT(8), 0xF8020100);
+
+	/* Ensure HMC clock is running */
+	if (!poll_hmc_clock_status()) {
+		puts("DDR: Error as HMC clock not running\n");
+		return -1;
+	}
+
+	/* release DDR scheduler from reset */
+	socfpga_per_reset(SOCFPGA_RESET(SDR), 0);
+
+	/* Try 3 times to do a calibration */
+	for (i = 0; i < 3; i++) {
+		cal_success = readl(&socfpga_ecc_hmc_base->ddrcalstat) &
+			      DDR_HMC_DDRCALSTAT_CAL_MSK;
+		/* A delay to wait for calibration bit to set */
+		for (j = 0; (j < 1000) && !cal_success; j++) {
+			WATCHDOG_RESET();
+			mdelay(1);
+			cal_success = readl(&socfpga_ecc_hmc_base->ddrcalstat)
+				      & DDR_HMC_DDRCALSTAT_CAL_MSK;
+		}
+
+		if (cal_success)
+			break;
+
+		emif_reset();
+	}
+
+	if (!cal_success) {
+		puts("DDR: Error as SDRAM calibration failed\n");
+		return -1;
+	}
+	puts("DDR: Calibration success\n");
+
+	union ctrlcfg0_reg ctrlcfg0 = (union ctrlcfg0_reg)
+				readl(&socfpga_io48_mmr_base->ctrlcfg0);
+	union ctrlcfg1_reg ctrlcfg1 = (union ctrlcfg1_reg)
+				readl(&socfpga_io48_mmr_base->ctrlcfg1);
+	union dramaddrw_reg dramaddrw = (union dramaddrw_reg)
+				readl(&socfpga_io48_mmr_base->dramaddrw);
+	union dramtiming0_reg dramtim0 = (union dramtiming0_reg)
+				readl(&socfpga_io48_mmr_base->dramtiming0);
+	union caltiming0_reg caltim0 = (union caltiming0_reg)
+				readl(&socfpga_io48_mmr_base->caltiming0);
+	union caltiming1_reg caltim1 = (union caltiming1_reg)
+				readl(&socfpga_io48_mmr_base->caltiming1);
+	union caltiming2_reg caltim2 = (union caltiming2_reg)
+				readl(&socfpga_io48_mmr_base->caltiming2);
+	union caltiming3_reg caltim3 = (union caltiming3_reg)
+				readl(&socfpga_io48_mmr_base->caltiming3);
+	union caltiming4_reg caltim4 = (union caltiming4_reg)
+				readl(&socfpga_io48_mmr_base->caltiming4);
+	union caltiming9_reg caltim9 = (union caltiming9_reg)
+				readl(&socfpga_io48_mmr_base->caltiming9);
+
+	/*
+	 * Configure the DDR IO size [0xFFCFB008]
+	 * niosreserve0: Used to indicate DDR width &
+	 *	bit[7:0] = Number of data bits (bit[6:5] 0x01=32bit, 0x10=64bit)
+	 *	bit[8]   = 1 if user-mode OCT is present
+	 *	bit[9]   = 1 if warm reset compiled into EMIF Cal Code
+	 *	bit[10]  = 1 if warm reset is on during generation in EMIF Cal
+	 * niosreserve1: IP ADCDS version encoded as 16 bit value
+	 *	bit[2:0] = Variant (0=not special,1=FAE beta, 2=Customer beta,
+	 *			    3=EAP, 4-6 are reserved)
+	 *	bit[5:3] = Service Pack # (e.g. 1)
+	 *	bit[9:6] = Minor Release #
+	 *	bit[14:10] = Major Release #
+	 */
+	update_value = readl(&socfpga_io48_mmr_base->niosreserve0);
+	writel(((update_value & 0xFF) >> 5), &socfpga_ecc_hmc_base->ddrioctrl);
+	ddrioctl = readl(&socfpga_ecc_hmc_base->ddrioctrl);
+
+	/* enable HPS interface to HMC */
+	writel(DDR_HMC_HPSINTFCSEL_ENABLE_MASK,
+	       &socfpga_ecc_hmc_base->hpsintfcsel);
+
+	/* Set the DDR Configuration */
+	io48_value = DDR_CONFIG(ctrlcfg1.cfg_addr_order,
+				(dramaddrw.cfg_bank_addr_width +
+				 dramaddrw.cfg_bank_group_addr_width),
+				dramaddrw.cfg_col_addr_width,
+				dramaddrw.cfg_row_addr_width);
+
+	update_value = match_ddr_conf(io48_value);
+	if (update_value)
+		writel(update_value,
+		       &socfpga_noc_ddr_scheduler_base->main_scheduler_ddrconf);
+
+	/* Configure HMC dramaddrw */
+	writel(readl(&socfpga_io48_mmr_base->dramaddrw),
+	       &socfpga_ecc_hmc_base->dramaddrwidth);
+
+	/*
+	 * Configure DDR timing
+	 *  RDTOMISS = tRTP + tRP + tRCD - BL/2
+	 *  WRTOMISS = WL + tWR + tRP + tRCD and
+	 *    WL = RL + BL/2 + 2 - rd-to-wr ; tWR = 15ns  so...
+	 *  First part of equation is in memory clock units so divide by 2
+	 *  for HMC clock units. 1066MHz is close to 1ns so use 15 directly.
+	 *  WRTOMISS = ((RL + BL/2 + 2 + tWR) >> 1)- rd-to-wr + tRP + tRCD
+	 */
+	update_value = caltim2.cfg_rd_to_pch + caltim4.cfg_pch_to_valid +
+		       caltim0.cfg_act_to_rdwr -
+		       (ctrlcfg0.cfg_ctrl_burst_len >> 2);
+	io48_value = (((dramtim0.cfg_tcl + 2 + DDR_TWR +
+		      (ctrlcfg0.cfg_ctrl_burst_len >> 1)) >> 1) -
+		      /* Up to here was in memory cycles so divide by 2 */
+		      caltim1.cfg_rd_to_wr + caltim0.cfg_act_to_rdwr +
+		      caltim4.cfg_pch_to_valid);
+
+	writel(((caltim0.cfg_act_to_act <<
+			DDR_SCHED_DDRTIMING_ACTTOACT_OFFSET) |
+		(update_value << DDR_SCHED_DDRTIMING_RDTOMISS_OFFSET) |
+		(io48_value << DDR_SCHED_DDRTIMING_WRTOMISS_OFFSET) |
+		((ctrlcfg0.cfg_ctrl_burst_len >> 2) <<
+			DDR_SCHED_DDRTIMING_BURSTLEN_OFFSET) |
+		(caltim1.cfg_rd_to_wr << DDR_SCHED_DDRTIMING_RDTOWR_OFFSET) |
+		(caltim3.cfg_wr_to_rd << DDR_SCHED_DDRTIMING_WRTORD_OFFSET) |
+		(((ddrioctl == 1) ? 1 : 0) <<
+			DDR_SCHED_DDRTIMING_BWRATIO_OFFSET)),
+		&socfpga_noc_ddr_scheduler_base->main_scheduler_ddrtiming);
+
+	/* Configure DDR mode [precharge = 0] */
+	writel(((ddrioctl ? 0 : 1) << DDR_SCHED_DDRMOD_BWRATIOEXTENDED_OFFSET),
+	       &socfpga_noc_ddr_scheduler_base->main_scheduler_ddrmode);
+
+	/* Configure the read latency */
+	writel((dramtim0.cfg_tcl >> 1) + DDR_READ_LATENCY_DELAY,
+	       &socfpga_noc_ddr_scheduler_base->main_scheduler_readlatency);
+
+	/*
+	 * Configuring timing values concerning activate commands
+	 * [FAWBANK alway 1 because always 4 bank DDR]
+	 */
+	writel(((caltim0.cfg_act_to_act_db << DDR_SCHED_ACTIVATE_RRD_OFFSET) |
+	       (caltim9.cfg_4_act_to_act << DDR_SCHED_ACTIVATE_FAW_OFFSET) |
+	       (DDR_ACTIVATE_FAWBANK << DDR_SCHED_ACTIVATE_FAWBANK_OFFSET)),
+	       &socfpga_noc_ddr_scheduler_base->main_scheduler_activate);
+
+	/*
+	 * Configuring timing values concerning device to device data bus
+	 * ownership change
+	 */
+	writel(((caltim1.cfg_rd_to_rd_dc <<
+			DDR_SCHED_DEVTODEV_BUSRDTORD_OFFSET) |
+	       (caltim1.cfg_rd_to_wr_dc <<
+			DDR_SCHED_DEVTODEV_BUSRDTOWR_OFFSET) |
+	       (caltim3.cfg_wr_to_rd_dc <<
+			DDR_SCHED_DEVTODEV_BUSWRTORD_OFFSET)),
+	       &socfpga_noc_ddr_scheduler_base->main_scheduler_devtodev);
+
+	/* assigning the SDRAM size */
+	unsigned long long size = sdram_calculate_size();
+	/* If the size is invalid, use default Config size */
+	if (size <= 0)
+		gd->ram_size = PHYS_SDRAM_1_SIZE;
+	else
+		gd->ram_size = size;
+
+	/* Enable or disable the SDRAM ECC */
+	if (ctrlcfg1.cfg_ctrl_enable_ecc) {
+		setbits_le32(&socfpga_ecc_hmc_base->eccctrl,
+			     (DDR_HMC_ECCCTL_AWB_CNT_RST_SET_MSK |
+			      DDR_HMC_ECCCTL_CNT_RST_SET_MSK |
+			      DDR_HMC_ECCCTL_ECC_EN_SET_MSK));
+		clrbits_le32(&socfpga_ecc_hmc_base->eccctrl,
+			     (DDR_HMC_ECCCTL_AWB_CNT_RST_SET_MSK |
+			      DDR_HMC_ECCCTL_CNT_RST_SET_MSK));
+		setbits_le32(&socfpga_ecc_hmc_base->eccctrl2,
+			     (DDR_HMC_ECCCTL2_RMW_EN_SET_MSK |
+			      DDR_HMC_ECCCTL2_AWB_EN_SET_MSK));
+	} else {
+		clrbits_le32(&socfpga_ecc_hmc_base->eccctrl,
+			     (DDR_HMC_ECCCTL_AWB_CNT_RST_SET_MSK |
+			      DDR_HMC_ECCCTL_CNT_RST_SET_MSK |
+			      DDR_HMC_ECCCTL_ECC_EN_SET_MSK));
+		clrbits_le32(&socfpga_ecc_hmc_base->eccctrl2,
+			     (DDR_HMC_ECCCTL2_RMW_EN_SET_MSK |
+			      DDR_HMC_ECCCTL2_AWB_EN_SET_MSK));
+	}
+
+	puts("DDR: HMC init success\n");
+	return 0;
+}
+
+/**
+ * sdram_calculate_size() - Calculate SDRAM size
+ *
+ * Calculate SDRAM device size based on SDRAM controller parameters.
+ * Size is specified in bytes.
+ */
+unsigned long sdram_calculate_size(void)
+{
+	union dramaddrw_reg dramaddrw =
+		(union dramaddrw_reg)readl(&socfpga_io48_mmr_base->dramaddrw);
+
+	u32 size = (1 << (dramaddrw.cfg_cs_addr_width +
+		    dramaddrw.cfg_bank_group_addr_width +
+		    dramaddrw.cfg_bank_addr_width +
+		    dramaddrw.cfg_row_addr_width +
+		    dramaddrw.cfg_col_addr_width));
+
+	size *= (2 << (readl(&socfpga_ecc_hmc_base->ddrioctrl) &
+		       DDR_HMC_DDRIOCTRL_IOSIZE_MSK));
+
+	return size;
+}
-- 
1.7.1

[U-Boot] [PATCH v1 15/16] board: altera: stratix10: Add socdk board support for Stratix10 SoC

[Ley Foon Tan]

Add socdk board support for Stratix SoC

Signed-off-by: Chin Liang See <chin.liang.see@intel.com>
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
---
 board/altera/stratix10-socdk/MAINTAINERS |    7 +++++++
 board/altera/stratix10-socdk/Makefile    |    7 +++++++
 board/altera/stratix10-socdk/socfpga.c   |    7 +++++++
 3 files changed, 21 insertions(+), 0 deletions(-)
 create mode 100644 board/altera/stratix10-socdk/MAINTAINERS
 create mode 100644 board/altera/stratix10-socdk/Makefile
 create mode 100644 board/altera/stratix10-socdk/socfpga.c

diff --git a/board/altera/stratix10-socdk/MAINTAINERS b/board/altera/stratix10-socdk/MAINTAINERS
new file mode 100644
index 0000000..6192bc9
--- /dev/null
+++ b/board/altera/stratix10-socdk/MAINTAINERS
@@ -0,0 +1,7 @@
+SOCFPGA BOARD
+M:	Chin-Liang See <chin.liang.see@intel.com>
+M:	Dinh Nguyen <dinh.nguyen@intel.com>
+S:	Maintained
+F:	board/altera/stratix10-socdk/
+F:	include/configs/socfpga_stratix10_socdk.h
+F:	configs/socfpga_stratix10_defconfig
diff --git a/board/altera/stratix10-socdk/Makefile b/board/altera/stratix10-socdk/Makefile
new file mode 100644
index 0000000..02a9cad
--- /dev/null
+++ b/board/altera/stratix10-socdk/Makefile
@@ -0,0 +1,7 @@
+#
+# Copyright (C) 2016-2017 Intel Corporation <www.intel.com>
+#
+# SPDX-License-Identifier:	GPL-2.0
+#
+
+obj-y	:= socfpga.o
diff --git a/board/altera/stratix10-socdk/socfpga.c b/board/altera/stratix10-socdk/socfpga.c
new file mode 100644
index 0000000..043fc54
--- /dev/null
+++ b/board/altera/stratix10-socdk/socfpga.c
@@ -0,0 +1,7 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2016-2018 Intel Corporation <www.intel.com>
+ *
+ */
+
+#include <common.h>
-- 
1.7.1

[U-Boot] [PATCH v1 16/16] arm: socfpga: stratix10: Enable Stratix10 SoC build

[Ley Foon Tan]

Add build support for Stratix SoC

Signed-off-by: Chin Liang See <chin.liang.see@intel.com>
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
---
 arch/arm/Kconfig                          |    9 +-
 arch/arm/mach-socfpga/Kconfig             |   13 ++
 configs/socfpga_stratix10_defconfig       |   52 +++++++
 include/configs/socfpga_stratix10_socdk.h |  234 +++++++++++++++++++++++++++++
 4 files changed, 304 insertions(+), 4 deletions(-)
 create mode 100644 configs/socfpga_stratix10_defconfig
 create mode 100644 include/configs/socfpga_stratix10_socdk.h

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 190f883..b31cc7e 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -693,22 +693,23 @@ config ARCH_SNAPDRAGON
 
 config ARCH_SOCFPGA
 	bool "Altera SOCFPGA family"
-	select CPU_V7
+	select CPU_V7 if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
+	select ARM64 if TARGET_SOCFPGA_STRATIX10
 	select SUPPORT_SPL
 	select OF_CONTROL
 	select SPL_OF_CONTROL
 	select DM
-	select ENABLE_ARM_SOC_BOOT0_HOOK
+	select ENABLE_ARM_SOC_BOOT0_HOOK if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
 	select ARCH_EARLY_INIT_R
 	select ARCH_MISC_INIT
-	select SYS_THUMB_BUILD
+	select SYS_THUMB_BUILD if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
 	imply CMD_MTDPARTS
 	imply CRC32_VERIFY
 	imply DM_SPI
 	imply DM_SPI_FLASH
 	imply FAT_WRITE
-	imply HW_WATCHDOG
 	imply SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION
+	select SPL_SEPARATE_BSS if TARGET_SOCFPGA_STRATIX10
 
 config ARCH_SUNXI
 	bool "Support sunxi (Allwinner) SoCs"
diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig
index afc38d5..f15a42e 100644
--- a/arch/arm/mach-socfpga/Kconfig
+++ b/arch/arm/mach-socfpga/Kconfig
@@ -49,6 +49,12 @@ config TARGET_SOCFPGA_GEN5
 	bool
 	select ALTERA_SDRAM
 
+config TARGET_SOCFPGA_STRATIX10
+	bool
+	select ARMV8_MULTIENTRY
+	select ARMV8_SPIN_TABLE
+	select ARMV8_SET_SMPEN
+
 choice
 	prompt "Altera SOCFPGA board select"
 	optional
@@ -90,6 +96,10 @@ config TARGET_SOCFPGA_SR1500
 	bool "SR1500 (Cyclone V)"
 	select TARGET_SOCFPGA_CYCLONE5
 
+config TARGET_SOCFPGA_STRATIX10_SOCDK
+	bool "Intel SOCFPGA SoCDK (Stratix 10)"
+	select TARGET_SOCFPGA_STRATIX10
+
 config TARGET_SOCFPGA_TERASIC_DE0_NANO
 	bool "Terasic DE0-Nano-Atlas (Cyclone V)"
 	select TARGET_SOCFPGA_CYCLONE5
@@ -121,12 +131,14 @@ config SYS_BOARD
 	default "sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
 	default "socrates" if TARGET_SOCFPGA_EBV_SOCRATES
 	default "sr1500" if TARGET_SOCFPGA_SR1500
+	default "stratix10-socdk" if TARGET_SOCFPGA_STRATIX10_SOCDK
 	default "vining_fpga" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
 
 config SYS_VENDOR
 	default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK
 	default "altera" if TARGET_SOCFPGA_ARRIA10_SOCDK
 	default "altera" if TARGET_SOCFPGA_CYCLONE5_SOCDK
+	default "altera" if TARGET_SOCFPGA_STRATIX10_SOCDK
 	default "aries" if TARGET_SOCFPGA_ARIES_MCVEVK
 	default "devboards" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
 	default "ebv" if TARGET_SOCFPGA_EBV_SOCRATES
@@ -152,6 +164,7 @@ config SYS_CONFIG_NAME
 	default "socfpga_sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
 	default "socfpga_socrates" if TARGET_SOCFPGA_EBV_SOCRATES
 	default "socfpga_sr1500" if TARGET_SOCFPGA_SR1500
+	default "socfpga_stratix10_socdk" if TARGET_SOCFPGA_STRATIX10_SOCDK
 	default "socfpga_vining_fpga" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
 
 endif
diff --git a/configs/socfpga_stratix10_defconfig b/configs/socfpga_stratix10_defconfig
new file mode 100644
index 0000000..46b7999
--- /dev/null
+++ b/configs/socfpga_stratix10_defconfig
@@ -0,0 +1,52 @@
+CONFIG_ARM=y
+CONFIG_ARCH_SOCFPGA=y
+CONFIG_SYS_TEXT_BASE=0x1000
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_TARGET_SOCFPGA_STRATIX10_SOCDK=y
+CONFIG_SPL=y
+CONFIG_IDENT_STRING="socfpga_stratix10"
+CONFIG_SPL_FAT_SUPPORT=y
+CONFIG_DEFAULT_DEVICE_TREE="socfpga_stratix10_socdk"
+CONFIG_BOOTDELAY=5
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_PROMPT="SOCFPGA_STRATIX10 # "
+CONFIG_CMD_MEMTEST=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_DM_GPIO=y
+CONFIG_DWAPB_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_DW=y
+CONFIG_DM_MMC=y
+CONFIG_MMC_DW=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_DM_ETH=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_SYS_NS16550=y
+CONFIG_CADENCE_QSPI=y
+CONFIG_DESIGNWARE_SPI=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_DWC2=y
+CONFIG_USB_STORAGE=y
+CONFIG_USE_TINY_PRINTF=y
diff --git a/include/configs/socfpga_stratix10_socdk.h b/include/configs/socfpga_stratix10_socdk.h
new file mode 100644
index 0000000..6419814
--- /dev/null
+++ b/include/configs/socfpga_stratix10_socdk.h
@@ -0,0 +1,234 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright (C) 2017-2018 Intel Corporation <www.intel.com>
+ *
+ */
+
+#ifndef __CONFIG_SOCFGPA_STRATIX10_H__
+#define __CONFIG_SOCFGPA_STRATIX10_H__
+
+#include <asm/arch/base_addr_s10.h>
+
+/*
+ * U-Boot general configurations
+ */
+#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE
+#define CONFIG_LOADADDR			0x2000000
+#define CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR
+#define CONFIG_REMAKE_ELF
+/* sysmgr.boot_scratch_cold4 & 5 (64bit) will be used for PSCI_CPU_ON call */
+#define CPU_RELEASE_ADDR		0xFFD12210
+#define CONFIG_SYS_CACHELINE_SIZE	64
+#define CONFIG_SYS_MEM_RESERVE_SECURE	0	/* using OCRAM, not DDR */
+
+/*
+ * U-Boot console configurations
+ */
+#define CONFIG_SYS_MAXARGS		64
+#define CONFIG_SYS_CBSIZE		2048
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
+					sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
+
+/* Extend size of kernel image for uncompression */
+#define CONFIG_SYS_BOOTM_LEN		(32 * 1024 * 1024)
+
+/*
+ * U-Boot run time memory configurations
+ */
+#define CONFIG_SYS_INIT_RAM_ADDR	0xFFE00000
+#define CONFIG_SYS_INIT_RAM_SIZE	0x40000
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INIT_RAM_ADDR \
+					+ CONFIG_SYS_INIT_RAM_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	(CONFIG_SYS_INIT_SP_ADDR)
+#define CONFIG_SYS_MALLOC_LEN		(5 * 1024 * 1024)
+
+/*
+ * U-Boot display configurations
+ */
+#define CONFIG_DISPLAY_BOARDINFO_LATE
+
+/*
+ * U-Boot environment configurations
+ */
+#define CONFIG_ENV_SIZE			0x1000
+#define CONFIG_SYS_MMC_ENV_DEV		0	/* device 0 */
+#define CONFIG_ENV_OFFSET		512	/* just after the MBR */
+
+/*
+ * QSPI support
+ */
+ #ifdef CONFIG_CADENCE_QSPI
+/* Enable it if you want to use dual-stacked mode */
+#undef CONFIG_SF_DUAL_FLASH
+/*#define CONFIG_QSPI_RBF_ADDR		0x720000*/
+
+/* Flash device info */
+#define CONFIG_SF_DEFAULT_SPEED		(50000000)
+#define CONFIG_SF_DEFAULT_MODE		(SPI_MODE_3 | SPI_RX_QUAD)
+#define CONFIG_SF_DEFAULT_BUS		0
+#define CONFIG_SF_DEFAULT_CS		0
+
+/*#define CONFIG_ENV_IS_IN_SPI_FLASH*/
+#ifdef CONFIG_ENV_IS_IN_SPI_FLASH
+#undef CONFIG_ENV_OFFSET
+#undef CONFIG_ENV_SIZE
+#define CONFIG_ENV_OFFSET		0x710000
+#define CONFIG_ENV_SIZE			(4 * 1024)
+#define CONFIG_ENV_SECT_SIZE		(4 * 1024)
+#endif /* CONFIG_ENV_IS_IN_SPI_FLASH */
+
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_MTD_DEVICE
+#define CONFIG_MTD_PARTITIONS
+#define MTDIDS_DEFAULT			"nor0=ff705000.spi.0"
+#endif /* CONFIG_SPL_BUILD */
+
+#ifndef __ASSEMBLY__
+unsigned int cm_get_qspi_controller_clk_hz(void);
+#define CONFIG_CQSPI_REF_CLK		cm_get_qspi_controller_clk_hz()
+#endif
+
+#endif /* CONFIG_CADENCE_QSPI */
+
+/*
+ * Boot arguments passed to the boot command. The value of
+ * CONFIG_BOOTARGS goes into the environment value "bootargs".
+ * Do note the value will override also the chosen node in FDT blob.
+ */
+#define CONFIG_BOOTARGS "earlycon"
+#define CONFIG_BOOTCOMMAND "run fatscript; run mmcload;run linux_qspi_enable;" \
+			   "run mmcboot"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
+	"bootfile=Image\0" \
+	"fdt_addr=8000000\0" \
+	"fdtimage=socfpga_stratix10_socdk.dtb\0" \
+	"mmcroot=/dev/mmcblk0p2\0" \
+	"mmcboot=setenv bootargs " CONFIG_BOOTARGS \
+		" root=${mmcroot} rw rootwait;" \
+		"booti ${loadaddr} - ${fdt_addr}\0" \
+	"mmcload=mmc rescan;" \
+		"load mmc 0:1 ${loadaddr} ${bootfile};" \
+		"load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \
+	"linux_qspi_enable=if sf probe; then " \
+		"echo Enabling QSPI at Linux DTB...;" \
+		"fdt addr ${fdt_addr}; fdt resize;" \
+		"fdt set /soc/spi at ff8d2000 status okay;" \
+		"fdt set /soc/clkmgr/clocks/qspi_clk clock-frequency " \
+		" ${qspi_clock}; fi; \0" \
+	"scriptaddr=0x02100000\0" \
+	"scriptfile=u-boot.scr\0" \
+	"fatscript=if fatload mmc 0:1 ${scriptaddr} ${scriptfile};" \
+		   "then source ${scriptaddr}; fi\0"
+
+/*
+ * Generic Interrupt Controller Definitions
+ */
+#define CONFIG_GICV2
+
+/*
+ * External memory configurations
+ */
+#define PHYS_SDRAM_1			0x0
+#define PHYS_SDRAM_1_SIZE		(1 * 1024 * 1024 * 1024)
+#define CONFIG_SYS_SDRAM_BASE		0
+#define CONFIG_NR_DRAM_BANKS		1
+#define CONFIG_SYS_MEMTEST_START	0
+#define CONFIG_SYS_MEMTEST_END		PHYS_SDRAM_1_SIZE - 0x200000
+
+/*
+ * SDRAM controller
+ */
+#define CONFIG_ALTERA_SDRAM
+
+/*
+ * Serial / UART configurations
+ */
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	-4
+#define CONFIG_SYS_NS16550_COM1		SOCFPGA_UART0_ADDRESS
+#define CONFIG_SYS_NS16550_CLK		100000000
+#define CONFIG_CONS_INDEX		1
+#define CONFIG_BAUDRATE			115200
+/* always write in 32 bit manner */
+#define CONFIG_SYS_NS16550_MEM32
+#define CONFIG_SYS_NS16550_REG_SIZE	-4
+
+/*
+ * Timer & watchdog configurations
+ */
+#define COUNTER_FREQUENCY		400000000
+
+/*
+ * SDMMC configurations
+ */
+#ifdef CONFIG_CMD_MMC
+#define CONFIG_BOUNCE_BUFFER
+#define CONFIG_SYS_MMC_MAX_BLK_COUNT	256
+#endif
+/*
+ * Flash configurations
+ */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1
+
+/* Ethernet on SoC (EMAC) */
+#if defined(CONFIG_CMD_NET)
+#define CONFIG_PHY_MICREL
+#define CONFIG_PHY_MICREL_KSZ9031
+#define CONFIG_DW_ALTDESCRIPTOR
+#define CONFIG_MII
+#define CONFIG_PHY_GIGE
+#endif /* CONFIG_CMD_NET */
+
+/*
+ * L4 Watchdog
+ */
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_HW_WATCHDOG
+#define CONFIG_DESIGNWARE_WATCHDOG
+#define CONFIG_DW_WDT_BASE		SOCFPGA_L4WD0_ADDRESS
+#ifndef __ASSEMBLY__
+unsigned int cm_get_l4_sys_free_clk_hz(void);
+#define CONFIG_DW_WDT_CLOCK_KHZ		(cm_get_l4_sys_free_clk_hz() / 1000)
+#endif
+#define CONFIG_WATCHDOG_TIMEOUT_MSECS	3000
+#endif
+
+/*
+ * SPL memory layout
+ *
+ * On chip RAM
+ * 0xFFE0_0000 ...... Start of OCRAM
+ * SPL code, rwdata
+ * 0xFFEx_xxxx ...... Top of stack (grows down)
+ * 0xFFEy_yyyy ...... Global Data
+ * 0xFFEz_zzzz ...... Malloc prior relocation (size CONFIG_SYS_MALLOC_F_LEN)
+ * 0xFFE3_FFFF ...... End of OCRAM
+ *
+ * SDRAM
+ * 0x0000_0000 ...... Start of SDRAM_1
+ * unused / empty space for image loading
+ * Size 64MB   ...... MALLOC (size CONFIG_SYS_SPL_MALLOC_SIZE)
+ * Size 1MB    ...... BSS (size CONFIG_SPL_BSS_MAX_SIZE)
+ * 0x8000_0000 ...... End of SDRAM_1 (assume 2GB)
+ *
+ */
+#define CONFIG_SPL_TEXT_BASE		CONFIG_SYS_INIT_RAM_ADDR
+#define CONFIG_SPL_MAX_SIZE		CONFIG_SYS_INIT_RAM_SIZE
+#define CONFIG_SPL_STACK		CONFIG_SYS_INIT_SP_ADDR
+#define CONFIG_SPL_BSS_MAX_SIZE		0x100000	/* 1 MB */
+#define CONFIG_SPL_BSS_START_ADDR	(PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE \
+					- CONFIG_SPL_BSS_MAX_SIZE)
+#define CONFIG_SYS_SPL_MALLOC_SIZE	(CONFIG_SYS_MALLOC_LEN)
+#define CONFIG_SYS_SPL_MALLOC_START	(CONFIG_SPL_BSS_START_ADDR \
+					- CONFIG_SYS_SPL_MALLOC_SIZE)
+#define CONFIG_SPL_SPI_LOAD
+#define CONFIG_SYS_SPI_U_BOOT_OFFS      0x3C00000
+
+/* SPL SDMMC boot support */
+#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION	1
+#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME		"u-boot-dtb.img"
+
+#endif	/* __CONFIG_H */
-- 
1.7.1

[U-Boot] [PATCH v1 05/16] arm: socfpga: misc: Add CONFIG_SYS_L2_PL310 switch

[Ley Foon Tan]

On Thu, Apr 19, 2018 at 4:19 PM, Marek Vasut <marex@denx.de> wrote:
> On 04/19/2018 07:15 AM, See, Chin Liang wrote:
>> On Thu, 2018-04-19 at 04:47 +0200, Marek Vasut wrote:
>>> On 04/19/2018 11:50 AM, Ley Foon Tan wrote:
>>>>
>>>> Add CONFIG_SYS_L2_PL310 conditional build.
>>> Why ?
>>>
>>
>> In ARM64, L2 cache controller is accessed through processor registers.
>> Hence we shall make this conditional in order this file can be shared
>> across SOCFPGAs.
>
> That should be in the patch description .
> Do you ever add the PL310 register access on S10 later in the set?
>
> --
Okay, will update description.
No, S10 doesn't use PL310 registers.

Thanks.

Regards
Ley Foon

[U-Boot] [PATCH v1 01/16] arm: socfpga: stratix10: Add base address map for Statix10 SoC

[Marek Vasut]

On 04/20/2018 05:22 PM, Ley Foon Tan wrote:
> On Thu, 2018-04-19 at 05:02 +0200, Marek Vasut wrote:
>> On 04/19/2018 11:50 AM, Ley Foon Tan wrote:
>>>
>>> Add the base address map for Statix10 SoC
>>>
>>> Signed-off-by: Chin Liang See <chin.liang.see@intel.com>
>>> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
>>> ---
>>>  arch/arm/mach-socfpga/include/mach/base_addr_s10.h |   38
>>> ++++++++++++++++++++
>>>  1 files changed, 38 insertions(+), 0 deletions(-)
>>>  create mode 100644 arch/arm/mach-
>>> socfpga/include/mach/base_addr_s10.h
>>>
>>> diff --git a/arch/arm/mach-socfpga/include/mach/base_addr_s10.h
>>> b/arch/arm/mach-socfpga/include/mach/base_addr_s10.h
>>> new file mode 100644
>>> index 0000000..e18d2bf
>>> --- /dev/null
>>> +++ b/arch/arm/mach-socfpga/include/mach/base_addr_s10.h
>>> @@ -0,0 +1,38 @@
>>> +/* SPDX-License-Identifier: GPL-2.0
>>> + *
>>> + * Copyright (C) 2016-2018 Intel Corporation <www.intel.com>
>>> + *
>>> + */
>>> +
>>> +#ifndef _SOCFPGA_S10_BASE_HARDWARE_H_
>>> +#define _SOCFPGA_S10_BASE_HARDWARE_H_
>>> +
>>> +#define SOCFPGA_SDR_SCHEDULER_ADDRESS		0xf8000400
>>> +#define SOCFPGA_HMC_MMR_IO48_ADDRESS		0xf8010000
>>> +#define SOCFPGA_SDR_ADDRESS			0xf8011000
>>> +#define SOCFPGA_SMMU_ADDRESS			0xfa000000
>>> +#define SOCFPGA_MAILBOX_ADDRESS			0xffA30000
>>> +#define SOCFPGA_UART0_ADDRESS			0xffc02000
>>> +#define SOCFPGA_UART1_ADDRESS			0xffc02100
>>> +#define SOCFPGA_L4WD0_ADDRESS			0xffd00200
>>> +#define SOCFPGA_L4WD1_ADDRESS			0xffd00300
>>> +#define SOCFPGA_L4WD2_ADDRESS			0xffd00400
>>> +#define SOCFPGA_L4WD3_ADDRESS			0xffd00500
>>> +#define SOCFPGA_GTIMER_SEC_ADDRESS		0xffd01000
>>> +#define SOCFPGA_GTIMER_NSEC_ADDRESS		0xffd02000
>>> +#define SOCFPGA_CLKMGR_ADDRESS			0xffd10000
>>> +#define SOCFPGA_RSTMGR_ADDRESS			0xffd11000
>>> +#define SOCFPGA_SYSMGR_ADDRESS			0xffd12000
>>> +#define SOCFPGA_PINMUX_DEDICATED_IO_ADDRESS	0xffd13000
>>> +#define SOCFPGA_FIREWALL_L4_PER			0xffd21000
>>> +#define SOCFPGA_FIREWALL_L4_SYS			0xffd21100
>>> +#define SOCFPGA_FIREWALL_SOC2FPGA		0xffd21200
>>> +#define SOCFPGA_FIREWALL_LWSOC2FPGA		0xffd21300
>>> +#define SOCFPGA_FIREWALL_TCU			0xffd21400
>>> +#define SOCFPGA_DMANONSECURE_ADDRESS		0xffda0000
>>> +#define SOCFPGA_DMASECURE_ADDRESS		0xffda1000
>>> +#define SOCFPGA_OCRAM_ADDRESS			0xffe00000
>>> +#define GICD_BASE				0xfffc1000
>>> +#define GICC_BASE				0xfffc2000
>> How much of this can come from DT ?
>>
> 
> Just found out Dinh already upstreamed this patch. BTW, we will try to 
> use DT when it is possible.

It is possible since years ago :-)

-- 
Best regards,
Marek Vasut

[U-Boot] [PATCH v1 05/16] arm: socfpga: misc: Add CONFIG_SYS_L2_PL310 switch

[Marek Vasut]

On 04/20/2018 09:49 AM, Ley Foon Tan wrote:
> On Thu, Apr 19, 2018 at 4:19 PM, Marek Vasut <marex@denx.de> wrote:
>> On 04/19/2018 07:15 AM, See, Chin Liang wrote:
>>> On Thu, 2018-04-19 at 04:47 +0200, Marek Vasut wrote:
>>>> On 04/19/2018 11:50 AM, Ley Foon Tan wrote:
>>>>>
>>>>> Add CONFIG_SYS_L2_PL310 conditional build.
>>>> Why ?
>>>>
>>>
>>> In ARM64, L2 cache controller is accessed through processor registers.
>>> Hence we shall make this conditional in order this file can be shared
>>> across SOCFPGAs.
>>
>> That should be in the patch description .
>> Do you ever add the PL310 register access on S10 later in the set?
>>
>> --
> Okay, will update description.
> No, S10 doesn't use PL310 registers.

If this PL310 is Gen5 specific, then keep it in some Gen5 file.

-- 
Best regards,
Marek Vasut

[U-Boot] [PATCH v1 01/16] arm: socfpga: stratix10: Add base address map for Statix10 SoC

[Ley Foon Tan]

On Thu, 2018-04-19 at 05:02 +0200, Marek Vasut wrote:
> On 04/19/2018 11:50 AM, Ley Foon Tan wrote:
> > 
> > Add the base address map for Statix10 SoC
> > 
> > Signed-off-by: Chin Liang See <chin.liang.see@intel.com>
> > Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
> > ---
> >  arch/arm/mach-socfpga/include/mach/base_addr_s10.h |   38
> > ++++++++++++++++++++
> >  1 files changed, 38 insertions(+), 0 deletions(-)
> >  create mode 100644 arch/arm/mach-
> > socfpga/include/mach/base_addr_s10.h
> > 
> > diff --git a/arch/arm/mach-socfpga/include/mach/base_addr_s10.h
> > b/arch/arm/mach-socfpga/include/mach/base_addr_s10.h
> > new file mode 100644
> > index 0000000..e18d2bf
> > --- /dev/null
> > +++ b/arch/arm/mach-socfpga/include/mach/base_addr_s10.h
> > @@ -0,0 +1,38 @@
> > +/* SPDX-License-Identifier: GPL-2.0
> > + *
> > + * Copyright (C) 2016-2018 Intel Corporation <www.intel.com>
> > + *
> > + */
> > +
> > +#ifndef _SOCFPGA_S10_BASE_HARDWARE_H_
> > +#define _SOCFPGA_S10_BASE_HARDWARE_H_
> > +
> > +#define SOCFPGA_SDR_SCHEDULER_ADDRESS		0xf8000400
> > +#define SOCFPGA_HMC_MMR_IO48_ADDRESS		0xf8010000
> > +#define SOCFPGA_SDR_ADDRESS			0xf8011000
> > +#define SOCFPGA_SMMU_ADDRESS			0xfa000000
> > +#define SOCFPGA_MAILBOX_ADDRESS			0xffA30000
> > +#define SOCFPGA_UART0_ADDRESS			0xffc02000
> > +#define SOCFPGA_UART1_ADDRESS			0xffc02100
> > +#define SOCFPGA_L4WD0_ADDRESS			0xffd00200
> > +#define SOCFPGA_L4WD1_ADDRESS			0xffd00300
> > +#define SOCFPGA_L4WD2_ADDRESS			0xffd00400
> > +#define SOCFPGA_L4WD3_ADDRESS			0xffd00500
> > +#define SOCFPGA_GTIMER_SEC_ADDRESS		0xffd01000
> > +#define SOCFPGA_GTIMER_NSEC_ADDRESS		0xffd02000
> > +#define SOCFPGA_CLKMGR_ADDRESS			0xffd10000
> > +#define SOCFPGA_RSTMGR_ADDRESS			0xffd11000
> > +#define SOCFPGA_SYSMGR_ADDRESS			0xffd12000
> > +#define SOCFPGA_PINMUX_DEDICATED_IO_ADDRESS	0xffd13000
> > +#define SOCFPGA_FIREWALL_L4_PER			0xffd21000
> > +#define SOCFPGA_FIREWALL_L4_SYS			0xffd21100
> > +#define SOCFPGA_FIREWALL_SOC2FPGA		0xffd21200
> > +#define SOCFPGA_FIREWALL_LWSOC2FPGA		0xffd21300
> > +#define SOCFPGA_FIREWALL_TCU			0xffd21400
> > +#define SOCFPGA_DMANONSECURE_ADDRESS		0xffda0000
> > +#define SOCFPGA_DMASECURE_ADDRESS		0xffda1000
> > +#define SOCFPGA_OCRAM_ADDRESS			0xffe00000
> > +#define GICD_BASE				0xfffc1000
> > +#define GICC_BASE				0xfffc2000
> How much of this can come from DT ?
> 

Just found out Dinh already upstreamed this patch. BTW, we will try to 
use DT when it is possible.

Thanks.

Regards
Ley Foon

[U-Boot] [PATCH v1 05/16] arm: socfpga: misc: Add CONFIG_SYS_L2_PL310 switch

[Ley Foon Tan]

On Fri, Apr 20, 2018 at 7:00 PM, Marek Vasut <marex@denx.de> wrote:
> On 04/20/2018 09:49 AM, Ley Foon Tan wrote:
>> On Thu, Apr 19, 2018 at 4:19 PM, Marek Vasut <marex@denx.de> wrote:
>>> On 04/19/2018 07:15 AM, See, Chin Liang wrote:
>>>> On Thu, 2018-04-19 at 04:47 +0200, Marek Vasut wrote:
>>>>> On 04/19/2018 11:50 AM, Ley Foon Tan wrote:
>>>>>>
>>>>>> Add CONFIG_SYS_L2_PL310 conditional build.
>>>>> Why ?
>>>>>
>>>>
>>>> In ARM64, L2 cache controller is accessed through processor registers.
>>>> Hence we shall make this conditional in order this file can be shared
>>>> across SOCFPGAs.
>>>
>>> That should be in the patch description .
>>> Do you ever add the PL310 register access on S10 later in the set?
>>>
>>> --
>> Okay, will update description.
>> No, S10 doesn't use PL310 registers.
>
> If this PL310 is Gen5 specific, then keep it in some Gen5 file.
>
> --
> Best regards,
> Marek Vasut.

Arria 10 needs this PL310 as well. So, we keep it in common misc.

Regards
Ley Foon

[U-Boot] [PATCH v1 06/16] arm: socfpga: misc: Move eth reset to common misc driver

[Ley Foon Tan]

On Thu, Apr 19, 2018 at 4:20 PM, Marek Vasut <marex@denx.de> wrote:
> On 04/19/2018 05:13 AM, Ley Foon Tan wrote:
>> On Thu, Apr 19, 2018 at 10:47 AM, Marek Vasut <marex@denx.de> wrote:
>>> On 04/19/2018 11:50 AM, Ley Foon Tan wrote:
>>>> Move eth reset to common misc driver so can used by other device families.
>>>>
>>>> Signed-off-by: Chin Liang See <chin.liang.see@intel.com>
>>>> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
>>>
>>> Shouldn't this use the reset framework instead ?
>>>
>> What reset framework you refer to? drivers/reset?
>
> I think so, there were patches from Dinh earlier this month
>  2ac718821a   | Dinh Nguyen  | reset: socfpga: add reset driver for
> SoCFPGA platform
>
Noted, will remove this change.

Regards
Ley Foon

[U-Boot] [PATCH v1 13/16] arm: socfpga: stratix10: Add timer support for Stratix10 SoC

[Ley Foon Tan]

On Thu, Apr 19, 2018 at 4:21 PM, Marek Vasut <marex@denx.de> wrote:
> On 04/19/2018 07:26 AM, See, Chin Liang wrote:
>> On Thu, 2018-04-19 at 04:59 +0200, Marek Vasut wrote:
>>> On 04/19/2018 11:50 AM, Ley Foon Tan wrote:
>>>>
>>>> Add timer support for Stratix SoC
>>> Is this really custom timer or is that some armv8 thing you're adding
>>> here ? Don't we already have a generic implementation for that ? If
>>> not,
>>> that's what we should do here.
>>
>> Yes but not the init function. It's left with platform specific code to
>> init it.
>
> Where is the common part ?
>
> --
> Best regards,
> Marek Vasut

timer_init weak function is in lib/time.c and common code is in this
file as well.

int __weak timer_init(void)
{
    return 0;
}

[U-Boot] [PATCH v1 10/16] arm: dts: Add dts for Stratix10 SoC

[Ley Foon Tan]

On Thu, Apr 19, 2018 at 10:54 AM, Marek Vasut <marex@denx.de> wrote:
> On 04/19/2018 11:50 AM, Ley Foon Tan wrote:
>> Device tree for Stratix10 SoC
>>
>> Signed-off-by: Chin Liang See <chin.liang.see@intel.com>
>> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
>
>
> Is this pulled from mainline Linux or not ?
>
> --
> Best regards,
> Marek Vasut

Will remove this patch and uses commit 81577a3b044645 from Dinh.

Regards
Ley Foon

[U-Boot] [PATCH v1 13/16] arm: socfpga: stratix10: Add timer support for Stratix10 SoC

[Marek Vasut]

On 04/23/2018 03:54 AM, Ley Foon Tan wrote:
> On Thu, Apr 19, 2018 at 4:21 PM, Marek Vasut <marex@denx.de> wrote:
>> On 04/19/2018 07:26 AM, See, Chin Liang wrote:
>>> On Thu, 2018-04-19 at 04:59 +0200, Marek Vasut wrote:
>>>> On 04/19/2018 11:50 AM, Ley Foon Tan wrote:
>>>>>
>>>>> Add timer support for Stratix SoC
>>>> Is this really custom timer or is that some armv8 thing you're adding
>>>> here ? Don't we already have a generic implementation for that ? If
>>>> not,
>>>> that's what we should do here.
>>>
>>> Yes but not the init function. It's left with platform specific code to
>>> init it.
>>
>> Where is the common part ?
>>
>> --
>> Best regards,
>> Marek Vasut
> 
> timer_init weak function is in lib/time.c and common code is in this
> file as well.
> 
> int __weak timer_init(void)
> {
>     return 0;
> }

Oh, that's what you use, I see.

I suspect having a timer_gen5. and timer_gen10.c would be a bit cleaner
than the ifdef.

-- 
Best regards,
Marek Vasut

[U-Boot] [PATCH v1 13/16] arm: socfpga: stratix10: Add timer support for Stratix10 SoC

[Ley Foon Tan]

On Mon, Apr 23, 2018 at 11:40 AM, Marek Vasut <marex@denx.de> wrote:
> On 04/23/2018 03:54 AM, Ley Foon Tan wrote:
>> On Thu, Apr 19, 2018 at 4:21 PM, Marek Vasut <marex@denx.de> wrote:
>>> On 04/19/2018 07:26 AM, See, Chin Liang wrote:
>>>> On Thu, 2018-04-19 at 04:59 +0200, Marek Vasut wrote:
>>>>> On 04/19/2018 11:50 AM, Ley Foon Tan wrote:
>>>>>>
>>>>>> Add timer support for Stratix SoC
>>>>> Is this really custom timer or is that some armv8 thing you're adding
>>>>> here ? Don't we already have a generic implementation for that ? If
>>>>> not,
>>>>> that's what we should do here.
>>>>
>>>> Yes but not the init function. It's left with platform specific code to
>>>> init it.
>>>
>>> Where is the common part ?
>>>
>>> --
>>> Best regards,
>>> Marek Vasut
>>
>> timer_init weak function is in lib/time.c and common code is in this
>> file as well.
>>
>> int __weak timer_init(void)
>> {
>>     return 0;
>> }
>
> Oh, that's what you use, I see.
>
> I suspect having a timer_gen5. and timer_gen10.c would be a bit cleaner
> than the ifdef.
>
> --
Okay, will split them into different files.

Thanks.

Regards
Ley Foon

[U-Boot] [PATCH v1 13/16] arm: socfpga: stratix10: Add timer support for Stratix10 SoC

[Marek Vasut]

On 04/23/2018 08:00 AM, Ley Foon Tan wrote:
> On Mon, Apr 23, 2018 at 11:40 AM, Marek Vasut <marex@denx.de> wrote:
>> On 04/23/2018 03:54 AM, Ley Foon Tan wrote:
>>> On Thu, Apr 19, 2018 at 4:21 PM, Marek Vasut <marex@denx.de> wrote:
>>>> On 04/19/2018 07:26 AM, See, Chin Liang wrote:
>>>>> On Thu, 2018-04-19 at 04:59 +0200, Marek Vasut wrote:
>>>>>> On 04/19/2018 11:50 AM, Ley Foon Tan wrote:
>>>>>>>
>>>>>>> Add timer support for Stratix SoC
>>>>>> Is this really custom timer or is that some armv8 thing you're adding
>>>>>> here ? Don't we already have a generic implementation for that ? If
>>>>>> not,
>>>>>> that's what we should do here.
>>>>>
>>>>> Yes but not the init function. It's left with platform specific code to
>>>>> init it.
>>>>
>>>> Where is the common part ?
>>>>
>>>> --
>>>> Best regards,
>>>> Marek Vasut
>>>
>>> timer_init weak function is in lib/time.c and common code is in this
>>> file as well.
>>>
>>> int __weak timer_init(void)
>>> {
>>>     return 0;
>>> }
>>
>> Oh, that's what you use, I see.
>>
>> I suspect having a timer_gen5. and timer_gen10.c would be a bit cleaner
>> than the ifdef.
>>
>> --
> Okay, will split them into different files.

Thanks

Also please rebase the patchset on u-boot/master , so you won't get
collisions.

-- 
Best regards,
Marek Vasut

[U-Boot] [PATCH v1 13/16] arm: socfpga: stratix10: Add timer support for Stratix10 SoC

[Ley Foon Tan]

On Mon, Apr 23, 2018 at 7:59 PM, Marek Vasut <marex@denx.de> wrote:
> On 04/23/2018 08:00 AM, Ley Foon Tan wrote:
>> On Mon, Apr 23, 2018 at 11:40 AM, Marek Vasut <marex@denx.de> wrote:
>>> On 04/23/2018 03:54 AM, Ley Foon Tan wrote:
>>>> On Thu, Apr 19, 2018 at 4:21 PM, Marek Vasut <marex@denx.de> wrote:
>>>>> On 04/19/2018 07:26 AM, See, Chin Liang wrote:
>>>>>> On Thu, 2018-04-19 at 04:59 +0200, Marek Vasut wrote:
>>>>>>> On 04/19/2018 11:50 AM, Ley Foon Tan wrote:
>>>>>>>>
>>>>>>>> Add timer support for Stratix SoC
>>>>>>> Is this really custom timer or is that some armv8 thing you're adding
>>>>>>> here ? Don't we already have a generic implementation for that ? If
>>>>>>> not,
>>>>>>> that's what we should do here.
>>>>>>
>>>>>> Yes but not the init function. It's left with platform specific code to
>>>>>> init it.
>>>>>
>>>>> Where is the common part ?
>>>>>
>>>>> --
>>>>> Best regards,
>>>>> Marek Vasut
>>>>
>>>> timer_init weak function is in lib/time.c and common code is in this
>>>> file as well.
>>>>
>>>> int __weak timer_init(void)
>>>> {
>>>>     return 0;
>>>> }
>>>
>>> Oh, that's what you use, I see.
>>>
>>> I suspect having a timer_gen5. and timer_gen10.c would be a bit cleaner
>>> than the ifdef.
>>>
>>> --
>> Okay, will split them into different files.
>
> Thanks
>
> Also please rebase the patchset on u-boot/master , so you won't get
> collisions.
>
Noted, will do that.

Thanks.

Regards
Ley Foon

[U-Boot] [PATCH v1 07/16] arm: socfpga: stratix10: Add misc support for Stratix10 SoC

[Ley Foon Tan]

On Thu, Apr 19, 2018 at 10:49 AM, Marek Vasut <marex@denx.de> wrote:
> On 04/19/2018 11:50 AM, Ley Foon Tan wrote:
>> Add misc support such as EMAC and cpu info printout for Stratix SoC
>>
>> Signed-off-by: Chin Liang See <chin.liang.see@intel.com>
>> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
>> ---
>>  arch/arm/mach-socfpga/Makefile   |    1 +
>>  arch/arm/mach-socfpga/misc_s10.c |  103 ++++++++++++++++++++++++++++++++++++++
>>  2 files changed, 104 insertions(+), 0 deletions(-)
>>  create mode 100644 arch/arm/mach-socfpga/misc_s10.c
>>
>> diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
>> index 910eb6f..b253914 100644
>> --- a/arch/arm/mach-socfpga/Makefile
>> +++ b/arch/arm/mach-socfpga/Makefile
>> @@ -32,6 +32,7 @@ endif
>>
>>  ifdef CONFIG_TARGET_SOCFPGA_STRATIX10
>>  obj-y        += clock_manager_s10.o
>> +obj-y        += misc_s10.o
>>  obj-y        += reset_manager_s10.o
>>  obj-y        += system_manager_s10.o
>>  obj-y        += wrap_pinmux_config_s10.o
>> diff --git a/arch/arm/mach-socfpga/misc_s10.c b/arch/arm/mach-socfpga/misc_s10.c
>> new file mode 100644
>> index 0000000..b1cc6ca
>> --- /dev/null
>> +++ b/arch/arm/mach-socfpga/misc_s10.c
>> @@ -0,0 +1,103 @@
>> +// SPDX-License-Identifier: GPL-2.0
>> +/*
>> + * Copyright (C) 2016-2018 Intel Corporation <www.intel.com>
>> + *
>> + */
>> +
>> +#include <altera.h>
>> +#include <common.h>
>> +#include <errno.h>
>> +#include <fdtdec.h>
>> +#include <miiphy.h>
>> +#include <netdev.h>
>> +#include <watchdog.h>
>> +#include <asm/io.h>
>> +#include <asm/arch/reset_manager.h>
>> +#include <asm/arch/system_manager.h>
>> +#include <asm/arch/misc.h>
>> +#include <asm/pl310.h>
>> +#include <linux/libfdt.h>
>> +
>> +#include <dt-bindings/reset/altr,rst-mgr-s10.h>
>> +
>> +DECLARE_GLOBAL_DATA_PTR;
>> +
>> +static struct socfpga_system_manager *sysmgr_regs =
>> +     (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
>> +
>> +/*
>> + * DesignWare Ethernet initialization
>> + */
>> +#ifdef CONFIG_ETH_DESIGNWARE
>
> Use the reset framework ? Talk to Dinh if in doubt
Yes, will convert this to reset framework. Will send out separate
patches to convert device drivers to use reset framework.

>
>> +void dwmac_deassert_reset(const unsigned int of_reset_id,
>> +                       const u32 phymode)
>> +{
>> +     /* Put the emac we're using into reset.
>> +      * This is required before configuring the PHY interface
>> +      */
>> +     socfpga_emac_manage_reset(of_reset_id, 1);
>> +
>> +     clrsetbits_le32(&sysmgr_regs->emac0 + (of_reset_id - EMAC0_RESET),
>> +                     SYSMGR_EMACGRP_CTRL_PHYSEL_MASK,
>> +                     phymode);
>> +
>> +     socfpga_emac_manage_reset(of_reset_id, 0);
>> +}
>> +#endif
>> +
>> +/*
>> + * Print CPU information
>> + */
>> +#if defined(CONFIG_DISPLAY_CPUINFO)
>> +int print_cpuinfo(void)
>> +{
>> +     puts("CPU:   Intel FPGA SoCFPGA Platform\n");
>> +     puts("FPGA:  Intel FPGA Stratix 10\n");
>
> This can well come from DT.

DT only contains the "model" and this is already display in
common/board_info.c:show_board_info().
So, will use simple puts here for the CPU info, unless we want add new
DT property.

Below is example output from console, model is retrieved from DT.

CPU:   Intel FPGA SoCFPGA Platform (ARMv8 64bit Cortex-A53)
Model: SoCFPGA Stratix 10 SoCDK


>
>> +     return 0;
>> +}
>> +#endif
>> +
>> +#ifdef CONFIG_ARCH_MISC_INIT
>> +int arch_misc_init(void)
>> +{
>> +     char qspi_string[13];
>> +
>> +     sprintf(qspi_string, "<0x%08x>", cm_get_qspi_controller_clk_hz());
>> +     env_set("qspi_clock", qspi_string);
>> +
>> +     return socfpga_eth_reset();
>> +}
>> +#endif
>> +
>> +int arch_early_init_r(void)
>> +{
>> +     return 0;
>
> Needed ?
Will remove.
>
>> +}
>> +
>> +int do_bridge(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
>> +{
>> +     if (argc != 2)
>> +             return CMD_RET_USAGE;
>> +
>> +     argv++;
>> +
>> +     switch (*argv[0]) {
>> +     case 'e':       /* Enable */
>> +             socfpga_bridges_reset(1);
>> +             break;
>> +     case 'd':       /* Disable */
>> +             socfpga_bridges_reset(0);
>> +             break;
>
> Do you really need to duplicate this command ?
Will rework this part and merge with Gen5.
>
>> +     default:
>> +             return CMD_RET_USAGE;
>> +     }
>> +
>> +     return 0;
>> +}
>> +
>> +U_BOOT_CMD(bridge, 2, 1, do_bridge,
>> +        "SoCFPGA HPS FPGA bridge control",
>> +        "enable  - Enable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA bridges\n"
>> +        "bridge disable - Disable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA bridges\n"
>> +        ""
>> +);
>>

Thanks.

Regards
Ley Foon

[U-Boot] [PATCH v1 12/16] arm: socfpga: stratix10: Add SPL driver for Stratix10 SoC

[Ley Foon Tan]

On Thu, Apr 19, 2018 at 10:58 AM, Marek Vasut <marex@denx.de> wrote:
> On 04/19/2018 11:50 AM, Ley Foon Tan wrote:
>> Add SPL driver support for Stratix SoC
>>
>> Signed-off-by: Chin Liang See <chin.liang.see@intel.com>
>> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
>> ---
>>  arch/arm/mach-socfpga/Makefile                    |    4 +
>>  arch/arm/mach-socfpga/include/mach/firewall_s10.h |   84 +++++++++
>>  arch/arm/mach-socfpga/spl_s10.c                   |  205 +++++++++++++++++++++
>>  3 files changed, 293 insertions(+), 0 deletions(-)
>>  create mode 100644 arch/arm/mach-socfpga/include/mach/firewall_s10.h
>>  create mode 100644 arch/arm/mach-socfpga/spl_s10.c
>>
>> diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
>> index b669d43..35b124a 100644
>> --- a/arch/arm/mach-socfpga/Makefile
>> +++ b/arch/arm/mach-socfpga/Makefile
>> @@ -40,6 +40,7 @@ obj-y       += system_manager_s10.o
>>  obj-y        += wrap_pinmux_config_s10.o
>>  obj-y        += wrap_pll_config_s10.o
>>  endif
>> +
>>  ifdef CONFIG_SPL_BUILD
>>  ifdef CONFIG_TARGET_SOCFPGA_GEN5
>>  obj-y        += spl_gen5.o
>> @@ -51,6 +52,9 @@ endif
>>  ifdef CONFIG_TARGET_SOCFPGA_ARRIA10
>>  obj-y        += spl_a10.o
>>  endif
>> +ifdef CONFIG_TARGET_SOCFPGA_STRATIX10
>> +obj-y        += spl_s10.o
>> +endif
>>  endif
>>
>>  ifdef CONFIG_TARGET_SOCFPGA_GEN5
>> diff --git a/arch/arm/mach-socfpga/include/mach/firewall_s10.h b/arch/arm/mach-socfpga/include/mach/firewall_s10.h
>> new file mode 100644
>> index 0000000..70aa9a6
>> --- /dev/null
>> +++ b/arch/arm/mach-socfpga/include/mach/firewall_s10.h
>> @@ -0,0 +1,84 @@
>> +/* SPDX-License-Identifier: GPL-2.0
>> + *
>> + * Copyright (C) 2017-2018 Intel Corporation <www.intel.com>
>> + *
>> + */
>> +
>> +#ifndef      _FIREWALL_S10_
>> +#define      _FIREWALL_S10_
>> +
>> +struct socfpga_firwall_l4_per {
>> +     u32     nand;           /* 0x00 */
>> +     u32     nand_data;
>> +     u32     _pad_0x8;
>> +     u32     usb0;
>> +     u32     usb1;           /* 0x10 */
>> +     u32     _pad_0x14;
>> +     u32     _pad_0x18;
>> +     u32     spim0;
>> +     u32     spim1;          /* 0x20 */
>> +     u32     spis0;
>> +     u32     spis1;
>> +     u32     emac0;
>> +     u32     emac1;          /* 0x30 */
>> +     u32     emac2;
>> +     u32     _pad_0x38;
>> +     u32     _pad_0x3c;
>> +     u32     sdmmc;          /* 0x40 */
>> +     u32     gpio0;
>> +     u32     gpio1;
>> +     u32     _pad_0x4c;
>> +     u32     i2c0;           /* 0x50 */
>> +     u32     i2c1;
>> +     u32     i2c2;
>> +     u32     i2c3;
>> +     u32     i2c4;           /* 0x60 */
>> +     u32     timer0;
>> +     u32     timer1;
>> +     u32     uart0;
>> +     u32     uart1;          /* 0x70 */
>> +};
>> +
>> +struct socfpga_firwall_l4_sys {
>> +     u32     _pad_0x00;              /* 0x00 */
>> +     u32     _pad_0x04;
>> +     u32     dma_ecc;
>> +     u32     emac0rx_ecc;
>> +     u32     emac0tx_ecc;            /* 0x10 */
>> +     u32     emac1rx_ecc;
>> +     u32     emac1tx_ecc;
>> +     u32     emac2rx_ecc;
>> +     u32     emac2tx_ecc;            /* 0x20 */
>> +     u32     _pad_0x24;
>> +     u32     _pad_0x28;
>> +     u32     nand_ecc;
>> +     u32     nand_read_ecc;          /* 0x30 */
>> +     u32     nand_write_ecc;
>> +     u32     ocram_ecc;
>> +     u32     _pad_0x3c;
>> +     u32     sdmmc_ecc;              /* 0x40 */
>> +     u32     usb0_ecc;
>> +     u32     usb1_ecc;
>> +     u32     clock_manager;
>> +     u32     _pad_0x50;              /* 0x50 */
>> +     u32     io_manager;
>> +     u32     reset_manager;
>> +     u32     system_manager;
>> +     u32     osc0_timer;             /* 0x60 */
>> +     u32     osc1_timer;
>> +     u32     watchdog0;
>> +     u32     watchdog1;
>> +     u32     watchdog2;              /* 0x70 */
>> +     u32     watchdog3;
>> +};
>> +
>> +#define FIREWALL_L4_DISABLE_ALL              (BIT(0) | BIT(24) | BIT(16))
>> +#define FIREWALL_BRIDGE_DISABLE_ALL  (~0)
>> +
>> +#define CCU_CPU0_MPRT_ADMASK_MEM_RAM0_ADDR   0xf7004688
>> +#define CCU_IOM_MPRT_ADMASK_MEM_RAM0_ADDR    0xf7018628
>> +
>> +#define CCU_ADMASK_P_MASK                    (BIT(0))
>> +#define CCU_ADMASK_NS_MASK                   (BIT(1))
>
> Drop outer parenthesis
Noted.
>
>> +
>> +#endif /* _FIREWALL_S10_ */
>> diff --git a/arch/arm/mach-socfpga/spl_s10.c b/arch/arm/mach-socfpga/spl_s10.c
>> new file mode 100644
>> index 0000000..3b3833d
>> --- /dev/null
>> +++ b/arch/arm/mach-socfpga/spl_s10.c
>> @@ -0,0 +1,205 @@
>> +// SPDX-License-Identifier: GPL-2.0
>> +/*
>> + * Copyright (C) 2016-2018 Intel Corporation <www.intel.com>
>> + *
>> + */
>> +
>> +#include <common.h>
>> +#include <asm/io.h>
>> +#include <asm/u-boot.h>
>> +#include <asm/utils.h>
>> +#include <image.h>
>> +#include <asm/arch/reset_manager.h>
>> +#include <spl.h>
>> +#include <asm/arch/system_manager.h>
>> +#include <asm/arch/clock_manager.h>
>> +#include <asm/arch/sdram_s10.h>
>> +#include <asm/arch/mailbox_s10.h>
>> +#include <asm/arch/firewall_s10.h>
>> +#include <watchdog.h>
>> +
>> +DECLARE_GLOBAL_DATA_PTR;
>> +
>> +static const struct socfpga_firwall_l4_per *firwall_l4_per_base =
>> +     (struct socfpga_firwall_l4_per *)SOCFPGA_FIREWALL_L4_PER;
>> +static const struct socfpga_firwall_l4_sys *firwall_l4_sys_base =
>> +     (struct socfpga_firwall_l4_sys *)SOCFPGA_FIREWALL_L4_SYS;
>> +static struct socfpga_system_manager *sysmgr_regs =
>> +     (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
>> +
>> +u32 spl_boot_device(void)
>> +{
>> +     /* TODO: Get from SDM or handoff */
>> +     return BOOT_DEVICE_MMC1;
>> +}
>> +
>> +#ifdef CONFIG_SPL_MMC_SUPPORT
>> +u32 spl_boot_mode(const u32 boot_device)
>> +{
>> +#if defined(CONFIG_SPL_FAT_SUPPORT) || defined(CONFIG_SPL_EXT_SUPPORT)
>> +     return MMCSD_MODE_FS;
>> +#else
>> +     return MMCSD_MODE_RAW;
>> +#endif
>> +}
>> +#endif
>> +
>> +void board_init_f(ulong dummy)
>> +{
>> +     const struct cm_config *cm_default_cfg = cm_get_default_config();
>> +
>> +#ifdef CONFIG_HW_WATCHDOG
>> +     /* Ensure watchdog is paused when debugging is happening */
>> +     writel(SYSMGR_WDDBG_PAUSE_ALL_CPU, &sysmgr_regs->wddbg);
>> +
>> +     /* Enable watchdog before initializing the HW */
>> +     socfpga_per_reset(SOCFPGA_RESET(L4WD0), 1);
>> +     socfpga_per_reset(SOCFPGA_RESET(L4WD0), 0);
>> +     hw_watchdog_init();
>> +#endif
>> +
>> +     /* ensure all processors are not released prior Linux boot */
>> +     writeq(0, CPU_RELEASE_ADDR);
>> +
>> +     socfpga_per_reset(SOCFPGA_RESET(OSC1TIMER0), 0);
>> +     timer_init();
>> +
>> +     populate_sysmgr_pinmux();
>> +
>> +     /* configuring the HPS clocks */
>> +     cm_basic_init(cm_default_cfg);
>> +
>> +     /* enable console uart printing */
>> +#if (CONFIG_SYS_NS16550_COM1 == SOCFPGA_UART0_ADDRESS)
>
> Yoda notation, please fix. Also, shouldn't the reset controller handle
> this ?
Will remove this and use reset framework.
>
>> +     socfpga_per_reset(SOCFPGA_RESET(UART0), 0);
>> +     /* enables nonsecure access to UART0 */
>> +     writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_per_base->uart0);
>> +#elif (CONFIG_SYS_NS16550_COM1 == SOCFPGA_UART1_ADDRESS)
>> +     socfpga_per_reset(SOCFPGA_RESET(UART1), 0);
>> +     /* enables nonsecure access to UART1 */
>> +     writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_per_base->uart1);
>> +#endif
>> +
>> +     preloader_console_init();
>> +     cm_print_clock_quick_summary();
>
> This function doesn't fit on my pivoted 4k screen with small font, it is
> clearly too long. Please split it.
Okay, will split this function into sub-functions.
>
>> +     /* enable non-secure interface to DMA330 DMA and peripherals */
>> +     writel(SYSMGR_DMA_IRQ_NS | SYSMGR_DMA_MGR_NS, &sysmgr_regs->dma);
>> +     writel(SYSMGR_DMAPERIPH_ALL_NS, &sysmgr_regs->dma_periph);
>> +     /* enable DMA330 DMA */
>> +     socfpga_per_reset(SOCFPGA_RESET(DMA), 0);
>> +
>> +     /*
>> +      * The following lines of code will enable non-secure access
>> +      * to nand, usb, spi, emac, sdmmc, gpio, i2c, and timers. This
>> +      * is needed as most OS run in non-secure mode. Thus we need to
>> +      * enable non-secure access to these peripherals in order for the
>> +      * OS to use these peripherals.
>> +      */
>> +     writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_per_base->nand);
>> +     writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_per_base->nand_data);
>> +     writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_per_base->usb0);
>> +     writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_per_base->usb1);
>> +     writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_per_base->spim0);
>> +     writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_per_base->spim1);
>> +     writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_per_base->emac0);
>> +     writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_per_base->emac1);
>> +     writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_per_base->emac2);
>> +     writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_per_base->sdmmc);
>> +     writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_sys_base->sdmmc_ecc);
>> +     writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_per_base->gpio0);
>> +     writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_per_base->gpio1);
>> +     writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_per_base->i2c0);
>> +     writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_per_base->i2c1);
>> +     writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_per_base->i2c2);
>> +     writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_per_base->i2c3);
>> +     writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_per_base->i2c4);
>> +     writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_per_base->timer0);
>> +     writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_per_base->timer1);
>
> Turn this into a table ?
Okay.
>
>> +     /* enables nonsecure access to clock mgr */
>> +     writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_sys_base->clock_manager);
>> +
>> +     /* enables nonsecure access to reset mgr */
>> +     writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_sys_base->reset_manager);
>> +
>> +     /* enables nonsecure access to system mgr */
>> +     writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_sys_base->system_manager);
>> +
>> +     /* enables nonsecure access to OCRAM */
>> +     writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_sys_base->ocram_ecc);
>> +
>> +     /* enables nonsecure access to all the emacs */
>> +     writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_sys_base->emac0rx_ecc);
>> +     writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_sys_base->emac0tx_ecc);
>> +     writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_sys_base->emac1rx_ecc);
>> +     writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_sys_base->emac1tx_ecc);
>> +     writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_sys_base->emac2rx_ecc);
>> +     writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_sys_base->emac2tx_ecc);
>> +
>> +     /* enables nonsecure access to SMMU */
>> +     writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_sys_base->io_manager);
>> +
>> +     /* enables nonsecure access to watchdog */
>> +     writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_sys_base->watchdog0);
>> +     writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_sys_base->watchdog1);
>> +     writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_sys_base->watchdog2);
>> +     writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_sys_base->watchdog3);
>> +
>> +     /* enables SDMMC */
>> +     socfpga_per_reset(SOCFPGA_RESET(SDMMC_OCP), 0);
>> +     socfpga_per_reset(SOCFPGA_RESET(SDMMC), 0);
>> +     /* enable usb0 and usb1 */
>> +     socfpga_per_reset(SOCFPGA_RESET(USB0), 0);
>> +     socfpga_per_reset(SOCFPGA_RESET(USB1), 0);
>> +     socfpga_per_reset(SOCFPGA_RESET(USB0_OCP), 0);
>> +     socfpga_per_reset(SOCFPGA_RESET(USB1_OCP), 0);
>> +     /* enable SPIM1 */
>> +     socfpga_per_reset(SOCFPGA_RESET(SPIM1), 0);
>
> See below.
>
>> +     /* disable lwsocf2fpga and soc2fpga bridge security */
>> +     writel(FIREWALL_BRIDGE_DISABLE_ALL, SOCFPGA_FIREWALL_SOC2FPGA);
>> +     writel(FIREWALL_BRIDGE_DISABLE_ALL, SOCFPGA_FIREWALL_LWSOC2FPGA);
>> +
>> +     /* disable SMMU security */
>> +     writel(FIREWALL_L4_DISABLE_ALL, SOCFPGA_FIREWALL_TCU);
>> +
>> +     /* disable ocram security at CCU for non secure access */
>> +     clrbits_le32(CCU_CPU0_MPRT_ADMASK_MEM_RAM0_ADDR,
>> +                  CCU_ADMASK_P_MASK | CCU_ADMASK_NS_MASK);
>> +     clrbits_le32(CCU_IOM_MPRT_ADMASK_MEM_RAM0_ADDR,
>> +                  CCU_ADMASK_P_MASK | CCU_ADMASK_NS_MASK);
>> +
>> +     /* enable i2c1 */
>> +     socfpga_per_reset(SOCFPGA_RESET(I2C1), 0);
>> +
>> +     /* Take GPIO0 & GPIO1 out of reset */
>> +     socfpga_per_reset(SOCFPGA_RESET(GPIO0), 0);
>> +     socfpga_per_reset(SOCFPGA_RESET(GPIO1), 0);
>
> Shouldn't this be done by the reset framework ?
Yes, will update DW GPIO to use reset framework.
>
>> +     /* enable SPIM0 and SPIM1 */
>> +     socfpga_per_reset(SOCFPGA_RESET(SPIM0), 0);
>> +     socfpga_per_reset(SOCFPGA_RESET(SPIM1), 0);
>
> You ungated this SPI block already like 20 lines above.
Will remove.
>
>> +     puts("DDR: Initializing Hard Memory Controller\n");
>> +     if (sdram_mmr_init_full(0)) {
>> +             puts("DDR: Initialization failed.\n");
>> +             hang();
>> +     }
>> +
>> +     gd->ram_size = sdram_calculate_size();
>> +     printf("DDR: %d MiB\n", (int)(gd->ram_size >> 20));
>> +
>> +     /* Sanity check ensure correct SDRAM size specified */
>> +     puts("DDR: Running SDRAM size sanity check\n");
>> +     if (get_ram_size(0, gd->ram_size) != gd->ram_size) {
>> +             puts("DDR: SDRAM size check failed!\n");
>> +             hang();
>> +     }
>> +     puts("DDR: SDRAM size check passed!\n");
>
> You can probably turn most of those ad-hoc prints into debug()s.
Noted.
>
>> +
>> +#ifdef CONFIG_CADENCE_QSPI
>> +     mbox_init();
>> +     mbox_qspi_open();
>> +#endif
>> +}
>>
>
>
> --
> Best regards,
> Marek Vasut

[U-Boot] [PATCH v1 07/16] arm: socfpga: stratix10: Add misc support for Stratix10 SoC

[Marek Vasut]

On 04/27/2018 04:10 AM, Ley Foon Tan wrote:
> On Thu, Apr 19, 2018 at 10:49 AM, Marek Vasut <marex@denx.de> wrote:
>> On 04/19/2018 11:50 AM, Ley Foon Tan wrote:
>>> Add misc support such as EMAC and cpu info printout for Stratix SoC
>>>
>>> Signed-off-by: Chin Liang See <chin.liang.see@intel.com>
>>> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
>>> ---
>>>  arch/arm/mach-socfpga/Makefile   |    1 +
>>>  arch/arm/mach-socfpga/misc_s10.c |  103 ++++++++++++++++++++++++++++++++++++++
>>>  2 files changed, 104 insertions(+), 0 deletions(-)
>>>  create mode 100644 arch/arm/mach-socfpga/misc_s10.c
>>>
>>> diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
>>> index 910eb6f..b253914 100644
>>> --- a/arch/arm/mach-socfpga/Makefile
>>> +++ b/arch/arm/mach-socfpga/Makefile
>>> @@ -32,6 +32,7 @@ endif
>>>
>>>  ifdef CONFIG_TARGET_SOCFPGA_STRATIX10
>>>  obj-y        += clock_manager_s10.o
>>> +obj-y        += misc_s10.o
>>>  obj-y        += reset_manager_s10.o
>>>  obj-y        += system_manager_s10.o
>>>  obj-y        += wrap_pinmux_config_s10.o
>>> diff --git a/arch/arm/mach-socfpga/misc_s10.c b/arch/arm/mach-socfpga/misc_s10.c
>>> new file mode 100644
>>> index 0000000..b1cc6ca
>>> --- /dev/null
>>> +++ b/arch/arm/mach-socfpga/misc_s10.c
>>> @@ -0,0 +1,103 @@
>>> +// SPDX-License-Identifier: GPL-2.0
>>> +/*
>>> + * Copyright (C) 2016-2018 Intel Corporation <www.intel.com>
>>> + *
>>> + */
>>> +
>>> +#include <altera.h>
>>> +#include <common.h>
>>> +#include <errno.h>
>>> +#include <fdtdec.h>
>>> +#include <miiphy.h>
>>> +#include <netdev.h>
>>> +#include <watchdog.h>
>>> +#include <asm/io.h>
>>> +#include <asm/arch/reset_manager.h>
>>> +#include <asm/arch/system_manager.h>
>>> +#include <asm/arch/misc.h>
>>> +#include <asm/pl310.h>
>>> +#include <linux/libfdt.h>
>>> +
>>> +#include <dt-bindings/reset/altr,rst-mgr-s10.h>
>>> +
>>> +DECLARE_GLOBAL_DATA_PTR;
>>> +
>>> +static struct socfpga_system_manager *sysmgr_regs =
>>> +     (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
>>> +
>>> +/*
>>> + * DesignWare Ethernet initialization
>>> + */
>>> +#ifdef CONFIG_ETH_DESIGNWARE
>>
>> Use the reset framework ? Talk to Dinh if in doubt
> Yes, will convert this to reset framework. Will send out separate
> patches to convert device drivers to use reset framework.

Thanks, this really helps even for the A10.

http://git.denx.de/?p=u-boot/u-boot-socfpga.git;a=shortlog;h=refs/heads/arria10

>>> +void dwmac_deassert_reset(const unsigned int of_reset_id,
>>> +                       const u32 phymode)
>>> +{
>>> +     /* Put the emac we're using into reset.
>>> +      * This is required before configuring the PHY interface
>>> +      */
>>> +     socfpga_emac_manage_reset(of_reset_id, 1);
>>> +
>>> +     clrsetbits_le32(&sysmgr_regs->emac0 + (of_reset_id - EMAC0_RESET),
>>> +                     SYSMGR_EMACGRP_CTRL_PHYSEL_MASK,
>>> +                     phymode);
>>> +
>>> +     socfpga_emac_manage_reset(of_reset_id, 0);
>>> +}
>>> +#endif
>>> +
>>> +/*
>>> + * Print CPU information
>>> + */
>>> +#if defined(CONFIG_DISPLAY_CPUINFO)
>>> +int print_cpuinfo(void)
>>> +{
>>> +     puts("CPU:   Intel FPGA SoCFPGA Platform\n");
>>> +     puts("FPGA:  Intel FPGA Stratix 10\n");
>>
>> This can well come from DT.
> 
> DT only contains the "model" and this is already display in
> common/board_info.c:show_board_info().
> So, will use simple puts here for the CPU info, unless we want add new
> DT property.

I don't, nope.

> Below is example output from console, model is retrieved from DT.
> 
> CPU:   Intel FPGA SoCFPGA Platform (ARMv8 64bit Cortex-A53)
> Model: SoCFPGA Stratix 10 SoCDK

Ah OK, got it.

>>> +     return 0;
>>> +}
>>> +#endif
>>> +
>>> +#ifdef CONFIG_ARCH_MISC_INIT
>>> +int arch_misc_init(void)
>>> +{
>>> +     char qspi_string[13];
>>> +
>>> +     sprintf(qspi_string, "<0x%08x>", cm_get_qspi_controller_clk_hz());
>>> +     env_set("qspi_clock", qspi_string);
>>> +
>>> +     return socfpga_eth_reset();
>>> +}
>>> +#endif
>>> +
>>> +int arch_early_init_r(void)
>>> +{
>>> +     return 0;
>>
>> Needed ?
> Will remove.
>>
>>> +}
>>> +
>>> +int do_bridge(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
>>> +{
>>> +     if (argc != 2)
>>> +             return CMD_RET_USAGE;
>>> +
>>> +     argv++;
>>> +
>>> +     switch (*argv[0]) {
>>> +     case 'e':       /* Enable */
>>> +             socfpga_bridges_reset(1);
>>> +             break;
>>> +     case 'd':       /* Disable */
>>> +             socfpga_bridges_reset(0);
>>> +             break;
>>
>> Do you really need to duplicate this command ?
> Will rework this part and merge with Gen5.

Great!

>>
>>> +     default:
>>> +             return CMD_RET_USAGE;
>>> +     }
>>> +
>>> +     return 0;
>>> +}
>>> +
>>> +U_BOOT_CMD(bridge, 2, 1, do_bridge,
>>> +        "SoCFPGA HPS FPGA bridge control",
>>> +        "enable  - Enable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA bridges\n"
>>> +        "bridge disable - Disable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA bridges\n"
>>> +        ""
>>> +);
>>>
> 
> Thanks.
> 
> Regards
> Ley Foon
> 


-- 
Best regards,
Marek Vasut

[U-Boot] [PATCH v1 12/16] arm: socfpga: stratix10: Add SPL driver for Stratix10 SoC

[Marek Vasut]

On 04/27/2018 04:14 AM, Ley Foon Tan wrote:
> On Thu, Apr 19, 2018 at 10:58 AM, Marek Vasut <marex@denx.de> wrote:
>> On 04/19/2018 11:50 AM, Ley Foon Tan wrote:
>>> Add SPL driver support for Stratix SoC
>>>
>>> Signed-off-by: Chin Liang See <chin.liang.see@intel.com>
>>> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
>>> ---
>>>  arch/arm/mach-socfpga/Makefile                    |    4 +
>>>  arch/arm/mach-socfpga/include/mach/firewall_s10.h |   84 +++++++++
>>>  arch/arm/mach-socfpga/spl_s10.c                   |  205 +++++++++++++++++++++
>>>  3 files changed, 293 insertions(+), 0 deletions(-)
>>>  create mode 100644 arch/arm/mach-socfpga/include/mach/firewall_s10.h
>>>  create mode 100644 arch/arm/mach-socfpga/spl_s10.c
>>>
>>> diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
>>> index b669d43..35b124a 100644
>>> --- a/arch/arm/mach-socfpga/Makefile
>>> +++ b/arch/arm/mach-socfpga/Makefile
>>> @@ -40,6 +40,7 @@ obj-y       += system_manager_s10.o
>>>  obj-y        += wrap_pinmux_config_s10.o
>>>  obj-y        += wrap_pll_config_s10.o
>>>  endif
>>> +
>>>  ifdef CONFIG_SPL_BUILD
>>>  ifdef CONFIG_TARGET_SOCFPGA_GEN5
>>>  obj-y        += spl_gen5.o
>>> @@ -51,6 +52,9 @@ endif
>>>  ifdef CONFIG_TARGET_SOCFPGA_ARRIA10
>>>  obj-y        += spl_a10.o
>>>  endif
>>> +ifdef CONFIG_TARGET_SOCFPGA_STRATIX10
>>> +obj-y        += spl_s10.o
>>> +endif
>>>  endif
>>>
>>>  ifdef CONFIG_TARGET_SOCFPGA_GEN5
>>> diff --git a/arch/arm/mach-socfpga/include/mach/firewall_s10.h b/arch/arm/mach-socfpga/include/mach/firewall_s10.h
>>> new file mode 100644
>>> index 0000000..70aa9a6
>>> --- /dev/null
>>> +++ b/arch/arm/mach-socfpga/include/mach/firewall_s10.h
>>> @@ -0,0 +1,84 @@
>>> +/* SPDX-License-Identifier: GPL-2.0
>>> + *
>>> + * Copyright (C) 2017-2018 Intel Corporation <www.intel.com>
>>> + *
>>> + */
>>> +
>>> +#ifndef      _FIREWALL_S10_
>>> +#define      _FIREWALL_S10_
>>> +
>>> +struct socfpga_firwall_l4_per {
>>> +     u32     nand;           /* 0x00 */
>>> +     u32     nand_data;
>>> +     u32     _pad_0x8;
>>> +     u32     usb0;
>>> +     u32     usb1;           /* 0x10 */
>>> +     u32     _pad_0x14;
>>> +     u32     _pad_0x18;
>>> +     u32     spim0;
>>> +     u32     spim1;          /* 0x20 */
>>> +     u32     spis0;
>>> +     u32     spis1;
>>> +     u32     emac0;
>>> +     u32     emac1;          /* 0x30 */
>>> +     u32     emac2;
>>> +     u32     _pad_0x38;
>>> +     u32     _pad_0x3c;
>>> +     u32     sdmmc;          /* 0x40 */
>>> +     u32     gpio0;
>>> +     u32     gpio1;
>>> +     u32     _pad_0x4c;
>>> +     u32     i2c0;           /* 0x50 */
>>> +     u32     i2c1;
>>> +     u32     i2c2;
>>> +     u32     i2c3;
>>> +     u32     i2c4;           /* 0x60 */
>>> +     u32     timer0;
>>> +     u32     timer1;
>>> +     u32     uart0;
>>> +     u32     uart1;          /* 0x70 */
>>> +};
>>> +
>>> +struct socfpga_firwall_l4_sys {
>>> +     u32     _pad_0x00;              /* 0x00 */
>>> +     u32     _pad_0x04;
>>> +     u32     dma_ecc;
>>> +     u32     emac0rx_ecc;
>>> +     u32     emac0tx_ecc;            /* 0x10 */
>>> +     u32     emac1rx_ecc;
>>> +     u32     emac1tx_ecc;
>>> +     u32     emac2rx_ecc;
>>> +     u32     emac2tx_ecc;            /* 0x20 */
>>> +     u32     _pad_0x24;
>>> +     u32     _pad_0x28;
>>> +     u32     nand_ecc;
>>> +     u32     nand_read_ecc;          /* 0x30 */
>>> +     u32     nand_write_ecc;
>>> +     u32     ocram_ecc;
>>> +     u32     _pad_0x3c;
>>> +     u32     sdmmc_ecc;              /* 0x40 */
>>> +     u32     usb0_ecc;
>>> +     u32     usb1_ecc;
>>> +     u32     clock_manager;
>>> +     u32     _pad_0x50;              /* 0x50 */
>>> +     u32     io_manager;
>>> +     u32     reset_manager;
>>> +     u32     system_manager;
>>> +     u32     osc0_timer;             /* 0x60 */
>>> +     u32     osc1_timer;
>>> +     u32     watchdog0;
>>> +     u32     watchdog1;
>>> +     u32     watchdog2;              /* 0x70 */
>>> +     u32     watchdog3;
>>> +};
>>> +
>>> +#define FIREWALL_L4_DISABLE_ALL              (BIT(0) | BIT(24) | BIT(16))
>>> +#define FIREWALL_BRIDGE_DISABLE_ALL  (~0)
>>> +
>>> +#define CCU_CPU0_MPRT_ADMASK_MEM_RAM0_ADDR   0xf7004688
>>> +#define CCU_IOM_MPRT_ADMASK_MEM_RAM0_ADDR    0xf7018628
>>> +
>>> +#define CCU_ADMASK_P_MASK                    (BIT(0))
>>> +#define CCU_ADMASK_NS_MASK                   (BIT(1))
>>
>> Drop outer parenthesis
> Noted.
>>
>>> +
>>> +#endif /* _FIREWALL_S10_ */
>>> diff --git a/arch/arm/mach-socfpga/spl_s10.c b/arch/arm/mach-socfpga/spl_s10.c
>>> new file mode 100644
>>> index 0000000..3b3833d
>>> --- /dev/null
>>> +++ b/arch/arm/mach-socfpga/spl_s10.c
>>> @@ -0,0 +1,205 @@
>>> +// SPDX-License-Identifier: GPL-2.0
>>> +/*
>>> + * Copyright (C) 2016-2018 Intel Corporation <www.intel.com>
>>> + *
>>> + */
>>> +
>>> +#include <common.h>
>>> +#include <asm/io.h>
>>> +#include <asm/u-boot.h>
>>> +#include <asm/utils.h>
>>> +#include <image.h>
>>> +#include <asm/arch/reset_manager.h>
>>> +#include <spl.h>
>>> +#include <asm/arch/system_manager.h>
>>> +#include <asm/arch/clock_manager.h>
>>> +#include <asm/arch/sdram_s10.h>
>>> +#include <asm/arch/mailbox_s10.h>
>>> +#include <asm/arch/firewall_s10.h>
>>> +#include <watchdog.h>
>>> +
>>> +DECLARE_GLOBAL_DATA_PTR;
>>> +
>>> +static const struct socfpga_firwall_l4_per *firwall_l4_per_base =
>>> +     (struct socfpga_firwall_l4_per *)SOCFPGA_FIREWALL_L4_PER;
>>> +static const struct socfpga_firwall_l4_sys *firwall_l4_sys_base =
>>> +     (struct socfpga_firwall_l4_sys *)SOCFPGA_FIREWALL_L4_SYS;
>>> +static struct socfpga_system_manager *sysmgr_regs =
>>> +     (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
>>> +
>>> +u32 spl_boot_device(void)
>>> +{
>>> +     /* TODO: Get from SDM or handoff */
>>> +     return BOOT_DEVICE_MMC1;
>>> +}
>>> +
>>> +#ifdef CONFIG_SPL_MMC_SUPPORT
>>> +u32 spl_boot_mode(const u32 boot_device)
>>> +{
>>> +#if defined(CONFIG_SPL_FAT_SUPPORT) || defined(CONFIG_SPL_EXT_SUPPORT)
>>> +     return MMCSD_MODE_FS;
>>> +#else
>>> +     return MMCSD_MODE_RAW;
>>> +#endif
>>> +}
>>> +#endif
>>> +
>>> +void board_init_f(ulong dummy)
>>> +{
>>> +     const struct cm_config *cm_default_cfg = cm_get_default_config();
>>> +
>>> +#ifdef CONFIG_HW_WATCHDOG
>>> +     /* Ensure watchdog is paused when debugging is happening */
>>> +     writel(SYSMGR_WDDBG_PAUSE_ALL_CPU, &sysmgr_regs->wddbg);
>>> +
>>> +     /* Enable watchdog before initializing the HW */
>>> +     socfpga_per_reset(SOCFPGA_RESET(L4WD0), 1);
>>> +     socfpga_per_reset(SOCFPGA_RESET(L4WD0), 0);
>>> +     hw_watchdog_init();
>>> +#endif
>>> +
>>> +     /* ensure all processors are not released prior Linux boot */
>>> +     writeq(0, CPU_RELEASE_ADDR);
>>> +
>>> +     socfpga_per_reset(SOCFPGA_RESET(OSC1TIMER0), 0);
>>> +     timer_init();
>>> +
>>> +     populate_sysmgr_pinmux();
>>> +
>>> +     /* configuring the HPS clocks */
>>> +     cm_basic_init(cm_default_cfg);
>>> +
>>> +     /* enable console uart printing */
>>> +#if (CONFIG_SYS_NS16550_COM1 == SOCFPGA_UART0_ADDRESS)
>>
>> Yoda notation, please fix. Also, shouldn't the reset controller handle
>> this ?
> Will remove this and use reset framework.
>>
>>> +     socfpga_per_reset(SOCFPGA_RESET(UART0), 0);
>>> +     /* enables nonsecure access to UART0 */
>>> +     writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_per_base->uart0);
>>> +#elif (CONFIG_SYS_NS16550_COM1 == SOCFPGA_UART1_ADDRESS)
>>> +     socfpga_per_reset(SOCFPGA_RESET(UART1), 0);
>>> +     /* enables nonsecure access to UART1 */
>>> +     writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_per_base->uart1);
>>> +#endif
>>> +
>>> +     preloader_console_init();
>>> +     cm_print_clock_quick_summary();
>>
>> This function doesn't fit on my pivoted 4k screen with small font, it is
>> clearly too long. Please split it.
> Okay, will split this function into sub-functions.
>>
>>> +     /* enable non-secure interface to DMA330 DMA and peripherals */
>>> +     writel(SYSMGR_DMA_IRQ_NS | SYSMGR_DMA_MGR_NS, &sysmgr_regs->dma);
>>> +     writel(SYSMGR_DMAPERIPH_ALL_NS, &sysmgr_regs->dma_periph);
>>> +     /* enable DMA330 DMA */
>>> +     socfpga_per_reset(SOCFPGA_RESET(DMA), 0);
>>> +
>>> +     /*
>>> +      * The following lines of code will enable non-secure access
>>> +      * to nand, usb, spi, emac, sdmmc, gpio, i2c, and timers. This
>>> +      * is needed as most OS run in non-secure mode. Thus we need to
>>> +      * enable non-secure access to these peripherals in order for the
>>> +      * OS to use these peripherals.
>>> +      */
>>> +     writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_per_base->nand);
>>> +     writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_per_base->nand_data);
>>> +     writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_per_base->usb0);
>>> +     writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_per_base->usb1);
>>> +     writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_per_base->spim0);
>>> +     writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_per_base->spim1);
>>> +     writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_per_base->emac0);
>>> +     writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_per_base->emac1);
>>> +     writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_per_base->emac2);
>>> +     writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_per_base->sdmmc);
>>> +     writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_sys_base->sdmmc_ecc);
>>> +     writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_per_base->gpio0);
>>> +     writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_per_base->gpio1);
>>> +     writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_per_base->i2c0);
>>> +     writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_per_base->i2c1);
>>> +     writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_per_base->i2c2);
>>> +     writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_per_base->i2c3);
>>> +     writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_per_base->i2c4);
>>> +     writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_per_base->timer0);
>>> +     writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_per_base->timer1);
>>
>> Turn this into a table ?
> Okay.
>>
>>> +     /* enables nonsecure access to clock mgr */
>>> +     writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_sys_base->clock_manager);
>>> +
>>> +     /* enables nonsecure access to reset mgr */
>>> +     writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_sys_base->reset_manager);
>>> +
>>> +     /* enables nonsecure access to system mgr */
>>> +     writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_sys_base->system_manager);
>>> +
>>> +     /* enables nonsecure access to OCRAM */
>>> +     writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_sys_base->ocram_ecc);
>>> +
>>> +     /* enables nonsecure access to all the emacs */
>>> +     writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_sys_base->emac0rx_ecc);
>>> +     writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_sys_base->emac0tx_ecc);
>>> +     writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_sys_base->emac1rx_ecc);
>>> +     writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_sys_base->emac1tx_ecc);
>>> +     writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_sys_base->emac2rx_ecc);
>>> +     writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_sys_base->emac2tx_ecc);
>>> +
>>> +     /* enables nonsecure access to SMMU */
>>> +     writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_sys_base->io_manager);
>>> +
>>> +     /* enables nonsecure access to watchdog */
>>> +     writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_sys_base->watchdog0);
>>> +     writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_sys_base->watchdog1);
>>> +     writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_sys_base->watchdog2);
>>> +     writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_sys_base->watchdog3);
>>> +
>>> +     /* enables SDMMC */
>>> +     socfpga_per_reset(SOCFPGA_RESET(SDMMC_OCP), 0);
>>> +     socfpga_per_reset(SOCFPGA_RESET(SDMMC), 0);
>>> +     /* enable usb0 and usb1 */
>>> +     socfpga_per_reset(SOCFPGA_RESET(USB0), 0);
>>> +     socfpga_per_reset(SOCFPGA_RESET(USB1), 0);
>>> +     socfpga_per_reset(SOCFPGA_RESET(USB0_OCP), 0);
>>> +     socfpga_per_reset(SOCFPGA_RESET(USB1_OCP), 0);
>>> +     /* enable SPIM1 */
>>> +     socfpga_per_reset(SOCFPGA_RESET(SPIM1), 0);
>>
>> See below.
>>
>>> +     /* disable lwsocf2fpga and soc2fpga bridge security */
>>> +     writel(FIREWALL_BRIDGE_DISABLE_ALL, SOCFPGA_FIREWALL_SOC2FPGA);
>>> +     writel(FIREWALL_BRIDGE_DISABLE_ALL, SOCFPGA_FIREWALL_LWSOC2FPGA);
>>> +
>>> +     /* disable SMMU security */
>>> +     writel(FIREWALL_L4_DISABLE_ALL, SOCFPGA_FIREWALL_TCU);
>>> +
>>> +     /* disable ocram security at CCU for non secure access */
>>> +     clrbits_le32(CCU_CPU0_MPRT_ADMASK_MEM_RAM0_ADDR,
>>> +                  CCU_ADMASK_P_MASK | CCU_ADMASK_NS_MASK);
>>> +     clrbits_le32(CCU_IOM_MPRT_ADMASK_MEM_RAM0_ADDR,
>>> +                  CCU_ADMASK_P_MASK | CCU_ADMASK_NS_MASK);
>>> +
>>> +     /* enable i2c1 */
>>> +     socfpga_per_reset(SOCFPGA_RESET(I2C1), 0);
>>> +
>>> +     /* Take GPIO0 & GPIO1 out of reset */
>>> +     socfpga_per_reset(SOCFPGA_RESET(GPIO0), 0);
>>> +     socfpga_per_reset(SOCFPGA_RESET(GPIO1), 0);
>>
>> Shouldn't this be done by the reset framework ?
> Yes, will update DW GPIO to use reset framework.
>>
>>> +     /* enable SPIM0 and SPIM1 */
>>> +     socfpga_per_reset(SOCFPGA_RESET(SPIM0), 0);
>>> +     socfpga_per_reset(SOCFPGA_RESET(SPIM1), 0);
>>
>> You ungated this SPI block already like 20 lines above.
> Will remove.
Thanks

-- 
Best regards,
Marek Vasut

[U-Boot] [PATCH v1 07/16] arm: socfpga: stratix10: Add misc support for Stratix10 SoC

[Ley Foon Tan]

On Fri, Apr 27, 2018 at 3:05 PM, Marek Vasut <marex@denx.de> wrote:
> On 04/27/2018 04:10 AM, Ley Foon Tan wrote:
>> On Thu, Apr 19, 2018 at 10:49 AM, Marek Vasut <marex@denx.de> wrote:
>>> On 04/19/2018 11:50 AM, Ley Foon Tan wrote:
>>>> Add misc support such as EMAC and cpu info printout for Stratix SoC
>>>>
>>>> Signed-off-by: Chin Liang See <chin.liang.see@intel.com>
>>>> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
>>>> ---
>>>>  arch/arm/mach-socfpga/Makefile   |    1 +
>>>>  arch/arm/mach-socfpga/misc_s10.c |  103 ++++++++++++++++++++++++++++++++++++++
>>>>  2 files changed, 104 insertions(+), 0 deletions(-)
>>>>  create mode 100644 arch/arm/mach-socfpga/misc_s10.c
>>>>
>>>> diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
>>>> index 910eb6f..b253914 100644
>>>> --- a/arch/arm/mach-socfpga/Makefile
>>>> +++ b/arch/arm/mach-socfpga/Makefile
>>>> @@ -32,6 +32,7 @@ endif
>>>>
>>>>  ifdef CONFIG_TARGET_SOCFPGA_STRATIX10
>>>>  obj-y        += clock_manager_s10.o
>>>> +obj-y        += misc_s10.o
>>>>  obj-y        += reset_manager_s10.o
>>>>  obj-y        += system_manager_s10.o
>>>>  obj-y        += wrap_pinmux_config_s10.o
>>>> diff --git a/arch/arm/mach-socfpga/misc_s10.c b/arch/arm/mach-socfpga/misc_s10.c
>>>> new file mode 100644
>>>> index 0000000..b1cc6ca
>>>> --- /dev/null
>>>> +++ b/arch/arm/mach-socfpga/misc_s10.c
>>>> @@ -0,0 +1,103 @@
>>>> +// SPDX-License-Identifier: GPL-2.0
>>>> +/*
>>>> + * Copyright (C) 2016-2018 Intel Corporation <www.intel.com>
>>>> + *
>>>> + */
>>>> +
>>>> +#include <altera.h>
>>>> +#include <common.h>
>>>> +#include <errno.h>
>>>> +#include <fdtdec.h>
>>>> +#include <miiphy.h>
>>>> +#include <netdev.h>
>>>> +#include <watchdog.h>
>>>> +#include <asm/io.h>
>>>> +#include <asm/arch/reset_manager.h>
>>>> +#include <asm/arch/system_manager.h>
>>>> +#include <asm/arch/misc.h>
>>>> +#include <asm/pl310.h>
>>>> +#include <linux/libfdt.h>
>>>> +
>>>> +#include <dt-bindings/reset/altr,rst-mgr-s10.h>
>>>> +
>>>> +DECLARE_GLOBAL_DATA_PTR;
>>>> +
>>>> +static struct socfpga_system_manager *sysmgr_regs =
>>>> +     (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
>>>> +
>>>> +/*
>>>> + * DesignWare Ethernet initialization
>>>> + */
>>>> +#ifdef CONFIG_ETH_DESIGNWARE
>>>
>>> Use the reset framework ? Talk to Dinh if in doubt
>> Yes, will convert this to reset framework. Will send out separate
>> patches to convert device drivers to use reset framework.
>
> Thanks, this really helps even for the A10.
>
> http://git.denx.de/?p=u-boot/u-boot-socfpga.git;a=shortlog;h=refs/heads/arria10

I saw you have new patches on this git repo, should I rebase my
patchset on top of this git repo or using main u-boot.git?

Regards
Ley Foon

[U-Boot] [PATCH v1 07/16] arm: socfpga: stratix10: Add misc support for Stratix10 SoC

[Marek Vasut]

On 04/27/2018 10:04 AM, Ley Foon Tan wrote:
> On Fri, Apr 27, 2018 at 3:05 PM, Marek Vasut <marex@denx.de> wrote:
>> On 04/27/2018 04:10 AM, Ley Foon Tan wrote:
>>> On Thu, Apr 19, 2018 at 10:49 AM, Marek Vasut <marex@denx.de> wrote:
>>>> On 04/19/2018 11:50 AM, Ley Foon Tan wrote:
>>>>> Add misc support such as EMAC and cpu info printout for Stratix SoC
>>>>>
>>>>> Signed-off-by: Chin Liang See <chin.liang.see@intel.com>
>>>>> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
>>>>> ---
>>>>>  arch/arm/mach-socfpga/Makefile   |    1 +
>>>>>  arch/arm/mach-socfpga/misc_s10.c |  103 ++++++++++++++++++++++++++++++++++++++
>>>>>  2 files changed, 104 insertions(+), 0 deletions(-)
>>>>>  create mode 100644 arch/arm/mach-socfpga/misc_s10.c
>>>>>
>>>>> diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
>>>>> index 910eb6f..b253914 100644
>>>>> --- a/arch/arm/mach-socfpga/Makefile
>>>>> +++ b/arch/arm/mach-socfpga/Makefile
>>>>> @@ -32,6 +32,7 @@ endif
>>>>>
>>>>>  ifdef CONFIG_TARGET_SOCFPGA_STRATIX10
>>>>>  obj-y        += clock_manager_s10.o
>>>>> +obj-y        += misc_s10.o
>>>>>  obj-y        += reset_manager_s10.o
>>>>>  obj-y        += system_manager_s10.o
>>>>>  obj-y        += wrap_pinmux_config_s10.o
>>>>> diff --git a/arch/arm/mach-socfpga/misc_s10.c b/arch/arm/mach-socfpga/misc_s10.c
>>>>> new file mode 100644
>>>>> index 0000000..b1cc6ca
>>>>> --- /dev/null
>>>>> +++ b/arch/arm/mach-socfpga/misc_s10.c
>>>>> @@ -0,0 +1,103 @@
>>>>> +// SPDX-License-Identifier: GPL-2.0
>>>>> +/*
>>>>> + * Copyright (C) 2016-2018 Intel Corporation <www.intel.com>
>>>>> + *
>>>>> + */
>>>>> +
>>>>> +#include <altera.h>
>>>>> +#include <common.h>
>>>>> +#include <errno.h>
>>>>> +#include <fdtdec.h>
>>>>> +#include <miiphy.h>
>>>>> +#include <netdev.h>
>>>>> +#include <watchdog.h>
>>>>> +#include <asm/io.h>
>>>>> +#include <asm/arch/reset_manager.h>
>>>>> +#include <asm/arch/system_manager.h>
>>>>> +#include <asm/arch/misc.h>
>>>>> +#include <asm/pl310.h>
>>>>> +#include <linux/libfdt.h>
>>>>> +
>>>>> +#include <dt-bindings/reset/altr,rst-mgr-s10.h>
>>>>> +
>>>>> +DECLARE_GLOBAL_DATA_PTR;
>>>>> +
>>>>> +static struct socfpga_system_manager *sysmgr_regs =
>>>>> +     (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
>>>>> +
>>>>> +/*
>>>>> + * DesignWare Ethernet initialization
>>>>> + */
>>>>> +#ifdef CONFIG_ETH_DESIGNWARE
>>>>
>>>> Use the reset framework ? Talk to Dinh if in doubt
>>> Yes, will convert this to reset framework. Will send out separate
>>> patches to convert device drivers to use reset framework.
>>
>> Thanks, this really helps even for the A10.
>>
>> http://git.denx.de/?p=u-boot/u-boot-socfpga.git;a=shortlog;h=refs/heads/arria10
> 
> I saw you have new patches on this git repo, should I rebase my
> patchset on top of this git repo or using main u-boot.git?

Is there anything that'll collide ? If you find anything useful there,
feel free to use it.

-- 
Best regards,
Marek Vasut

[U-Boot] [PATCH v1 08/16] arm: socfpga: stratix10: Add mailbox support for Stratix10 SoC

[Ley Foon Tan]

On Thu, Apr 19, 2018 at 10:53 AM, Marek Vasut <marex@denx.de> wrote:
> On 04/19/2018 11:50 AM, Ley Foon Tan wrote:
>> Add mailbox support for Stratix SoC
>>
>> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
>> Signed-off-by: Chin Liang See <chin.liang.see@intel.com>
>> ---
>>  arch/arm/mach-socfpga/Makefile                   |    1 +
>>  arch/arm/mach-socfpga/include/mach/mailbox_s10.h |  155 +++++++++
>>  arch/arm/mach-socfpga/mailbox_s10.c              |  378 ++++++++++++++++++++++
>>  3 files changed, 534 insertions(+), 0 deletions(-)
>>  create mode 100644 arch/arm/mach-socfpga/include/mach/mailbox_s10.h
>>  create mode 100644 arch/arm/mach-socfpga/mailbox_s10.c
>>
>> diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
>> index b253914..43e18d2 100644
>> --- a/arch/arm/mach-socfpga/Makefile
>> +++ b/arch/arm/mach-socfpga/Makefile
>> @@ -32,6 +32,7 @@ endif
>>
>>  ifdef CONFIG_TARGET_SOCFPGA_STRATIX10
>>  obj-y        += clock_manager_s10.o
>> +obj-y        += mailbox_s10.o
>>  obj-y        += misc_s10.o
>>  obj-y        += reset_manager_s10.o
>>  obj-y        += system_manager_s10.o
>> diff --git a/arch/arm/mach-socfpga/include/mach/mailbox_s10.h b/arch/arm/mach-socfpga/include/mach/mailbox_s10.h
>> new file mode 100644
>> index 0000000..85e7f84
>> --- /dev/null
>> +++ b/arch/arm/mach-socfpga/include/mach/mailbox_s10.h
>> @@ -0,0 +1,155 @@
>> +/* SPDX-License-Identifier: GPL-2.0
>> + *
>> + * Copyright (C) 2017-2018 Intel Corporation <www.intel.com>
>> + *
>> + */
>> +
>> +#ifndef _MAILBOX_S10_H_
>> +#define _MAILBOX_S10_H_
>> +
>> +/* user define Uboot ID */
>> +#define MBOX_CLIENT_ID_UBOOT 0xB
>> +#define MBOX_ID_UBOOT                0x1
>> +
>> +#define MBOX_CMD_DIRECT      0
>> +#define MBOX_CMD_INDIRECT    1
>> +
>> +#define MBOX_MAX_CMD_INDEX   2047
>> +#define MBOX_CMD_BUFFER_SIZE 32
>> +#define MBOX_RESP_BUFFER_SIZE        16
>> +
>> +#define MBOX_HDR_CMD_LSB     0
>> +#define MBOX_HDR_CMD_MSK     (BIT(11) - 1)
>> +#define MBOX_HDR_I_LSB               11
>> +#define MBOX_HDR_I_MSK               BIT(11)
>> +#define MBOX_HDR_LEN_LSB     12
>> +#define MBOX_HDR_LEN_MSK     0x007FF000
>> +#define MBOX_HDR_ID_LSB              24
>> +#define MBOX_HDR_ID_MSK              0x0F000000
>> +#define MBOX_HDR_CLIENT_LSB  28
>> +#define MBOX_HDR_CLIENT_MSK  0xF0000000
>> +
>> +/* Interrupt flags */
>> +#define MBOX_FLAGS_INT_COE   BIT(0)  /* COUT update interrupt enable */
>> +#define MBOX_FLAGS_INT_RIE   BIT(1)  /* RIN update interrupt enable */
>> +#define MBOX_FLAGS_INT_UAE   BIT(8)  /* Urgent ACK interrupt enable */
>> +#define MBOX_ALL_INTRS               (MBOX_FLAGS_INT_COE | \
>> +                              MBOX_FLAGS_INT_RIE | \
>> +                              MBOX_FLAGS_INT_UAE)
>> +
>> +/* Status */
>> +#define MBOX_STATUS_UA_MSK   BIT(8)
>> +
>> +#define MBOX_CMD_HEADER(client, id, len, indirect, cmd)     \
>> +     ((((cmd) << MBOX_HDR_CMD_LSB) & MBOX_HDR_CMD_MSK) | \
>> +     (((indirect) << MBOX_HDR_I_LSB) & MBOX_HDR_I_MSK) | \
>> +     (((len) << MBOX_HDR_LEN_LSB) & MBOX_HDR_LEN_MSK)  | \
>> +     (((id) << MBOX_HDR_ID_LSB) & MBOX_HDR_ID_MSK)     | \
>> +     (((client) << MBOX_HDR_CLIENT_LSB) & MBOX_HDR_CLIENT_MSK))
>> +
>> +#define MBOX_RESP_ERR_GET(resp)                              \
>> +     (((resp) & MBOX_HDR_CMD_MSK) >> MBOX_HDR_CMD_LSB)
>> +#define MBOX_RESP_LEN_GET(resp)                      \
>> +     (((resp) & MBOX_HDR_LEN_MSK) >> MBOX_HDR_LEN_LSB)
>> +#define MBOX_RESP_ID_GET(resp)                               \
>> +     (((resp) & MBOX_HDR_ID_MSK) >> MBOX_HDR_ID_LSB)
>> +#define MBOX_RESP_CLIENT_GET(resp)                   \
>> +     (((resp) & MBOX_HDR_CLIENT_MSK) >> MBOX_HDR_CLIENT_LSB)
>> +
>> +/* Response error list */
>> +enum ALT_SDM_MBOX_RESP_CODE {
>> +     /* CMD completed successfully, but check resp ARGS for any errors */
>> +     MBOX_RESP_STATOK = 0,
>> +     /* CMD is incorrectly formatted in some way */
>> +     MBOX_RESP_INVALID_COMMAND = 1,
>> +     /* BootROM Command code not undesrtood */
>> +     MBOX_RESP_UNKNOWN_BR = 2,
>> +     /* CMD code not recognized by firmware */
>> +     MBOX_RESP_UNKNOWN = 3,
>> +     /* Indicates that the device is not configured */
>> +     MBOX_RESP_NOT_CONFIGURED = 256,
>> +     /* Indicates that the device is busy */
>> +     MBOX_RESP_DEVICE_BUSY = 0x1FF,
>> +     /* Indicates that there is no valid response available */
>> +     MBOX_RESP_NO_VALID_RESP_AVAILABLE = 0x2FF,
>> +     /* General Error */
>> +     MBOX_RESP_ERROR = 0x3FF,
>> +};
>> +
>> +/* Mailbox command list */
>> +#define MBOX_RESTART         2
>> +#define MBOX_CONFIG_STATUS   4
>> +#define MBOX_RECONFIG                6
>> +#define MBOX_RECONFIG_MSEL   7
>> +#define MBOX_RECONFIG_DATA   8
>> +#define MBOX_RECONFIG_STATUS 9
>> +#define MBOX_QSPI_OPEN               50
>> +#define MBOX_QSPI_CLOSE              51
>> +#define MBOX_QSPI_DIRECT     59
>> +#define MBOX_REBOOT_HPS              71
>> +
>> +struct socfpga_mailbox {
>
> We should probably just use register offset macros in new code, this
> struct {} stuff often doesn't work too well and the limitations are showing.
Okay, will change this.
>
>> +     u32 cin;                /* command valid offset */
>> +     u32 rout;               /* response output offset */
>> +     u32 urg;                /* urgent command */
>> +     u32 flags;              /* interrupt enables */
>> +     u32 pad_0x10_0x1f[4];   /* 0x10 - 0x1F reserved */
>> +     u32 cout;               /* command free offset */
>> +     u32 rin;                /* respond valid offset */
>> +     u32 pad_0x28;           /* 0x28 reserved */
>> +     u32 status;             /* mailbox status */
>> +     u32 pad_0x30_0x3f[4];   /* 0x30 - 0x3F reserved */
>> +     u32 cmd_buf[MBOX_CMD_BUFFER_SIZE];      /* 0x40 - 0xBC circular command
>> +                                              * buffer to SDM
>> +                                              */
>> +     u32 resp_buf[MBOX_RESP_BUFFER_SIZE];    /* 0xC0 - 0xFF circular
>> +                                              * response buffer
>> +                                              */
>> +};
>> +
>> +/* Use define other than put into struct socfpga_mailbox to save spaces */
>> +#define MBOX_DOORBELL_TO_SDM_REG     (SOCFPGA_MAILBOX_ADDRESS + 0x400)
>> +#define MBOX_DOORBELL_FROM_SDM_REG   (SOCFPGA_MAILBOX_ADDRESS + 0x480)
>> +
>> +/******** Status and bit information returned by RECONFIG_STATUS ********/
>> +#define RECONFIG_STATUS_RESPONSE_LEN                 6
>> +#define RECONFIG_STATUS_STATE                                0
>> +#define RECONFIG_STATUS_PIN_STATUS                   2
>> +#define RECONFIG_STATUS_SOFTFUNC_STATUS                      3
>> +
>> +#define MBOX_CFGSTAT_STATE_IDLE                              0x00000000
>> +#define MBOX_CFGSTAT_STATE_CONFIG                    0x10000000
>> +#define MBOX_CFGSTAT_STATE_FAILACK                   0x08000000
>> +#define MBOX_CFGSTAT_STATE_ERROR_INVALID             0xf0000001
>> +#define MBOX_CFGSTAT_STATE_ERROR_CORRUPT             0xf0000002
>> +#define MBOX_CFGSTAT_STATE_ERROR_AUTH                        0xf0000003
>> +#define MBOX_CFGSTAT_STATE_ERROR_CORE_IO             0xf0000004
>> +#define MBOX_CFGSTAT_STATE_ERROR_HARDWARE            0xf0000005
>> +#define MBOX_CFGSTAT_STATE_ERROR_FAKE                        0xf0000006
>> +#define MBOX_CFGSTAT_STATE_ERROR_BOOT_INFO           0xf0000007
>> +#define MBOX_CFGSTAT_STATE_ERROR_QSPI_ERROR          0xf0000008
>> +
>> +#define RCF_SOFTFUNC_STATUS_CONF_DONE                        BIT(0)
>> +#define RCF_SOFTFUNC_STATUS_INIT_DONE                        BIT(1)
>> +#define RCF_SOFTFUNC_STATUS_SEU_ERROR                        BIT(3)
>> +#define RCF_PIN_STATUS_NSTATUS                               BIT(31)
>> +/************************************************************************/
>> +
>> +int mbox_send_cmd(u8 id, u32 cmd, u8 is_indirect, u32 len, u32 *arg, u8 urgent,
>> +               u32 *resp_buf_len, u32 *resp_buf);
>> +int mbox_send_cmd_psci(u8 id, u32 cmd, u8 is_indirect, u32 len, u32 *arg,
>> +                    u8 urgent, u32 *resp_buf_len, u32 *resp_buf);
>> +int mbox_send_cmd_only(u8 id, u32 cmd, u8 is_indirect, u32 len, u32 *arg);
>> +int mbox_send_cmd_only_psci(u8 id, u32 cmd, u8 is_indirect, u32 len, u32 *arg);
>> +int mbox_rcv_resp(u32 *resp_buf, u32 resp_buf_max_len);
>> +int mbox_rcv_resp_psci(u32 *resp_buf, u32 resp_buf_max_len);
>> +int mbox_init(void);
>> +
>> +#ifdef CONFIG_CADENCE_QSPI
>> +int mbox_qspi_close(void);
>> +int mbox_qspi_open(void);
>> +#endif
>> +
>> +int mbox_reset_cold(void);
>> +
>> +#endif /* _MAILBOX_S10_H_ */
>> diff --git a/arch/arm/mach-socfpga/mailbox_s10.c b/arch/arm/mach-socfpga/mailbox_s10.c
>> new file mode 100644
>> index 0000000..ed713a9
>> --- /dev/null
>> +++ b/arch/arm/mach-socfpga/mailbox_s10.c
>> @@ -0,0 +1,378 @@
>> +// SPDX-License-Identifier: GPL-2.0
>> +/*
>> + * Copyright (C) 2017-2018 Intel Corporation <www.intel.com>
>> + *
>> + */
>> +
>> +#include <common.h>
>> +#include <wait_bit.h>
>> +#include <asm/io.h>
>> +#include <asm/arch/mailbox_s10.h>
>> +#include <asm/arch/system_manager.h>
>> +#include <asm/secure.h>
>> +
>> +DECLARE_GLOBAL_DATA_PTR;
>> +
>> +static __always_inline int mbox_polling_resp(u32 rout)
>> +{
>> +     static const struct socfpga_mailbox *mbox_base =
>> +                                     (void *)SOCFPGA_MAILBOX_ADDRESS;
>> +     u32 rin;
>> +     unsigned long i = ~0;
>> +
>> +     while (i) {
>> +             rin = readl(&mbox_base->rin);
>> +             if (rout != rin)
>> +                     return 0;
>
> This looks like include/wait_bit.h reimplementation
The reason we use this method instead of using wait_bit because this
function will use in Secure Monitor Call (SMC) call as well.
When run in secure section, timer is not available.  So, we can't use
wait_for_bit.

>
>> +             i--;
>> +     }
>> +
>> +     return -ETIMEDOUT;
>> +}
>> +
>> +/* Check for available slot and write to circular buffer.
>> + * It also update command valid offset (cin) register.
>> + */
>> +static __always_inline int mbox_fill_cmd_circular_buff(u32 header, u32 len,
>> +                                                    u32 *arg)
>> +{
>> +     static const struct socfpga_mailbox *mbox_base =
>> +                                     (void *)SOCFPGA_MAILBOX_ADDRESS;
>> +     u32 cin;
>> +     u32 cout;
>> +     u32 i;
>> +
>> +     cin = readl(&mbox_base->cin) % MBOX_CMD_BUFFER_SIZE;
>> +     cout = readl(&mbox_base->cout) % MBOX_CMD_BUFFER_SIZE;
>> +
>> +     /* if command buffer is full or not enough free space
>> +      * to fit the data
>> +      */
>> +     if (((cin + 1) % MBOX_CMD_BUFFER_SIZE) == cout ||
>> +         ((MBOX_CMD_BUFFER_SIZE - cin + cout - 1) %
>> +          MBOX_CMD_BUFFER_SIZE) < len)
>> +             return -ENOMEM;
>> +
>> +     /* write header to circular buffer */
>> +     writel(header, &mbox_base->cmd_buf[cin++]);
>> +     /* wrapping around when it reach the buffer size */
>> +     cin %= MBOX_CMD_BUFFER_SIZE;
>> +
>> +     /* write arguments */
>> +     for (i = 0; i < len; i++) {
>> +             writel(arg[i], &mbox_base->cmd_buf[cin++]);
>> +             /* wrapping around when it reach the buffer size */
>> +             cin %= MBOX_CMD_BUFFER_SIZE;
>> +     }
>> +
>> +     /* write command valid offset */
>> +     writel(cin, &mbox_base->cin);
>> +
>> +     return 0;
>> +}
>> +
>> +/* Check the command and fill it into circular buffer */
>> +static __always_inline int mbox_prepare_cmd_only(u8 id, u32 cmd,
>> +                                              u8 is_indirect, u32 len,
>> +                                              u32 *arg)
>> +{
>> +     u32 header;
>> +     int ret;
>> +
>> +     /* Total length is command + argument length */
>> +     if ((len + 1) > MBOX_CMD_BUFFER_SIZE)
>> +             return -EINVAL;
>> +
>> +     if (cmd > MBOX_MAX_CMD_INDEX)
>> +             return -EINVAL;
>> +
>> +     header = MBOX_CMD_HEADER(MBOX_CLIENT_ID_UBOOT, id, len,
>> +                              (is_indirect) ? 1 : 0, cmd);
>> +
>> +     ret = mbox_fill_cmd_circular_buff(header, len, arg);
>> +
>> +     return ret;
>> +}
>> +
>> +/* Send command only without waiting for responses from SDM */
>> +static __always_inline int __mbox_send_cmd_only(u8 id, u32 cmd,
>> +                                             u8 is_indirect, u32 len,
>> +                                             u32 *arg)
>> +{
>> +     int ret = mbox_prepare_cmd_only(id, cmd, is_indirect, len, arg);
>> +     /* write doorbell */
>> +     writel(1, MBOX_DOORBELL_TO_SDM_REG);
>> +
>> +     return ret;
>> +}
>> +
>> +/* Return number of responses received in buffer */
>> +static __always_inline int __mbox_rcv_resp(u32 *resp_buf, u32 resp_buf_max_len)
>
> __always_inline is nonsense, drop it. Let the compiler do it's thing.
This function used in SMC call as well, so it needs to be inline when
in secure section.

>
>> +{
>> +     static const struct socfpga_mailbox *mbox_base =
>> +                                     (void *)SOCFPGA_MAILBOX_ADDRESS;
>> +     u32 rin;
>> +     u32 rout;
>> +     u32 resp_len = 0;
>> +
>> +     /* clear doorbell from SDM if it was SET */
>> +     if (readl((const u32 *)MBOX_DOORBELL_FROM_SDM_REG) & 1)
>> +             writel(0, MBOX_DOORBELL_FROM_SDM_REG);
>> +
>> +     /* read current response offset */
>> +     rout = readl(&mbox_base->rout);
>> +     /* read response valid offset */
>> +     rin = readl(&mbox_base->rin);
>> +
>> +     while (rin != rout && (resp_len < resp_buf_max_len)) {
>> +             /* Response received */
>> +             if (resp_buf)
>> +                     resp_buf[resp_len++] =
>> +                             readl(&mbox_base->resp_buf[rout]);
>> +             rout++;
>> +             /* wrapping around when it reach the buffer size */
>> +             rout %= MBOX_RESP_BUFFER_SIZE;
>> +             /* update next ROUT */
>> +             writel(rout, &mbox_base->rout);
>> +     }
>> +
>> +     return resp_len;
>> +}
>> +
>> +/* Support one command and up to 31 words argument length only */
>> +static __always_inline int __mbox_send_cmd(u8 id, u32 cmd, u8 is_indirect,
>> +                                        u32 len, u32 *arg, u8 urgent,
>> +                                        u32 *resp_buf_len, u32 *resp_buf)
>> +{
>> +     static const struct socfpga_mailbox *mbox_base =
>> +                                     (void *)SOCFPGA_MAILBOX_ADDRESS;
>> +
>> +     u32 rin;
>> +     u32 resp;
>> +     u32 rout;
>> +     u32 status;
>> +     u32 resp_len;
>> +     u32 buf_len;
>> +     int ret;
>> +
>> +     ret = mbox_prepare_cmd_only(id, cmd, is_indirect, len, arg);
>> +     if (ret)
>> +             return ret;
>> +
>> +     if (urgent) {
>> +             /* Read status because it is toggled */
>> +             status = readl(&mbox_base->status) & MBOX_STATUS_UA_MSK;
>> +             /* Send command as urgent command */
>> +             writel(1, &mbox_base->urg);
>> +     }
>> +
>> +     /* write doorbell */
>> +     writel(1, MBOX_DOORBELL_TO_SDM_REG);
>> +
>> +     while (1) {
>> +             ret = ~0;
>> +
>> +             /* Wait for doorbell from SDM */
>> +             while (!readl(MBOX_DOORBELL_FROM_SDM_REG) && ret--)
>> +                     ;
>> +             if (!ret)
>> +                     return -ETIMEDOUT;
>
> wait_for_bit...
Same reason as above.
>
>> +             /* clear interrupt */
>> +             writel(0, MBOX_DOORBELL_FROM_SDM_REG);
>> +
>> +             if (urgent) {
>> +                     u32 new_status = readl(&mbox_base->status);
>> +                     /* urgent command doesn't have response */
>> +                     writel(0, &mbox_base->urg);
>> +                     /* Urgent ACK is toggled */
>> +                     if ((new_status & MBOX_STATUS_UA_MSK) ^ status)
>> +                             return 0;
>> +
>> +                     return -ECOMM;
>> +             }
>> +
>> +             /* read current response offset */
>> +             rout = readl(&mbox_base->rout);
>> +
>> +             /* read response valid offset */
>> +             rin = readl(&mbox_base->rin);
>> +
>> +             if (rout != rin) {
>> +                     /* Response received */
>> +                     resp = readl(&mbox_base->resp_buf[rout]);
>> +                     rout++;
>> +                     /* wrapping around when it reach the buffer size */
>> +                     rout %= MBOX_RESP_BUFFER_SIZE;
>> +                     /* update next ROUT */
>> +                     writel(rout, &mbox_base->rout);
>> +
>> +                     /* check client ID and ID */
>> +                     if ((MBOX_RESP_CLIENT_GET(resp) == MBOX_CLIENT_ID_UBOOT) &&
>> +                         (MBOX_RESP_ID_GET(resp) == id)) {
>> +                             ret = MBOX_RESP_ERR_GET(resp);
>> +                             if (ret)
>> +                                     return ret;
>> +
>> +                             if (resp_buf_len) {
>> +                                     buf_len = *resp_buf_len;
>> +                                     *resp_buf_len = 0;
>> +                             } else {
>> +                                     buf_len = 0;
>> +                             }
>> +
>> +                             resp_len = MBOX_RESP_LEN_GET(resp);
>> +                             while (resp_len) {
>> +                                     ret = mbox_polling_resp(rout);
>> +                                     if (ret)
>> +                                             return ret;
>> +                                     /* we need to process response buffer
>> +                                      * even caller doesn't need it
>> +                                      */
>> +                                     resp = readl(&mbox_base->resp_buf[rout]);
>> +                                     rout++;
>> +                                     resp_len--;
>> +                                     rout %= MBOX_RESP_BUFFER_SIZE;
>> +                                     writel(rout, &mbox_base->rout);
>> +                                     if (buf_len) {
>> +                                             /* copy response to buffer */
>> +                                             resp_buf[*resp_buf_len] = resp;
>> +                                             (*resp_buf_len)++;
>> +                                             buf_len--;
>> +                                     }
>> +                             }
>> +                             return ret;
>> +                     }
>> +             }
>> +     };
>> +
>> +     return -EIO;
>> +}
>> +
>> +int mbox_init(void)
>> +{
>> +     static const struct socfpga_mailbox *mbox_base =
>> +                                     (void *)SOCFPGA_MAILBOX_ADDRESS;
>> +     int ret;
>> +
>> +     /* enable mailbox interrupts */
>> +     writel(MBOX_ALL_INTRS, &mbox_base->flags);
>> +
>> +     /* Ensure urgent request is cleared */
>> +     writel(0, &mbox_base->urg);
>> +
>> +     /* Ensure the Doorbell Interrupt is cleared */
>> +     writel(0, MBOX_DOORBELL_FROM_SDM_REG);
>> +
>> +     ret = mbox_send_cmd(MBOX_ID_UBOOT, MBOX_RESTART, MBOX_CMD_DIRECT, 0,
>> +                         NULL, 1, 0, NULL);
>> +     if (ret)
>> +             return ret;
>> +
>> +     /* Renable mailbox interrupts after MBOX_RESTART */
>> +     writel(MBOX_ALL_INTRS, &mbox_base->flags);
>> +
>> +     return 0;
>> +}
>> +
>> +#ifdef CONFIG_CADENCE_QSPI
>> +int mbox_qspi_close(void)
>> +{
>> +     return mbox_send_cmd(MBOX_ID_UBOOT, MBOX_QSPI_CLOSE, MBOX_CMD_DIRECT,
>> +                          0, NULL, 0, 0, NULL);
>> +}
>> +
>> +int mbox_qspi_open(void)
>> +{
>> +     static const struct socfpga_system_manager *sysmgr_regs =
>> +             (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
>> +
>> +     int ret;
>> +     u32 resp_buf[1];
>> +     u32 resp_buf_len;
>> +
>> +     ret = mbox_send_cmd(MBOX_ID_UBOOT, MBOX_QSPI_OPEN, MBOX_CMD_DIRECT,
>> +                         0, NULL, 0, 0, NULL);
>> +     if (ret) {
>> +             /* retry again by closing and reopen the QSPI again */
>> +             ret = mbox_qspi_close();
>> +             if (ret)
>> +                     return ret;
>> +
>> +             ret = mbox_send_cmd(MBOX_ID_UBOOT, MBOX_QSPI_OPEN,
>> +                                 MBOX_CMD_DIRECT, 0, NULL, 0, 0, NULL);
>> +             if (ret)
>> +                     return ret;
>> +     }
>> +
>> +     /* HPS will directly control the QSPI controller, no longer mailbox */
>> +     resp_buf_len = 1;
>> +     ret = mbox_send_cmd(MBOX_ID_UBOOT, MBOX_QSPI_DIRECT, MBOX_CMD_DIRECT,
>> +                         0, NULL, 0, (u32 *)&resp_buf_len,
>> +                         (u32 *)&resp_buf);
>> +     if (ret)
>> +             goto error;
>> +
>> +     /* We are getting QSPI ref clock and set into sysmgr boot register */
>> +     printf("QSPI: Reference clock at %d Hz\n", resp_buf[0]);
>
> Certainly something I can get out of clock or clk command, drop the print.
In Stratix 10, QSPI IP is not in HPS, but in the SDM side. So, SW
needs send mailbox command to get QSPI clock.
Will change printf to debug().

>
>> +     writel(resp_buf[0], &sysmgr_regs->boot_scratch_cold0);
>> +
>> +     return 0;
>> +
>> +error:
>> +     mbox_qspi_close();
>> +
>> +     return ret;
>> +}
>> +#endif /* CONFIG_CADENCE_QSPI */
>> +
>> +int mbox_reset_cold(void)
>> +{
>> +     int ret;
>> +
>> +     ret = mbox_send_cmd(MBOX_ID_UBOOT, MBOX_REBOOT_HPS, MBOX_CMD_DIRECT,
>> +                         0, NULL, 0, 0, NULL);
>> +     if (ret) {
>> +             /* mailbox sent failure, wait for watchdog to kick in */
>> +             while (1)
>> +                     ;
>
> Is this supposed to be hang() ?
Okay, will change this.

>
>> +     }
>> +     return 0;
>> +}
>> +
>> +int mbox_send_cmd(u8 id, u32 cmd, u8 is_indirect, u32 len, u32 *arg,
>> +               u8 urgent, u32 *resp_buf_len, u32 *resp_buf)
>> +{
>> +     return __mbox_send_cmd(id, cmd, is_indirect, len, arg, urgent,
>> +                            resp_buf_len, resp_buf);
>> +}
>
> __anything is reserved for compiler, drop the leading underscores
Okay, will change to other name.

>>
>
>
> --
> Best regards,
> Marek Vasut

[U-Boot] [PATCH v1 08/16] arm: socfpga: stratix10: Add mailbox support for Stratix10 SoC

[Marek Vasut]

On 05/08/2018 08:49 AM, Ley Foon Tan wrote:
> On Thu, Apr 19, 2018 at 10:53 AM, Marek Vasut <marex@denx.de> wrote:
>> On 04/19/2018 11:50 AM, Ley Foon Tan wrote:
>>> Add mailbox support for Stratix SoC
>>>
>>> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
>>> Signed-off-by: Chin Liang See <chin.liang.see@intel.com>
>>> ---

[...]

>>> +static __always_inline int mbox_polling_resp(u32 rout)
>>> +{
>>> +     static const struct socfpga_mailbox *mbox_base =
>>> +                                     (void *)SOCFPGA_MAILBOX_ADDRESS;
>>> +     u32 rin;
>>> +     unsigned long i = ~0;
>>> +
>>> +     while (i) {
>>> +             rin = readl(&mbox_base->rin);
>>> +             if (rout != rin)
>>> +                     return 0;
>>
>> This looks like include/wait_bit.h reimplementation
> The reason we use this method instead of using wait_bit because this
> function will use in Secure Monitor Call (SMC) call as well.
> When run in secure section, timer is not available.  So, we can't use
> wait_for_bit.

Can't you just do timer_init() then ?

>>> +/* Send command only without waiting for responses from SDM */
>>> +static __always_inline int __mbox_send_cmd_only(u8 id, u32 cmd,
>>> +                                             u8 is_indirect, u32 len,
>>> +                                             u32 *arg)
>>> +{
>>> +     int ret = mbox_prepare_cmd_only(id, cmd, is_indirect, len, arg);
>>> +     /* write doorbell */
>>> +     writel(1, MBOX_DOORBELL_TO_SDM_REG);
>>> +
>>> +     return ret;
>>> +}
>>> +
>>> +/* Return number of responses received in buffer */
>>> +static __always_inline int __mbox_rcv_resp(u32 *resp_buf, u32 resp_buf_max_len)
>>
>> __always_inline is nonsense, drop it. Let the compiler do it's thing.
> This function used in SMC call as well, so it needs to be inline when
> in secure section.

Why ?

-- 
Best regards,
Marek Vasut

[U-Boot] [PATCH v1 14/16] ddr: altera: stratix10: Add DDR support for Stratix10 SoC

[Ley Foon Tan]

On Thu, Apr 19, 2018 at 11:02 AM, Marek Vasut <marex@denx.de> wrote:
> On 04/19/2018 11:50 AM, Ley Foon Tan wrote:
>> Add DDR support for Stratix SoC
>
> OT: How very different is the DDR controller on Stratix 10 and Arria 10?
The IP blocks are different, so can't combine both of them.
>
>> Signed-off-by: Chin Liang See <chin.liang.see@intel.com>
>> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
>> ---
>>  arch/arm/mach-socfpga/include/mach/sdram_s10.h |  340 ++++++++++++++++++++
>
> If this is used only be the driver, no point having it in mach/
>
>>  drivers/ddr/altera/Makefile                    |    1 +
>>  drivers/ddr/altera/sdram_s10.c                 |  392 ++++++++++++++++++++++++
>>  3 files changed, 733 insertions(+), 0 deletions(-)
>>  create mode 100644 arch/arm/mach-socfpga/include/mach/sdram_s10.h
>>  create mode 100644 drivers/ddr/altera/sdram_s10.c
> [...]
>
>> +
>> +union caltiming9_reg {
>> +     struct {
>> +             u32 cfg_4_act_to_act:8;
>> +             u32 reserved:24;
>> +     };
>> +     u32 word;
>> +};
>
> I wonder if this struct stuff is really a good idea.
This easier for driver to access each field in register.
>
>> +#define DDR_SCHED_DDRTIMING_ACTTOACT_OFFSET  0
>> +#define DDR_SCHED_DDRTIMING_RDTOMISS_OFFSET  6
>> +#define DDR_SCHED_DDRTIMING_WRTOMISS_OFFSET  12
>> +#define DDR_SCHED_DDRTIMING_BURSTLEN_OFFSET  18
>> +#define DDR_SCHED_DDRTIMING_RDTOWR_OFFSET    21
>> +#define DDR_SCHED_DDRTIMING_WRTORD_OFFSET    26
>> +#define DDR_SCHED_DDRTIMING_BWRATIO_OFFSET   31
>> +#define DDR_SCHED_DDRMOD_BWRATIOEXTENDED_OFFSET      1
>> +#define DDR_SCHED_ACTIVATE_RRD_OFFSET                0
>> +#define DDR_SCHED_ACTIVATE_FAW_OFFSET                4
>> +#define DDR_SCHED_ACTIVATE_FAWBANK_OFFSET    10
>> +#define DDR_SCHED_DEVTODEV_BUSRDTORD_OFFSET  0
>> +#define DDR_SCHED_DEVTODEV_BUSRDTOWR_OFFSET  2
>> +#define DDR_SCHED_DEVTODEV_BUSWRTORD_OFFSET  4
>> +#define DDR_HMC_DDRIOCTRL_IOSIZE_MSK         0x00000003
>> +#define DDR_HMC_DDRCALSTAT_CAL_MSK           0x00000001
>> +#define DDR_HMC_ECCCTL_AWB_CNT_RST_SET_MSK   0x00010000
>> +#define DDR_HMC_ECCCTL_CNT_RST_SET_MSK               0x00000100
>> +#define DDR_HMC_ECCCTL_ECC_EN_SET_MSK                0x00000001
>> +#define DDR_HMC_ECCCTL2_RMW_EN_SET_MSK               0x00000100
>> +#define DDR_HMC_ECCCTL2_AWB_EN_SET_MSK               0x00000001
>> +#define DDR_HMC_ECC_DIAGON_ECCDIAGON_EN_SET_MSK      0x00010000
>> +#define DDR_HMC_ECC_DIAGON_WRDIAGON_EN_SET_MSK       0x00000001
>> +#define DDR_HMC_ERRINTEN_SERRINTEN_EN_SET_MSK        0x00000001
>> +#define DDR_HMC_ERRINTEN_DERRINTEN_EN_SET_MSK        0x00000002
>> +#define DDR_HMC_INTSTAT_SERRPENA_SET_MSK     0x00000001
>> +#define DDR_HMC_INTSTAT_DERRPENA_SET_MSK     0x00000002
>> +#define DDR_HMC_INTSTAT_ADDRMTCFLG_SET_MSK   0x00010000
>> +#define DDR_HMC_INTMODE_INTMODE_SET_MSK              0x00000001
>> +#define DDR_HMC_RSTHANDSHAKE_MASK            0x000000ff
>> +#define DDR_HMC_CORE2SEQ_INT_REQ             0xF
>> +#define DDR_HMC_SEQ2CORE_INT_RESP_MASK               0x8
>> +#define DDR_HMC_HPSINTFCSEL_ENABLE_MASK              0x001f1f1f
>> +
>> +#define CCU_CPU0_MPRT_ADBASE_DDRREG_ADDR     0xf7004400
>> +#define CCU_CPU0_MPRT_ADBASE_MEMSPACE0_ADDR  0xf70045c0
>> +#define CCU_CPU0_MPRT_ADBASE_MEMSPACE1A_ADDR 0xf70045e0
>> +#define CCU_CPU0_MPRT_ADBASE_MEMSPACE1B_ADDR 0xf7004600
>> +#define CCU_CPU0_MPRT_ADBASE_MEMSPACE1C_ADDR 0xf7004620
>> +#define CCU_CPU0_MPRT_ADBASE_MEMSPACE1D_ADDR 0xf7004640
>> +#define CCU_CPU0_MPRT_ADBASE_MEMSPACE1E_ADDR 0xf7004660
>
> Can all this come from DT, maybe except for the offsets ?
Need to add a new node in DT if want get from DT. Or another way is
add CCU base address to base_addr_s10.h and remove all these defines
and use offset instead. Is it okay?

>
>> +#define CCU_IOM_MPRT_ADBASE_MEMSPACE0_ADDR   0xf7018560
>> +#define CCU_IOM_MPRT_ADBASE_MEMSPACE1A_ADDR  0xf7018580
>> +#define CCU_IOM_MPRT_ADBASE_MEMSPACE1B_ADDR  0xf70185a0
>> +#define CCU_IOM_MPRT_ADBASE_MEMSPACE1C_ADDR  0xf70185c0
>> +#define CCU_IOM_MPRT_ADBASE_MEMSPACE1D_ADDR  0xf70185e0
>> +#define CCU_IOM_MPRT_ADBASE_MEMSPACE1E_ADDR  0xf7018600
>> +
>> +#define CCU_ADBASE_DI_MASK                   0x00000010
>
> [...]
>
>> +#define DDR_CONFIG(A, B, C, R)       ((A << 24) | (B << 16) | (C << 8) | R)
>
> You need parenthesis around A, B, C, R in the macro.
Okay.
>
>> +/* The followring are the supported configurations */
>> +u32 ddr_config[] = {
>> +     /* DDR_CONFIG(Address order,Bank,Column,Row) */
>> +     /* List for DDR3 or LPDDR3 (pinout order > chip, row, bank, column) */
>> +     DDR_CONFIG(0, 3, 10, 12),
>> +     DDR_CONFIG(0, 3,  9, 13),
>> +     DDR_CONFIG(0, 3, 10, 13),
>> +     DDR_CONFIG(0, 3,  9, 14),
>> +     DDR_CONFIG(0, 3, 10, 14),
>> +     DDR_CONFIG(0, 3, 10, 15),
>> +     DDR_CONFIG(0, 3, 11, 14),
>> +     DDR_CONFIG(0, 3, 11, 15),
>> +     DDR_CONFIG(0, 3, 10, 16),
>> +     DDR_CONFIG(0, 3, 11, 16),
>> +     DDR_CONFIG(0, 3, 12, 15),       /* 0xa */
>> +     /* List for DDR4 only (pinout order > chip, bank, row, column) */
>> +     DDR_CONFIG(1, 3, 10, 14),
>> +     DDR_CONFIG(1, 4, 10, 14),
>> +     DDR_CONFIG(1, 3, 10, 15),
>> +     DDR_CONFIG(1, 4, 10, 15),
>> +     DDR_CONFIG(1, 3, 10, 16),
>> +     DDR_CONFIG(1, 4, 10, 16),
>> +     DDR_CONFIG(1, 3, 10, 17),
>> +     DDR_CONFIG(1, 4, 10, 17),
>> +};
>> +
>> +#define DDR_CONFIG_ELEMENTS  (sizeof(ddr_config) / sizeof(u32))
>
> Is that ARRAY_SIZE() ?
Yes, will change this.
>
>> +int match_ddr_conf(u32 ddr_conf)
>> +{
>> +     int i;
>> +
>> +     for (i = 0; i < DDR_CONFIG_ELEMENTS; i++) {
>> +             if (ddr_conf == ddr_config[i])
>> +                     return i;
>> +     }
>> +     return 0;
>> +}
>> +
>> +static int emif_clear(void)
>> +{
>> +     u32 s2c, i;
>> +
>> +     writel(0, &socfpga_ecc_hmc_base->rsthandshakectrl);
>> +     s2c = readl(&socfpga_ecc_hmc_base->rsthandshakestat) &
>> +           DDR_HMC_RSTHANDSHAKE_MASK;
>> +
>> +     for (i = 1000; (i > 0) && s2c; i--) {
>> +             WATCHDOG_RESET();
>> +             mdelay(1);
>> +             s2c = readl(&socfpga_ecc_hmc_base->rsthandshakestat) &
>> +                   DDR_HMC_RSTHANDSHAKE_MASK;
>
> wait_for_bit() ?
Okay.
>
>> +     }
>> +     return !s2c;
>> +}
>> +
>> +static int emif_reset(void)
>> +{
>> +     u32 c2s, s2c, i;
>> +
>> +     c2s = readl(&socfpga_ecc_hmc_base->rsthandshakectrl) &
>> +           DDR_HMC_RSTHANDSHAKE_MASK;
>> +     s2c = readl(&socfpga_ecc_hmc_base->rsthandshakestat) &
>> +           DDR_HMC_RSTHANDSHAKE_MASK;
>> +
>> +     debug("DDR: c2s=%08x s2c=%08x nr0=%08x nr1=%08x nr2=%08x dst=%08x\n",
>> +           c2s, s2c, readl(&socfpga_io48_mmr_base->niosreserve0),
>> +           readl(&socfpga_io48_mmr_base->niosreserve1),
>> +           readl(&socfpga_io48_mmr_base->niosreserve2),
>> +           readl(&socfpga_io48_mmr_base->dramsts));
>> +
>> +     if (s2c && emif_clear()) {
>> +             printf("DDR: emif_clear() failed\n");
>> +             return -1;
>> +     }
>> +
>> +     puts("DDR: Triggerring emif reset\n");
>> +     writel(DDR_HMC_CORE2SEQ_INT_REQ,
>> +            &socfpga_ecc_hmc_base->rsthandshakectrl);
>> +
>> +     for (i = 1000; i > 0; i--) {
>> +             /* if seq2core[3] = 0, we are good */
>> +             if (!(readl(&socfpga_ecc_hmc_base->rsthandshakestat) &
>> +                 DDR_HMC_SEQ2CORE_INT_RESP_MASK))
>> +                     break;
>> +             WATCHDOG_RESET();
>> +             mdelay(1);
>
> Another wait_for_bit() ?
Okay.
>
>> +     }
>> +
>> +     if (!i) {
>> +             printf("DDR: failed to get ack from EMIF\n");
>> +             return -2;
>> +     }
>> +
>> +     if (emif_clear()) {
>> +             printf("DDR: emif_clear() failed\n");
>> +             return -3;
>> +     }
>> +
>> +     printf("DDR: %s triggered successly\n", __func__);
>
> debug() ?
Okay.
>
>> +     return 0;
>> +}
> Comb through this and fix the things mentioned above globally.
>
> --
> Best regards,
> Marek Vasut

Regards
Ley Foon

[U-Boot] [PATCH v1 08/16] arm: socfpga: stratix10: Add mailbox support for Stratix10 SoC

[Ley Foon Tan]

On Tue, May 8, 2018 at 5:21 PM, Marek Vasut <marex@denx.de> wrote:
> On 05/08/2018 08:49 AM, Ley Foon Tan wrote:
>> On Thu, Apr 19, 2018 at 10:53 AM, Marek Vasut <marex@denx.de> wrote:
>>> On 04/19/2018 11:50 AM, Ley Foon Tan wrote:
>>>> Add mailbox support for Stratix SoC
>>>>
>>>> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
>>>> Signed-off-by: Chin Liang See <chin.liang.see@intel.com>
>>>> ---
>
> [...]
>
>>>> +static __always_inline int mbox_polling_resp(u32 rout)
>>>> +{
>>>> +     static const struct socfpga_mailbox *mbox_base =
>>>> +                                     (void *)SOCFPGA_MAILBOX_ADDRESS;
>>>> +     u32 rin;
>>>> +     unsigned long i = ~0;
>>>> +
>>>> +     while (i) {
>>>> +             rin = readl(&mbox_base->rin);
>>>> +             if (rout != rin)
>>>> +                     return 0;
>>>
>>> This looks like include/wait_bit.h reimplementation
>> The reason we use this method instead of using wait_bit because this
>> function will use in Secure Monitor Call (SMC) call as well.
>> When run in secure section, timer is not available.  So, we can't use
>> wait_for_bit.
>
> Can't you just do timer_init() then ?
We can't use timer in secure region. This SMC code is resident in
onchip memory (secure region) while Linux is running.
So, timer might be used by Linux.

>
>>>> +/* Send command only without waiting for responses from SDM */
>>>> +static __always_inline int __mbox_send_cmd_only(u8 id, u32 cmd,
>>>> +                                             u8 is_indirect, u32 len,
>>>> +                                             u32 *arg)
>>>> +{
>>>> +     int ret = mbox_prepare_cmd_only(id, cmd, is_indirect, len, arg);
>>>> +     /* write doorbell */
>>>> +     writel(1, MBOX_DOORBELL_TO_SDM_REG);
>>>> +
>>>> +     return ret;
>>>> +}
>>>> +
>>>> +/* Return number of responses received in buffer */
>>>> +static __always_inline int __mbox_rcv_resp(u32 *resp_buf, u32 resp_buf_max_len)
>>>
>>> __always_inline is nonsense, drop it. Let the compiler do it's thing.
>> This function used in SMC call as well, so it needs to be inline when
>> in secure section.
>
> Why ?
These functions needed for normal U-boot and SMC (secure section in
OCM) and we need to copy the whole function to secure section, not
just the API call.
This also avoid code duplication for U-boot and SMC.

Regards
Ley Foon

[U-Boot] [PATCH v1 08/16] arm: socfpga: stratix10: Add mailbox support for Stratix10 SoC

[Marek Vasut]

On 05/10/2018 10:45 AM, Ley Foon Tan wrote:
> On Tue, May 8, 2018 at 5:21 PM, Marek Vasut <marex@denx.de> wrote:
>> On 05/08/2018 08:49 AM, Ley Foon Tan wrote:
>>> On Thu, Apr 19, 2018 at 10:53 AM, Marek Vasut <marex@denx.de> wrote:
>>>> On 04/19/2018 11:50 AM, Ley Foon Tan wrote:
>>>>> Add mailbox support for Stratix SoC
>>>>>
>>>>> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
>>>>> Signed-off-by: Chin Liang See <chin.liang.see@intel.com>
>>>>> ---
>>
>> [...]
>>
>>>>> +static __always_inline int mbox_polling_resp(u32 rout)
>>>>> +{
>>>>> +     static const struct socfpga_mailbox *mbox_base =
>>>>> +                                     (void *)SOCFPGA_MAILBOX_ADDRESS;
>>>>> +     u32 rin;
>>>>> +     unsigned long i = ~0;
>>>>> +
>>>>> +     while (i) {
>>>>> +             rin = readl(&mbox_base->rin);
>>>>> +             if (rout != rin)
>>>>> +                     return 0;
>>>>
>>>> This looks like include/wait_bit.h reimplementation
>>> The reason we use this method instead of using wait_bit because this
>>> function will use in Secure Monitor Call (SMC) call as well.
>>> When run in secure section, timer is not available.  So, we can't use
>>> wait_for_bit.
>>
>> Can't you just do timer_init() then ?
> We can't use timer in secure region. This SMC code is resident in
> onchip memory (secure region) while Linux is running.
> So, timer might be used by Linux.

So pieces of U-Boot remain in memory and get called by Linux, right ?

I am CCing a few more people , since this might need further discussion.

btw does this work when Linux is compiled in AArch32 mode while U-Boot
is AArch64 ? I think it might not.

>>>>> +/* Send command only without waiting for responses from SDM */
>>>>> +static __always_inline int __mbox_send_cmd_only(u8 id, u32 cmd,
>>>>> +                                             u8 is_indirect, u32 len,
>>>>> +                                             u32 *arg)
>>>>> +{
>>>>> +     int ret = mbox_prepare_cmd_only(id, cmd, is_indirect, len, arg);
>>>>> +     /* write doorbell */
>>>>> +     writel(1, MBOX_DOORBELL_TO_SDM_REG);
>>>>> +
>>>>> +     return ret;
>>>>> +}
>>>>> +
>>>>> +/* Return number of responses received in buffer */
>>>>> +static __always_inline int __mbox_rcv_resp(u32 *resp_buf, u32 resp_buf_max_len)
>>>>
>>>> __always_inline is nonsense, drop it. Let the compiler do it's thing.
>>> This function used in SMC call as well, so it needs to be inline when
>>> in secure section.
>>
>> Why ?
> These functions needed for normal U-boot and SMC (secure section in
> OCM) and we need to copy the whole function to secure section, not
> just the API call.
> This also avoid code duplication for U-boot and SMC.

Thanks for the explanation!

-- 
Best regards,
Marek Vasut

[U-Boot] [PATCH v1 14/16] ddr: altera: stratix10: Add DDR support for Stratix10 SoC

[Marek Vasut]

On 05/10/2018 09:47 AM, Ley Foon Tan wrote:
> On Thu, Apr 19, 2018 at 11:02 AM, Marek Vasut <marex@denx.de> wrote:
>> On 04/19/2018 11:50 AM, Ley Foon Tan wrote:
>>> Add DDR support for Stratix SoC
>>
>> OT: How very different is the DDR controller on Stratix 10 and Arria 10?
> The IP blocks are different, so can't combine both of them.

I see, thanks

>>> Signed-off-by: Chin Liang See <chin.liang.see@intel.com>
>>> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
>>> ---
>>>  arch/arm/mach-socfpga/include/mach/sdram_s10.h |  340 ++++++++++++++++++++
>>
>> If this is used only be the driver, no point having it in mach/
>>
>>>  drivers/ddr/altera/Makefile                    |    1 +
>>>  drivers/ddr/altera/sdram_s10.c                 |  392 ++++++++++++++++++++++++
>>>  3 files changed, 733 insertions(+), 0 deletions(-)
>>>  create mode 100644 arch/arm/mach-socfpga/include/mach/sdram_s10.h
>>>  create mode 100644 drivers/ddr/altera/sdram_s10.c
>> [...]
>>
>>> +
>>> +union caltiming9_reg {
>>> +     struct {
>>> +             u32 cfg_4_act_to_act:8;
>>> +             u32 reserved:24;
>>> +     };
>>> +     u32 word;
>>> +};
>>
>> I wonder if this struct stuff is really a good idea.
> This easier for driver to access each field in register.

And also not super portable. I'd rather see a macro really.
Something like define foo (((x) >> 24) & 0xff)

>>> +#define DDR_SCHED_DDRTIMING_ACTTOACT_OFFSET  0
>>> +#define DDR_SCHED_DDRTIMING_RDTOMISS_OFFSET  6
>>> +#define DDR_SCHED_DDRTIMING_WRTOMISS_OFFSET  12
>>> +#define DDR_SCHED_DDRTIMING_BURSTLEN_OFFSET  18
>>> +#define DDR_SCHED_DDRTIMING_RDTOWR_OFFSET    21
>>> +#define DDR_SCHED_DDRTIMING_WRTORD_OFFSET    26
>>> +#define DDR_SCHED_DDRTIMING_BWRATIO_OFFSET   31
>>> +#define DDR_SCHED_DDRMOD_BWRATIOEXTENDED_OFFSET      1
>>> +#define DDR_SCHED_ACTIVATE_RRD_OFFSET                0
>>> +#define DDR_SCHED_ACTIVATE_FAW_OFFSET                4
>>> +#define DDR_SCHED_ACTIVATE_FAWBANK_OFFSET    10
>>> +#define DDR_SCHED_DEVTODEV_BUSRDTORD_OFFSET  0
>>> +#define DDR_SCHED_DEVTODEV_BUSRDTOWR_OFFSET  2
>>> +#define DDR_SCHED_DEVTODEV_BUSWRTORD_OFFSET  4
>>> +#define DDR_HMC_DDRIOCTRL_IOSIZE_MSK         0x00000003
>>> +#define DDR_HMC_DDRCALSTAT_CAL_MSK           0x00000001
>>> +#define DDR_HMC_ECCCTL_AWB_CNT_RST_SET_MSK   0x00010000
>>> +#define DDR_HMC_ECCCTL_CNT_RST_SET_MSK               0x00000100
>>> +#define DDR_HMC_ECCCTL_ECC_EN_SET_MSK                0x00000001
>>> +#define DDR_HMC_ECCCTL2_RMW_EN_SET_MSK               0x00000100
>>> +#define DDR_HMC_ECCCTL2_AWB_EN_SET_MSK               0x00000001
>>> +#define DDR_HMC_ECC_DIAGON_ECCDIAGON_EN_SET_MSK      0x00010000
>>> +#define DDR_HMC_ECC_DIAGON_WRDIAGON_EN_SET_MSK       0x00000001
>>> +#define DDR_HMC_ERRINTEN_SERRINTEN_EN_SET_MSK        0x00000001
>>> +#define DDR_HMC_ERRINTEN_DERRINTEN_EN_SET_MSK        0x00000002
>>> +#define DDR_HMC_INTSTAT_SERRPENA_SET_MSK     0x00000001
>>> +#define DDR_HMC_INTSTAT_DERRPENA_SET_MSK     0x00000002
>>> +#define DDR_HMC_INTSTAT_ADDRMTCFLG_SET_MSK   0x00010000
>>> +#define DDR_HMC_INTMODE_INTMODE_SET_MSK              0x00000001
>>> +#define DDR_HMC_RSTHANDSHAKE_MASK            0x000000ff
>>> +#define DDR_HMC_CORE2SEQ_INT_REQ             0xF
>>> +#define DDR_HMC_SEQ2CORE_INT_RESP_MASK               0x8
>>> +#define DDR_HMC_HPSINTFCSEL_ENABLE_MASK              0x001f1f1f
>>> +
>>> +#define CCU_CPU0_MPRT_ADBASE_DDRREG_ADDR     0xf7004400
>>> +#define CCU_CPU0_MPRT_ADBASE_MEMSPACE0_ADDR  0xf70045c0
>>> +#define CCU_CPU0_MPRT_ADBASE_MEMSPACE1A_ADDR 0xf70045e0
>>> +#define CCU_CPU0_MPRT_ADBASE_MEMSPACE1B_ADDR 0xf7004600
>>> +#define CCU_CPU0_MPRT_ADBASE_MEMSPACE1C_ADDR 0xf7004620
>>> +#define CCU_CPU0_MPRT_ADBASE_MEMSPACE1D_ADDR 0xf7004640
>>> +#define CCU_CPU0_MPRT_ADBASE_MEMSPACE1E_ADDR 0xf7004660
>>
>> Can all this come from DT, maybe except for the offsets ?
> Need to add a new node in DT if want get from DT. Or another way is
> add CCU base address to base_addr_s10.h and remove all these defines
> and use offset instead. Is it okay?

I'd prefer to have everything in DT obviously, but I guess using CCU
base + offset is a good start for now. It could be easily converted to
DT when the bindings are ready later.

>>> +#define CCU_IOM_MPRT_ADBASE_MEMSPACE0_ADDR   0xf7018560
>>> +#define CCU_IOM_MPRT_ADBASE_MEMSPACE1A_ADDR  0xf7018580
>>> +#define CCU_IOM_MPRT_ADBASE_MEMSPACE1B_ADDR  0xf70185a0
>>> +#define CCU_IOM_MPRT_ADBASE_MEMSPACE1C_ADDR  0xf70185c0
>>> +#define CCU_IOM_MPRT_ADBASE_MEMSPACE1D_ADDR  0xf70185e0
>>> +#define CCU_IOM_MPRT_ADBASE_MEMSPACE1E_ADDR  0xf7018600
>>> +
>>> +#define CCU_ADBASE_DI_MASK                   0x00000010
>>

[...]

-- 
Best regards,
Marek Vasut

[U-Boot] [PATCH v1 14/16] ddr: altera: stratix10: Add DDR support for Stratix10 SoC

[Ley Foon Tan]

On Thu, May 10, 2018 at 6:12 PM, Marek Vasut <marex@denx.de> wrote:
> On 05/10/2018 09:47 AM, Ley Foon Tan wrote:
>> On Thu, Apr 19, 2018 at 11:02 AM, Marek Vasut <marex@denx.de> wrote:
>>> On 04/19/2018 11:50 AM, Ley Foon Tan wrote:
>>>> Add DDR support for Stratix SoC
>>>
>>> OT: How very different is the DDR controller on Stratix 10 and Arria 10?
>> The IP blocks are different, so can't combine both of them.
>
> I see, thanks
>
>>>> Signed-off-by: Chin Liang See <chin.liang.see@intel.com>
>>>> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
>>>> ---
>>>>  arch/arm/mach-socfpga/include/mach/sdram_s10.h |  340 ++++++++++++++++++++
>>>
>>> If this is used only be the driver, no point having it in mach/
>>>
>>>>  drivers/ddr/altera/Makefile                    |    1 +
>>>>  drivers/ddr/altera/sdram_s10.c                 |  392 ++++++++++++++++++++++++
>>>>  3 files changed, 733 insertions(+), 0 deletions(-)
>>>>  create mode 100644 arch/arm/mach-socfpga/include/mach/sdram_s10.h
>>>>  create mode 100644 drivers/ddr/altera/sdram_s10.c
>>> [...]
>>>
>>>> +
>>>> +union caltiming9_reg {
>>>> +     struct {
>>>> +             u32 cfg_4_act_to_act:8;
>>>> +             u32 reserved:24;
>>>> +     };
>>>> +     u32 word;
>>>> +};
>>>
>>> I wonder if this struct stuff is really a good idea.
>> This easier for driver to access each field in register.
>
> And also not super portable. I'd rather see a macro really.
> Something like define foo (((x) >> 24) & 0xff)
Okay, I will to update these.
>
>>>> +#define DDR_SCHED_DDRTIMING_ACTTOACT_OFFSET  0
>>>> +#define DDR_SCHED_DDRTIMING_RDTOMISS_OFFSET  6
>>>> +#define DDR_SCHED_DDRTIMING_WRTOMISS_OFFSET  12
>>>> +#define DDR_SCHED_DDRTIMING_BURSTLEN_OFFSET  18
>>>> +#define DDR_SCHED_DDRTIMING_RDTOWR_OFFSET    21
>>>> +#define DDR_SCHED_DDRTIMING_WRTORD_OFFSET    26
>>>> +#define DDR_SCHED_DDRTIMING_BWRATIO_OFFSET   31
>>>> +#define DDR_SCHED_DDRMOD_BWRATIOEXTENDED_OFFSET      1
>>>> +#define DDR_SCHED_ACTIVATE_RRD_OFFSET                0
>>>> +#define DDR_SCHED_ACTIVATE_FAW_OFFSET                4
>>>> +#define DDR_SCHED_ACTIVATE_FAWBANK_OFFSET    10
>>>> +#define DDR_SCHED_DEVTODEV_BUSRDTORD_OFFSET  0
>>>> +#define DDR_SCHED_DEVTODEV_BUSRDTOWR_OFFSET  2
>>>> +#define DDR_SCHED_DEVTODEV_BUSWRTORD_OFFSET  4
>>>> +#define DDR_HMC_DDRIOCTRL_IOSIZE_MSK         0x00000003
>>>> +#define DDR_HMC_DDRCALSTAT_CAL_MSK           0x00000001
>>>> +#define DDR_HMC_ECCCTL_AWB_CNT_RST_SET_MSK   0x00010000
>>>> +#define DDR_HMC_ECCCTL_CNT_RST_SET_MSK               0x00000100
>>>> +#define DDR_HMC_ECCCTL_ECC_EN_SET_MSK                0x00000001
>>>> +#define DDR_HMC_ECCCTL2_RMW_EN_SET_MSK               0x00000100
>>>> +#define DDR_HMC_ECCCTL2_AWB_EN_SET_MSK               0x00000001
>>>> +#define DDR_HMC_ECC_DIAGON_ECCDIAGON_EN_SET_MSK      0x00010000
>>>> +#define DDR_HMC_ECC_DIAGON_WRDIAGON_EN_SET_MSK       0x00000001
>>>> +#define DDR_HMC_ERRINTEN_SERRINTEN_EN_SET_MSK        0x00000001
>>>> +#define DDR_HMC_ERRINTEN_DERRINTEN_EN_SET_MSK        0x00000002
>>>> +#define DDR_HMC_INTSTAT_SERRPENA_SET_MSK     0x00000001
>>>> +#define DDR_HMC_INTSTAT_DERRPENA_SET_MSK     0x00000002
>>>> +#define DDR_HMC_INTSTAT_ADDRMTCFLG_SET_MSK   0x00010000
>>>> +#define DDR_HMC_INTMODE_INTMODE_SET_MSK              0x00000001
>>>> +#define DDR_HMC_RSTHANDSHAKE_MASK            0x000000ff
>>>> +#define DDR_HMC_CORE2SEQ_INT_REQ             0xF
>>>> +#define DDR_HMC_SEQ2CORE_INT_RESP_MASK               0x8
>>>> +#define DDR_HMC_HPSINTFCSEL_ENABLE_MASK              0x001f1f1f
>>>> +
>>>> +#define CCU_CPU0_MPRT_ADBASE_DDRREG_ADDR     0xf7004400
>>>> +#define CCU_CPU0_MPRT_ADBASE_MEMSPACE0_ADDR  0xf70045c0
>>>> +#define CCU_CPU0_MPRT_ADBASE_MEMSPACE1A_ADDR 0xf70045e0
>>>> +#define CCU_CPU0_MPRT_ADBASE_MEMSPACE1B_ADDR 0xf7004600
>>>> +#define CCU_CPU0_MPRT_ADBASE_MEMSPACE1C_ADDR 0xf7004620
>>>> +#define CCU_CPU0_MPRT_ADBASE_MEMSPACE1D_ADDR 0xf7004640
>>>> +#define CCU_CPU0_MPRT_ADBASE_MEMSPACE1E_ADDR 0xf7004660
>>>
>>> Can all this come from DT, maybe except for the offsets ?
>> Need to add a new node in DT if want get from DT. Or another way is
>> add CCU base address to base_addr_s10.h and remove all these defines
>> and use offset instead. Is it okay?
>
> I'd prefer to have everything in DT obviously, but I guess using CCU
> base + offset is a good start for now. It could be easily converted to
> DT when the bindings are ready later.
Yes, will use base+offset as for now.

>
>>>> +#define CCU_IOM_MPRT_ADBASE_MEMSPACE0_ADDR   0xf7018560
>>>> +#define CCU_IOM_MPRT_ADBASE_MEMSPACE1A_ADDR  0xf7018580
>>>> +#define CCU_IOM_MPRT_ADBASE_MEMSPACE1B_ADDR  0xf70185a0
>>>> +#define CCU_IOM_MPRT_ADBASE_MEMSPACE1C_ADDR  0xf70185c0
>>>> +#define CCU_IOM_MPRT_ADBASE_MEMSPACE1D_ADDR  0xf70185e0
>>>> +#define CCU_IOM_MPRT_ADBASE_MEMSPACE1E_ADDR  0xf7018600
>>>> +
>>>> +#define CCU_ADBASE_DI_MASK                   0x00000010
>>>
>

Regards
Ley Foon

[U-Boot] [PATCH v1 08/16] arm: socfpga: stratix10: Add mailbox support for Stratix10 SoC

[Ley Foon Tan]

On Thu, May 10, 2018 at 6:09 PM, Marek Vasut <marex@denx.de> wrote:
> On 05/10/2018 10:45 AM, Ley Foon Tan wrote:
>> On Tue, May 8, 2018 at 5:21 PM, Marek Vasut <marex@denx.de> wrote:
>>> On 05/08/2018 08:49 AM, Ley Foon Tan wrote:
>>>> On Thu, Apr 19, 2018 at 10:53 AM, Marek Vasut <marex@denx.de> wrote:
>>>>> On 04/19/2018 11:50 AM, Ley Foon Tan wrote:
>>>>>> Add mailbox support for Stratix SoC
>>>>>>
>>>>>> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
>>>>>> Signed-off-by: Chin Liang See <chin.liang.see@intel.com>
>>>>>> ---
>>>
>>> [...]
>>>
>>>>>> +static __always_inline int mbox_polling_resp(u32 rout)
>>>>>> +{
>>>>>> +     static const struct socfpga_mailbox *mbox_base =
>>>>>> +                                     (void *)SOCFPGA_MAILBOX_ADDRESS;
>>>>>> +     u32 rin;
>>>>>> +     unsigned long i = ~0;
>>>>>> +
>>>>>> +     while (i) {
>>>>>> +             rin = readl(&mbox_base->rin);
>>>>>> +             if (rout != rin)
>>>>>> +                     return 0;
>>>>>
>>>>> This looks like include/wait_bit.h reimplementation
>>>> The reason we use this method instead of using wait_bit because this
>>>> function will use in Secure Monitor Call (SMC) call as well.
>>>> When run in secure section, timer is not available.  So, we can't use
>>>> wait_for_bit.
>>>
>>> Can't you just do timer_init() then ?
>> We can't use timer in secure region. This SMC code is resident in
>> onchip memory (secure region) while Linux is running.
>> So, timer might be used by Linux.
>
> So pieces of U-Boot remain in memory and get called by Linux, right ?
Normal U-boot (in DDR) is destroyed after Linux is running, only SMC
code Onchip memory will remain.
The existing U-boot have support this SMC feature, platform just need
to configure the CONFIG_ARMV8_SECURE_BASE for the secure section.
Of course, we need to enable CONFIG_ARMV8_PSCI too.

>
> I am CCing a few more people , since this might need further discussion.
>
> btw does this work when Linux is compiled in AArch32 mode while U-Boot
> is AArch64 ? I think it might not.
It should work. PSCI handle checks ESR_EL3.EC field to know whether it
is SMC32 or SMC64.
See code in handle_sync near line 230 in
http://git.denx.de/?p=u-boot.git;a=blob;f=arch/arm/cpu/armv8/psci.S

>
>>>>>> +/* Send command only without waiting for responses from SDM */
>>>>>> +static __always_inline int __mbox_send_cmd_only(u8 id, u32 cmd,
>>>>>> +                                             u8 is_indirect, u32 len,
>>>>>> +                                             u32 *arg)
>>>>>> +{
>>>>>> +     int ret = mbox_prepare_cmd_only(id, cmd, is_indirect, len, arg);
>>>>>> +     /* write doorbell */
>>>>>> +     writel(1, MBOX_DOORBELL_TO_SDM_REG);
>>>>>> +
>>>>>> +     return ret;
>>>>>> +}
>>>>>> +
>>>>>> +/* Return number of responses received in buffer */
>>>>>> +static __always_inline int __mbox_rcv_resp(u32 *resp_buf, u32 resp_buf_max_len)
>>>>>
>>>>> __always_inline is nonsense, drop it. Let the compiler do it's thing.
>>>> This function used in SMC call as well, so it needs to be inline when
>>>> in secure section.
>>>
>>> Why ?
>> These functions needed for normal U-boot and SMC (secure section in
>> OCM) and we need to copy the whole function to secure section, not
>> just the API call.
>> This also avoid code duplication for U-boot and SMC.
>
> Thanks for the explanation!
>
> --

Regards
Ley Foon

[U-Boot] [PATCH v1 08/16] arm: socfpga: stratix10: Add mailbox support for Stratix10 SoC

[Marek Vasut]

On 05/11/2018 07:45 AM, Ley Foon Tan wrote:
> On Thu, May 10, 2018 at 6:09 PM, Marek Vasut <marex@denx.de> wrote:
>> On 05/10/2018 10:45 AM, Ley Foon Tan wrote:
>>> On Tue, May 8, 2018 at 5:21 PM, Marek Vasut <marex@denx.de> wrote:
>>>> On 05/08/2018 08:49 AM, Ley Foon Tan wrote:
>>>>> On Thu, Apr 19, 2018 at 10:53 AM, Marek Vasut <marex@denx.de> wrote:
>>>>>> On 04/19/2018 11:50 AM, Ley Foon Tan wrote:
>>>>>>> Add mailbox support for Stratix SoC
>>>>>>>
>>>>>>> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
>>>>>>> Signed-off-by: Chin Liang See <chin.liang.see@intel.com>
>>>>>>> ---
>>>>
>>>> [...]
>>>>
>>>>>>> +static __always_inline int mbox_polling_resp(u32 rout)
>>>>>>> +{
>>>>>>> +     static const struct socfpga_mailbox *mbox_base =
>>>>>>> +                                     (void *)SOCFPGA_MAILBOX_ADDRESS;
>>>>>>> +     u32 rin;
>>>>>>> +     unsigned long i = ~0;
>>>>>>> +
>>>>>>> +     while (i) {
>>>>>>> +             rin = readl(&mbox_base->rin);
>>>>>>> +             if (rout != rin)
>>>>>>> +                     return 0;
>>>>>>
>>>>>> This looks like include/wait_bit.h reimplementation
>>>>> The reason we use this method instead of using wait_bit because this
>>>>> function will use in Secure Monitor Call (SMC) call as well.
>>>>> When run in secure section, timer is not available.  So, we can't use
>>>>> wait_for_bit.
>>>>
>>>> Can't you just do timer_init() then ?
>>> We can't use timer in secure region. This SMC code is resident in
>>> onchip memory (secure region) while Linux is running.
>>> So, timer might be used by Linux.
>>
>> So pieces of U-Boot remain in memory and get called by Linux, right ?
> Normal U-boot (in DDR) is destroyed after Linux is running, only SMC
> code Onchip memory will remain.
> The existing U-boot have support this SMC feature, platform just need
> to configure the CONFIG_ARMV8_SECURE_BASE for the secure section.
> Of course, we need to enable CONFIG_ARMV8_PSCI too.

So piece of U-Boot then becomes the part which handles PSCI calls from
Linux, do I understand it correctly ?

>> I am CCing a few more people , since this might need further discussion.
>>
>> btw does this work when Linux is compiled in AArch32 mode while U-Boot
>> is AArch64 ? I think it might not.
> It should work. PSCI handle checks ESR_EL3.EC field to know whether it
> is SMC32 or SMC64.
> See code in handle_sync near line 230 in
> http://git.denx.de/?p=u-boot.git;a=blob;f=arch/arm/cpu/armv8/psci.S
Will do, thanks!

-- 
Best regards,
Marek Vasut

[U-Boot] [PATCH v1 08/16] arm: socfpga: stratix10: Add mailbox support for Stratix10 SoC

[Ley Foon Tan]

On Fri, May 11, 2018 at 4:44 PM, Marek Vasut <marex@denx.de> wrote:
> On 05/11/2018 07:45 AM, Ley Foon Tan wrote:
>> On Thu, May 10, 2018 at 6:09 PM, Marek Vasut <marex@denx.de> wrote:
>>> On 05/10/2018 10:45 AM, Ley Foon Tan wrote:
>>>> On Tue, May 8, 2018 at 5:21 PM, Marek Vasut <marex@denx.de> wrote:
>>>>> On 05/08/2018 08:49 AM, Ley Foon Tan wrote:
>>>>>> On Thu, Apr 19, 2018 at 10:53 AM, Marek Vasut <marex@denx.de> wrote:
>>>>>>> On 04/19/2018 11:50 AM, Ley Foon Tan wrote:
>>>>>>>> Add mailbox support for Stratix SoC
>>>>>>>>
>>>>>>>> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
>>>>>>>> Signed-off-by: Chin Liang See <chin.liang.see@intel.com>
>>>>>>>> ---
>>>>>
>>>>> [...]
>>>>>
>>>>>>>> +static __always_inline int mbox_polling_resp(u32 rout)
>>>>>>>> +{
>>>>>>>> +     static const struct socfpga_mailbox *mbox_base =
>>>>>>>> +                                     (void *)SOCFPGA_MAILBOX_ADDRESS;
>>>>>>>> +     u32 rin;
>>>>>>>> +     unsigned long i = ~0;
>>>>>>>> +
>>>>>>>> +     while (i) {
>>>>>>>> +             rin = readl(&mbox_base->rin);
>>>>>>>> +             if (rout != rin)
>>>>>>>> +                     return 0;
>>>>>>>
>>>>>>> This looks like include/wait_bit.h reimplementation
>>>>>> The reason we use this method instead of using wait_bit because this
>>>>>> function will use in Secure Monitor Call (SMC) call as well.
>>>>>> When run in secure section, timer is not available.  So, we can't use
>>>>>> wait_for_bit.
>>>>>
>>>>> Can't you just do timer_init() then ?
>>>> We can't use timer in secure region. This SMC code is resident in
>>>> onchip memory (secure region) while Linux is running.
>>>> So, timer might be used by Linux.
>>>
>>> So pieces of U-Boot remain in memory and get called by Linux, right ?
>> Normal U-boot (in DDR) is destroyed after Linux is running, only SMC
>> code Onchip memory will remain.
>> The existing U-boot have support this SMC feature, platform just need
>> to configure the CONFIG_ARMV8_SECURE_BASE for the secure section.
>> Of course, we need to enable CONFIG_ARMV8_PSCI too.
>
> So piece of U-Boot then becomes the part which handles PSCI calls from
> Linux, do I understand it correctly ?
Yes, and we put this piece of code in onchip memory in our platform so
it doesn't corrupted by Linux.

You can see detail in
http://git.denx.de/?p=u-boot.git;a=blob;f=arch/arm/cpu/armv8/u-boot.lds
All code related to PSCI/SMC will put in secure section.

>
>>> I am CCing a few more people , since this might need further discussion.
>>>
>>> btw does this work when Linux is compiled in AArch32 mode while U-Boot
>>> is AArch64 ? I think it might not.
>> It should work. PSCI handle checks ESR_EL3.EC field to know whether it
>> is SMC32 or SMC64.
>> See code in handle_sync near line 230 in
>> http://git.denx.de/?p=u-boot.git;a=blob;f=arch/arm/cpu/armv8/psci.S
> Will do, thanks!
>
> --

Regards
Ley Foon

[U-Boot] [PATCH v1 08/16] arm: socfpga: stratix10: Add mailbox support for Stratix10 SoC

[Marek Vasut]

On 05/11/2018 11:25 AM, Ley Foon Tan wrote:
> On Fri, May 11, 2018 at 4:44 PM, Marek Vasut <marex@denx.de> wrote:
>> On 05/11/2018 07:45 AM, Ley Foon Tan wrote:
>>> On Thu, May 10, 2018 at 6:09 PM, Marek Vasut <marex@denx.de> wrote:
>>>> On 05/10/2018 10:45 AM, Ley Foon Tan wrote:
>>>>> On Tue, May 8, 2018 at 5:21 PM, Marek Vasut <marex@denx.de> wrote:
>>>>>> On 05/08/2018 08:49 AM, Ley Foon Tan wrote:
>>>>>>> On Thu, Apr 19, 2018 at 10:53 AM, Marek Vasut <marex@denx.de> wrote:
>>>>>>>> On 04/19/2018 11:50 AM, Ley Foon Tan wrote:
>>>>>>>>> Add mailbox support for Stratix SoC
>>>>>>>>>
>>>>>>>>> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
>>>>>>>>> Signed-off-by: Chin Liang See <chin.liang.see@intel.com>
>>>>>>>>> ---
>>>>>>
>>>>>> [...]
>>>>>>
>>>>>>>>> +static __always_inline int mbox_polling_resp(u32 rout)
>>>>>>>>> +{
>>>>>>>>> +     static const struct socfpga_mailbox *mbox_base =
>>>>>>>>> +                                     (void *)SOCFPGA_MAILBOX_ADDRESS;
>>>>>>>>> +     u32 rin;
>>>>>>>>> +     unsigned long i = ~0;
>>>>>>>>> +
>>>>>>>>> +     while (i) {
>>>>>>>>> +             rin = readl(&mbox_base->rin);
>>>>>>>>> +             if (rout != rin)
>>>>>>>>> +                     return 0;
>>>>>>>>
>>>>>>>> This looks like include/wait_bit.h reimplementation
>>>>>>> The reason we use this method instead of using wait_bit because this
>>>>>>> function will use in Secure Monitor Call (SMC) call as well.
>>>>>>> When run in secure section, timer is not available.  So, we can't use
>>>>>>> wait_for_bit.
>>>>>>
>>>>>> Can't you just do timer_init() then ?
>>>>> We can't use timer in secure region. This SMC code is resident in
>>>>> onchip memory (secure region) while Linux is running.
>>>>> So, timer might be used by Linux.
>>>>
>>>> So pieces of U-Boot remain in memory and get called by Linux, right ?
>>> Normal U-boot (in DDR) is destroyed after Linux is running, only SMC
>>> code Onchip memory will remain.
>>> The existing U-boot have support this SMC feature, platform just need
>>> to configure the CONFIG_ARMV8_SECURE_BASE for the secure section.
>>> Of course, we need to enable CONFIG_ARMV8_PSCI too.
>>
>> So piece of U-Boot then becomes the part which handles PSCI calls from
>> Linux, do I understand it correctly ?
> Yes, and we put this piece of code in onchip memory in our platform so
> it doesn't corrupted by Linux.
> 
> You can see detail in
> http://git.denx.de/?p=u-boot.git;a=blob;f=arch/arm/cpu/armv8/u-boot.lds
> All code related to PSCI/SMC will put in secure section.

I see, nice, I didnt know about that. Thanks

-- 
Best regards,
Marek Vasut