[PATCH 0/9] ARM: mstar: Add basic support for i2m and SMP

[PATCH 0/9] ARM: mstar: Add basic support for i2m and SMP

[Daniel Palmer]

This series adds basic support for the infinity2m series
of chips. For now the SigmaStar SSD202D which is a dual
Cortex A7 in a QFN128 package.

These chips share most of the same hardware with the
currently supported infinity, infinity3 and mercury5
chips.

Daniel Palmer (9):
  dt-bindings: mstar: Add binding details for mstar,smpctrl
  dt-bindings: vendor-prefixes: Add honestar vendor prefix
  dt-bindings: mstar: Add Honestar SSD201_HT_V2 to mstar boards
  ARM: mstar: Add infinity2m support
  ARM: mstar: Add common dtsi for SSD201/SSD202D
  ARM: mstar: Add chip level dtsi for SSD202D
  ARM: mstar: Add dts for Honestar ssd201htv2
  ARM: mstar: Add smp ctrl registers to infinity2m dtsi
  ARM: mstar: SMP support

 .../bindings/arm/mstar/mstar,smpctrl.yaml     | 38 ++++++++++++++
 .../devicetree/bindings/arm/mstar/mstar.yaml  |  6 +++
 .../devicetree/bindings/vendor-prefixes.yaml  |  2 +
 arch/arm/boot/dts/Makefile                    |  1 +
 .../mstar-infinity2m-ssd202d-ssd201htv2.dts   | 25 +++++++++
 .../boot/dts/mstar-infinity2m-ssd202d.dtsi    | 14 +++++
 .../boot/dts/mstar-infinity2m-ssd20xd.dtsi    |  7 +++
 arch/arm/boot/dts/mstar-infinity2m.dtsi       | 23 +++++++++
 arch/arm/boot/dts/mstar-v7.dtsi               |  2 +-
 arch/arm/mach-mstar/mstarv7.c                 | 51 +++++++++++++++++++
 10 files changed, 168 insertions(+), 1 deletion(-)
 create mode 100644 Documentation/devicetree/bindings/arm/mstar/mstar,smpctrl.yaml
 create mode 100644 arch/arm/boot/dts/mstar-infinity2m-ssd202d-ssd201htv2.dts
 create mode 100644 arch/arm/boot/dts/mstar-infinity2m-ssd202d.dtsi
 create mode 100644 arch/arm/boot/dts/mstar-infinity2m-ssd20xd.dtsi
 create mode 100644 arch/arm/boot/dts/mstar-infinity2m.dtsi

-- 
2.29.2

[PATCH 0/9] ARM: mstar: Add basic support for i2m and SMP

[Daniel Palmer]

This series adds basic support for the infinity2m series
of chips. For now the SigmaStar SSD202D which is a dual
Cortex A7 in a QFN128 package.

These chips share most of the same hardware with the
currently supported infinity, infinity3 and mercury5
chips.

Daniel Palmer (9):
  dt-bindings: mstar: Add binding details for mstar,smpctrl
  dt-bindings: vendor-prefixes: Add honestar vendor prefix
  dt-bindings: mstar: Add Honestar SSD201_HT_V2 to mstar boards
  ARM: mstar: Add infinity2m support
  ARM: mstar: Add common dtsi for SSD201/SSD202D
  ARM: mstar: Add chip level dtsi for SSD202D
  ARM: mstar: Add dts for Honestar ssd201htv2
  ARM: mstar: Add smp ctrl registers to infinity2m dtsi
  ARM: mstar: SMP support

 .../bindings/arm/mstar/mstar,smpctrl.yaml     | 38 ++++++++++++++
 .../devicetree/bindings/arm/mstar/mstar.yaml  |  6 +++
 .../devicetree/bindings/vendor-prefixes.yaml  |  2 +
 arch/arm/boot/dts/Makefile                    |  1 +
 .../mstar-infinity2m-ssd202d-ssd201htv2.dts   | 25 +++++++++
 .../boot/dts/mstar-infinity2m-ssd202d.dtsi    | 14 +++++
 .../boot/dts/mstar-infinity2m-ssd20xd.dtsi    |  7 +++
 arch/arm/boot/dts/mstar-infinity2m.dtsi       | 23 +++++++++
 arch/arm/boot/dts/mstar-v7.dtsi               |  2 +-
 arch/arm/mach-mstar/mstarv7.c                 | 51 +++++++++++++++++++
 10 files changed, 168 insertions(+), 1 deletion(-)
 create mode 100644 Documentation/devicetree/bindings/arm/mstar/mstar,smpctrl.yaml
 create mode 100644 arch/arm/boot/dts/mstar-infinity2m-ssd202d-ssd201htv2.dts
 create mode 100644 arch/arm/boot/dts/mstar-infinity2m-ssd202d.dtsi
 create mode 100644 arch/arm/boot/dts/mstar-infinity2m-ssd20xd.dtsi
 create mode 100644 arch/arm/boot/dts/mstar-infinity2m.dtsi

-- 
2.29.2


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[PATCH 1/9] dt-bindings: mstar: Add binding details for mstar,smpctrl

[Daniel Palmer]

This adds a YAML description of the smpctrl node needed by the
platform code for the MStar/SigmaStar Armv7 SoCs to boot secondary cpus.

Signed-off-by: Daniel Palmer <daniel@0x0f.com>
---
 .../bindings/arm/mstar/mstar,smpctrl.yaml     | 38 +++++++++++++++++++
 1 file changed, 38 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/arm/mstar/mstar,smpctrl.yaml

diff --git a/Documentation/devicetree/bindings/arm/mstar/mstar,smpctrl.yaml b/Documentation/devicetree/bindings/arm/mstar/mstar,smpctrl.yaml
new file mode 100644
index 000000000000..a102287b5c88
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/mstar/mstar,smpctrl.yaml
@@ -0,0 +1,38 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+# Copyright 2020 thingy.jp.
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/arm/mstar/mstar,smpctrl.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: MStar/SigmaStar Armv7 SoC SMP control registers
+
+maintainers:
+  - Daniel Palmer <daniel@thingy.jp>
+
+description: |
+  MStar/SigmaStar's Armv7 SoCs that have more than one processor
+  have a region of registers that allow setting the boot address
+  and a magic number that allows secondary processors to leave
+  the loop they are parked in by the boot ROM.
+
+properties:
+  compatible:
+    items:
+      - const: mstar,smpctrl
+
+  reg:
+    maxItems: 1
+
+required:
+  - compatible
+  - reg
+
+additionalProperties: false
+
+examples:
+  - |
+    smpctrl@204000 {
+        compatible = "mstar,smpctrl";
+        reg = <0x204000 0x200>;
+    };
-- 
2.29.2

[PATCH 1/9] dt-bindings: mstar: Add binding details for mstar, smpctrl

[Daniel Palmer]

This adds a YAML description of the smpctrl node needed by the
platform code for the MStar/SigmaStar Armv7 SoCs to boot secondary cpus.

Signed-off-by: Daniel Palmer <daniel@0x0f.com>
---
 .../bindings/arm/mstar/mstar,smpctrl.yaml     | 38 +++++++++++++++++++
 1 file changed, 38 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/arm/mstar/mstar,smpctrl.yaml

diff --git a/Documentation/devicetree/bindings/arm/mstar/mstar,smpctrl.yaml b/Documentation/devicetree/bindings/arm/mstar/mstar,smpctrl.yaml
new file mode 100644
index 000000000000..a102287b5c88
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/mstar/mstar,smpctrl.yaml
@@ -0,0 +1,38 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+# Copyright 2020 thingy.jp.
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/arm/mstar/mstar,smpctrl.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: MStar/SigmaStar Armv7 SoC SMP control registers
+
+maintainers:
+  - Daniel Palmer <daniel@thingy.jp>
+
+description: |
+  MStar/SigmaStar's Armv7 SoCs that have more than one processor
+  have a region of registers that allow setting the boot address
+  and a magic number that allows secondary processors to leave
+  the loop they are parked in by the boot ROM.
+
+properties:
+  compatible:
+    items:
+      - const: mstar,smpctrl
+
+  reg:
+    maxItems: 1
+
+required:
+  - compatible
+  - reg
+
+additionalProperties: false
+
+examples:
+  - |
+    smpctrl@204000 {
+        compatible = "mstar,smpctrl";
+        reg = <0x204000 0x200>;
+    };
-- 
2.29.2


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[PATCH 2/9] dt-bindings: vendor-prefixes: Add honestar vendor prefix

[Daniel Palmer]

Add prefix for Honestar Technologies Co., Ltd.

Signed-off-by: Daniel Palmer <daniel@0x0f.com>
---
 Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml
index 2735be1a8470..a6cf2cef6f89 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.yaml
+++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml
@@ -451,6 +451,8 @@ patternProperties:
     description: Holt Integrated Circuits, Inc.
   "^honeywell,.*":
     description: Honeywell
+  "^honestar,.*":
+    description: Honestar Technologies Co., Ltd.
   "^hoperun,.*":
     description: Jiangsu HopeRun Software Co., Ltd.
   "^hp,.*":
-- 
2.29.2

[PATCH 2/9] dt-bindings: vendor-prefixes: Add honestar vendor prefix

[Daniel Palmer]

Add prefix for Honestar Technologies Co., Ltd.

Signed-off-by: Daniel Palmer <daniel@0x0f.com>
---
 Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml
index 2735be1a8470..a6cf2cef6f89 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.yaml
+++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml
@@ -451,6 +451,8 @@ patternProperties:
     description: Holt Integrated Circuits, Inc.
   "^honeywell,.*":
     description: Honeywell
+  "^honestar,.*":
+    description: Honestar Technologies Co., Ltd.
   "^hoperun,.*":
     description: Jiangsu HopeRun Software Co., Ltd.
   "^hp,.*":
-- 
2.29.2


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[PATCH 3/9] dt-bindings: mstar: Add Honestar SSD201_HT_V2 to mstar boards

[Daniel Palmer]

The Honestar SSD201_HT_V2 is a full size devkit for the SigmaStar
SSD201 or SSD202D (they are pin compatible).

Currently only the SSD202D version is supported as that's the one
I have.

Link: https://linux-chenxing.org/infinity2/ssd201_ht_v2/
Signed-off-by: Daniel Palmer <daniel@0x0f.com>
---
 Documentation/devicetree/bindings/arm/mstar/mstar.yaml | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/mstar/mstar.yaml b/Documentation/devicetree/bindings/arm/mstar/mstar.yaml
index 7c787405bb2f..61d08c473eb8 100644
--- a/Documentation/devicetree/bindings/arm/mstar/mstar.yaml
+++ b/Documentation/devicetree/bindings/arm/mstar/mstar.yaml
@@ -20,6 +20,12 @@ properties:
               - thingyjp,breadbee-crust # thingy.jp BreadBee Crust
           - const: mstar,infinity
 
+      - description: infinity2m boards
+        items:
+          - enum:
+              - honestar,ssd201htv2 # Honestar SSD201_HT_V2 devkit
+          - const: mstar,infinity2m
+
       - description: infinity3 boards
         items:
           - enum:
-- 
2.29.2

[PATCH 3/9] dt-bindings: mstar: Add Honestar SSD201_HT_V2 to mstar boards

[Daniel Palmer]

The Honestar SSD201_HT_V2 is a full size devkit for the SigmaStar
SSD201 or SSD202D (they are pin compatible).

Currently only the SSD202D version is supported as that's the one
I have.

Link: https://linux-chenxing.org/infinity2/ssd201_ht_v2/
Signed-off-by: Daniel Palmer <daniel@0x0f.com>
---
 Documentation/devicetree/bindings/arm/mstar/mstar.yaml | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/mstar/mstar.yaml b/Documentation/devicetree/bindings/arm/mstar/mstar.yaml
index 7c787405bb2f..61d08c473eb8 100644
--- a/Documentation/devicetree/bindings/arm/mstar/mstar.yaml
+++ b/Documentation/devicetree/bindings/arm/mstar/mstar.yaml
@@ -20,6 +20,12 @@ properties:
               - thingyjp,breadbee-crust # thingy.jp BreadBee Crust
           - const: mstar,infinity
 
+      - description: infinity2m boards
+        items:
+          - enum:
+              - honestar,ssd201htv2 # Honestar SSD201_HT_V2 devkit
+          - const: mstar,infinity2m
+
       - description: infinity3 boards
         items:
           - enum:
-- 
2.29.2


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[PATCH 4/9] ARM: mstar: Add infinity2m support

[Daniel Palmer]

The infinity2m series of chips are like the other Mstar/Sigmastar
chips in that they have a Cortex A7 system with DDR memory integrated
in a single package.

The infinity2m chips are intended for recording the incoming streams
from IP cameras. So instead of video encoders they have video decoders,
instead of a camera interface they have display hardware and so on.

Aside from the above points the big difference about these chips is that
they include a second Cortex A7 core.

Signed-off-by: Daniel Palmer <daniel@0x0f.com>
---
 arch/arm/boot/dts/mstar-infinity2m.dtsi | 15 +++++++++++++++
 arch/arm/boot/dts/mstar-v7.dtsi         |  2 +-
 arch/arm/mach-mstar/mstarv7.c           |  1 +
 3 files changed, 17 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/boot/dts/mstar-infinity2m.dtsi

diff --git a/arch/arm/boot/dts/mstar-infinity2m.dtsi b/arch/arm/boot/dts/mstar-infinity2m.dtsi
new file mode 100644
index 000000000000..02adb9fe9d3c
--- /dev/null
+++ b/arch/arm/boot/dts/mstar-infinity2m.dtsi
@@ -0,0 +1,15 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright (c) 2020 thingy.jp.
+ * Author: Daniel Palmer <daniel@thingy.jp>
+ */
+
+#include "mstar-infinity.dtsi"
+
+&cpus {
+	cpu1: cpu@1 {
+		device_type = "cpu";
+		compatible = "arm,cortex-a7";
+		reg = <0x1>;
+	};
+};
diff --git a/arch/arm/boot/dts/mstar-v7.dtsi b/arch/arm/boot/dts/mstar-v7.dtsi
index 07fc46c7b4d4..2862b32c7f63 100644
--- a/arch/arm/boot/dts/mstar-v7.dtsi
+++ b/arch/arm/boot/dts/mstar-v7.dtsi
@@ -13,7 +13,7 @@ / {
 	#size-cells = <1>;
 	interrupt-parent = <&gic>;
 
-	cpus {
+	cpus: cpus {
 		#address-cells = <1>;
 		#size-cells = <0>;
 
diff --git a/arch/arm/mach-mstar/mstarv7.c b/arch/arm/mach-mstar/mstarv7.c
index 81a4cbcab206..1aa748fa006e 100644
--- a/arch/arm/mach-mstar/mstarv7.c
+++ b/arch/arm/mach-mstar/mstarv7.c
@@ -35,6 +35,7 @@ static void __iomem *l3bridge;
 
 static const char * const mstarv7_board_dt_compat[] __initconst = {
 	"mstar,infinity",
+	"mstar,infinity2m",
 	"mstar,infinity3",
 	"mstar,mercury5",
 	NULL,
-- 
2.29.2

[PATCH 4/9] ARM: mstar: Add infinity2m support

[Daniel Palmer]

The infinity2m series of chips are like the other Mstar/Sigmastar
chips in that they have a Cortex A7 system with DDR memory integrated
in a single package.

The infinity2m chips are intended for recording the incoming streams
from IP cameras. So instead of video encoders they have video decoders,
instead of a camera interface they have display hardware and so on.

Aside from the above points the big difference about these chips is that
they include a second Cortex A7 core.

Signed-off-by: Daniel Palmer <daniel@0x0f.com>
---
 arch/arm/boot/dts/mstar-infinity2m.dtsi | 15 +++++++++++++++
 arch/arm/boot/dts/mstar-v7.dtsi         |  2 +-
 arch/arm/mach-mstar/mstarv7.c           |  1 +
 3 files changed, 17 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/boot/dts/mstar-infinity2m.dtsi

diff --git a/arch/arm/boot/dts/mstar-infinity2m.dtsi b/arch/arm/boot/dts/mstar-infinity2m.dtsi
new file mode 100644
index 000000000000..02adb9fe9d3c
--- /dev/null
+++ b/arch/arm/boot/dts/mstar-infinity2m.dtsi
@@ -0,0 +1,15 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright (c) 2020 thingy.jp.
+ * Author: Daniel Palmer <daniel@thingy.jp>
+ */
+
+#include "mstar-infinity.dtsi"
+
+&cpus {
+	cpu1: cpu@1 {
+		device_type = "cpu";
+		compatible = "arm,cortex-a7";
+		reg = <0x1>;
+	};
+};
diff --git a/arch/arm/boot/dts/mstar-v7.dtsi b/arch/arm/boot/dts/mstar-v7.dtsi
index 07fc46c7b4d4..2862b32c7f63 100644
--- a/arch/arm/boot/dts/mstar-v7.dtsi
+++ b/arch/arm/boot/dts/mstar-v7.dtsi
@@ -13,7 +13,7 @@ / {
 	#size-cells = <1>;
 	interrupt-parent = <&gic>;
 
-	cpus {
+	cpus: cpus {
 		#address-cells = <1>;
 		#size-cells = <0>;
 
diff --git a/arch/arm/mach-mstar/mstarv7.c b/arch/arm/mach-mstar/mstarv7.c
index 81a4cbcab206..1aa748fa006e 100644
--- a/arch/arm/mach-mstar/mstarv7.c
+++ b/arch/arm/mach-mstar/mstarv7.c
@@ -35,6 +35,7 @@ static void __iomem *l3bridge;
 
 static const char * const mstarv7_board_dt_compat[] __initconst = {
 	"mstar,infinity",
+	"mstar,infinity2m",
 	"mstar,infinity3",
 	"mstar,mercury5",
 	NULL,
-- 
2.29.2


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[PATCH 5/9] ARM: mstar: Add common dtsi for SSD201/SSD202D

[Daniel Palmer]

The SSD201 and SSD202D are basically the same chip with a different DDR die
packaged (64MB DDR2 or 128MB DDR3).

This patch adds a shared dtsi for the common parts of these chips like
gpio, pinctrl etc.

Signed-off-by: Daniel Palmer <daniel@0x0f.com>
---
 arch/arm/boot/dts/mstar-infinity2m-ssd20xd.dtsi | 7 +++++++
 1 file changed, 7 insertions(+)
 create mode 100644 arch/arm/boot/dts/mstar-infinity2m-ssd20xd.dtsi

diff --git a/arch/arm/boot/dts/mstar-infinity2m-ssd20xd.dtsi b/arch/arm/boot/dts/mstar-infinity2m-ssd20xd.dtsi
new file mode 100644
index 000000000000..0811220f0a79
--- /dev/null
+++ b/arch/arm/boot/dts/mstar-infinity2m-ssd20xd.dtsi
@@ -0,0 +1,7 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright (c) 2020 thingy.jp.
+ * Author: Daniel Palmer <daniel@thingy.jp>
+ */
+
+#include "mstar-infinity2m.dtsi"
-- 
2.29.2

[PATCH 5/9] ARM: mstar: Add common dtsi for SSD201/SSD202D

[Daniel Palmer]

The SSD201 and SSD202D are basically the same chip with a different DDR die
packaged (64MB DDR2 or 128MB DDR3).

This patch adds a shared dtsi for the common parts of these chips like
gpio, pinctrl etc.

Signed-off-by: Daniel Palmer <daniel@0x0f.com>
---
 arch/arm/boot/dts/mstar-infinity2m-ssd20xd.dtsi | 7 +++++++
 1 file changed, 7 insertions(+)
 create mode 100644 arch/arm/boot/dts/mstar-infinity2m-ssd20xd.dtsi

diff --git a/arch/arm/boot/dts/mstar-infinity2m-ssd20xd.dtsi b/arch/arm/boot/dts/mstar-infinity2m-ssd20xd.dtsi
new file mode 100644
index 000000000000..0811220f0a79
--- /dev/null
+++ b/arch/arm/boot/dts/mstar-infinity2m-ssd20xd.dtsi
@@ -0,0 +1,7 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright (c) 2020 thingy.jp.
+ * Author: Daniel Palmer <daniel@thingy.jp>
+ */
+
+#include "mstar-infinity2m.dtsi"
-- 
2.29.2


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[PATCH 6/9] ARM: mstar: Add chip level dtsi for SSD202D

[Daniel Palmer]

Add a chip level dtsi for the SigmaStar SSD202D

Signed-off-by: Daniel Palmer <daniel@0x0f.com>
---
 arch/arm/boot/dts/mstar-infinity2m-ssd202d.dtsi | 14 ++++++++++++++
 1 file changed, 14 insertions(+)
 create mode 100644 arch/arm/boot/dts/mstar-infinity2m-ssd202d.dtsi

diff --git a/arch/arm/boot/dts/mstar-infinity2m-ssd202d.dtsi b/arch/arm/boot/dts/mstar-infinity2m-ssd202d.dtsi
new file mode 100644
index 000000000000..176e10a29896
--- /dev/null
+++ b/arch/arm/boot/dts/mstar-infinity2m-ssd202d.dtsi
@@ -0,0 +1,14 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright (c) 2020 thingy.jp.
+ * Author: Daniel Palmer <daniel@thingy.jp>
+ */
+
+#include "mstar-infinity2m-ssd20xd.dtsi"
+
+/ {
+	memory {
+		device_type = "memory";
+		reg = <0x20000000 0x8000000>;
+	};
+};
-- 
2.29.2

[PATCH 6/9] ARM: mstar: Add chip level dtsi for SSD202D

[Daniel Palmer]

Add a chip level dtsi for the SigmaStar SSD202D

Signed-off-by: Daniel Palmer <daniel@0x0f.com>
---
 arch/arm/boot/dts/mstar-infinity2m-ssd202d.dtsi | 14 ++++++++++++++
 1 file changed, 14 insertions(+)
 create mode 100644 arch/arm/boot/dts/mstar-infinity2m-ssd202d.dtsi

diff --git a/arch/arm/boot/dts/mstar-infinity2m-ssd202d.dtsi b/arch/arm/boot/dts/mstar-infinity2m-ssd202d.dtsi
new file mode 100644
index 000000000000..176e10a29896
--- /dev/null
+++ b/arch/arm/boot/dts/mstar-infinity2m-ssd202d.dtsi
@@ -0,0 +1,14 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright (c) 2020 thingy.jp.
+ * Author: Daniel Palmer <daniel@thingy.jp>
+ */
+
+#include "mstar-infinity2m-ssd20xd.dtsi"
+
+/ {
+	memory {
+		device_type = "memory";
+		reg = <0x20000000 0x8000000>;
+	};
+};
-- 
2.29.2


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[PATCH 7/9] ARM: mstar: Add dts for Honestar ssd201htv2

[Daniel Palmer]

Add a dts for the Honestar ssd201htv2 devkit.
This is for the board populated with a SSD202D.

Signed-off-by: Daniel Palmer <daniel@0x0f.com>
---
 arch/arm/boot/dts/Makefile                    |  1 +
 .../mstar-infinity2m-ssd202d-ssd201htv2.dts   | 25 +++++++++++++++++++
 2 files changed, 26 insertions(+)
 create mode 100644 arch/arm/boot/dts/mstar-infinity2m-ssd202d-ssd201htv2.dts

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index ce66ffd5a1bb..ccbf44b6f32a 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -1372,6 +1372,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \
 dtb-$(CONFIG_ARCH_MILBEAUT) += milbeaut-m10v-evb.dtb
 dtb-$(CONFIG_ARCH_MSTARV7) += \
 	mstar-infinity-msc313-breadbee_crust.dtb \
+	mstar-infinity2m-ssd202d-ssd201htv2.dtb \
 	mstar-infinity3-msc313e-breadbee.dtb \
 	mstar-mercury5-ssc8336n-midrived08.dtb
 dtb-$(CONFIG_ARCH_ZX) += zx296702-ad1.dtb
diff --git a/arch/arm/boot/dts/mstar-infinity2m-ssd202d-ssd201htv2.dts b/arch/arm/boot/dts/mstar-infinity2m-ssd202d-ssd201htv2.dts
new file mode 100644
index 000000000000..5d81641414a2
--- /dev/null
+++ b/arch/arm/boot/dts/mstar-infinity2m-ssd202d-ssd201htv2.dts
@@ -0,0 +1,25 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright (c) 2020 thingy.jp.
+ * Author: Daniel Palmer <daniel@thingy.jp>
+ */
+
+/dts-v1/;
+#include "mstar-infinity2m-ssd202d.dtsi"
+
+/ {
+	model = "SSD201_HT_V2";
+	compatible = "honestar,ssd201htv2", "mstar,infinity2m";
+
+	aliases {
+		serial0 = &pm_uart;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+};
+
+&pm_uart {
+	status = "okay";
+};
-- 
2.29.2

[PATCH 7/9] ARM: mstar: Add dts for Honestar ssd201htv2

[Daniel Palmer]

Add a dts for the Honestar ssd201htv2 devkit.
This is for the board populated with a SSD202D.

Signed-off-by: Daniel Palmer <daniel@0x0f.com>
---
 arch/arm/boot/dts/Makefile                    |  1 +
 .../mstar-infinity2m-ssd202d-ssd201htv2.dts   | 25 +++++++++++++++++++
 2 files changed, 26 insertions(+)
 create mode 100644 arch/arm/boot/dts/mstar-infinity2m-ssd202d-ssd201htv2.dts

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index ce66ffd5a1bb..ccbf44b6f32a 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -1372,6 +1372,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \
 dtb-$(CONFIG_ARCH_MILBEAUT) += milbeaut-m10v-evb.dtb
 dtb-$(CONFIG_ARCH_MSTARV7) += \
 	mstar-infinity-msc313-breadbee_crust.dtb \
+	mstar-infinity2m-ssd202d-ssd201htv2.dtb \
 	mstar-infinity3-msc313e-breadbee.dtb \
 	mstar-mercury5-ssc8336n-midrived08.dtb
 dtb-$(CONFIG_ARCH_ZX) += zx296702-ad1.dtb
diff --git a/arch/arm/boot/dts/mstar-infinity2m-ssd202d-ssd201htv2.dts b/arch/arm/boot/dts/mstar-infinity2m-ssd202d-ssd201htv2.dts
new file mode 100644
index 000000000000..5d81641414a2
--- /dev/null
+++ b/arch/arm/boot/dts/mstar-infinity2m-ssd202d-ssd201htv2.dts
@@ -0,0 +1,25 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright (c) 2020 thingy.jp.
+ * Author: Daniel Palmer <daniel@thingy.jp>
+ */
+
+/dts-v1/;
+#include "mstar-infinity2m-ssd202d.dtsi"
+
+/ {
+	model = "SSD201_HT_V2";
+	compatible = "honestar,ssd201htv2", "mstar,infinity2m";
+
+	aliases {
+		serial0 = &pm_uart;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+};
+
+&pm_uart {
+	status = "okay";
+};
-- 
2.29.2


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[PATCH 8/9] ARM: mstar: Add smp ctrl registers to infinity2m dtsi

[Daniel Palmer]

Add the smpctrl registers to the infinity2m dtsi so that the
second CPU can be enabled on chips in this family.

Signed-off-by: Daniel Palmer <daniel@0x0f.com>
---
 arch/arm/boot/dts/mstar-infinity2m.dtsi | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/arm/boot/dts/mstar-infinity2m.dtsi b/arch/arm/boot/dts/mstar-infinity2m.dtsi
index 02adb9fe9d3c..85e178368ba4 100644
--- a/arch/arm/boot/dts/mstar-infinity2m.dtsi
+++ b/arch/arm/boot/dts/mstar-infinity2m.dtsi
@@ -13,3 +13,11 @@ cpu1: cpu@1 {
 		reg = <0x1>;
 	};
 };
+
+&riu {
+	smpctrl@204000 {
+		compatible = "mstar,smpctrl";
+		reg = <0x204000 0x200>;
+		status = "okay";
+	};
+};
-- 
2.29.2

[PATCH 8/9] ARM: mstar: Add smp ctrl registers to infinity2m dtsi

[Daniel Palmer]

Add the smpctrl registers to the infinity2m dtsi so that the
second CPU can be enabled on chips in this family.

Signed-off-by: Daniel Palmer <daniel@0x0f.com>
---
 arch/arm/boot/dts/mstar-infinity2m.dtsi | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/arm/boot/dts/mstar-infinity2m.dtsi b/arch/arm/boot/dts/mstar-infinity2m.dtsi
index 02adb9fe9d3c..85e178368ba4 100644
--- a/arch/arm/boot/dts/mstar-infinity2m.dtsi
+++ b/arch/arm/boot/dts/mstar-infinity2m.dtsi
@@ -13,3 +13,11 @@ cpu1: cpu@1 {
 		reg = <0x1>;
 	};
 };
+
+&riu {
+	smpctrl@204000 {
+		compatible = "mstar,smpctrl";
+		reg = <0x204000 0x200>;
+		status = "okay";
+	};
+};
-- 
2.29.2


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Re: [PATCH 8/9] ARM: mstar: Add smp ctrl registers to infinity2m dtsi

[Arnd Bergmann]

On Mon, Nov 30, 2020 at 2:10 PM Daniel Palmer <daniel@0x0f.com> wrote:
>
> +&riu {
> +       smpctrl@204000 {
> +               compatible = "mstar,smpctrl";
> +               reg = <0x204000 0x200>;
> +               status = "okay";
> +       };

You probably want some more specific compatible value, in case there are
multiple SoCs from mstar that have an smpctrl block and they don't all use
an exactly identical register layout.

     Arnd

Re: [PATCH 8/9] ARM: mstar: Add smp ctrl registers to infinity2m dtsi

[Arnd Bergmann]

On Mon, Nov 30, 2020 at 2:10 PM Daniel Palmer <daniel@0x0f.com> wrote:
>
> +&riu {
> +       smpctrl@204000 {
> +               compatible = "mstar,smpctrl";
> +               reg = <0x204000 0x200>;
> +               status = "okay";
> +       };

You probably want some more specific compatible value, in case there are
multiple SoCs from mstar that have an smpctrl block and they don't all use
an exactly identical register layout.

     Arnd

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Re: [PATCH 8/9] ARM: mstar: Add smp ctrl registers to infinity2m dtsi

[Daniel Palmer]

Hi Arnd,

On Mon, 30 Nov 2020 at 22:44, Arnd Bergmann <arnd@kernel.org> wrote:
>
> On Mon, Nov 30, 2020 at 2:10 PM Daniel Palmer <daniel@0x0f.com> wrote:
> >
> > +&riu {
> > +       smpctrl@204000 {
> > +               compatible = "mstar,smpctrl";
> > +               reg = <0x204000 0x200>;
> > +               status = "okay";
> > +       };
>
> You probably want some more specific compatible value, in case there are
> multiple SoCs from mstar that have an smpctrl block and they don't all use
> an exactly identical register layout.
>

From what I can tell these are in the same place for the infinity2m and
the other SMP chip in this series that are in the infinity6 series.

Would "mstar,i2m-smpctrl" make more sense?

Thanks,

Daniel

Re: [PATCH 8/9] ARM: mstar: Add smp ctrl registers to infinity2m dtsi

[Daniel Palmer]

Hi Arnd,

On Mon, 30 Nov 2020 at 22:44, Arnd Bergmann <arnd@kernel.org> wrote:
>
> On Mon, Nov 30, 2020 at 2:10 PM Daniel Palmer <daniel@0x0f.com> wrote:
> >
> > +&riu {
> > +       smpctrl@204000 {
> > +               compatible = "mstar,smpctrl";
> > +               reg = <0x204000 0x200>;
> > +               status = "okay";
> > +       };
>
> You probably want some more specific compatible value, in case there are
> multiple SoCs from mstar that have an smpctrl block and they don't all use
> an exactly identical register layout.
>

From what I can tell these are in the same place for the infinity2m and
the other SMP chip in this series that are in the infinity6 series.

Would "mstar,i2m-smpctrl" make more sense?

Thanks,

Daniel

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Re: [PATCH 8/9] ARM: mstar: Add smp ctrl registers to infinity2m dtsi

[Arnd Bergmann]

On Mon, Nov 30, 2020 at 3:11 PM Daniel Palmer <daniel@0x0f.com> wrote:
>
> Hi Arnd,
>
> On Mon, 30 Nov 2020 at 22:44, Arnd Bergmann <arnd@kernel.org> wrote:
> >
> > On Mon, Nov 30, 2020 at 2:10 PM Daniel Palmer <daniel@0x0f.com> wrote:
> > >
> > > +&riu {
> > > +       smpctrl@204000 {
> > > +               compatible = "mstar,smpctrl";
> > > +               reg = <0x204000 0x200>;
> > > +               status = "okay";
> > > +       };
> >
> > You probably want some more specific compatible value, in case there are
> > multiple SoCs from mstar that have an smpctrl block and they don't all use
> > an exactly identical register layout.
>
> From what I can tell these are in the same place for the infinity2m and
> the other SMP chip in this series that are in the infinity6 series.
>
> Would "mstar,i2m-smpctrl" make more sense?

Please use the exact name of the chip for the most specific name,
plus a generic identifier that makes sense for all of them. For the
generic identifier, you can normally just use whatever the oldest
chip is that you can find with that IP block.

      Arnd

Re: [PATCH 8/9] ARM: mstar: Add smp ctrl registers to infinity2m dtsi

[Arnd Bergmann]

On Mon, Nov 30, 2020 at 3:11 PM Daniel Palmer <daniel@0x0f.com> wrote:
>
> Hi Arnd,
>
> On Mon, 30 Nov 2020 at 22:44, Arnd Bergmann <arnd@kernel.org> wrote:
> >
> > On Mon, Nov 30, 2020 at 2:10 PM Daniel Palmer <daniel@0x0f.com> wrote:
> > >
> > > +&riu {
> > > +       smpctrl@204000 {
> > > +               compatible = "mstar,smpctrl";
> > > +               reg = <0x204000 0x200>;
> > > +               status = "okay";
> > > +       };
> >
> > You probably want some more specific compatible value, in case there are
> > multiple SoCs from mstar that have an smpctrl block and they don't all use
> > an exactly identical register layout.
>
> From what I can tell these are in the same place for the infinity2m and
> the other SMP chip in this series that are in the infinity6 series.
>
> Would "mstar,i2m-smpctrl" make more sense?

Please use the exact name of the chip for the most specific name,
plus a generic identifier that makes sense for all of them. For the
generic identifier, you can normally just use whatever the oldest
chip is that you can find with that IP block.

      Arnd

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[PATCH 9/9] ARM: mstar: SMP support

[Daniel Palmer]

This patch adds SMP support for MStar/Sigmastar chips that have a second core
like those in the infinity2m family.

So far only single and dual core chips have been found so this does
the bare minimum to boot the second core. From what I can tell not having
the "holding pen" code to handle multiple cores is fine if there is only
one core the will get booted. This might need to be reconsidered if chips
with more cores turn up.

Signed-off-by: Daniel Palmer <daniel@0x0f.com>
---
 arch/arm/mach-mstar/mstarv7.c | 50 +++++++++++++++++++++++++++++++++++
 1 file changed, 50 insertions(+)

diff --git a/arch/arm/mach-mstar/mstarv7.c b/arch/arm/mach-mstar/mstarv7.c
index 1aa748fa006e..23fe47a8f1a5 100644
--- a/arch/arm/mach-mstar/mstarv7.c
+++ b/arch/arm/mach-mstar/mstarv7.c
@@ -31,6 +31,13 @@
 #define MSTARV7_L3BRIDGE_FLUSH_TRIGGER	BIT(0)
 #define MSTARV7_L3BRIDGE_STATUS_DONE	BIT(12)
 
+#ifdef CONFIG_SMP
+#define MSTARV7_CPU1_BOOT_ADDR_HIGH	0x4c
+#define MSTARV7_CPU1_BOOT_ADDR_LOW	0x50
+#define MSTARV7_CPU1_UNLOCK		0x58
+#define MSTARV7_CPU1_UNLOCK_MAGIC	0xbabe
+#endif
+
 static void __iomem *l3bridge;
 
 static const char * const mstarv7_board_dt_compat[] __initconst = {
@@ -63,6 +70,46 @@ static void mstarv7_mb(void)
 	}
 }
 
+#ifdef CONFIG_SMP
+static int mstarv7_boot_secondary(unsigned int cpu, struct task_struct *idle)
+{
+	struct device_node *np;
+	u32 bootaddr = (u32) __pa_symbol(secondary_startup_arm);
+	void __iomem *smpctrl = 0;
+
+	/*
+	 * right now we don't know how to boot anything except
+	 * cpu 1.
+	 */
+	if (cpu != 1)
+		return -EINVAL;
+
+	np = of_find_compatible_node(NULL, NULL, "mstar,smpctrl");
+	smpctrl = of_iomap(np, 0);
+
+	if (!smpctrl)
+		return -ENODEV;
+
+	/* set the boot address for the second cpu */
+	writew(bootaddr & 0xffff, smpctrl + MSTARV7_CPU1_BOOT_ADDR_LOW);
+	writew((bootaddr >> 16) & 0xffff, smpctrl + MSTARV7_CPU1_BOOT_ADDR_HIGH);
+
+	/* unlock the second cpu */
+	writew(MSTARV7_CPU1_UNLOCK_MAGIC, smpctrl + MSTARV7_CPU1_UNLOCK);
+
+	/* and away we go...*/
+	arch_send_wakeup_ipi_mask(cpumask_of(cpu));
+
+	iounmap(smpctrl);
+
+	return 0;
+}
+
+struct smp_operations __initdata mstarv7_smp_ops  = {
+	.smp_boot_secondary = mstarv7_boot_secondary,
+};
+#endif
+
 static void __init mstarv7_init(void)
 {
 	struct device_node *np;
@@ -78,4 +125,7 @@ static void __init mstarv7_init(void)
 DT_MACHINE_START(MSTARV7_DT, "MStar/Sigmastar Armv7 (Device Tree)")
 	.dt_compat	= mstarv7_board_dt_compat,
 	.init_machine	= mstarv7_init,
+#ifdef CONFIG_SMP
+	.smp		= smp_ops(mstarv7_smp_ops),
+#endif
 MACHINE_END
-- 
2.29.2

[PATCH 9/9] ARM: mstar: SMP support

[Daniel Palmer]

This patch adds SMP support for MStar/Sigmastar chips that have a second core
like those in the infinity2m family.

So far only single and dual core chips have been found so this does
the bare minimum to boot the second core. From what I can tell not having
the "holding pen" code to handle multiple cores is fine if there is only
one core the will get booted. This might need to be reconsidered if chips
with more cores turn up.

Signed-off-by: Daniel Palmer <daniel@0x0f.com>
---
 arch/arm/mach-mstar/mstarv7.c | 50 +++++++++++++++++++++++++++++++++++
 1 file changed, 50 insertions(+)

diff --git a/arch/arm/mach-mstar/mstarv7.c b/arch/arm/mach-mstar/mstarv7.c
index 1aa748fa006e..23fe47a8f1a5 100644
--- a/arch/arm/mach-mstar/mstarv7.c
+++ b/arch/arm/mach-mstar/mstarv7.c
@@ -31,6 +31,13 @@
 #define MSTARV7_L3BRIDGE_FLUSH_TRIGGER	BIT(0)
 #define MSTARV7_L3BRIDGE_STATUS_DONE	BIT(12)
 
+#ifdef CONFIG_SMP
+#define MSTARV7_CPU1_BOOT_ADDR_HIGH	0x4c
+#define MSTARV7_CPU1_BOOT_ADDR_LOW	0x50
+#define MSTARV7_CPU1_UNLOCK		0x58
+#define MSTARV7_CPU1_UNLOCK_MAGIC	0xbabe
+#endif
+
 static void __iomem *l3bridge;
 
 static const char * const mstarv7_board_dt_compat[] __initconst = {
@@ -63,6 +70,46 @@ static void mstarv7_mb(void)
 	}
 }
 
+#ifdef CONFIG_SMP
+static int mstarv7_boot_secondary(unsigned int cpu, struct task_struct *idle)
+{
+	struct device_node *np;
+	u32 bootaddr = (u32) __pa_symbol(secondary_startup_arm);
+	void __iomem *smpctrl = 0;
+
+	/*
+	 * right now we don't know how to boot anything except
+	 * cpu 1.
+	 */
+	if (cpu != 1)
+		return -EINVAL;
+
+	np = of_find_compatible_node(NULL, NULL, "mstar,smpctrl");
+	smpctrl = of_iomap(np, 0);
+
+	if (!smpctrl)
+		return -ENODEV;
+
+	/* set the boot address for the second cpu */
+	writew(bootaddr & 0xffff, smpctrl + MSTARV7_CPU1_BOOT_ADDR_LOW);
+	writew((bootaddr >> 16) & 0xffff, smpctrl + MSTARV7_CPU1_BOOT_ADDR_HIGH);
+
+	/* unlock the second cpu */
+	writew(MSTARV7_CPU1_UNLOCK_MAGIC, smpctrl + MSTARV7_CPU1_UNLOCK);
+
+	/* and away we go...*/
+	arch_send_wakeup_ipi_mask(cpumask_of(cpu));
+
+	iounmap(smpctrl);
+
+	return 0;
+}
+
+struct smp_operations __initdata mstarv7_smp_ops  = {
+	.smp_boot_secondary = mstarv7_boot_secondary,
+};
+#endif
+
 static void __init mstarv7_init(void)
 {
 	struct device_node *np;
@@ -78,4 +125,7 @@ static void __init mstarv7_init(void)
 DT_MACHINE_START(MSTARV7_DT, "MStar/Sigmastar Armv7 (Device Tree)")
 	.dt_compat	= mstarv7_board_dt_compat,
 	.init_machine	= mstarv7_init,
+#ifdef CONFIG_SMP
+	.smp		= smp_ops(mstarv7_smp_ops),
+#endif
 MACHINE_END
-- 
2.29.2


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Re: [PATCH 9/9] ARM: mstar: SMP support

[Arnd Bergmann]

On Mon, Nov 30, 2020 at 2:10 PM Daniel Palmer <daniel@0x0f.com> wrote:

> +#ifdef CONFIG_SMP
> +static int mstarv7_boot_secondary(unsigned int cpu, struct task_struct *idle)
> +{
> +       struct device_node *np;
> +       u32 bootaddr = (u32) __pa_symbol(secondary_startup_arm);
> +       void __iomem *smpctrl = 0;

The initialization is wrong here: it's not a pointer and the value '0'
is not useful.

> +struct smp_operations __initdata mstarv7_smp_ops  = {
> +       .smp_boot_secondary = mstarv7_boot_secondary,
> +};
> +#endif

So no hotplug operations?

> @@ -78,4 +125,7 @@ static void __init mstarv7_init(void)
>  DT_MACHINE_START(MSTARV7_DT, "MStar/Sigmastar Armv7 (Device Tree)")
>         .dt_compat      = mstarv7_board_dt_compat,
>         .init_machine   = mstarv7_init,
> +#ifdef CONFIG_SMP
> +       .smp            = smp_ops(mstarv7_smp_ops),
> +#endif
>  MACHINE_END

Drop the #ifdef, smp_ops() already makes the assignment conditional.

Or better, use CPU_METHOD_OF_DECLARE() instead of smp_ops.

       Arnd

Re: [PATCH 9/9] ARM: mstar: SMP support

[Arnd Bergmann]

On Mon, Nov 30, 2020 at 2:10 PM Daniel Palmer <daniel@0x0f.com> wrote:

> +#ifdef CONFIG_SMP
> +static int mstarv7_boot_secondary(unsigned int cpu, struct task_struct *idle)
> +{
> +       struct device_node *np;
> +       u32 bootaddr = (u32) __pa_symbol(secondary_startup_arm);
> +       void __iomem *smpctrl = 0;

The initialization is wrong here: it's not a pointer and the value '0'
is not useful.

> +struct smp_operations __initdata mstarv7_smp_ops  = {
> +       .smp_boot_secondary = mstarv7_boot_secondary,
> +};
> +#endif

So no hotplug operations?

> @@ -78,4 +125,7 @@ static void __init mstarv7_init(void)
>  DT_MACHINE_START(MSTARV7_DT, "MStar/Sigmastar Armv7 (Device Tree)")
>         .dt_compat      = mstarv7_board_dt_compat,
>         .init_machine   = mstarv7_init,
> +#ifdef CONFIG_SMP
> +       .smp            = smp_ops(mstarv7_smp_ops),
> +#endif
>  MACHINE_END

Drop the #ifdef, smp_ops() already makes the assignment conditional.

Or better, use CPU_METHOD_OF_DECLARE() instead of smp_ops.

       Arnd

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Re: [PATCH 9/9] ARM: mstar: SMP support

[Daniel Palmer]

Hi Arnd,

On Mon, 30 Nov 2020 at 22:42, Arnd Bergmann <arnd@kernel.org> wrote:
> > +struct smp_operations __initdata mstarv7_smp_ops  = {
> > +       .smp_boot_secondary = mstarv7_boot_secondary,
> > +};
> > +#endif
>
> So no hotplug operations?

Not yet. There are controls to power down different bits of the chip,
assert internal resets and so on so it might be possible to add that
later but I haven't worked out where those bits are yet for the second
cpu.

> Or better, use CPU_METHOD_OF_DECLARE() instead of smp_ops.

I'll do that for the v2.

Was there anything else that looked fishy? Every other platform seems
to have a lot of code for moving secondary CPUs from the boot ROM into
somewhere the kernel can control the order in which they come online
(vendor code has a copy/paste of the vexpress code) so I was worried I
missed something.

Thanks,

Daniel

Re: [PATCH 9/9] ARM: mstar: SMP support

[Daniel Palmer]

Hi Arnd,

On Mon, 30 Nov 2020 at 22:42, Arnd Bergmann <arnd@kernel.org> wrote:
> > +struct smp_operations __initdata mstarv7_smp_ops  = {
> > +       .smp_boot_secondary = mstarv7_boot_secondary,
> > +};
> > +#endif
>
> So no hotplug operations?

Not yet. There are controls to power down different bits of the chip,
assert internal resets and so on so it might be possible to add that
later but I haven't worked out where those bits are yet for the second
cpu.

> Or better, use CPU_METHOD_OF_DECLARE() instead of smp_ops.

I'll do that for the v2.

Was there anything else that looked fishy? Every other platform seems
to have a lot of code for moving secondary CPUs from the boot ROM into
somewhere the kernel can control the order in which they come online
(vendor code has a copy/paste of the vexpress code) so I was worried I
missed something.

Thanks,

Daniel

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Re: [PATCH 9/9] ARM: mstar: SMP support

[Arnd Bergmann]

On Mon, Nov 30, 2020 at 3:25 PM Daniel Palmer <daniel@0x0f.com> wrote:
>
> Hi Arnd,
>
> On Mon, 30 Nov 2020 at 22:42, Arnd Bergmann <arnd@kernel.org> wrote:
> > > +struct smp_operations __initdata mstarv7_smp_ops  = {
> > > +       .smp_boot_secondary = mstarv7_boot_secondary,
> > > +};
> > > +#endif
> >
> > So no hotplug operations?
>
> Not yet. There are controls to power down different bits of the chip,
> assert internal resets and so on so it might be possible to add that
> later but I haven't worked out where those bits are yet for the second
> cpu.
>
> > Or better, use CPU_METHOD_OF_DECLARE() instead of smp_ops.
>
> I'll do that for the v2.

Ok.

> Was there anything else that looked fishy? Every other platform seems
> to have a lot of code for moving secondary CPUs from the boot ROM into
> somewhere the kernel can control the order in which they come online
> (vendor code has a copy/paste of the vexpress code) so I was worried I
> missed something.

No, it looks fine to me, but I'm not an expert in this area.

As far as I can tell, platforms will either execute from bootrom with
the secondary_startup function in a register like you have, or
they start from SRAM, with that function somewhere else, but
you wouldn't need both.

           Arnd

Re: [PATCH 9/9] ARM: mstar: SMP support

[Arnd Bergmann]

On Mon, Nov 30, 2020 at 3:25 PM Daniel Palmer <daniel@0x0f.com> wrote:
>
> Hi Arnd,
>
> On Mon, 30 Nov 2020 at 22:42, Arnd Bergmann <arnd@kernel.org> wrote:
> > > +struct smp_operations __initdata mstarv7_smp_ops  = {
> > > +       .smp_boot_secondary = mstarv7_boot_secondary,
> > > +};
> > > +#endif
> >
> > So no hotplug operations?
>
> Not yet. There are controls to power down different bits of the chip,
> assert internal resets and so on so it might be possible to add that
> later but I haven't worked out where those bits are yet for the second
> cpu.
>
> > Or better, use CPU_METHOD_OF_DECLARE() instead of smp_ops.
>
> I'll do that for the v2.

Ok.

> Was there anything else that looked fishy? Every other platform seems
> to have a lot of code for moving secondary CPUs from the boot ROM into
> somewhere the kernel can control the order in which they come online
> (vendor code has a copy/paste of the vexpress code) so I was worried I
> missed something.

No, it looks fine to me, but I'm not an expert in this area.

As far as I can tell, platforms will either execute from bootrom with
the secondary_startup function in a register like you have, or
they start from SRAM, with that function somewhere else, but
you wouldn't need both.

           Arnd

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