From: Alexey Baturo <baturo.alexey@gmail.com> To: Richard Henderson <richard.henderson@linaro.org> Cc: "open list:RISC-V TCG CPUs" <qemu-riscv@nongnu.org>, Sagar Karandikar <sagark@eecs.berkeley.edu>, Bastian Koppelmann <kbastian@mail.uni-paderborn.de>, "open list:All patches CC here" <qemu-devel@nongnu.org>, "space.monkey.delivers@gmail.com" <space.monkey.delivers@gmail.com>, Alistair Francis <Alistair.Francis@wdc.com>, Dave Smith <kupokupokupopo@gmail.com>, Palmer Dabbelt <palmer@dabbelt.com> Subject: Re: [PATCH v2 5/5] [RISCV_PM] Implement address masking functions required for RISC-V Pointer Masking extension Date: Thu, 15 Oct 2020 20:33:06 +0300 [thread overview] Message-ID: <CAFukJ-CBdO=EWs2F3SWG7nGvzKsKkeW-iYNvEZw+aaZaqWbi3A@mail.gmail.com> (raw) In-Reply-To: <3975e121-fb59-ffaa-456b-13e1a1b871be@linaro.org> [-- Attachment #1: Type: text/plain, Size: 1518 bytes --] > g_assert_not_reached(); Would fix, thanks. > bool Would fix. >!s->pm_enabled Same. > Don't need the if. Would remove, thanks. > And should it in fact be placed outside the ifdef? Sure, you're right. Richard, thank you for your time and effort reviewing these changes! чт, 15 окт. 2020 г. в 20:07, Richard Henderson <richard.henderson@linaro.org >: > On 10/15/20 8:21 AM, Alexey Baturo wrote: > > + switch (priv) { > > + case PRV_U: > > + pm_enabled = env->mmte & U_PM_ENABLE; > > + break; > > + case PRV_S: > > + pm_enabled = env->mmte & S_PM_ENABLE; > > + break; > > + case PRV_M: > > + pm_enabled = env->mmte & M_PM_ENABLE; > > + break; > > + default: > > + assert(0 && "Unreachable"); > > g_assert_not_reached(); > > > + /* PointerMasking extension */ > > + uint8_t pm_enabled; > > bool > > > + if (s->pm_enabled == 0) { > > !s->pm_enabled > > > + if (riscv_has_ext(env, RVJ)) { > > + ctx->pm_enabled = FIELD_EX32(tb_flags, TB_FLAGS, PM_ENABLED); > > + int priv = cpu_mmu_index(env, false); > > + ctx->pm_mask = pm_mask[priv]; > > + ctx->pm_base = pm_base[priv]; > > + } else { > > + ctx->pm_enabled = 0; > > + } > > Don't need the if. And should it in fact be placed outside the ifdef? > This > shouldn't be related to !CONFIG_USER_ONLY here and nowhere else. > > > r~ > [-- Attachment #2: Type: text/html, Size: 2297 bytes --]
WARNING: multiple messages have this Message-ID (diff)
From: Alexey Baturo <baturo.alexey@gmail.com> To: Richard Henderson <richard.henderson@linaro.org> Cc: "space.monkey.delivers@gmail.com" <space.monkey.delivers@gmail.com>, Dave Smith <kupokupokupopo@gmail.com>, Palmer Dabbelt <palmer@dabbelt.com>, Alistair Francis <Alistair.Francis@wdc.com>, Sagar Karandikar <sagark@eecs.berkeley.edu>, Bastian Koppelmann <kbastian@mail.uni-paderborn.de>, "open list:All patches CC here" <qemu-devel@nongnu.org>, "open list:RISC-V TCG CPUs" <qemu-riscv@nongnu.org> Subject: Re: [PATCH v2 5/5] [RISCV_PM] Implement address masking functions required for RISC-V Pointer Masking extension Date: Thu, 15 Oct 2020 20:33:06 +0300 [thread overview] Message-ID: <CAFukJ-CBdO=EWs2F3SWG7nGvzKsKkeW-iYNvEZw+aaZaqWbi3A@mail.gmail.com> (raw) In-Reply-To: <3975e121-fb59-ffaa-456b-13e1a1b871be@linaro.org> [-- Attachment #1: Type: text/plain, Size: 1518 bytes --] > g_assert_not_reached(); Would fix, thanks. > bool Would fix. >!s->pm_enabled Same. > Don't need the if. Would remove, thanks. > And should it in fact be placed outside the ifdef? Sure, you're right. Richard, thank you for your time and effort reviewing these changes! чт, 15 окт. 2020 г. в 20:07, Richard Henderson <richard.henderson@linaro.org >: > On 10/15/20 8:21 AM, Alexey Baturo wrote: > > + switch (priv) { > > + case PRV_U: > > + pm_enabled = env->mmte & U_PM_ENABLE; > > + break; > > + case PRV_S: > > + pm_enabled = env->mmte & S_PM_ENABLE; > > + break; > > + case PRV_M: > > + pm_enabled = env->mmte & M_PM_ENABLE; > > + break; > > + default: > > + assert(0 && "Unreachable"); > > g_assert_not_reached(); > > > + /* PointerMasking extension */ > > + uint8_t pm_enabled; > > bool > > > + if (s->pm_enabled == 0) { > > !s->pm_enabled > > > + if (riscv_has_ext(env, RVJ)) { > > + ctx->pm_enabled = FIELD_EX32(tb_flags, TB_FLAGS, PM_ENABLED); > > + int priv = cpu_mmu_index(env, false); > > + ctx->pm_mask = pm_mask[priv]; > > + ctx->pm_base = pm_base[priv]; > > + } else { > > + ctx->pm_enabled = 0; > > + } > > Don't need the if. And should it in fact be placed outside the ifdef? > This > shouldn't be related to !CONFIG_USER_ONLY here and nowhere else. > > > r~ > [-- Attachment #2: Type: text/html, Size: 2297 bytes --]
next prev parent reply other threads:[~2020-10-15 17:34 UTC|newest] Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top 2020-10-15 15:21 [PATCH v2 1/5] [RISCV_PM] Add J-extension into RISC-V Alexey Baturo 2020-10-15 15:21 ` Alexey Baturo 2020-10-15 15:21 ` [PATCH v2 2/5] [RISCV_PM] Support CSRs required for RISC-V PM extension except for ones in hypervisor mode Alexey Baturo 2020-10-15 15:21 ` Alexey Baturo 2020-10-15 16:48 ` Richard Henderson 2020-10-15 16:48 ` Richard Henderson 2020-10-15 17:28 ` Alexey Baturo 2020-10-15 17:28 ` Alexey Baturo 2020-10-15 18:05 ` Alexey Baturo 2020-10-15 18:05 ` Alexey Baturo 2020-10-16 17:16 ` Richard Henderson 2020-10-16 17:16 ` Richard Henderson 2020-10-15 15:21 ` [PATCH v2 3/5] [RISCV_PM] Print new PM CSRs in QEMU logs Alexey Baturo 2020-10-15 15:21 ` Alexey Baturo 2020-10-15 15:21 ` [PATCH v2 4/5] [RISCV_PM] Support pointer masking for RISC-V for i/c/f/d/a types of instructions Alexey Baturo 2020-10-15 15:21 ` Alexey Baturo 2020-10-15 17:00 ` Richard Henderson 2020-10-15 17:00 ` Richard Henderson 2020-10-15 17:30 ` Alexey Baturo 2020-10-15 17:30 ` Alexey Baturo 2020-10-15 15:21 ` [PATCH v2 5/5] [RISCV_PM] Implement address masking functions required for RISC-V Pointer Masking extension Alexey Baturo 2020-10-15 15:21 ` Alexey Baturo 2020-10-15 17:07 ` Richard Henderson 2020-10-15 17:07 ` Richard Henderson 2020-10-15 17:33 ` Alexey Baturo [this message] 2020-10-15 17:33 ` Alexey Baturo
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