* [PATCH v2 00/14] Add Flexgen Clock support
@ 2014-06-27 13:24 ` Gabriel FERNANDEZ
0 siblings, 0 replies; 49+ messages in thread
From: Gabriel FERNANDEZ @ 2014-06-27 13:24 UTC (permalink / raw)
To: mturquette, robh+dt, pawel.moll, mark.rutland, ijc+devicetree, galak
Cc: devicetree, linux-doc, linux-kernel, linux-arm-kernel, kernel,
Lee Jones, Gabriel Fernandez
Changes in v2:
- use static const for clkgen_pll_data and stm_fs tables (from
Peter Griffin review)
- add 326 and 333 Mhz frequencies
- cosmetic correction in st,clkgen-vcc.txt
- use of kcalloc instead of kzalloc in drivers/clk/st/clk-flexgen.c
The goal of this series is to add Flexgen clock support to ST SoCs.
A Flexgen clock is composed by:
- a clock cross bar (represented by a mux element)
- a pre and final dividers (represented by a divider and gate elements)
Tested on B2120 board.
Gabriel Fernandez (14):
clk: st: Update ST clock binding documentation
drivers: clk: st: use static const for stm_fs tables
drivers: clk: st: use static const for clkgen_pll_data tables
clk: st: Adds Flexgen clock binding
drivers: clk: st: STiH407: Support for Flexgen Clocks
drivers: clk: st: STiH407: Support for A9 MUX Clocks
drivers: clk: st: STiH407: Support for clockgenA0
drivers: clk: st: Add polarity bit indication
drivers: clk: st: Add quadfs reset handling
drivers: clk: st: STiH407: Support for clockgenC0
drivers: clk: st: STiH407: Support for clockgenD0/D2/D3
drivers: clk: st: STiH407: Support for clockgenA9
drivers: clk: st: Update frequency tables for fs660c32 and fs432c65
drivers: clk: st: Use round to closest divider flag
.../bindings/clock/st/st,clkgen-divmux.txt | 28 +-
.../devicetree/bindings/clock/st/st,clkgen-mux.txt | 6 +-
.../devicetree/bindings/clock/st/st,clkgen-pll.txt | 17 +-
.../bindings/clock/st/st,clkgen-prediv.txt | 8 +-
.../devicetree/bindings/clock/st/st,clkgen-vcc.txt | 34 ++-
.../devicetree/bindings/clock/st/st,clkgen.txt | 59 ++--
.../devicetree/bindings/clock/st/st,flexgen.txt | 48 +++
.../devicetree/bindings/clock/st/st,quadfs.txt | 15 +-
drivers/clk/st/Makefile | 2 +-
drivers/clk/st/clk-flexgen.c | 332 +++++++++++++++++++++
drivers/clk/st/clkgen-fsyn.c | 211 +++++++++++--
drivers/clk/st/clkgen-mux.c | 12 +-
drivers/clk/st/clkgen-pll.c | 94 +++++-
13 files changed, 750 insertions(+), 116 deletions(-)
create mode 100644 Documentation/devicetree/bindings/clock/st/st,flexgen.txt
create mode 100644 drivers/clk/st/clk-flexgen.c
--
1.9.1
^ permalink raw reply [flat|nested] 49+ messages in thread
* [PATCH v2 00/14] Add Flexgen Clock support
@ 2014-06-27 13:24 ` Gabriel FERNANDEZ
0 siblings, 0 replies; 49+ messages in thread
From: Gabriel FERNANDEZ @ 2014-06-27 13:24 UTC (permalink / raw)
To: linux-arm-kernel
Changes in v2:
- use static const for clkgen_pll_data and stm_fs tables (from
Peter Griffin review)
- add 326 and 333 Mhz frequencies
- cosmetic correction in st,clkgen-vcc.txt
- use of kcalloc instead of kzalloc in drivers/clk/st/clk-flexgen.c
The goal of this series is to add Flexgen clock support to ST SoCs.
A Flexgen clock is composed by:
- a clock cross bar (represented by a mux element)
- a pre and final dividers (represented by a divider and gate elements)
Tested on B2120 board.
Gabriel Fernandez (14):
clk: st: Update ST clock binding documentation
drivers: clk: st: use static const for stm_fs tables
drivers: clk: st: use static const for clkgen_pll_data tables
clk: st: Adds Flexgen clock binding
drivers: clk: st: STiH407: Support for Flexgen Clocks
drivers: clk: st: STiH407: Support for A9 MUX Clocks
drivers: clk: st: STiH407: Support for clockgenA0
drivers: clk: st: Add polarity bit indication
drivers: clk: st: Add quadfs reset handling
drivers: clk: st: STiH407: Support for clockgenC0
drivers: clk: st: STiH407: Support for clockgenD0/D2/D3
drivers: clk: st: STiH407: Support for clockgenA9
drivers: clk: st: Update frequency tables for fs660c32 and fs432c65
drivers: clk: st: Use round to closest divider flag
.../bindings/clock/st/st,clkgen-divmux.txt | 28 +-
.../devicetree/bindings/clock/st/st,clkgen-mux.txt | 6 +-
.../devicetree/bindings/clock/st/st,clkgen-pll.txt | 17 +-
.../bindings/clock/st/st,clkgen-prediv.txt | 8 +-
.../devicetree/bindings/clock/st/st,clkgen-vcc.txt | 34 ++-
.../devicetree/bindings/clock/st/st,clkgen.txt | 59 ++--
.../devicetree/bindings/clock/st/st,flexgen.txt | 48 +++
.../devicetree/bindings/clock/st/st,quadfs.txt | 15 +-
drivers/clk/st/Makefile | 2 +-
drivers/clk/st/clk-flexgen.c | 332 +++++++++++++++++++++
drivers/clk/st/clkgen-fsyn.c | 211 +++++++++++--
drivers/clk/st/clkgen-mux.c | 12 +-
drivers/clk/st/clkgen-pll.c | 94 +++++-
13 files changed, 750 insertions(+), 116 deletions(-)
create mode 100644 Documentation/devicetree/bindings/clock/st/st,flexgen.txt
create mode 100644 drivers/clk/st/clk-flexgen.c
--
1.9.1
^ permalink raw reply [flat|nested] 49+ messages in thread
* [PATCH v2 01/14] clk: st: Update ST clock binding documentation
2014-06-27 13:24 ` Gabriel FERNANDEZ
@ 2014-06-27 13:24 ` Gabriel FERNANDEZ
-1 siblings, 0 replies; 49+ messages in thread
From: Gabriel FERNANDEZ @ 2014-06-27 13:24 UTC (permalink / raw)
To: mturquette, robh+dt, pawel.moll, mark.rutland, ijc+devicetree, galak
Cc: devicetree, linux-doc, linux-kernel, linux-arm-kernel, kernel,
Lee Jones, Gabriel Fernandez
This patch adds new compatibilities to support STiH407 SoC.
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org>
Acked-by: Peter Griffin <peter.griffin@linaro.org>
---
.../bindings/clock/st/st,clkgen-divmux.txt | 28 +++++------
.../devicetree/bindings/clock/st/st,clkgen-mux.txt | 6 +--
.../devicetree/bindings/clock/st/st,clkgen-pll.txt | 17 ++++---
.../bindings/clock/st/st,clkgen-prediv.txt | 8 ++--
.../devicetree/bindings/clock/st/st,clkgen-vcc.txt | 34 ++++++++------
.../devicetree/bindings/clock/st/st,clkgen.txt | 54 +++++++++++++---------
.../devicetree/bindings/clock/st/st,quadfs.txt | 15 +++---
7 files changed, 94 insertions(+), 68 deletions(-)
diff --git a/Documentation/devicetree/bindings/clock/st/st,clkgen-divmux.txt b/Documentation/devicetree/bindings/clock/st/st,clkgen-divmux.txt
index ae56315..6247652 100644
--- a/Documentation/devicetree/bindings/clock/st/st,clkgen-divmux.txt
+++ b/Documentation/devicetree/bindings/clock/st/st,clkgen-divmux.txt
@@ -24,26 +24,26 @@ Required properties:
Example:
- clockgenA@fd345000 {
+ clockgen-a@fd345000 {
reg = <0xfd345000 0xb50>;
- CLK_M_A1_DIV1: CLK_M_A1_DIV1 {
+ clk_m_a1_div1: clk-m-a1-div1 {
#clock-cells = <1>;
compatible = "st,clkgena-divmux-c32-odf1",
"st,clkgena-divmux";
- clocks = <&CLK_M_A1_OSC_PREDIV>,
- <&CLK_M_A1_PLL0 1>, /* PLL0 PHI1 */
- <&CLK_M_A1_PLL1 1>; /* PLL1 PHI1 */
-
- clock-output-names = "CLK_M_RX_ICN_TS",
- "CLK_M_RX_ICN_VDP_0",
- "", /* Unused */
- "CLK_M_PRV_T1_BUS",
- "CLK_M_ICN_REG_12",
- "CLK_M_ICN_REG_10",
- "", /* Unused */
- "CLK_M_ICN_ST231";
+ clocks = <&clk_m_a1_osc_prediv>,
+ <&clk_m_a1_pll0 1>, /* PLL0 PHI1 */
+ <&clk_m_a1_pll1 1>; /* PLL1 PHI1 */
+
+ clock-output-names = "clk-m-rx-icn-ts",
+ "clk-m-rx-icn-vdp-0",
+ "", /* unused */
+ "clk-m-prv-t1-bus",
+ "clk-m-icn-reg-12",
+ "clk-m-icn-reg-10",
+ "", /* unused */
+ "clk-m-icn-st231";
};
};
diff --git a/Documentation/devicetree/bindings/clock/st/st,clkgen-mux.txt b/Documentation/devicetree/bindings/clock/st/st,clkgen-mux.txt
index 943e080..f1fa91c 100644
--- a/Documentation/devicetree/bindings/clock/st/st,clkgen-mux.txt
+++ b/Documentation/devicetree/bindings/clock/st/st,clkgen-mux.txt
@@ -17,7 +17,7 @@ Required properties:
"st,stih416-clkgenf-vcc-sd", "st,clkgen-mux"
"st,stih415-clkgen-a9-mux", "st,clkgen-mux"
"st,stih416-clkgen-a9-mux", "st,clkgen-mux"
-
+ "st,stih407-clkgen-a9-mux", "st,clkgen-mux"
- #clock-cells : from common clock binding; shall be set to 0.
@@ -27,10 +27,10 @@ Required properties:
Example:
- CLK_M_HVA: CLK_M_HVA {
+ clk_m_hva: clk-m-hva@fd690868 {
#clock-cells = <0>;
compatible = "st,stih416-clkgenf-vcc-hva", "st,clkgen-mux";
reg = <0xfd690868 4>;
- clocks = <&CLOCKGEN_F 1>, <&CLK_M_A1_DIV0 3>;
+ clocks = <&clockgen_f 1>, <&clk_m_a1_div0 3>;
};
diff --git a/Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt b/Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt
index 81eb385..efb51cf 100644
--- a/Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt
+++ b/Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt
@@ -19,11 +19,14 @@ Required properties:
"st,stih415-plls-c32-ddr", "st,clkgen-plls-c32"
"st,stih416-plls-c32-a9", "st,clkgen-plls-c32"
"st,stih416-plls-c32-ddr", "st,clkgen-plls-c32"
+ "st,stih407-plls-c32-a0", "st,clkgen-plls-c32"
+ "st,stih407-plls-c32-a9", "st,clkgen-plls-c32"
+ "st,stih407-plls-c32-c0_0", "st,clkgen-plls-c32"
+ "st,stih407-plls-c32-c0_1", "st,clkgen-plls-c32"
"st,stih415-gpu-pll-c32", "st,clkgengpu-pll-c32"
"st,stih416-gpu-pll-c32", "st,clkgengpu-pll-c32"
-
- #clock-cells : From common clock binding; shall be set to 1.
- clocks : From common clock binding
@@ -32,17 +35,17 @@ Required properties:
Example:
- clockgenA@fee62000 {
+ clockgen-a@fee62000 {
reg = <0xfee62000 0xb48>;
- CLK_S_A0_PLL: CLK_S_A0_PLL {
+ clk_s_a0_pll: clk-s-a0-pll {
#clock-cells = <1>;
compatible = "st,clkgena-plls-c65";
- clocks = <&CLK_SYSIN>;
+ clocks = <&clk_sysin>;
- clock-output-names = "CLK_S_A0_PLL0_HS",
- "CLK_S_A0_PLL0_LS",
- "CLK_S_A0_PLL1";
+ clock-output-names = "clk-s-a0-pll0-hs",
+ "clk-s-a0-pll0-ls",
+ "clk-s-a0-pll1";
};
};
diff --git a/Documentation/devicetree/bindings/clock/st/st,clkgen-prediv.txt b/Documentation/devicetree/bindings/clock/st/st,clkgen-prediv.txt
index 566c9d7..604766c 100644
--- a/Documentation/devicetree/bindings/clock/st/st,clkgen-prediv.txt
+++ b/Documentation/devicetree/bindings/clock/st/st,clkgen-prediv.txt
@@ -20,17 +20,17 @@ Required properties:
Example:
- clockgenA@fd345000 {
+ clockgen-a@fd345000 {
reg = <0xfd345000 0xb50>;
- CLK_M_A2_OSC_PREDIV: CLK_M_A2_OSC_PREDIV {
+ clk_m_a2_osc_prediv: clk-m-a2-osc-prediv {
#clock-cells = <0>;
compatible = "st,clkgena-prediv-c32",
"st,clkgena-prediv";
- clocks = <&CLK_SYSIN>;
+ clocks = <&clk_sysin>;
- clock-output-names = "CLK_M_A2_OSC_PREDIV";
+ clock-output-names = "clk-m-a2-osc-prediv";
};
};
diff --git a/Documentation/devicetree/bindings/clock/st/st,clkgen-vcc.txt b/Documentation/devicetree/bindings/clock/st/st,clkgen-vcc.txt
index 4e3ff28..109b3ed 100644
--- a/Documentation/devicetree/bindings/clock/st/st,clkgen-vcc.txt
+++ b/Documentation/devicetree/bindings/clock/st/st,clkgen-vcc.txt
@@ -32,22 +32,30 @@ Required properties:
Example:
- CLOCKGEN_C_VCC: CLOCKGEN_C_VCC {
+ clockgen_c_vcc: clockgen-c-vcc@0xfe8308ac {
#clock-cells = <1>;
compatible = "st,stih416-clkgenc", "st,clkgen-vcc";
reg = <0xfe8308ac 12>;
- clocks = <&CLK_S_VCC_HD>, <&CLOCKGEN_C 1>,
- <&CLK_S_TMDS_FROMPHY>, <&CLOCKGEN_C 2>;
-
- clock-output-names =
- "CLK_S_PIX_HDMI", "CLK_S_PIX_DVO",
- "CLK_S_OUT_DVO", "CLK_S_PIX_HD",
- "CLK_S_HDDAC", "CLK_S_DENC",
- "CLK_S_SDDAC", "CLK_S_PIX_MAIN",
- "CLK_S_PIX_AUX", "CLK_S_STFE_FRC_0",
- "CLK_S_REF_MCRU", "CLK_S_SLAVE_MCRU",
- "CLK_S_TMDS_HDMI", "CLK_S_HDMI_REJECT_PLL",
- "CLK_S_THSENS";
+ clocks = <&clk_s_vcc_hd>,
+ <&clockgen_c 1>,
+ <&clk_s_tmds_fromphy>,
+ <&clockgen_c 2>;
+
+ clock-output-names = "clk-s-pix-hdmi",
+ "clk-s-pix-dvo",
+ "clk-s-out-dvo",
+ "clk-s-pix-hd",
+ "clk-s-hddac",
+ "clk-s-denc",
+ "clk-s-sddac",
+ "clk-s-pix-main",
+ "clk-s-pix-aux",
+ "clk-s-stfe-frc-0",
+ "clk-s-ref-mcru",
+ "clk-s-slave-mcru",
+ "clk-s-tmds-hdmi",
+ "clk-s-hdmi-reject-pll",
+ "clk-s-thsens";
};
diff --git a/Documentation/devicetree/bindings/clock/st/st,clkgen.txt b/Documentation/devicetree/bindings/clock/st/st,clkgen.txt
index 49ec5ae..427bad8 100644
--- a/Documentation/devicetree/bindings/clock/st/st,clkgen.txt
+++ b/Documentation/devicetree/bindings/clock/st/st,clkgen.txt
@@ -24,60 +24,72 @@ address is common of all subnode.
quadfs_node {
...
};
+
+ mux_node {
+ ...
+ };
+
+ vcc_node {
+ ...
+ };
...
};
This binding uses the common clock binding[1].
-Each subnode should use the binding discribe in [2]..[4]
+Each subnode should use the binding discribe in [2]..[7]
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
-[2] Documentation/devicetree/bindings/clock/st,quadfs.txt
-[3] Documentation/devicetree/bindings/clock/st,quadfs.txt
-[4] Documentation/devicetree/bindings/clock/st,quadfs.txt
+[2] Documentation/devicetree/bindings/clock/st,clkgen-divmux.txt
+[3] Documentation/devicetree/bindings/clock/st,clkgen-mux.txt
+[4] Documentation/devicetree/bindings/clock/st,clkgen-pll.txt
+[5] Documentation/devicetree/bindings/clock/st,clkgen-prediv.txt
+[6] Documentation/devicetree/bindings/clock/st,vcc.txt
+[7] Documentation/devicetree/bindings/clock/st,quadfs.txt
+
Required properties:
- reg : A Base address and length of the register set.
Example:
- clockgenA@fee62000 {
+ clockgen-a@fee62000 {
reg = <0xfee62000 0xb48>;
- CLK_S_A0_PLL: CLK_S_A0_PLL {
+ clk_s_a0_pll: clk-s-a0-pll {
#clock-cells = <1>;
compatible = "st,clkgena-plls-c65";
- clocks = <&CLK_SYSIN>;
+ clocks = <&clk-sysin>;
- clock-output-names = "CLK_S_A0_PLL0_HS",
- "CLK_S_A0_PLL0_LS",
- "CLK_S_A0_PLL1";
+ clock-output-names = "clk-s-a0-pll0-hs",
+ "clk-s-a0-pll0-ls",
+ "clk-s-a0-pll1";
};
- CLK_S_A0_OSC_PREDIV: CLK_S_A0_OSC_PREDIV {
+ clk_s_a0_osc_prediv: clk-s-a0-osc-prediv {
#clock-cells = <0>;
compatible = "st,clkgena-prediv-c65",
"st,clkgena-prediv";
- clocks = <&CLK_SYSIN>;
+ clocks = <&clk_sysin>;
- clock-output-names = "CLK_S_A0_OSC_PREDIV";
+ clock-output-names = "clk-s-a0-osc-prediv";
};
- CLK_S_A0_HS: CLK_S_A0_HS {
+ clk_s_a0_hs: clk-s-a0-hs {
#clock-cells = <1>;
compatible = "st,clkgena-divmux-c65-hs",
"st,clkgena-divmux";
- clocks = <&CLK_S_A0_OSC_PREDIV>,
- <&CLK_S_A0_PLL 0>, /* PLL0 HS */
- <&CLK_S_A0_PLL 2>; /* PLL1 */
+ clocks = <&clk-s_a0_osc_prediv>,
+ <&clk-s_a0_pll 0>, /* pll0 hs */
+ <&clk-s_a0_pll 2>; /* pll1 */
- clock-output-names = "CLK_S_FDMA_0",
- "CLK_S_FDMA_1",
- ""; /* CLK_S_JIT_SENSE */
- /* Fourth output unused */
+ clock-output-names = "clk-s-fdma-0",
+ "clk-s-fdma-1",
+ ""; /* clk-s-jit-sense */
+ /* fourth output unused */
};
};
diff --git a/Documentation/devicetree/bindings/clock/st/st,quadfs.txt b/Documentation/devicetree/bindings/clock/st/st,quadfs.txt
index ec86d62..cedeb9c 100644
--- a/Documentation/devicetree/bindings/clock/st/st,quadfs.txt
+++ b/Documentation/devicetree/bindings/clock/st/st,quadfs.txt
@@ -15,6 +15,9 @@ Required properties:
"st,stih416-quadfs432", "st,quadfs"
"st,stih416-quadfs660-E", "st,quadfs"
"st,stih416-quadfs660-F", "st,quadfs"
+ "st,stih407-quadfs660-C", "st,quadfs"
+ "st,stih407-quadfs660-D", "st,quadfs"
+
- #clock-cells : from common clock binding; shall be set to 1.
@@ -32,14 +35,14 @@ Required properties:
Example:
- CLOCKGEN_E: CLOCKGEN_E {
+ clockgen_e: clockgen-e@fd3208bc {
#clock-cells = <1>;
compatible = "st,stih416-quadfs660-E", "st,quadfs";
reg = <0xfd3208bc 0xB0>;
- clocks = <&CLK_SYSIN>;
- clock-output-names = "CLK_M_PIX_MDTP_0",
- "CLK_M_PIX_MDTP_1",
- "CLK_M_PIX_MDTP_2",
- "CLK_M_MPELPC";
+ clocks = <&clk_sysin>;
+ clock-output-names = "clk-m-pix-mdtp-0",
+ "clk-m-pix-mdtp-1",
+ "clk-m-pix-mdtp-2",
+ "clk-m-mpelpc";
};
--
1.9.1
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [PATCH v2 01/14] clk: st: Update ST clock binding documentation
@ 2014-06-27 13:24 ` Gabriel FERNANDEZ
0 siblings, 0 replies; 49+ messages in thread
From: Gabriel FERNANDEZ @ 2014-06-27 13:24 UTC (permalink / raw)
To: linux-arm-kernel
This patch adds new compatibilities to support STiH407 SoC.
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org>
Acked-by: Peter Griffin <peter.griffin@linaro.org>
---
.../bindings/clock/st/st,clkgen-divmux.txt | 28 +++++------
.../devicetree/bindings/clock/st/st,clkgen-mux.txt | 6 +--
.../devicetree/bindings/clock/st/st,clkgen-pll.txt | 17 ++++---
.../bindings/clock/st/st,clkgen-prediv.txt | 8 ++--
.../devicetree/bindings/clock/st/st,clkgen-vcc.txt | 34 ++++++++------
.../devicetree/bindings/clock/st/st,clkgen.txt | 54 +++++++++++++---------
.../devicetree/bindings/clock/st/st,quadfs.txt | 15 +++---
7 files changed, 94 insertions(+), 68 deletions(-)
diff --git a/Documentation/devicetree/bindings/clock/st/st,clkgen-divmux.txt b/Documentation/devicetree/bindings/clock/st/st,clkgen-divmux.txt
index ae56315..6247652 100644
--- a/Documentation/devicetree/bindings/clock/st/st,clkgen-divmux.txt
+++ b/Documentation/devicetree/bindings/clock/st/st,clkgen-divmux.txt
@@ -24,26 +24,26 @@ Required properties:
Example:
- clockgenA at fd345000 {
+ clockgen-a at fd345000 {
reg = <0xfd345000 0xb50>;
- CLK_M_A1_DIV1: CLK_M_A1_DIV1 {
+ clk_m_a1_div1: clk-m-a1-div1 {
#clock-cells = <1>;
compatible = "st,clkgena-divmux-c32-odf1",
"st,clkgena-divmux";
- clocks = <&CLK_M_A1_OSC_PREDIV>,
- <&CLK_M_A1_PLL0 1>, /* PLL0 PHI1 */
- <&CLK_M_A1_PLL1 1>; /* PLL1 PHI1 */
-
- clock-output-names = "CLK_M_RX_ICN_TS",
- "CLK_M_RX_ICN_VDP_0",
- "", /* Unused */
- "CLK_M_PRV_T1_BUS",
- "CLK_M_ICN_REG_12",
- "CLK_M_ICN_REG_10",
- "", /* Unused */
- "CLK_M_ICN_ST231";
+ clocks = <&clk_m_a1_osc_prediv>,
+ <&clk_m_a1_pll0 1>, /* PLL0 PHI1 */
+ <&clk_m_a1_pll1 1>; /* PLL1 PHI1 */
+
+ clock-output-names = "clk-m-rx-icn-ts",
+ "clk-m-rx-icn-vdp-0",
+ "", /* unused */
+ "clk-m-prv-t1-bus",
+ "clk-m-icn-reg-12",
+ "clk-m-icn-reg-10",
+ "", /* unused */
+ "clk-m-icn-st231";
};
};
diff --git a/Documentation/devicetree/bindings/clock/st/st,clkgen-mux.txt b/Documentation/devicetree/bindings/clock/st/st,clkgen-mux.txt
index 943e080..f1fa91c 100644
--- a/Documentation/devicetree/bindings/clock/st/st,clkgen-mux.txt
+++ b/Documentation/devicetree/bindings/clock/st/st,clkgen-mux.txt
@@ -17,7 +17,7 @@ Required properties:
"st,stih416-clkgenf-vcc-sd", "st,clkgen-mux"
"st,stih415-clkgen-a9-mux", "st,clkgen-mux"
"st,stih416-clkgen-a9-mux", "st,clkgen-mux"
-
+ "st,stih407-clkgen-a9-mux", "st,clkgen-mux"
- #clock-cells : from common clock binding; shall be set to 0.
@@ -27,10 +27,10 @@ Required properties:
Example:
- CLK_M_HVA: CLK_M_HVA {
+ clk_m_hva: clk-m-hva at fd690868 {
#clock-cells = <0>;
compatible = "st,stih416-clkgenf-vcc-hva", "st,clkgen-mux";
reg = <0xfd690868 4>;
- clocks = <&CLOCKGEN_F 1>, <&CLK_M_A1_DIV0 3>;
+ clocks = <&clockgen_f 1>, <&clk_m_a1_div0 3>;
};
diff --git a/Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt b/Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt
index 81eb385..efb51cf 100644
--- a/Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt
+++ b/Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt
@@ -19,11 +19,14 @@ Required properties:
"st,stih415-plls-c32-ddr", "st,clkgen-plls-c32"
"st,stih416-plls-c32-a9", "st,clkgen-plls-c32"
"st,stih416-plls-c32-ddr", "st,clkgen-plls-c32"
+ "st,stih407-plls-c32-a0", "st,clkgen-plls-c32"
+ "st,stih407-plls-c32-a9", "st,clkgen-plls-c32"
+ "st,stih407-plls-c32-c0_0", "st,clkgen-plls-c32"
+ "st,stih407-plls-c32-c0_1", "st,clkgen-plls-c32"
"st,stih415-gpu-pll-c32", "st,clkgengpu-pll-c32"
"st,stih416-gpu-pll-c32", "st,clkgengpu-pll-c32"
-
- #clock-cells : From common clock binding; shall be set to 1.
- clocks : From common clock binding
@@ -32,17 +35,17 @@ Required properties:
Example:
- clockgenA at fee62000 {
+ clockgen-a at fee62000 {
reg = <0xfee62000 0xb48>;
- CLK_S_A0_PLL: CLK_S_A0_PLL {
+ clk_s_a0_pll: clk-s-a0-pll {
#clock-cells = <1>;
compatible = "st,clkgena-plls-c65";
- clocks = <&CLK_SYSIN>;
+ clocks = <&clk_sysin>;
- clock-output-names = "CLK_S_A0_PLL0_HS",
- "CLK_S_A0_PLL0_LS",
- "CLK_S_A0_PLL1";
+ clock-output-names = "clk-s-a0-pll0-hs",
+ "clk-s-a0-pll0-ls",
+ "clk-s-a0-pll1";
};
};
diff --git a/Documentation/devicetree/bindings/clock/st/st,clkgen-prediv.txt b/Documentation/devicetree/bindings/clock/st/st,clkgen-prediv.txt
index 566c9d7..604766c 100644
--- a/Documentation/devicetree/bindings/clock/st/st,clkgen-prediv.txt
+++ b/Documentation/devicetree/bindings/clock/st/st,clkgen-prediv.txt
@@ -20,17 +20,17 @@ Required properties:
Example:
- clockgenA at fd345000 {
+ clockgen-a at fd345000 {
reg = <0xfd345000 0xb50>;
- CLK_M_A2_OSC_PREDIV: CLK_M_A2_OSC_PREDIV {
+ clk_m_a2_osc_prediv: clk-m-a2-osc-prediv {
#clock-cells = <0>;
compatible = "st,clkgena-prediv-c32",
"st,clkgena-prediv";
- clocks = <&CLK_SYSIN>;
+ clocks = <&clk_sysin>;
- clock-output-names = "CLK_M_A2_OSC_PREDIV";
+ clock-output-names = "clk-m-a2-osc-prediv";
};
};
diff --git a/Documentation/devicetree/bindings/clock/st/st,clkgen-vcc.txt b/Documentation/devicetree/bindings/clock/st/st,clkgen-vcc.txt
index 4e3ff28..109b3ed 100644
--- a/Documentation/devicetree/bindings/clock/st/st,clkgen-vcc.txt
+++ b/Documentation/devicetree/bindings/clock/st/st,clkgen-vcc.txt
@@ -32,22 +32,30 @@ Required properties:
Example:
- CLOCKGEN_C_VCC: CLOCKGEN_C_VCC {
+ clockgen_c_vcc: clockgen-c-vcc at 0xfe8308ac {
#clock-cells = <1>;
compatible = "st,stih416-clkgenc", "st,clkgen-vcc";
reg = <0xfe8308ac 12>;
- clocks = <&CLK_S_VCC_HD>, <&CLOCKGEN_C 1>,
- <&CLK_S_TMDS_FROMPHY>, <&CLOCKGEN_C 2>;
-
- clock-output-names =
- "CLK_S_PIX_HDMI", "CLK_S_PIX_DVO",
- "CLK_S_OUT_DVO", "CLK_S_PIX_HD",
- "CLK_S_HDDAC", "CLK_S_DENC",
- "CLK_S_SDDAC", "CLK_S_PIX_MAIN",
- "CLK_S_PIX_AUX", "CLK_S_STFE_FRC_0",
- "CLK_S_REF_MCRU", "CLK_S_SLAVE_MCRU",
- "CLK_S_TMDS_HDMI", "CLK_S_HDMI_REJECT_PLL",
- "CLK_S_THSENS";
+ clocks = <&clk_s_vcc_hd>,
+ <&clockgen_c 1>,
+ <&clk_s_tmds_fromphy>,
+ <&clockgen_c 2>;
+
+ clock-output-names = "clk-s-pix-hdmi",
+ "clk-s-pix-dvo",
+ "clk-s-out-dvo",
+ "clk-s-pix-hd",
+ "clk-s-hddac",
+ "clk-s-denc",
+ "clk-s-sddac",
+ "clk-s-pix-main",
+ "clk-s-pix-aux",
+ "clk-s-stfe-frc-0",
+ "clk-s-ref-mcru",
+ "clk-s-slave-mcru",
+ "clk-s-tmds-hdmi",
+ "clk-s-hdmi-reject-pll",
+ "clk-s-thsens";
};
diff --git a/Documentation/devicetree/bindings/clock/st/st,clkgen.txt b/Documentation/devicetree/bindings/clock/st/st,clkgen.txt
index 49ec5ae..427bad8 100644
--- a/Documentation/devicetree/bindings/clock/st/st,clkgen.txt
+++ b/Documentation/devicetree/bindings/clock/st/st,clkgen.txt
@@ -24,60 +24,72 @@ address is common of all subnode.
quadfs_node {
...
};
+
+ mux_node {
+ ...
+ };
+
+ vcc_node {
+ ...
+ };
...
};
This binding uses the common clock binding[1].
-Each subnode should use the binding discribe in [2]..[4]
+Each subnode should use the binding discribe in [2]..[7]
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
-[2] Documentation/devicetree/bindings/clock/st,quadfs.txt
-[3] Documentation/devicetree/bindings/clock/st,quadfs.txt
-[4] Documentation/devicetree/bindings/clock/st,quadfs.txt
+[2] Documentation/devicetree/bindings/clock/st,clkgen-divmux.txt
+[3] Documentation/devicetree/bindings/clock/st,clkgen-mux.txt
+[4] Documentation/devicetree/bindings/clock/st,clkgen-pll.txt
+[5] Documentation/devicetree/bindings/clock/st,clkgen-prediv.txt
+[6] Documentation/devicetree/bindings/clock/st,vcc.txt
+[7] Documentation/devicetree/bindings/clock/st,quadfs.txt
+
Required properties:
- reg : A Base address and length of the register set.
Example:
- clockgenA at fee62000 {
+ clockgen-a at fee62000 {
reg = <0xfee62000 0xb48>;
- CLK_S_A0_PLL: CLK_S_A0_PLL {
+ clk_s_a0_pll: clk-s-a0-pll {
#clock-cells = <1>;
compatible = "st,clkgena-plls-c65";
- clocks = <&CLK_SYSIN>;
+ clocks = <&clk-sysin>;
- clock-output-names = "CLK_S_A0_PLL0_HS",
- "CLK_S_A0_PLL0_LS",
- "CLK_S_A0_PLL1";
+ clock-output-names = "clk-s-a0-pll0-hs",
+ "clk-s-a0-pll0-ls",
+ "clk-s-a0-pll1";
};
- CLK_S_A0_OSC_PREDIV: CLK_S_A0_OSC_PREDIV {
+ clk_s_a0_osc_prediv: clk-s-a0-osc-prediv {
#clock-cells = <0>;
compatible = "st,clkgena-prediv-c65",
"st,clkgena-prediv";
- clocks = <&CLK_SYSIN>;
+ clocks = <&clk_sysin>;
- clock-output-names = "CLK_S_A0_OSC_PREDIV";
+ clock-output-names = "clk-s-a0-osc-prediv";
};
- CLK_S_A0_HS: CLK_S_A0_HS {
+ clk_s_a0_hs: clk-s-a0-hs {
#clock-cells = <1>;
compatible = "st,clkgena-divmux-c65-hs",
"st,clkgena-divmux";
- clocks = <&CLK_S_A0_OSC_PREDIV>,
- <&CLK_S_A0_PLL 0>, /* PLL0 HS */
- <&CLK_S_A0_PLL 2>; /* PLL1 */
+ clocks = <&clk-s_a0_osc_prediv>,
+ <&clk-s_a0_pll 0>, /* pll0 hs */
+ <&clk-s_a0_pll 2>; /* pll1 */
- clock-output-names = "CLK_S_FDMA_0",
- "CLK_S_FDMA_1",
- ""; /* CLK_S_JIT_SENSE */
- /* Fourth output unused */
+ clock-output-names = "clk-s-fdma-0",
+ "clk-s-fdma-1",
+ ""; /* clk-s-jit-sense */
+ /* fourth output unused */
};
};
diff --git a/Documentation/devicetree/bindings/clock/st/st,quadfs.txt b/Documentation/devicetree/bindings/clock/st/st,quadfs.txt
index ec86d62..cedeb9c 100644
--- a/Documentation/devicetree/bindings/clock/st/st,quadfs.txt
+++ b/Documentation/devicetree/bindings/clock/st/st,quadfs.txt
@@ -15,6 +15,9 @@ Required properties:
"st,stih416-quadfs432", "st,quadfs"
"st,stih416-quadfs660-E", "st,quadfs"
"st,stih416-quadfs660-F", "st,quadfs"
+ "st,stih407-quadfs660-C", "st,quadfs"
+ "st,stih407-quadfs660-D", "st,quadfs"
+
- #clock-cells : from common clock binding; shall be set to 1.
@@ -32,14 +35,14 @@ Required properties:
Example:
- CLOCKGEN_E: CLOCKGEN_E {
+ clockgen_e: clockgen-e at fd3208bc {
#clock-cells = <1>;
compatible = "st,stih416-quadfs660-E", "st,quadfs";
reg = <0xfd3208bc 0xB0>;
- clocks = <&CLK_SYSIN>;
- clock-output-names = "CLK_M_PIX_MDTP_0",
- "CLK_M_PIX_MDTP_1",
- "CLK_M_PIX_MDTP_2",
- "CLK_M_MPELPC";
+ clocks = <&clk_sysin>;
+ clock-output-names = "clk-m-pix-mdtp-0",
+ "clk-m-pix-mdtp-1",
+ "clk-m-pix-mdtp-2",
+ "clk-m-mpelpc";
};
--
1.9.1
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [PATCH v2 02/14] drivers: clk: st: use static const for stm_fs tables
2014-06-27 13:24 ` Gabriel FERNANDEZ
@ 2014-06-27 13:24 ` Gabriel FERNANDEZ
-1 siblings, 0 replies; 49+ messages in thread
From: Gabriel FERNANDEZ @ 2014-06-27 13:24 UTC (permalink / raw)
To: mturquette, robh+dt, pawel.moll, mark.rutland, ijc+devicetree, galak
Cc: devicetree, linux-doc, linux-kernel, linux-arm-kernel, kernel,
Lee Jones, Gabriel Fernandez
converts stm_fs tables into static const
---
drivers/clk/st/clkgen-fsyn.c | 34 +++++++++++++++++-----------------
1 file changed, 17 insertions(+), 17 deletions(-)
diff --git a/drivers/clk/st/clkgen-fsyn.c b/drivers/clk/st/clkgen-fsyn.c
index 4f53ee0..a7e5db4 100644
--- a/drivers/clk/st/clkgen-fsyn.c
+++ b/drivers/clk/st/clkgen-fsyn.c
@@ -41,7 +41,7 @@ struct stm_fs {
unsigned long nsdiv;
};
-static struct stm_fs fs216c65_rtbl[] = {
+static const struct stm_fs fs216c65_rtbl[] = {
{ .mdiv = 0x1f, .pe = 0x0, .sdiv = 0x7, .nsdiv = 0 }, /* 312.5 Khz */
{ .mdiv = 0x17, .pe = 0x25ed, .sdiv = 0x1, .nsdiv = 0 }, /* 27 MHz */
{ .mdiv = 0x1a, .pe = 0x7b36, .sdiv = 0x2, .nsdiv = 1 }, /* 36.87 MHz */
@@ -49,13 +49,13 @@ static struct stm_fs fs216c65_rtbl[] = {
{ .mdiv = 0x11, .pe = 0x1c72, .sdiv = 0x1, .nsdiv = 1 }, /* 108 MHz */
};
-static struct stm_fs fs432c65_rtbl[] = {
+static const struct stm_fs fs432c65_rtbl[] = {
{ .mdiv = 0x1f, .pe = 0x0, .sdiv = 0x7, .nsdiv = 0 }, /* 625 Khz */
{ .mdiv = 0x11, .pe = 0x1c72, .sdiv = 0x2, .nsdiv = 1 }, /* 108 MHz */
{ .mdiv = 0x19, .pe = 0x121a, .sdiv = 0x0, .nsdiv = 1 }, /* 297 MHz */
};
-static struct stm_fs fs660c32_rtbl[] = {
+static const struct stm_fs fs660c32_rtbl[] = {
{ .mdiv = 0x01, .pe = 0x2aaa, .sdiv = 0x8, .nsdiv = 0 }, /* 600 KHz */
{ .mdiv = 0x02, .pe = 0x3d33, .sdiv = 0x0, .nsdiv = 0 }, /* 148.5 Mhz */
{ .mdiv = 0x13, .pe = 0x5bcc, .sdiv = 0x0, .nsdiv = 1 }, /* 297 Mhz */
@@ -82,9 +82,9 @@ struct clkgen_quadfs_data {
struct clkgen_field nsdiv[QUADFS_MAX_CHAN];
const struct clk_ops *pll_ops;
- struct stm_fs *rtbl;
+ const struct stm_fs *rtbl;
u8 rtbl_cnt;
- int (*get_rate)(unsigned long , struct stm_fs *,
+ int (*get_rate)(unsigned long , const struct stm_fs *,
unsigned long *);
};
@@ -94,11 +94,11 @@ static const struct clk_ops st_quadfs_fs216c65_ops;
static const struct clk_ops st_quadfs_fs432c65_ops;
static const struct clk_ops st_quadfs_fs660c32_ops;
-static int clk_fs216c65_get_rate(unsigned long, struct stm_fs *,
+static int clk_fs216c65_get_rate(unsigned long, const struct stm_fs *,
unsigned long *);
-static int clk_fs432c65_get_rate(unsigned long, struct stm_fs *,
+static int clk_fs432c65_get_rate(unsigned long, const struct stm_fs *,
unsigned long *);
-static int clk_fs660c32_dig_get_rate(unsigned long, struct stm_fs *,
+static int clk_fs660c32_dig_get_rate(unsigned long, const struct stm_fs *,
unsigned long *);
/*
* Values for all of the standalone instances of this clock
@@ -106,7 +106,7 @@ static int clk_fs660c32_dig_get_rate(unsigned long, struct stm_fs *,
* that the individual channel standby control bits (nsb) are in the
* first register along with the PLL control bits.
*/
-static struct clkgen_quadfs_data st_fs216c65_416 = {
+static const struct clkgen_quadfs_data st_fs216c65_416 = {
/* 416 specific */
.npda = CLKGEN_FIELD(0x0, 0x1, 14),
.nsb = { CLKGEN_FIELD(0x0, 0x1, 10),
@@ -143,7 +143,7 @@ static struct clkgen_quadfs_data st_fs216c65_416 = {
.get_rate = clk_fs216c65_get_rate,
};
-static struct clkgen_quadfs_data st_fs432c65_416 = {
+static const struct clkgen_quadfs_data st_fs432c65_416 = {
.npda = CLKGEN_FIELD(0x0, 0x1, 14),
.nsb = { CLKGEN_FIELD(0x0, 0x1, 10),
CLKGEN_FIELD(0x0, 0x1, 11),
@@ -179,7 +179,7 @@ static struct clkgen_quadfs_data st_fs432c65_416 = {
.get_rate = clk_fs432c65_get_rate,
};
-static struct clkgen_quadfs_data st_fs660c32_E_416 = {
+static const struct clkgen_quadfs_data st_fs660c32_E_416 = {
.npda = CLKGEN_FIELD(0x0, 0x1, 14),
.nsb = { CLKGEN_FIELD(0x0, 0x1, 10),
CLKGEN_FIELD(0x0, 0x1, 11),
@@ -215,7 +215,7 @@ static struct clkgen_quadfs_data st_fs660c32_E_416 = {
.get_rate = clk_fs660c32_dig_get_rate,
};
-static struct clkgen_quadfs_data st_fs660c32_F_416 = {
+static const struct clkgen_quadfs_data st_fs660c32_F_416 = {
.npda = CLKGEN_FIELD(0x0, 0x1, 14),
.nsb = { CLKGEN_FIELD(0x0, 0x1, 10),
CLKGEN_FIELD(0x0, 0x1, 11),
@@ -650,7 +650,7 @@ static int quadfs_fsynth_is_enabled(struct clk_hw *hw)
#define P15 (uint64_t)(1 << 15)
-static int clk_fs216c65_get_rate(unsigned long input, struct stm_fs *fs,
+static int clk_fs216c65_get_rate(unsigned long input, const struct stm_fs *fs,
unsigned long *rate)
{
uint64_t res;
@@ -670,7 +670,7 @@ static int clk_fs216c65_get_rate(unsigned long input, struct stm_fs *fs,
return 0;
}
-static int clk_fs432c65_get_rate(unsigned long input, struct stm_fs *fs,
+static int clk_fs432c65_get_rate(unsigned long input, const struct stm_fs *fs,
unsigned long *rate)
{
uint64_t res;
@@ -693,7 +693,7 @@ static int clk_fs432c65_get_rate(unsigned long input, struct stm_fs *fs,
#define P20 (uint64_t)(1 << 20)
static int clk_fs660c32_dig_get_rate(unsigned long input,
- struct stm_fs *fs, unsigned long *rate)
+ const struct stm_fs *fs, unsigned long *rate)
{
unsigned long s = (1 << fs->sdiv);
unsigned long ns;
@@ -749,7 +749,7 @@ static long quadfs_find_best_rate(struct clk_hw *hw, unsigned long drate,
{
struct st_clk_quadfs_fsynth *fs = to_quadfs_fsynth(hw);
int (*clk_fs_get_rate)(unsigned long ,
- struct stm_fs *, unsigned long *);
+ const struct stm_fs *, unsigned long *);
struct stm_fs prev_params;
unsigned long prev_rate, rate = 0;
unsigned long diff_rate, prev_diff_rate = ~0;
@@ -793,7 +793,7 @@ static unsigned long quadfs_recalc_rate(struct clk_hw *hw,
unsigned long rate = 0;
struct stm_fs params;
int (*clk_fs_get_rate)(unsigned long ,
- struct stm_fs *, unsigned long *);
+ const struct stm_fs *, unsigned long *);
clk_fs_get_rate = fs->data->get_rate;
--
1.9.1
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [PATCH v2 02/14] drivers: clk: st: use static const for stm_fs tables
@ 2014-06-27 13:24 ` Gabriel FERNANDEZ
0 siblings, 0 replies; 49+ messages in thread
From: Gabriel FERNANDEZ @ 2014-06-27 13:24 UTC (permalink / raw)
To: linux-arm-kernel
converts stm_fs tables into static const
---
drivers/clk/st/clkgen-fsyn.c | 34 +++++++++++++++++-----------------
1 file changed, 17 insertions(+), 17 deletions(-)
diff --git a/drivers/clk/st/clkgen-fsyn.c b/drivers/clk/st/clkgen-fsyn.c
index 4f53ee0..a7e5db4 100644
--- a/drivers/clk/st/clkgen-fsyn.c
+++ b/drivers/clk/st/clkgen-fsyn.c
@@ -41,7 +41,7 @@ struct stm_fs {
unsigned long nsdiv;
};
-static struct stm_fs fs216c65_rtbl[] = {
+static const struct stm_fs fs216c65_rtbl[] = {
{ .mdiv = 0x1f, .pe = 0x0, .sdiv = 0x7, .nsdiv = 0 }, /* 312.5 Khz */
{ .mdiv = 0x17, .pe = 0x25ed, .sdiv = 0x1, .nsdiv = 0 }, /* 27 MHz */
{ .mdiv = 0x1a, .pe = 0x7b36, .sdiv = 0x2, .nsdiv = 1 }, /* 36.87 MHz */
@@ -49,13 +49,13 @@ static struct stm_fs fs216c65_rtbl[] = {
{ .mdiv = 0x11, .pe = 0x1c72, .sdiv = 0x1, .nsdiv = 1 }, /* 108 MHz */
};
-static struct stm_fs fs432c65_rtbl[] = {
+static const struct stm_fs fs432c65_rtbl[] = {
{ .mdiv = 0x1f, .pe = 0x0, .sdiv = 0x7, .nsdiv = 0 }, /* 625 Khz */
{ .mdiv = 0x11, .pe = 0x1c72, .sdiv = 0x2, .nsdiv = 1 }, /* 108 MHz */
{ .mdiv = 0x19, .pe = 0x121a, .sdiv = 0x0, .nsdiv = 1 }, /* 297 MHz */
};
-static struct stm_fs fs660c32_rtbl[] = {
+static const struct stm_fs fs660c32_rtbl[] = {
{ .mdiv = 0x01, .pe = 0x2aaa, .sdiv = 0x8, .nsdiv = 0 }, /* 600 KHz */
{ .mdiv = 0x02, .pe = 0x3d33, .sdiv = 0x0, .nsdiv = 0 }, /* 148.5 Mhz */
{ .mdiv = 0x13, .pe = 0x5bcc, .sdiv = 0x0, .nsdiv = 1 }, /* 297 Mhz */
@@ -82,9 +82,9 @@ struct clkgen_quadfs_data {
struct clkgen_field nsdiv[QUADFS_MAX_CHAN];
const struct clk_ops *pll_ops;
- struct stm_fs *rtbl;
+ const struct stm_fs *rtbl;
u8 rtbl_cnt;
- int (*get_rate)(unsigned long , struct stm_fs *,
+ int (*get_rate)(unsigned long , const struct stm_fs *,
unsigned long *);
};
@@ -94,11 +94,11 @@ static const struct clk_ops st_quadfs_fs216c65_ops;
static const struct clk_ops st_quadfs_fs432c65_ops;
static const struct clk_ops st_quadfs_fs660c32_ops;
-static int clk_fs216c65_get_rate(unsigned long, struct stm_fs *,
+static int clk_fs216c65_get_rate(unsigned long, const struct stm_fs *,
unsigned long *);
-static int clk_fs432c65_get_rate(unsigned long, struct stm_fs *,
+static int clk_fs432c65_get_rate(unsigned long, const struct stm_fs *,
unsigned long *);
-static int clk_fs660c32_dig_get_rate(unsigned long, struct stm_fs *,
+static int clk_fs660c32_dig_get_rate(unsigned long, const struct stm_fs *,
unsigned long *);
/*
* Values for all of the standalone instances of this clock
@@ -106,7 +106,7 @@ static int clk_fs660c32_dig_get_rate(unsigned long, struct stm_fs *,
* that the individual channel standby control bits (nsb) are in the
* first register along with the PLL control bits.
*/
-static struct clkgen_quadfs_data st_fs216c65_416 = {
+static const struct clkgen_quadfs_data st_fs216c65_416 = {
/* 416 specific */
.npda = CLKGEN_FIELD(0x0, 0x1, 14),
.nsb = { CLKGEN_FIELD(0x0, 0x1, 10),
@@ -143,7 +143,7 @@ static struct clkgen_quadfs_data st_fs216c65_416 = {
.get_rate = clk_fs216c65_get_rate,
};
-static struct clkgen_quadfs_data st_fs432c65_416 = {
+static const struct clkgen_quadfs_data st_fs432c65_416 = {
.npda = CLKGEN_FIELD(0x0, 0x1, 14),
.nsb = { CLKGEN_FIELD(0x0, 0x1, 10),
CLKGEN_FIELD(0x0, 0x1, 11),
@@ -179,7 +179,7 @@ static struct clkgen_quadfs_data st_fs432c65_416 = {
.get_rate = clk_fs432c65_get_rate,
};
-static struct clkgen_quadfs_data st_fs660c32_E_416 = {
+static const struct clkgen_quadfs_data st_fs660c32_E_416 = {
.npda = CLKGEN_FIELD(0x0, 0x1, 14),
.nsb = { CLKGEN_FIELD(0x0, 0x1, 10),
CLKGEN_FIELD(0x0, 0x1, 11),
@@ -215,7 +215,7 @@ static struct clkgen_quadfs_data st_fs660c32_E_416 = {
.get_rate = clk_fs660c32_dig_get_rate,
};
-static struct clkgen_quadfs_data st_fs660c32_F_416 = {
+static const struct clkgen_quadfs_data st_fs660c32_F_416 = {
.npda = CLKGEN_FIELD(0x0, 0x1, 14),
.nsb = { CLKGEN_FIELD(0x0, 0x1, 10),
CLKGEN_FIELD(0x0, 0x1, 11),
@@ -650,7 +650,7 @@ static int quadfs_fsynth_is_enabled(struct clk_hw *hw)
#define P15 (uint64_t)(1 << 15)
-static int clk_fs216c65_get_rate(unsigned long input, struct stm_fs *fs,
+static int clk_fs216c65_get_rate(unsigned long input, const struct stm_fs *fs,
unsigned long *rate)
{
uint64_t res;
@@ -670,7 +670,7 @@ static int clk_fs216c65_get_rate(unsigned long input, struct stm_fs *fs,
return 0;
}
-static int clk_fs432c65_get_rate(unsigned long input, struct stm_fs *fs,
+static int clk_fs432c65_get_rate(unsigned long input, const struct stm_fs *fs,
unsigned long *rate)
{
uint64_t res;
@@ -693,7 +693,7 @@ static int clk_fs432c65_get_rate(unsigned long input, struct stm_fs *fs,
#define P20 (uint64_t)(1 << 20)
static int clk_fs660c32_dig_get_rate(unsigned long input,
- struct stm_fs *fs, unsigned long *rate)
+ const struct stm_fs *fs, unsigned long *rate)
{
unsigned long s = (1 << fs->sdiv);
unsigned long ns;
@@ -749,7 +749,7 @@ static long quadfs_find_best_rate(struct clk_hw *hw, unsigned long drate,
{
struct st_clk_quadfs_fsynth *fs = to_quadfs_fsynth(hw);
int (*clk_fs_get_rate)(unsigned long ,
- struct stm_fs *, unsigned long *);
+ const struct stm_fs *, unsigned long *);
struct stm_fs prev_params;
unsigned long prev_rate, rate = 0;
unsigned long diff_rate, prev_diff_rate = ~0;
@@ -793,7 +793,7 @@ static unsigned long quadfs_recalc_rate(struct clk_hw *hw,
unsigned long rate = 0;
struct stm_fs params;
int (*clk_fs_get_rate)(unsigned long ,
- struct stm_fs *, unsigned long *);
+ const struct stm_fs *, unsigned long *);
clk_fs_get_rate = fs->data->get_rate;
--
1.9.1
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [PATCH v2 03/14] drivers: clk: st: use static const for clkgen_pll_data tables
2014-06-27 13:24 ` Gabriel FERNANDEZ
@ 2014-06-27 13:25 ` Gabriel FERNANDEZ
-1 siblings, 0 replies; 49+ messages in thread
From: Gabriel FERNANDEZ @ 2014-06-27 13:25 UTC (permalink / raw)
To: mturquette, robh+dt, pawel.moll, mark.rutland, ijc+devicetree, galak
Cc: devicetree, linux-doc, linux-kernel, linux-arm-kernel, kernel,
Lee Jones, Gabriel Fernandez
converts clkgen_pll_data tables into static const
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org>
---
drivers/clk/st/clkgen-pll.c | 30 ++++++++++++++----------------
1 file changed, 14 insertions(+), 16 deletions(-)
diff --git a/drivers/clk/st/clkgen-pll.c b/drivers/clk/st/clkgen-pll.c
index d8b9b1a..cdf23db 100644
--- a/drivers/clk/st/clkgen-pll.c
+++ b/drivers/clk/st/clkgen-pll.c
@@ -59,7 +59,7 @@ static const struct clk_ops st_pll800c65_ops;
static const struct clk_ops stm_pll3200c32_ops;
static const struct clk_ops st_pll1200c32_ops;
-static struct clkgen_pll_data st_pll1600c65_ax = {
+static const struct clkgen_pll_data st_pll1600c65_ax = {
.pdn_status = CLKGEN_FIELD(0x0, 0x1, 19),
.locked_status = CLKGEN_FIELD(0x0, 0x1, 31),
.mdiv = CLKGEN_FIELD(0x0, C65_MDIV_PLL1600_MASK, 0),
@@ -67,7 +67,7 @@ static struct clkgen_pll_data st_pll1600c65_ax = {
.ops = &st_pll1600c65_ops
};
-static struct clkgen_pll_data st_pll800c65_ax = {
+static const struct clkgen_pll_data st_pll800c65_ax = {
.pdn_status = CLKGEN_FIELD(0x0, 0x1, 19),
.locked_status = CLKGEN_FIELD(0x0, 0x1, 31),
.mdiv = CLKGEN_FIELD(0x0, C65_MDIV_PLL800_MASK, 0),
@@ -76,7 +76,7 @@ static struct clkgen_pll_data st_pll800c65_ax = {
.ops = &st_pll800c65_ops
};
-static struct clkgen_pll_data st_pll3200c32_a1x_0 = {
+static const struct clkgen_pll_data st_pll3200c32_a1x_0 = {
.pdn_status = CLKGEN_FIELD(0x0, 0x1, 31),
.locked_status = CLKGEN_FIELD(0x4, 0x1, 31),
.ndiv = CLKGEN_FIELD(0x0, C32_NDIV_MASK, 0x0),
@@ -93,7 +93,7 @@ static struct clkgen_pll_data st_pll3200c32_a1x_0 = {
.ops = &stm_pll3200c32_ops,
};
-static struct clkgen_pll_data st_pll3200c32_a1x_1 = {
+static const struct clkgen_pll_data st_pll3200c32_a1x_1 = {
.pdn_status = CLKGEN_FIELD(0xC, 0x1, 31),
.locked_status = CLKGEN_FIELD(0x10, 0x1, 31),
.ndiv = CLKGEN_FIELD(0xC, C32_NDIV_MASK, 0x0),
@@ -111,7 +111,7 @@ static struct clkgen_pll_data st_pll3200c32_a1x_1 = {
};
/* 415 specific */
-static struct clkgen_pll_data st_pll3200c32_a9_415 = {
+static const struct clkgen_pll_data st_pll3200c32_a9_415 = {
.pdn_status = CLKGEN_FIELD(0x0, 0x1, 0),
.locked_status = CLKGEN_FIELD(0x6C, 0x1, 0),
.ndiv = CLKGEN_FIELD(0x0, C32_NDIV_MASK, 9),
@@ -122,7 +122,7 @@ static struct clkgen_pll_data st_pll3200c32_a9_415 = {
.ops = &stm_pll3200c32_ops,
};
-static struct clkgen_pll_data st_pll3200c32_ddr_415 = {
+static const struct clkgen_pll_data st_pll3200c32_ddr_415 = {
.pdn_status = CLKGEN_FIELD(0x0, 0x1, 0),
.locked_status = CLKGEN_FIELD(0x100, 0x1, 0),
.ndiv = CLKGEN_FIELD(0x8, C32_NDIV_MASK, 0),
@@ -135,7 +135,7 @@ static struct clkgen_pll_data st_pll3200c32_ddr_415 = {
.ops = &stm_pll3200c32_ops,
};
-static struct clkgen_pll_data st_pll1200c32_gpu_415 = {
+static const struct clkgen_pll_data st_pll1200c32_gpu_415 = {
.pdn_status = CLKGEN_FIELD(0x144, 0x1, 3),
.locked_status = CLKGEN_FIELD(0x168, 0x1, 0),
.ldf = CLKGEN_FIELD(0x0, C32_LDF_MASK, 3),
@@ -146,7 +146,7 @@ static struct clkgen_pll_data st_pll1200c32_gpu_415 = {
};
/* 416 specific */
-static struct clkgen_pll_data st_pll3200c32_a9_416 = {
+static const struct clkgen_pll_data st_pll3200c32_a9_416 = {
.pdn_status = CLKGEN_FIELD(0x0, 0x1, 0),
.locked_status = CLKGEN_FIELD(0x6C, 0x1, 0),
.ndiv = CLKGEN_FIELD(0x8, C32_NDIV_MASK, 0),
@@ -157,7 +157,7 @@ static struct clkgen_pll_data st_pll3200c32_a9_416 = {
.ops = &stm_pll3200c32_ops,
};
-static struct clkgen_pll_data st_pll3200c32_ddr_416 = {
+static const struct clkgen_pll_data st_pll3200c32_ddr_416 = {
.pdn_status = CLKGEN_FIELD(0x0, 0x1, 0),
.locked_status = CLKGEN_FIELD(0x10C, 0x1, 0),
.ndiv = CLKGEN_FIELD(0x8, C32_NDIV_MASK, 0),
@@ -170,7 +170,7 @@ static struct clkgen_pll_data st_pll3200c32_ddr_416 = {
.ops = &stm_pll3200c32_ops,
};
-static struct clkgen_pll_data st_pll1200c32_gpu_416 = {
+static const struct clkgen_pll_data st_pll1200c32_gpu_416 = {
.pdn_status = CLKGEN_FIELD(0x8E4, 0x1, 3),
.locked_status = CLKGEN_FIELD(0x90C, 0x1, 0),
.ldf = CLKGEN_FIELD(0x0, C32_LDF_MASK, 3),
@@ -450,9 +450,8 @@ static void __init clkgena_c65_pll_setup(struct device_node *np)
* PLL0 HS (high speed) output
*/
clk_data->clks[0] = clkgen_pll_register(parent_name,
- &st_pll1600c65_ax,
- reg + CLKGENAx_PLL0_OFFSET,
- clk_name);
+ (struct clkgen_pll_data *) &st_pll1600c65_ax,
+ reg + CLKGENAx_PLL0_OFFSET, clk_name);
if (IS_ERR(clk_data->clks[0]))
goto err;
@@ -480,9 +479,8 @@ static void __init clkgena_c65_pll_setup(struct device_node *np)
* PLL1 output
*/
clk_data->clks[2] = clkgen_pll_register(parent_name,
- &st_pll800c65_ax,
- reg + CLKGENAx_PLL1_OFFSET,
- clk_name);
+ (struct clkgen_pll_data *) &st_pll800c65_ax,
+ reg + CLKGENAx_PLL1_OFFSET, clk_name);
if (IS_ERR(clk_data->clks[2]))
goto err;
--
1.9.1
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [PATCH v2 03/14] drivers: clk: st: use static const for clkgen_pll_data tables
@ 2014-06-27 13:25 ` Gabriel FERNANDEZ
0 siblings, 0 replies; 49+ messages in thread
From: Gabriel FERNANDEZ @ 2014-06-27 13:25 UTC (permalink / raw)
To: linux-arm-kernel
converts clkgen_pll_data tables into static const
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org>
---
drivers/clk/st/clkgen-pll.c | 30 ++++++++++++++----------------
1 file changed, 14 insertions(+), 16 deletions(-)
diff --git a/drivers/clk/st/clkgen-pll.c b/drivers/clk/st/clkgen-pll.c
index d8b9b1a..cdf23db 100644
--- a/drivers/clk/st/clkgen-pll.c
+++ b/drivers/clk/st/clkgen-pll.c
@@ -59,7 +59,7 @@ static const struct clk_ops st_pll800c65_ops;
static const struct clk_ops stm_pll3200c32_ops;
static const struct clk_ops st_pll1200c32_ops;
-static struct clkgen_pll_data st_pll1600c65_ax = {
+static const struct clkgen_pll_data st_pll1600c65_ax = {
.pdn_status = CLKGEN_FIELD(0x0, 0x1, 19),
.locked_status = CLKGEN_FIELD(0x0, 0x1, 31),
.mdiv = CLKGEN_FIELD(0x0, C65_MDIV_PLL1600_MASK, 0),
@@ -67,7 +67,7 @@ static struct clkgen_pll_data st_pll1600c65_ax = {
.ops = &st_pll1600c65_ops
};
-static struct clkgen_pll_data st_pll800c65_ax = {
+static const struct clkgen_pll_data st_pll800c65_ax = {
.pdn_status = CLKGEN_FIELD(0x0, 0x1, 19),
.locked_status = CLKGEN_FIELD(0x0, 0x1, 31),
.mdiv = CLKGEN_FIELD(0x0, C65_MDIV_PLL800_MASK, 0),
@@ -76,7 +76,7 @@ static struct clkgen_pll_data st_pll800c65_ax = {
.ops = &st_pll800c65_ops
};
-static struct clkgen_pll_data st_pll3200c32_a1x_0 = {
+static const struct clkgen_pll_data st_pll3200c32_a1x_0 = {
.pdn_status = CLKGEN_FIELD(0x0, 0x1, 31),
.locked_status = CLKGEN_FIELD(0x4, 0x1, 31),
.ndiv = CLKGEN_FIELD(0x0, C32_NDIV_MASK, 0x0),
@@ -93,7 +93,7 @@ static struct clkgen_pll_data st_pll3200c32_a1x_0 = {
.ops = &stm_pll3200c32_ops,
};
-static struct clkgen_pll_data st_pll3200c32_a1x_1 = {
+static const struct clkgen_pll_data st_pll3200c32_a1x_1 = {
.pdn_status = CLKGEN_FIELD(0xC, 0x1, 31),
.locked_status = CLKGEN_FIELD(0x10, 0x1, 31),
.ndiv = CLKGEN_FIELD(0xC, C32_NDIV_MASK, 0x0),
@@ -111,7 +111,7 @@ static struct clkgen_pll_data st_pll3200c32_a1x_1 = {
};
/* 415 specific */
-static struct clkgen_pll_data st_pll3200c32_a9_415 = {
+static const struct clkgen_pll_data st_pll3200c32_a9_415 = {
.pdn_status = CLKGEN_FIELD(0x0, 0x1, 0),
.locked_status = CLKGEN_FIELD(0x6C, 0x1, 0),
.ndiv = CLKGEN_FIELD(0x0, C32_NDIV_MASK, 9),
@@ -122,7 +122,7 @@ static struct clkgen_pll_data st_pll3200c32_a9_415 = {
.ops = &stm_pll3200c32_ops,
};
-static struct clkgen_pll_data st_pll3200c32_ddr_415 = {
+static const struct clkgen_pll_data st_pll3200c32_ddr_415 = {
.pdn_status = CLKGEN_FIELD(0x0, 0x1, 0),
.locked_status = CLKGEN_FIELD(0x100, 0x1, 0),
.ndiv = CLKGEN_FIELD(0x8, C32_NDIV_MASK, 0),
@@ -135,7 +135,7 @@ static struct clkgen_pll_data st_pll3200c32_ddr_415 = {
.ops = &stm_pll3200c32_ops,
};
-static struct clkgen_pll_data st_pll1200c32_gpu_415 = {
+static const struct clkgen_pll_data st_pll1200c32_gpu_415 = {
.pdn_status = CLKGEN_FIELD(0x144, 0x1, 3),
.locked_status = CLKGEN_FIELD(0x168, 0x1, 0),
.ldf = CLKGEN_FIELD(0x0, C32_LDF_MASK, 3),
@@ -146,7 +146,7 @@ static struct clkgen_pll_data st_pll1200c32_gpu_415 = {
};
/* 416 specific */
-static struct clkgen_pll_data st_pll3200c32_a9_416 = {
+static const struct clkgen_pll_data st_pll3200c32_a9_416 = {
.pdn_status = CLKGEN_FIELD(0x0, 0x1, 0),
.locked_status = CLKGEN_FIELD(0x6C, 0x1, 0),
.ndiv = CLKGEN_FIELD(0x8, C32_NDIV_MASK, 0),
@@ -157,7 +157,7 @@ static struct clkgen_pll_data st_pll3200c32_a9_416 = {
.ops = &stm_pll3200c32_ops,
};
-static struct clkgen_pll_data st_pll3200c32_ddr_416 = {
+static const struct clkgen_pll_data st_pll3200c32_ddr_416 = {
.pdn_status = CLKGEN_FIELD(0x0, 0x1, 0),
.locked_status = CLKGEN_FIELD(0x10C, 0x1, 0),
.ndiv = CLKGEN_FIELD(0x8, C32_NDIV_MASK, 0),
@@ -170,7 +170,7 @@ static struct clkgen_pll_data st_pll3200c32_ddr_416 = {
.ops = &stm_pll3200c32_ops,
};
-static struct clkgen_pll_data st_pll1200c32_gpu_416 = {
+static const struct clkgen_pll_data st_pll1200c32_gpu_416 = {
.pdn_status = CLKGEN_FIELD(0x8E4, 0x1, 3),
.locked_status = CLKGEN_FIELD(0x90C, 0x1, 0),
.ldf = CLKGEN_FIELD(0x0, C32_LDF_MASK, 3),
@@ -450,9 +450,8 @@ static void __init clkgena_c65_pll_setup(struct device_node *np)
* PLL0 HS (high speed) output
*/
clk_data->clks[0] = clkgen_pll_register(parent_name,
- &st_pll1600c65_ax,
- reg + CLKGENAx_PLL0_OFFSET,
- clk_name);
+ (struct clkgen_pll_data *) &st_pll1600c65_ax,
+ reg + CLKGENAx_PLL0_OFFSET, clk_name);
if (IS_ERR(clk_data->clks[0]))
goto err;
@@ -480,9 +479,8 @@ static void __init clkgena_c65_pll_setup(struct device_node *np)
* PLL1 output
*/
clk_data->clks[2] = clkgen_pll_register(parent_name,
- &st_pll800c65_ax,
- reg + CLKGENAx_PLL1_OFFSET,
- clk_name);
+ (struct clkgen_pll_data *) &st_pll800c65_ax,
+ reg + CLKGENAx_PLL1_OFFSET, clk_name);
if (IS_ERR(clk_data->clks[2]))
goto err;
--
1.9.1
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [PATCH v2 04/14] clk: st: Adds Flexgen clock binding
2014-06-27 13:24 ` Gabriel FERNANDEZ
@ 2014-06-27 13:25 ` Gabriel FERNANDEZ
-1 siblings, 0 replies; 49+ messages in thread
From: Gabriel FERNANDEZ @ 2014-06-27 13:25 UTC (permalink / raw)
To: mturquette, robh+dt, pawel.moll, mark.rutland, ijc+devicetree, galak
Cc: devicetree, linux-doc, linux-kernel, linux-arm-kernel, kernel,
Lee Jones, Gabriel Fernandez
A Flexgen structure is composed by:
- a clock cross bar (represented by a mux element)
- a pre and final dividers (represented by a divider and gate elements)
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org>
Acked-by: Peter Griffin <peter.griffin@linaro.org>
---
.../devicetree/bindings/clock/st/st,clkgen.txt | 5 +++
.../devicetree/bindings/clock/st/st,flexgen.txt | 48 ++++++++++++++++++++++
2 files changed, 53 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/st/st,flexgen.txt
diff --git a/Documentation/devicetree/bindings/clock/st/st,clkgen.txt b/Documentation/devicetree/bindings/clock/st/st,clkgen.txt
index 427bad8..78978f1 100644
--- a/Documentation/devicetree/bindings/clock/st/st,clkgen.txt
+++ b/Documentation/devicetree/bindings/clock/st/st,clkgen.txt
@@ -32,6 +32,10 @@ address is common of all subnode.
vcc_node {
...
};
+
+ flexgen_node {
+ ...
+ };
...
};
@@ -45,6 +49,7 @@ Each subnode should use the binding discribe in [2]..[7]
[5] Documentation/devicetree/bindings/clock/st,clkgen-prediv.txt
[6] Documentation/devicetree/bindings/clock/st,vcc.txt
[7] Documentation/devicetree/bindings/clock/st,quadfs.txt
+[8] Documentation/devicetree/bindings/clock/st,flexgen.txt
Required properties:
diff --git a/Documentation/devicetree/bindings/clock/st/st,flexgen.txt b/Documentation/devicetree/bindings/clock/st/st,flexgen.txt
new file mode 100644
index 0000000..f2d4333
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/st/st,flexgen.txt
@@ -0,0 +1,48 @@
+Binding for a type of flexgen structure found on certain
+STMicroelectronics consumer electronics SoC devices
+
+This structure includes:
+- a clock cross bar (represented by a mux element)
+- a pre and final dividers (represented by a divider and gate elements)
+
+This binding uses the common clock binding[1].
+
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+
+Required properties:
+- compatible : shall be:
+ "st,flexgen"
+
+- #clock-cells : from common clock binding; shall be set to 1.
+
+- clocks : from common clock binding
+
+- clock-output-names : From common clock binding. The block has 4
+ clock outputs but not all of them in a specific instance
+ have to be used in the SoC. If a clock name is left as
+ an empty string then no clock will be created for the
+ output associated with that string index. If fewer than
+ 4 strings are provided then no clocks will be created
+ for the remaining outputs.
+
+Example:
+
+ clockgen-d2@x9106000 {
+ compatible = "st,clkgen-c32";
+ reg = <0x9106000 0x1000>;
+
+ clk_s_d2_flexgen: clk-s-d2-flexgen {
+ compatible = "st,flexgen";
+
+ #clock-cells = <1>;
+ clocks = <&clk_s_d2_quadfs 0>,
+ <&clk_s_d2_quadfs 1>,
+ <&clk_s_d2_quadfs 2>,
+ <&clk_s_d2_quadfs 3>;
+
+ clock-output-names = "clk-pix-main-disp",
+ "clk-pix-pip",
+ "clk-pix-gdp1",
+ "clk-pix-gdp2";
+ };
+ };
--
1.9.1
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [PATCH v2 04/14] clk: st: Adds Flexgen clock binding
@ 2014-06-27 13:25 ` Gabriel FERNANDEZ
0 siblings, 0 replies; 49+ messages in thread
From: Gabriel FERNANDEZ @ 2014-06-27 13:25 UTC (permalink / raw)
To: linux-arm-kernel
A Flexgen structure is composed by:
- a clock cross bar (represented by a mux element)
- a pre and final dividers (represented by a divider and gate elements)
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org>
Acked-by: Peter Griffin <peter.griffin@linaro.org>
---
.../devicetree/bindings/clock/st/st,clkgen.txt | 5 +++
.../devicetree/bindings/clock/st/st,flexgen.txt | 48 ++++++++++++++++++++++
2 files changed, 53 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/st/st,flexgen.txt
diff --git a/Documentation/devicetree/bindings/clock/st/st,clkgen.txt b/Documentation/devicetree/bindings/clock/st/st,clkgen.txt
index 427bad8..78978f1 100644
--- a/Documentation/devicetree/bindings/clock/st/st,clkgen.txt
+++ b/Documentation/devicetree/bindings/clock/st/st,clkgen.txt
@@ -32,6 +32,10 @@ address is common of all subnode.
vcc_node {
...
};
+
+ flexgen_node {
+ ...
+ };
...
};
@@ -45,6 +49,7 @@ Each subnode should use the binding discribe in [2]..[7]
[5] Documentation/devicetree/bindings/clock/st,clkgen-prediv.txt
[6] Documentation/devicetree/bindings/clock/st,vcc.txt
[7] Documentation/devicetree/bindings/clock/st,quadfs.txt
+[8] Documentation/devicetree/bindings/clock/st,flexgen.txt
Required properties:
diff --git a/Documentation/devicetree/bindings/clock/st/st,flexgen.txt b/Documentation/devicetree/bindings/clock/st/st,flexgen.txt
new file mode 100644
index 0000000..f2d4333
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/st/st,flexgen.txt
@@ -0,0 +1,48 @@
+Binding for a type of flexgen structure found on certain
+STMicroelectronics consumer electronics SoC devices
+
+This structure includes:
+- a clock cross bar (represented by a mux element)
+- a pre and final dividers (represented by a divider and gate elements)
+
+This binding uses the common clock binding[1].
+
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+
+Required properties:
+- compatible : shall be:
+ "st,flexgen"
+
+- #clock-cells : from common clock binding; shall be set to 1.
+
+- clocks : from common clock binding
+
+- clock-output-names : From common clock binding. The block has 4
+ clock outputs but not all of them in a specific instance
+ have to be used in the SoC. If a clock name is left as
+ an empty string then no clock will be created for the
+ output associated with that string index. If fewer than
+ 4 strings are provided then no clocks will be created
+ for the remaining outputs.
+
+Example:
+
+ clockgen-d2 at x9106000 {
+ compatible = "st,clkgen-c32";
+ reg = <0x9106000 0x1000>;
+
+ clk_s_d2_flexgen: clk-s-d2-flexgen {
+ compatible = "st,flexgen";
+
+ #clock-cells = <1>;
+ clocks = <&clk_s_d2_quadfs 0>,
+ <&clk_s_d2_quadfs 1>,
+ <&clk_s_d2_quadfs 2>,
+ <&clk_s_d2_quadfs 3>;
+
+ clock-output-names = "clk-pix-main-disp",
+ "clk-pix-pip",
+ "clk-pix-gdp1",
+ "clk-pix-gdp2";
+ };
+ };
--
1.9.1
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [PATCH v2 05/14] drivers: clk: st: STiH407: Support for Flexgen Clocks
@ 2014-06-27 13:25 ` Gabriel FERNANDEZ
0 siblings, 0 replies; 49+ messages in thread
From: Gabriel FERNANDEZ @ 2014-06-27 13:25 UTC (permalink / raw)
To: mturquette, robh+dt, pawel.moll, mark.rutland, ijc+devicetree, galak
Cc: devicetree, linux-doc, linux-kernel, linux-arm-kernel, kernel,
Lee Jones, Gabriel Fernandez, Maxime Coquelin, Olivier Bideau
This patch is the Flexgen implementation reusing as much as possible
of Common Clock Framework functions.
The idea is to have an instance of "struct flexgen" per output clock.
It represents the clock cross bar (by a mux element), and the pre and final dividers
(using dividers and gates elements).
Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
Signed-off-by: Olivier Bideau <olivier.bideau@st.com>
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org>
Acked-by: Peter Griffin <peter.griffin@linaro.org>
---
drivers/clk/st/Makefile | 2 +-
drivers/clk/st/clk-flexgen.c | 332 +++++++++++++++++++++++++++++++++++++++++++
2 files changed, 333 insertions(+), 1 deletion(-)
create mode 100644 drivers/clk/st/clk-flexgen.c
diff --git a/drivers/clk/st/Makefile b/drivers/clk/st/Makefile
index c7455ff..ede7b2f 100644
--- a/drivers/clk/st/Makefile
+++ b/drivers/clk/st/Makefile
@@ -1 +1 @@
-obj-y += clkgen-mux.o clkgen-pll.o clkgen-fsyn.o
+obj-y += clkgen-mux.o clkgen-pll.o clkgen-fsyn.o clk-flexgen.o
diff --git a/drivers/clk/st/clk-flexgen.c b/drivers/clk/st/clk-flexgen.c
new file mode 100644
index 0000000..c12d0c1
--- /dev/null
+++ b/drivers/clk/st/clk-flexgen.c
@@ -0,0 +1,332 @@
+/*
+ * clk-flexgen.c
+ *
+ * Copyright (C) ST-Microelectronics SA 2013
+ * Author: Maxime Coquelin <maxime.coquelin@st.com> for ST-Microelectronics.
+ * License terms: GNU General Public License (GPL), version 2 */
+
+#include <linux/clk-provider.h>
+#include <linux/module.h>
+#include <linux/slab.h>
+#include <linux/io.h>
+#include <linux/err.h>
+#include <linux/string.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+
+struct flexgen {
+ struct clk_hw hw;
+
+ /* Crossbar */
+ struct clk_mux mux;
+ /* Pre-divisor's gate */
+ struct clk_gate pgate;
+ /* Pre-divisor */
+ struct clk_divider pdiv;
+ /* Final divisor's gate */
+ struct clk_gate fgate;
+ /* Final divisor */
+ struct clk_divider fdiv;
+};
+
+#define to_flexgen(_hw) container_of(_hw, struct flexgen, hw)
+
+static int flexgen_enable(struct clk_hw *hw)
+{
+ struct flexgen *flexgen = to_flexgen(hw);
+ struct clk_hw *pgate_hw = &flexgen->pgate.hw;
+ struct clk_hw *fgate_hw = &flexgen->fgate.hw;
+
+ pgate_hw->clk = hw->clk;
+ fgate_hw->clk = hw->clk;
+
+ clk_gate_ops.enable(pgate_hw);
+
+ clk_gate_ops.enable(fgate_hw);
+
+ pr_debug("%s: flexgen output enabled\n", __clk_get_name(hw->clk));
+ return 0;
+}
+
+static void flexgen_disable(struct clk_hw *hw)
+{
+ struct flexgen *flexgen = to_flexgen(hw);
+ struct clk_hw *fgate_hw = &flexgen->fgate.hw;
+
+ /* disable only the final gate */
+ fgate_hw->clk = hw->clk;
+
+ clk_gate_ops.disable(fgate_hw);
+
+ pr_debug("%s: flexgen output disabled\n", __clk_get_name(hw->clk));
+}
+
+static int flexgen_is_enabled(struct clk_hw *hw)
+{
+ struct flexgen *flexgen = to_flexgen(hw);
+ struct clk_hw *fgate_hw = &flexgen->fgate.hw;
+
+ fgate_hw->clk = hw->clk;
+
+ if (!clk_gate_ops.is_enabled(fgate_hw))
+ return 0;
+
+ return 1;
+}
+
+static u8 flexgen_get_parent(struct clk_hw *hw)
+{
+ struct flexgen *flexgen = to_flexgen(hw);
+ struct clk_hw *mux_hw = &flexgen->mux.hw;
+
+ mux_hw->clk = hw->clk;
+
+ return clk_mux_ops.get_parent(mux_hw);
+}
+
+static int flexgen_set_parent(struct clk_hw *hw, u8 index)
+{
+ struct flexgen *flexgen = to_flexgen(hw);
+ struct clk_hw *mux_hw = &flexgen->mux.hw;
+
+ mux_hw->clk = hw->clk;
+
+ return clk_mux_ops.set_parent(mux_hw, index);
+}
+
+static inline unsigned long
+clk_best_div(unsigned long parent_rate, unsigned long rate)
+{
+ return parent_rate / rate + ((rate > (2*(parent_rate % rate))) ? 0 : 1);
+}
+
+static long flexgen_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *prate)
+{
+ unsigned long div;
+
+ /* Round div according to exact prate and wished rate */
+ div = clk_best_div(*prate, rate);
+
+ if (__clk_get_flags(hw->clk) & CLK_SET_RATE_PARENT) {
+ *prate = rate * div;
+ return rate;
+ } else
+ return *prate / div;
+}
+
+unsigned long flexgen_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ struct flexgen *flexgen = to_flexgen(hw);
+ struct clk_hw *pdiv_hw = &flexgen->pdiv.hw;
+ struct clk_hw *fdiv_hw = &flexgen->fdiv.hw;
+ unsigned long mid_rate;
+
+ pdiv_hw->clk = hw->clk;
+ fdiv_hw->clk = hw->clk;
+
+ mid_rate = clk_divider_ops.recalc_rate(pdiv_hw, parent_rate);
+
+ return clk_divider_ops.recalc_rate(fdiv_hw, mid_rate);
+}
+
+static int flexgen_set_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long parent_rate)
+{
+ struct flexgen *flexgen = to_flexgen(hw);
+ struct clk_hw *pdiv_hw = &flexgen->pdiv.hw;
+ struct clk_hw *fdiv_hw = &flexgen->fdiv.hw;
+ unsigned long primary_div = 0;
+ int ret = 0;
+
+ pdiv_hw->clk = hw->clk;
+ fdiv_hw->clk = hw->clk;
+
+ primary_div = clk_best_div(parent_rate, rate);
+
+ clk_divider_ops.set_rate(fdiv_hw, parent_rate, parent_rate);
+ ret = clk_divider_ops.set_rate(pdiv_hw, rate, rate * primary_div);
+
+ return ret;
+}
+
+static const struct clk_ops flexgen_ops = {
+ .enable = flexgen_enable,
+ .disable = flexgen_disable,
+ .is_enabled = flexgen_is_enabled,
+ .get_parent = flexgen_get_parent,
+ .set_parent = flexgen_set_parent,
+ .round_rate = flexgen_round_rate,
+ .recalc_rate = flexgen_recalc_rate,
+ .set_rate = flexgen_set_rate,
+};
+
+struct clk *clk_register_flexgen(const char *name,
+ const char **parent_names, u8 num_parents,
+ void __iomem *reg, spinlock_t *lock, u32 idx,
+ unsigned long flexgen_flags) {
+ struct flexgen *fgxbar;
+ struct clk *clk;
+ struct clk_init_data init;
+ u32 xbar_shift;
+ void __iomem *xbar_reg, *fdiv_reg;
+
+ fgxbar = kzalloc(sizeof(struct flexgen), GFP_KERNEL);
+ if (!fgxbar)
+ return ERR_PTR(-ENOMEM);
+
+ init.name = name;
+ init.ops = &flexgen_ops;
+ init.flags = CLK_IS_BASIC | flexgen_flags;
+ init.parent_names = parent_names;
+ init.num_parents = num_parents;
+
+ xbar_reg = reg + 0x18 + (idx & ~0x3);
+ xbar_shift = (idx % 4) * 0x8;
+ fdiv_reg = reg + 0x164 + idx * 4;
+
+ /* Crossbar element config */
+ fgxbar->mux.lock = lock;
+ fgxbar->mux.mask = BIT(6) - 1;
+ fgxbar->mux.reg = xbar_reg;
+ fgxbar->mux.shift = xbar_shift;
+ fgxbar->mux.table = NULL;
+
+
+ /* Pre-divider's gate config (in xbar register)*/
+ fgxbar->pgate.lock = lock;
+ fgxbar->pgate.reg = xbar_reg;
+ fgxbar->pgate.bit_idx = xbar_shift + 6;
+
+ /* Pre-divider config */
+ fgxbar->pdiv.lock = lock;
+ fgxbar->pdiv.reg = reg + 0x58 + idx * 4;
+ fgxbar->pdiv.width = 10;
+
+ /* Final divider's gate config */
+ fgxbar->fgate.lock = lock;
+ fgxbar->fgate.reg = fdiv_reg;
+ fgxbar->fgate.bit_idx = 6;
+
+ /* Final divider config */
+ fgxbar->fdiv.lock = lock;
+ fgxbar->fdiv.reg = fdiv_reg;
+ fgxbar->fdiv.width = 6;
+
+ fgxbar->hw.init = &init;
+
+ clk = clk_register(NULL, &fgxbar->hw);
+ if (IS_ERR(clk))
+ kfree(fgxbar);
+ else
+ pr_debug("%s: parent %s rate %u\n",
+ __clk_get_name(clk),
+ __clk_get_name(clk_get_parent(clk)),
+ (unsigned int)clk_get_rate(clk));
+ return clk;
+}
+
+static const char ** __init flexgen_get_parents(struct device_node *np,
+ int *num_parents)
+{
+ const char **parents;
+ int nparents, i;
+
+ nparents = of_count_phandle_with_args(np, "clocks", "#clock-cells");
+ if (WARN_ON(nparents <= 0))
+ return NULL;
+
+ parents = kcalloc(nparents, sizeof(const char *), GFP_KERNEL);
+ if (!parents)
+ return NULL;
+
+ for (i = 0; i < nparents; i++)
+ parents[i] = of_clk_get_parent_name(np, i);
+
+ *num_parents = nparents;
+ return parents;
+}
+
+void __init st_of_flexgen_setup(struct device_node *np)
+{
+ struct device_node *pnode;
+ void __iomem *reg;
+ struct clk_onecell_data *clk_data;
+ const char **parents;
+ int num_parents, i;
+ spinlock_t *rlock = NULL;
+ unsigned long flex_flags = 0;
+
+ pnode = of_get_parent(np);
+ if (!pnode)
+ return;
+
+ reg = of_iomap(pnode, 0);
+ if (!reg)
+ return;
+
+ parents = flexgen_get_parents(np, &num_parents);
+ if (!parents)
+ return;
+
+ clk_data = kzalloc(sizeof(*clk_data), GFP_KERNEL);
+ if (!clk_data)
+ goto err;
+
+ clk_data->clk_num = of_property_count_strings(np ,
+ "clock-output-names");
+ if (clk_data->clk_num <= 0) {
+ pr_err("%s: Failed to get number of output clocks (%d)",
+ __func__, clk_data->clk_num);
+ goto err;
+ }
+
+ clk_data->clks = kcalloc(clk_data->clk_num, sizeof(struct clk *),
+ GFP_KERNEL);
+ if (!clk_data->clks)
+ goto err;
+
+ rlock = kzalloc(sizeof(spinlock_t), GFP_KERNEL);
+ if (!rlock)
+ goto err;
+
+ for (i = 0; i < clk_data->clk_num; i++) {
+ struct clk *clk;
+ const char *clk_name;
+
+ if (of_property_read_string_index(np, "clock-output-names",
+ i, &clk_name)) {
+ break;
+ }
+
+ /*
+ * If we read an empty clock name then the output is unused
+ */
+ if (*clk_name == '\0')
+ continue;
+
+ clk = clk_register_flexgen(clk_name, parents, num_parents,
+ reg, rlock, i, flex_flags);
+
+ if (IS_ERR(clk))
+ goto err;
+
+ clk_data->clks[i] = clk;
+ }
+
+ kfree(parents);
+ of_clk_add_provider(np, of_clk_src_onecell_get, clk_data);
+
+ return;
+
+err:
+ if (clk_data)
+ kfree(clk_data->clks);
+ kfree(clk_data);
+ kfree(parents);
+ kfree(rlock);
+
+ return;
+}
+CLK_OF_DECLARE(flexgen, "st,flexgen", st_of_flexgen_setup);
--
1.9.1
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [PATCH v2 05/14] drivers: clk: st: STiH407: Support for Flexgen Clocks
@ 2014-06-27 13:25 ` Gabriel FERNANDEZ
0 siblings, 0 replies; 49+ messages in thread
From: Gabriel FERNANDEZ @ 2014-06-27 13:25 UTC (permalink / raw)
To: mturquette-QSEj5FYQhm4dnm+yROfE0A,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A, pawel.moll-5wv7dgnIgG8,
mark.rutland-5wv7dgnIgG8, ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg,
galak-sgV2jX0FEOL9JmXXK+q4OQ
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-doc-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
kernel-F5mvAk5X5gdBDgjK7y7TUQ, Lee Jones, Gabriel Fernandez,
Maxime Coquelin, Olivier Bideau
This patch is the Flexgen implementation reusing as much as possible
of Common Clock Framework functions.
The idea is to have an instance of "struct flexgen" per output clock.
It represents the clock cross bar (by a mux element), and the pre and final dividers
(using dividers and gates elements).
Signed-off-by: Maxime Coquelin <maxime.coquelin-qxv4g6HH51o@public.gmane.org>
Signed-off-by: Olivier Bideau <olivier.bideau-qxv4g6HH51o@public.gmane.org>
Signed-off-by: Gabriel Fernandez <gabriel.fernandez-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
Acked-by: Peter Griffin <peter.griffin-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
---
drivers/clk/st/Makefile | 2 +-
drivers/clk/st/clk-flexgen.c | 332 +++++++++++++++++++++++++++++++++++++++++++
2 files changed, 333 insertions(+), 1 deletion(-)
create mode 100644 drivers/clk/st/clk-flexgen.c
diff --git a/drivers/clk/st/Makefile b/drivers/clk/st/Makefile
index c7455ff..ede7b2f 100644
--- a/drivers/clk/st/Makefile
+++ b/drivers/clk/st/Makefile
@@ -1 +1 @@
-obj-y += clkgen-mux.o clkgen-pll.o clkgen-fsyn.o
+obj-y += clkgen-mux.o clkgen-pll.o clkgen-fsyn.o clk-flexgen.o
diff --git a/drivers/clk/st/clk-flexgen.c b/drivers/clk/st/clk-flexgen.c
new file mode 100644
index 0000000..c12d0c1
--- /dev/null
+++ b/drivers/clk/st/clk-flexgen.c
@@ -0,0 +1,332 @@
+/*
+ * clk-flexgen.c
+ *
+ * Copyright (C) ST-Microelectronics SA 2013
+ * Author: Maxime Coquelin <maxime.coquelin-qxv4g6HH51o@public.gmane.org> for ST-Microelectronics.
+ * License terms: GNU General Public License (GPL), version 2 */
+
+#include <linux/clk-provider.h>
+#include <linux/module.h>
+#include <linux/slab.h>
+#include <linux/io.h>
+#include <linux/err.h>
+#include <linux/string.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+
+struct flexgen {
+ struct clk_hw hw;
+
+ /* Crossbar */
+ struct clk_mux mux;
+ /* Pre-divisor's gate */
+ struct clk_gate pgate;
+ /* Pre-divisor */
+ struct clk_divider pdiv;
+ /* Final divisor's gate */
+ struct clk_gate fgate;
+ /* Final divisor */
+ struct clk_divider fdiv;
+};
+
+#define to_flexgen(_hw) container_of(_hw, struct flexgen, hw)
+
+static int flexgen_enable(struct clk_hw *hw)
+{
+ struct flexgen *flexgen = to_flexgen(hw);
+ struct clk_hw *pgate_hw = &flexgen->pgate.hw;
+ struct clk_hw *fgate_hw = &flexgen->fgate.hw;
+
+ pgate_hw->clk = hw->clk;
+ fgate_hw->clk = hw->clk;
+
+ clk_gate_ops.enable(pgate_hw);
+
+ clk_gate_ops.enable(fgate_hw);
+
+ pr_debug("%s: flexgen output enabled\n", __clk_get_name(hw->clk));
+ return 0;
+}
+
+static void flexgen_disable(struct clk_hw *hw)
+{
+ struct flexgen *flexgen = to_flexgen(hw);
+ struct clk_hw *fgate_hw = &flexgen->fgate.hw;
+
+ /* disable only the final gate */
+ fgate_hw->clk = hw->clk;
+
+ clk_gate_ops.disable(fgate_hw);
+
+ pr_debug("%s: flexgen output disabled\n", __clk_get_name(hw->clk));
+}
+
+static int flexgen_is_enabled(struct clk_hw *hw)
+{
+ struct flexgen *flexgen = to_flexgen(hw);
+ struct clk_hw *fgate_hw = &flexgen->fgate.hw;
+
+ fgate_hw->clk = hw->clk;
+
+ if (!clk_gate_ops.is_enabled(fgate_hw))
+ return 0;
+
+ return 1;
+}
+
+static u8 flexgen_get_parent(struct clk_hw *hw)
+{
+ struct flexgen *flexgen = to_flexgen(hw);
+ struct clk_hw *mux_hw = &flexgen->mux.hw;
+
+ mux_hw->clk = hw->clk;
+
+ return clk_mux_ops.get_parent(mux_hw);
+}
+
+static int flexgen_set_parent(struct clk_hw *hw, u8 index)
+{
+ struct flexgen *flexgen = to_flexgen(hw);
+ struct clk_hw *mux_hw = &flexgen->mux.hw;
+
+ mux_hw->clk = hw->clk;
+
+ return clk_mux_ops.set_parent(mux_hw, index);
+}
+
+static inline unsigned long
+clk_best_div(unsigned long parent_rate, unsigned long rate)
+{
+ return parent_rate / rate + ((rate > (2*(parent_rate % rate))) ? 0 : 1);
+}
+
+static long flexgen_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *prate)
+{
+ unsigned long div;
+
+ /* Round div according to exact prate and wished rate */
+ div = clk_best_div(*prate, rate);
+
+ if (__clk_get_flags(hw->clk) & CLK_SET_RATE_PARENT) {
+ *prate = rate * div;
+ return rate;
+ } else
+ return *prate / div;
+}
+
+unsigned long flexgen_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ struct flexgen *flexgen = to_flexgen(hw);
+ struct clk_hw *pdiv_hw = &flexgen->pdiv.hw;
+ struct clk_hw *fdiv_hw = &flexgen->fdiv.hw;
+ unsigned long mid_rate;
+
+ pdiv_hw->clk = hw->clk;
+ fdiv_hw->clk = hw->clk;
+
+ mid_rate = clk_divider_ops.recalc_rate(pdiv_hw, parent_rate);
+
+ return clk_divider_ops.recalc_rate(fdiv_hw, mid_rate);
+}
+
+static int flexgen_set_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long parent_rate)
+{
+ struct flexgen *flexgen = to_flexgen(hw);
+ struct clk_hw *pdiv_hw = &flexgen->pdiv.hw;
+ struct clk_hw *fdiv_hw = &flexgen->fdiv.hw;
+ unsigned long primary_div = 0;
+ int ret = 0;
+
+ pdiv_hw->clk = hw->clk;
+ fdiv_hw->clk = hw->clk;
+
+ primary_div = clk_best_div(parent_rate, rate);
+
+ clk_divider_ops.set_rate(fdiv_hw, parent_rate, parent_rate);
+ ret = clk_divider_ops.set_rate(pdiv_hw, rate, rate * primary_div);
+
+ return ret;
+}
+
+static const struct clk_ops flexgen_ops = {
+ .enable = flexgen_enable,
+ .disable = flexgen_disable,
+ .is_enabled = flexgen_is_enabled,
+ .get_parent = flexgen_get_parent,
+ .set_parent = flexgen_set_parent,
+ .round_rate = flexgen_round_rate,
+ .recalc_rate = flexgen_recalc_rate,
+ .set_rate = flexgen_set_rate,
+};
+
+struct clk *clk_register_flexgen(const char *name,
+ const char **parent_names, u8 num_parents,
+ void __iomem *reg, spinlock_t *lock, u32 idx,
+ unsigned long flexgen_flags) {
+ struct flexgen *fgxbar;
+ struct clk *clk;
+ struct clk_init_data init;
+ u32 xbar_shift;
+ void __iomem *xbar_reg, *fdiv_reg;
+
+ fgxbar = kzalloc(sizeof(struct flexgen), GFP_KERNEL);
+ if (!fgxbar)
+ return ERR_PTR(-ENOMEM);
+
+ init.name = name;
+ init.ops = &flexgen_ops;
+ init.flags = CLK_IS_BASIC | flexgen_flags;
+ init.parent_names = parent_names;
+ init.num_parents = num_parents;
+
+ xbar_reg = reg + 0x18 + (idx & ~0x3);
+ xbar_shift = (idx % 4) * 0x8;
+ fdiv_reg = reg + 0x164 + idx * 4;
+
+ /* Crossbar element config */
+ fgxbar->mux.lock = lock;
+ fgxbar->mux.mask = BIT(6) - 1;
+ fgxbar->mux.reg = xbar_reg;
+ fgxbar->mux.shift = xbar_shift;
+ fgxbar->mux.table = NULL;
+
+
+ /* Pre-divider's gate config (in xbar register)*/
+ fgxbar->pgate.lock = lock;
+ fgxbar->pgate.reg = xbar_reg;
+ fgxbar->pgate.bit_idx = xbar_shift + 6;
+
+ /* Pre-divider config */
+ fgxbar->pdiv.lock = lock;
+ fgxbar->pdiv.reg = reg + 0x58 + idx * 4;
+ fgxbar->pdiv.width = 10;
+
+ /* Final divider's gate config */
+ fgxbar->fgate.lock = lock;
+ fgxbar->fgate.reg = fdiv_reg;
+ fgxbar->fgate.bit_idx = 6;
+
+ /* Final divider config */
+ fgxbar->fdiv.lock = lock;
+ fgxbar->fdiv.reg = fdiv_reg;
+ fgxbar->fdiv.width = 6;
+
+ fgxbar->hw.init = &init;
+
+ clk = clk_register(NULL, &fgxbar->hw);
+ if (IS_ERR(clk))
+ kfree(fgxbar);
+ else
+ pr_debug("%s: parent %s rate %u\n",
+ __clk_get_name(clk),
+ __clk_get_name(clk_get_parent(clk)),
+ (unsigned int)clk_get_rate(clk));
+ return clk;
+}
+
+static const char ** __init flexgen_get_parents(struct device_node *np,
+ int *num_parents)
+{
+ const char **parents;
+ int nparents, i;
+
+ nparents = of_count_phandle_with_args(np, "clocks", "#clock-cells");
+ if (WARN_ON(nparents <= 0))
+ return NULL;
+
+ parents = kcalloc(nparents, sizeof(const char *), GFP_KERNEL);
+ if (!parents)
+ return NULL;
+
+ for (i = 0; i < nparents; i++)
+ parents[i] = of_clk_get_parent_name(np, i);
+
+ *num_parents = nparents;
+ return parents;
+}
+
+void __init st_of_flexgen_setup(struct device_node *np)
+{
+ struct device_node *pnode;
+ void __iomem *reg;
+ struct clk_onecell_data *clk_data;
+ const char **parents;
+ int num_parents, i;
+ spinlock_t *rlock = NULL;
+ unsigned long flex_flags = 0;
+
+ pnode = of_get_parent(np);
+ if (!pnode)
+ return;
+
+ reg = of_iomap(pnode, 0);
+ if (!reg)
+ return;
+
+ parents = flexgen_get_parents(np, &num_parents);
+ if (!parents)
+ return;
+
+ clk_data = kzalloc(sizeof(*clk_data), GFP_KERNEL);
+ if (!clk_data)
+ goto err;
+
+ clk_data->clk_num = of_property_count_strings(np ,
+ "clock-output-names");
+ if (clk_data->clk_num <= 0) {
+ pr_err("%s: Failed to get number of output clocks (%d)",
+ __func__, clk_data->clk_num);
+ goto err;
+ }
+
+ clk_data->clks = kcalloc(clk_data->clk_num, sizeof(struct clk *),
+ GFP_KERNEL);
+ if (!clk_data->clks)
+ goto err;
+
+ rlock = kzalloc(sizeof(spinlock_t), GFP_KERNEL);
+ if (!rlock)
+ goto err;
+
+ for (i = 0; i < clk_data->clk_num; i++) {
+ struct clk *clk;
+ const char *clk_name;
+
+ if (of_property_read_string_index(np, "clock-output-names",
+ i, &clk_name)) {
+ break;
+ }
+
+ /*
+ * If we read an empty clock name then the output is unused
+ */
+ if (*clk_name == '\0')
+ continue;
+
+ clk = clk_register_flexgen(clk_name, parents, num_parents,
+ reg, rlock, i, flex_flags);
+
+ if (IS_ERR(clk))
+ goto err;
+
+ clk_data->clks[i] = clk;
+ }
+
+ kfree(parents);
+ of_clk_add_provider(np, of_clk_src_onecell_get, clk_data);
+
+ return;
+
+err:
+ if (clk_data)
+ kfree(clk_data->clks);
+ kfree(clk_data);
+ kfree(parents);
+ kfree(rlock);
+
+ return;
+}
+CLK_OF_DECLARE(flexgen, "st,flexgen", st_of_flexgen_setup);
--
1.9.1
--
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^ permalink raw reply related [flat|nested] 49+ messages in thread
* [PATCH v2 05/14] drivers: clk: st: STiH407: Support for Flexgen Clocks
@ 2014-06-27 13:25 ` Gabriel FERNANDEZ
0 siblings, 0 replies; 49+ messages in thread
From: Gabriel FERNANDEZ @ 2014-06-27 13:25 UTC (permalink / raw)
To: linux-arm-kernel
This patch is the Flexgen implementation reusing as much as possible
of Common Clock Framework functions.
The idea is to have an instance of "struct flexgen" per output clock.
It represents the clock cross bar (by a mux element), and the pre and final dividers
(using dividers and gates elements).
Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
Signed-off-by: Olivier Bideau <olivier.bideau@st.com>
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org>
Acked-by: Peter Griffin <peter.griffin@linaro.org>
---
drivers/clk/st/Makefile | 2 +-
drivers/clk/st/clk-flexgen.c | 332 +++++++++++++++++++++++++++++++++++++++++++
2 files changed, 333 insertions(+), 1 deletion(-)
create mode 100644 drivers/clk/st/clk-flexgen.c
diff --git a/drivers/clk/st/Makefile b/drivers/clk/st/Makefile
index c7455ff..ede7b2f 100644
--- a/drivers/clk/st/Makefile
+++ b/drivers/clk/st/Makefile
@@ -1 +1 @@
-obj-y += clkgen-mux.o clkgen-pll.o clkgen-fsyn.o
+obj-y += clkgen-mux.o clkgen-pll.o clkgen-fsyn.o clk-flexgen.o
diff --git a/drivers/clk/st/clk-flexgen.c b/drivers/clk/st/clk-flexgen.c
new file mode 100644
index 0000000..c12d0c1
--- /dev/null
+++ b/drivers/clk/st/clk-flexgen.c
@@ -0,0 +1,332 @@
+/*
+ * clk-flexgen.c
+ *
+ * Copyright (C) ST-Microelectronics SA 2013
+ * Author: Maxime Coquelin <maxime.coquelin@st.com> for ST-Microelectronics.
+ * License terms: GNU General Public License (GPL), version 2 */
+
+#include <linux/clk-provider.h>
+#include <linux/module.h>
+#include <linux/slab.h>
+#include <linux/io.h>
+#include <linux/err.h>
+#include <linux/string.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+
+struct flexgen {
+ struct clk_hw hw;
+
+ /* Crossbar */
+ struct clk_mux mux;
+ /* Pre-divisor's gate */
+ struct clk_gate pgate;
+ /* Pre-divisor */
+ struct clk_divider pdiv;
+ /* Final divisor's gate */
+ struct clk_gate fgate;
+ /* Final divisor */
+ struct clk_divider fdiv;
+};
+
+#define to_flexgen(_hw) container_of(_hw, struct flexgen, hw)
+
+static int flexgen_enable(struct clk_hw *hw)
+{
+ struct flexgen *flexgen = to_flexgen(hw);
+ struct clk_hw *pgate_hw = &flexgen->pgate.hw;
+ struct clk_hw *fgate_hw = &flexgen->fgate.hw;
+
+ pgate_hw->clk = hw->clk;
+ fgate_hw->clk = hw->clk;
+
+ clk_gate_ops.enable(pgate_hw);
+
+ clk_gate_ops.enable(fgate_hw);
+
+ pr_debug("%s: flexgen output enabled\n", __clk_get_name(hw->clk));
+ return 0;
+}
+
+static void flexgen_disable(struct clk_hw *hw)
+{
+ struct flexgen *flexgen = to_flexgen(hw);
+ struct clk_hw *fgate_hw = &flexgen->fgate.hw;
+
+ /* disable only the final gate */
+ fgate_hw->clk = hw->clk;
+
+ clk_gate_ops.disable(fgate_hw);
+
+ pr_debug("%s: flexgen output disabled\n", __clk_get_name(hw->clk));
+}
+
+static int flexgen_is_enabled(struct clk_hw *hw)
+{
+ struct flexgen *flexgen = to_flexgen(hw);
+ struct clk_hw *fgate_hw = &flexgen->fgate.hw;
+
+ fgate_hw->clk = hw->clk;
+
+ if (!clk_gate_ops.is_enabled(fgate_hw))
+ return 0;
+
+ return 1;
+}
+
+static u8 flexgen_get_parent(struct clk_hw *hw)
+{
+ struct flexgen *flexgen = to_flexgen(hw);
+ struct clk_hw *mux_hw = &flexgen->mux.hw;
+
+ mux_hw->clk = hw->clk;
+
+ return clk_mux_ops.get_parent(mux_hw);
+}
+
+static int flexgen_set_parent(struct clk_hw *hw, u8 index)
+{
+ struct flexgen *flexgen = to_flexgen(hw);
+ struct clk_hw *mux_hw = &flexgen->mux.hw;
+
+ mux_hw->clk = hw->clk;
+
+ return clk_mux_ops.set_parent(mux_hw, index);
+}
+
+static inline unsigned long
+clk_best_div(unsigned long parent_rate, unsigned long rate)
+{
+ return parent_rate / rate + ((rate > (2*(parent_rate % rate))) ? 0 : 1);
+}
+
+static long flexgen_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *prate)
+{
+ unsigned long div;
+
+ /* Round div according to exact prate and wished rate */
+ div = clk_best_div(*prate, rate);
+
+ if (__clk_get_flags(hw->clk) & CLK_SET_RATE_PARENT) {
+ *prate = rate * div;
+ return rate;
+ } else
+ return *prate / div;
+}
+
+unsigned long flexgen_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ struct flexgen *flexgen = to_flexgen(hw);
+ struct clk_hw *pdiv_hw = &flexgen->pdiv.hw;
+ struct clk_hw *fdiv_hw = &flexgen->fdiv.hw;
+ unsigned long mid_rate;
+
+ pdiv_hw->clk = hw->clk;
+ fdiv_hw->clk = hw->clk;
+
+ mid_rate = clk_divider_ops.recalc_rate(pdiv_hw, parent_rate);
+
+ return clk_divider_ops.recalc_rate(fdiv_hw, mid_rate);
+}
+
+static int flexgen_set_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long parent_rate)
+{
+ struct flexgen *flexgen = to_flexgen(hw);
+ struct clk_hw *pdiv_hw = &flexgen->pdiv.hw;
+ struct clk_hw *fdiv_hw = &flexgen->fdiv.hw;
+ unsigned long primary_div = 0;
+ int ret = 0;
+
+ pdiv_hw->clk = hw->clk;
+ fdiv_hw->clk = hw->clk;
+
+ primary_div = clk_best_div(parent_rate, rate);
+
+ clk_divider_ops.set_rate(fdiv_hw, parent_rate, parent_rate);
+ ret = clk_divider_ops.set_rate(pdiv_hw, rate, rate * primary_div);
+
+ return ret;
+}
+
+static const struct clk_ops flexgen_ops = {
+ .enable = flexgen_enable,
+ .disable = flexgen_disable,
+ .is_enabled = flexgen_is_enabled,
+ .get_parent = flexgen_get_parent,
+ .set_parent = flexgen_set_parent,
+ .round_rate = flexgen_round_rate,
+ .recalc_rate = flexgen_recalc_rate,
+ .set_rate = flexgen_set_rate,
+};
+
+struct clk *clk_register_flexgen(const char *name,
+ const char **parent_names, u8 num_parents,
+ void __iomem *reg, spinlock_t *lock, u32 idx,
+ unsigned long flexgen_flags) {
+ struct flexgen *fgxbar;
+ struct clk *clk;
+ struct clk_init_data init;
+ u32 xbar_shift;
+ void __iomem *xbar_reg, *fdiv_reg;
+
+ fgxbar = kzalloc(sizeof(struct flexgen), GFP_KERNEL);
+ if (!fgxbar)
+ return ERR_PTR(-ENOMEM);
+
+ init.name = name;
+ init.ops = &flexgen_ops;
+ init.flags = CLK_IS_BASIC | flexgen_flags;
+ init.parent_names = parent_names;
+ init.num_parents = num_parents;
+
+ xbar_reg = reg + 0x18 + (idx & ~0x3);
+ xbar_shift = (idx % 4) * 0x8;
+ fdiv_reg = reg + 0x164 + idx * 4;
+
+ /* Crossbar element config */
+ fgxbar->mux.lock = lock;
+ fgxbar->mux.mask = BIT(6) - 1;
+ fgxbar->mux.reg = xbar_reg;
+ fgxbar->mux.shift = xbar_shift;
+ fgxbar->mux.table = NULL;
+
+
+ /* Pre-divider's gate config (in xbar register)*/
+ fgxbar->pgate.lock = lock;
+ fgxbar->pgate.reg = xbar_reg;
+ fgxbar->pgate.bit_idx = xbar_shift + 6;
+
+ /* Pre-divider config */
+ fgxbar->pdiv.lock = lock;
+ fgxbar->pdiv.reg = reg + 0x58 + idx * 4;
+ fgxbar->pdiv.width = 10;
+
+ /* Final divider's gate config */
+ fgxbar->fgate.lock = lock;
+ fgxbar->fgate.reg = fdiv_reg;
+ fgxbar->fgate.bit_idx = 6;
+
+ /* Final divider config */
+ fgxbar->fdiv.lock = lock;
+ fgxbar->fdiv.reg = fdiv_reg;
+ fgxbar->fdiv.width = 6;
+
+ fgxbar->hw.init = &init;
+
+ clk = clk_register(NULL, &fgxbar->hw);
+ if (IS_ERR(clk))
+ kfree(fgxbar);
+ else
+ pr_debug("%s: parent %s rate %u\n",
+ __clk_get_name(clk),
+ __clk_get_name(clk_get_parent(clk)),
+ (unsigned int)clk_get_rate(clk));
+ return clk;
+}
+
+static const char ** __init flexgen_get_parents(struct device_node *np,
+ int *num_parents)
+{
+ const char **parents;
+ int nparents, i;
+
+ nparents = of_count_phandle_with_args(np, "clocks", "#clock-cells");
+ if (WARN_ON(nparents <= 0))
+ return NULL;
+
+ parents = kcalloc(nparents, sizeof(const char *), GFP_KERNEL);
+ if (!parents)
+ return NULL;
+
+ for (i = 0; i < nparents; i++)
+ parents[i] = of_clk_get_parent_name(np, i);
+
+ *num_parents = nparents;
+ return parents;
+}
+
+void __init st_of_flexgen_setup(struct device_node *np)
+{
+ struct device_node *pnode;
+ void __iomem *reg;
+ struct clk_onecell_data *clk_data;
+ const char **parents;
+ int num_parents, i;
+ spinlock_t *rlock = NULL;
+ unsigned long flex_flags = 0;
+
+ pnode = of_get_parent(np);
+ if (!pnode)
+ return;
+
+ reg = of_iomap(pnode, 0);
+ if (!reg)
+ return;
+
+ parents = flexgen_get_parents(np, &num_parents);
+ if (!parents)
+ return;
+
+ clk_data = kzalloc(sizeof(*clk_data), GFP_KERNEL);
+ if (!clk_data)
+ goto err;
+
+ clk_data->clk_num = of_property_count_strings(np ,
+ "clock-output-names");
+ if (clk_data->clk_num <= 0) {
+ pr_err("%s: Failed to get number of output clocks (%d)",
+ __func__, clk_data->clk_num);
+ goto err;
+ }
+
+ clk_data->clks = kcalloc(clk_data->clk_num, sizeof(struct clk *),
+ GFP_KERNEL);
+ if (!clk_data->clks)
+ goto err;
+
+ rlock = kzalloc(sizeof(spinlock_t), GFP_KERNEL);
+ if (!rlock)
+ goto err;
+
+ for (i = 0; i < clk_data->clk_num; i++) {
+ struct clk *clk;
+ const char *clk_name;
+
+ if (of_property_read_string_index(np, "clock-output-names",
+ i, &clk_name)) {
+ break;
+ }
+
+ /*
+ * If we read an empty clock name then the output is unused
+ */
+ if (*clk_name == '\0')
+ continue;
+
+ clk = clk_register_flexgen(clk_name, parents, num_parents,
+ reg, rlock, i, flex_flags);
+
+ if (IS_ERR(clk))
+ goto err;
+
+ clk_data->clks[i] = clk;
+ }
+
+ kfree(parents);
+ of_clk_add_provider(np, of_clk_src_onecell_get, clk_data);
+
+ return;
+
+err:
+ if (clk_data)
+ kfree(clk_data->clks);
+ kfree(clk_data);
+ kfree(parents);
+ kfree(rlock);
+
+ return;
+}
+CLK_OF_DECLARE(flexgen, "st,flexgen", st_of_flexgen_setup);
--
1.9.1
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [PATCH v2 06/14] drivers: clk: st: STiH407: Support for A9 MUX Clocks
2014-06-27 13:24 ` Gabriel FERNANDEZ
@ 2014-06-27 13:25 ` Gabriel FERNANDEZ
-1 siblings, 0 replies; 49+ messages in thread
From: Gabriel FERNANDEZ @ 2014-06-27 13:25 UTC (permalink / raw)
To: mturquette, robh+dt, pawel.moll, mark.rutland, ijc+devicetree, galak
Cc: devicetree, linux-doc, linux-kernel, linux-arm-kernel, kernel,
Lee Jones, Gabriel Fernandez, Olivier Bideau
The patch supports the A9-mux clocks used by ClockGenA9
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org>
Signed-off-by: Olivier Bideau <olivier.bideau@st.com>
Acked-by: Peter Griffin <peter.griffin@linaro.org>
---
drivers/clk/st/clkgen-mux.c | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/drivers/clk/st/clkgen-mux.c b/drivers/clk/st/clkgen-mux.c
index a329906..9bdedc8 100644
--- a/drivers/clk/st/clkgen-mux.c
+++ b/drivers/clk/st/clkgen-mux.c
@@ -580,6 +580,11 @@ static struct clkgen_mux_data stih416_a9_mux_data = {
.shift = 0,
.width = 2,
};
+static struct clkgen_mux_data stih407_a9_mux_data = {
+ .offset = 0x1a4,
+ .shift = 1,
+ .width = 2,
+};
static struct of_device_id mux_of_match[] = {
{
@@ -610,6 +615,10 @@ static struct of_device_id mux_of_match[] = {
.compatible = "st,stih416-clkgen-a9-mux",
.data = &stih416_a9_mux_data,
},
+ {
+ .compatible = "st,stih407-clkgen-a9-mux",
+ .data = &stih407_a9_mux_data,
+ },
{}
};
--
1.9.1
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [PATCH v2 06/14] drivers: clk: st: STiH407: Support for A9 MUX Clocks
@ 2014-06-27 13:25 ` Gabriel FERNANDEZ
0 siblings, 0 replies; 49+ messages in thread
From: Gabriel FERNANDEZ @ 2014-06-27 13:25 UTC (permalink / raw)
To: linux-arm-kernel
The patch supports the A9-mux clocks used by ClockGenA9
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org>
Signed-off-by: Olivier Bideau <olivier.bideau@st.com>
Acked-by: Peter Griffin <peter.griffin@linaro.org>
---
drivers/clk/st/clkgen-mux.c | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/drivers/clk/st/clkgen-mux.c b/drivers/clk/st/clkgen-mux.c
index a329906..9bdedc8 100644
--- a/drivers/clk/st/clkgen-mux.c
+++ b/drivers/clk/st/clkgen-mux.c
@@ -580,6 +580,11 @@ static struct clkgen_mux_data stih416_a9_mux_data = {
.shift = 0,
.width = 2,
};
+static struct clkgen_mux_data stih407_a9_mux_data = {
+ .offset = 0x1a4,
+ .shift = 1,
+ .width = 2,
+};
static struct of_device_id mux_of_match[] = {
{
@@ -610,6 +615,10 @@ static struct of_device_id mux_of_match[] = {
.compatible = "st,stih416-clkgen-a9-mux",
.data = &stih416_a9_mux_data,
},
+ {
+ .compatible = "st,stih407-clkgen-a9-mux",
+ .data = &stih407_a9_mux_data,
+ },
{}
};
--
1.9.1
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [PATCH v2 07/14] drivers: clk: st: STiH407: Support for clockgenA0
2014-06-27 13:24 ` Gabriel FERNANDEZ
@ 2014-06-27 13:25 ` Gabriel FERNANDEZ
-1 siblings, 0 replies; 49+ messages in thread
From: Gabriel FERNANDEZ @ 2014-06-27 13:25 UTC (permalink / raw)
To: mturquette, robh+dt, pawel.moll, mark.rutland, ijc+devicetree, galak
Cc: devicetree, linux-doc, linux-kernel, linux-arm-kernel, kernel,
Lee Jones, Gabriel Fernandez, Olivier Bideau
The patch added support for DT registration of ClockGenA0
It includes c32 type PLL.
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org>
Signed-off-by: Olivier Bideau <olivier.bideau@st.com>
---
drivers/clk/st/clkgen-pll.c | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/drivers/clk/st/clkgen-pll.c b/drivers/clk/st/clkgen-pll.c
index cdf23db..d4ef4f4 100644
--- a/drivers/clk/st/clkgen-pll.c
+++ b/drivers/clk/st/clkgen-pll.c
@@ -180,6 +180,18 @@ static const struct clkgen_pll_data st_pll1200c32_gpu_416 = {
.ops = &st_pll1200c32_ops,
};
+static const struct clkgen_pll_data st_pll3200c32_407_a0 = {
+ /* 407 A0 */
+ .pdn_status = CLKGEN_FIELD(0x2a0, 0x1, 8),
+ .locked_status = CLKGEN_FIELD(0x2a0, 0x1, 24),
+ .ndiv = CLKGEN_FIELD(0x2a4, C32_NDIV_MASK, 16),
+ .idf = CLKGEN_FIELD(0x2a4, C32_IDF_MASK, 0x0),
+ .num_odfs = 1,
+ .odf = { CLKGEN_FIELD(0x2b4, C32_ODF_MASK, 0) },
+ .odf_gate = { CLKGEN_FIELD(0x2b4, 0x1, 6) },
+ .ops = &stm_pll3200c32_ops,
+};
+
/**
* DOC: Clock Generated by PLL, rate set and enabled by bootloader
*
@@ -570,6 +582,10 @@ static struct of_device_id c32_pll_of_match[] = {
.compatible = "st,stih416-plls-c32-ddr",
.data = &st_pll3200c32_ddr_416,
},
+ {
+ .compatible = "st,stih407-plls-c32-a0",
+ .data = &st_pll3200c32_407_a0,
+ },
{}
};
--
1.9.1
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [PATCH v2 07/14] drivers: clk: st: STiH407: Support for clockgenA0
@ 2014-06-27 13:25 ` Gabriel FERNANDEZ
0 siblings, 0 replies; 49+ messages in thread
From: Gabriel FERNANDEZ @ 2014-06-27 13:25 UTC (permalink / raw)
To: linux-arm-kernel
The patch added support for DT registration of ClockGenA0
It includes c32 type PLL.
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org>
Signed-off-by: Olivier Bideau <olivier.bideau@st.com>
---
drivers/clk/st/clkgen-pll.c | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/drivers/clk/st/clkgen-pll.c b/drivers/clk/st/clkgen-pll.c
index cdf23db..d4ef4f4 100644
--- a/drivers/clk/st/clkgen-pll.c
+++ b/drivers/clk/st/clkgen-pll.c
@@ -180,6 +180,18 @@ static const struct clkgen_pll_data st_pll1200c32_gpu_416 = {
.ops = &st_pll1200c32_ops,
};
+static const struct clkgen_pll_data st_pll3200c32_407_a0 = {
+ /* 407 A0 */
+ .pdn_status = CLKGEN_FIELD(0x2a0, 0x1, 8),
+ .locked_status = CLKGEN_FIELD(0x2a0, 0x1, 24),
+ .ndiv = CLKGEN_FIELD(0x2a4, C32_NDIV_MASK, 16),
+ .idf = CLKGEN_FIELD(0x2a4, C32_IDF_MASK, 0x0),
+ .num_odfs = 1,
+ .odf = { CLKGEN_FIELD(0x2b4, C32_ODF_MASK, 0) },
+ .odf_gate = { CLKGEN_FIELD(0x2b4, 0x1, 6) },
+ .ops = &stm_pll3200c32_ops,
+};
+
/**
* DOC: Clock Generated by PLL, rate set and enabled by bootloader
*
@@ -570,6 +582,10 @@ static struct of_device_id c32_pll_of_match[] = {
.compatible = "st,stih416-plls-c32-ddr",
.data = &st_pll3200c32_ddr_416,
},
+ {
+ .compatible = "st,stih407-plls-c32-a0",
+ .data = &st_pll3200c32_407_a0,
+ },
{}
};
--
1.9.1
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [PATCH v2 08/14] drivers: clk: st: Add polarity bit indication
2014-06-27 13:24 ` Gabriel FERNANDEZ
@ 2014-06-27 13:25 ` Gabriel FERNANDEZ
-1 siblings, 0 replies; 49+ messages in thread
From: Gabriel FERNANDEZ @ 2014-06-27 13:25 UTC (permalink / raw)
To: mturquette, robh+dt, pawel.moll, mark.rutland, ijc+devicetree, galak
Cc: devicetree, linux-doc, linux-kernel, linux-arm-kernel, kernel,
Lee Jones, Gabriel Fernandez
This patch introduces polarity indication for pll power up bit
and for standby bit in order to have same code between stih416
and stih407 boards.
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org>
Acked-by: Peter Griffin <peter.griffin@linaro.org>
---
drivers/clk/st/clkgen-fsyn.c | 12 +++++++-----
1 file changed, 7 insertions(+), 5 deletions(-)
diff --git a/drivers/clk/st/clkgen-fsyn.c b/drivers/clk/st/clkgen-fsyn.c
index a7e5db4..43936b6 100644
--- a/drivers/clk/st/clkgen-fsyn.c
+++ b/drivers/clk/st/clkgen-fsyn.c
@@ -67,6 +67,8 @@ struct clkgen_quadfs_data {
bool reset_present;
bool bwfilter_present;
bool lockstatus_present;
+ bool powerup_polarity;
+ bool standby_polarity;
bool nsdiv_present;
struct clkgen_field ndiv;
struct clkgen_field ref_bw;
@@ -308,7 +310,7 @@ static int quadfs_pll_enable(struct clk_hw *hw)
/*
* Power up the PLL
*/
- CLKGEN_WRITE(pll, npda, 1);
+ CLKGEN_WRITE(pll, npda, !pll->data->powerup_polarity);
if (pll->lock)
spin_unlock_irqrestore(pll->lock, flags);
@@ -335,7 +337,7 @@ static void quadfs_pll_disable(struct clk_hw *hw)
* Powerdown the PLL and then put block into soft reset if we have
* reset control.
*/
- CLKGEN_WRITE(pll, npda, 0);
+ CLKGEN_WRITE(pll, npda, pll->data->powerup_polarity);
if (pll->data->reset_present)
CLKGEN_WRITE(pll, nreset, 0);
@@ -611,7 +613,7 @@ static int quadfs_fsynth_enable(struct clk_hw *hw)
if (fs->lock)
spin_lock_irqsave(fs->lock, flags);
- CLKGEN_WRITE(fs, nsb[fs->chan], 1);
+ CLKGEN_WRITE(fs, nsb[fs->chan], !fs->data->standby_polarity);
if (fs->lock)
spin_unlock_irqrestore(fs->lock, flags);
@@ -631,7 +633,7 @@ static void quadfs_fsynth_disable(struct clk_hw *hw)
if (fs->lock)
spin_lock_irqsave(fs->lock, flags);
- CLKGEN_WRITE(fs, nsb[fs->chan], 0);
+ CLKGEN_WRITE(fs, nsb[fs->chan], !fs->data->standby_polarity);
if (fs->lock)
spin_unlock_irqrestore(fs->lock, flags);
@@ -645,7 +647,7 @@ static int quadfs_fsynth_is_enabled(struct clk_hw *hw)
pr_debug("%s: %s enable bit = 0x%x\n",
__func__, __clk_get_name(hw->clk), nsb);
- return !!nsb;
+ return fs->data->standby_polarity ? !nsb : !!nsb;
}
#define P15 (uint64_t)(1 << 15)
--
1.9.1
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [PATCH v2 08/14] drivers: clk: st: Add polarity bit indication
@ 2014-06-27 13:25 ` Gabriel FERNANDEZ
0 siblings, 0 replies; 49+ messages in thread
From: Gabriel FERNANDEZ @ 2014-06-27 13:25 UTC (permalink / raw)
To: linux-arm-kernel
This patch introduces polarity indication for pll power up bit
and for standby bit in order to have same code between stih416
and stih407 boards.
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org>
Acked-by: Peter Griffin <peter.griffin@linaro.org>
---
drivers/clk/st/clkgen-fsyn.c | 12 +++++++-----
1 file changed, 7 insertions(+), 5 deletions(-)
diff --git a/drivers/clk/st/clkgen-fsyn.c b/drivers/clk/st/clkgen-fsyn.c
index a7e5db4..43936b6 100644
--- a/drivers/clk/st/clkgen-fsyn.c
+++ b/drivers/clk/st/clkgen-fsyn.c
@@ -67,6 +67,8 @@ struct clkgen_quadfs_data {
bool reset_present;
bool bwfilter_present;
bool lockstatus_present;
+ bool powerup_polarity;
+ bool standby_polarity;
bool nsdiv_present;
struct clkgen_field ndiv;
struct clkgen_field ref_bw;
@@ -308,7 +310,7 @@ static int quadfs_pll_enable(struct clk_hw *hw)
/*
* Power up the PLL
*/
- CLKGEN_WRITE(pll, npda, 1);
+ CLKGEN_WRITE(pll, npda, !pll->data->powerup_polarity);
if (pll->lock)
spin_unlock_irqrestore(pll->lock, flags);
@@ -335,7 +337,7 @@ static void quadfs_pll_disable(struct clk_hw *hw)
* Powerdown the PLL and then put block into soft reset if we have
* reset control.
*/
- CLKGEN_WRITE(pll, npda, 0);
+ CLKGEN_WRITE(pll, npda, pll->data->powerup_polarity);
if (pll->data->reset_present)
CLKGEN_WRITE(pll, nreset, 0);
@@ -611,7 +613,7 @@ static int quadfs_fsynth_enable(struct clk_hw *hw)
if (fs->lock)
spin_lock_irqsave(fs->lock, flags);
- CLKGEN_WRITE(fs, nsb[fs->chan], 1);
+ CLKGEN_WRITE(fs, nsb[fs->chan], !fs->data->standby_polarity);
if (fs->lock)
spin_unlock_irqrestore(fs->lock, flags);
@@ -631,7 +633,7 @@ static void quadfs_fsynth_disable(struct clk_hw *hw)
if (fs->lock)
spin_lock_irqsave(fs->lock, flags);
- CLKGEN_WRITE(fs, nsb[fs->chan], 0);
+ CLKGEN_WRITE(fs, nsb[fs->chan], !fs->data->standby_polarity);
if (fs->lock)
spin_unlock_irqrestore(fs->lock, flags);
@@ -645,7 +647,7 @@ static int quadfs_fsynth_is_enabled(struct clk_hw *hw)
pr_debug("%s: %s enable bit = 0x%x\n",
__func__, __clk_get_name(hw->clk), nsb);
- return !!nsb;
+ return fs->data->standby_polarity ? !nsb : !!nsb;
}
#define P15 (uint64_t)(1 << 15)
--
1.9.1
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [PATCH v2 09/14] drivers: clk: st: Add quadfs reset handling
2014-06-27 13:24 ` Gabriel FERNANDEZ
@ 2014-06-27 13:25 ` Gabriel FERNANDEZ
-1 siblings, 0 replies; 49+ messages in thread
From: Gabriel FERNANDEZ @ 2014-06-27 13:25 UTC (permalink / raw)
To: mturquette, robh+dt, pawel.moll, mark.rutland, ijc+devicetree, galak
Cc: devicetree, linux-doc, linux-kernel, linux-arm-kernel, kernel,
Lee Jones, Gabriel Fernandez, Olivier Bideau
This patch adds the support of quadfs reset handling.
Signed-off-by: Olivier Bideau <olivier.bideau@st.com>
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org>
Acked-by: Peter Griffin <peter.griffin@linaro.org>
---
drivers/clk/st/clkgen-fsyn.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/drivers/clk/st/clkgen-fsyn.c b/drivers/clk/st/clkgen-fsyn.c
index 43936b6..b2b73f4 100644
--- a/drivers/clk/st/clkgen-fsyn.c
+++ b/drivers/clk/st/clkgen-fsyn.c
@@ -70,12 +70,14 @@ struct clkgen_quadfs_data {
bool powerup_polarity;
bool standby_polarity;
bool nsdiv_present;
+ bool nrst_present;
struct clkgen_field ndiv;
struct clkgen_field ref_bw;
struct clkgen_field nreset;
struct clkgen_field npda;
struct clkgen_field lock_status;
+ struct clkgen_field nrst[QUADFS_MAX_CHAN];
struct clkgen_field nsb[QUADFS_MAX_CHAN];
struct clkgen_field en[QUADFS_MAX_CHAN];
struct clkgen_field mdiv[QUADFS_MAX_CHAN];
@@ -615,6 +617,9 @@ static int quadfs_fsynth_enable(struct clk_hw *hw)
CLKGEN_WRITE(fs, nsb[fs->chan], !fs->data->standby_polarity);
+ if (fs->data->nrst_present)
+ CLKGEN_WRITE(fs, nrst[fs->chan], 0);
+
if (fs->lock)
spin_unlock_irqrestore(fs->lock, flags);
--
1.9.1
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [PATCH v2 09/14] drivers: clk: st: Add quadfs reset handling
@ 2014-06-27 13:25 ` Gabriel FERNANDEZ
0 siblings, 0 replies; 49+ messages in thread
From: Gabriel FERNANDEZ @ 2014-06-27 13:25 UTC (permalink / raw)
To: linux-arm-kernel
This patch adds the support of quadfs reset handling.
Signed-off-by: Olivier Bideau <olivier.bideau@st.com>
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org>
Acked-by: Peter Griffin <peter.griffin@linaro.org>
---
drivers/clk/st/clkgen-fsyn.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/drivers/clk/st/clkgen-fsyn.c b/drivers/clk/st/clkgen-fsyn.c
index 43936b6..b2b73f4 100644
--- a/drivers/clk/st/clkgen-fsyn.c
+++ b/drivers/clk/st/clkgen-fsyn.c
@@ -70,12 +70,14 @@ struct clkgen_quadfs_data {
bool powerup_polarity;
bool standby_polarity;
bool nsdiv_present;
+ bool nrst_present;
struct clkgen_field ndiv;
struct clkgen_field ref_bw;
struct clkgen_field nreset;
struct clkgen_field npda;
struct clkgen_field lock_status;
+ struct clkgen_field nrst[QUADFS_MAX_CHAN];
struct clkgen_field nsb[QUADFS_MAX_CHAN];
struct clkgen_field en[QUADFS_MAX_CHAN];
struct clkgen_field mdiv[QUADFS_MAX_CHAN];
@@ -615,6 +617,9 @@ static int quadfs_fsynth_enable(struct clk_hw *hw)
CLKGEN_WRITE(fs, nsb[fs->chan], !fs->data->standby_polarity);
+ if (fs->data->nrst_present)
+ CLKGEN_WRITE(fs, nrst[fs->chan], 0);
+
if (fs->lock)
spin_unlock_irqrestore(fs->lock, flags);
--
1.9.1
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [PATCH v2 10/14] drivers: clk: st: STiH407: Support for clockgenC0
2014-06-27 13:24 ` Gabriel FERNANDEZ
@ 2014-06-27 13:25 ` Gabriel FERNANDEZ
-1 siblings, 0 replies; 49+ messages in thread
From: Gabriel FERNANDEZ @ 2014-06-27 13:25 UTC (permalink / raw)
To: mturquette, robh+dt, pawel.moll, mark.rutland, ijc+devicetree, galak
Cc: devicetree, linux-doc, linux-kernel, linux-arm-kernel, kernel,
Lee Jones, Gabriel Fernandez, Olivier Bideau
The patch added support for DT registration of ClockGenC0
It includes 2 c32 type PLL and a 660 Quadfs.
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org>
Signed-off-by: Olivier Bideau <olivier.bideau@st.com>
Acked-by: Peter Griffin <peter.griffin@linaro.org>
---
drivers/clk/st/clkgen-fsyn.c | 47 ++++++++++++++++++++++++++++++++++++++++++++
drivers/clk/st/clkgen-pll.c | 32 ++++++++++++++++++++++++++++++
2 files changed, 79 insertions(+)
diff --git a/drivers/clk/st/clkgen-fsyn.c b/drivers/clk/st/clkgen-fsyn.c
index b2b73f4..0e0d5f9 100644
--- a/drivers/clk/st/clkgen-fsyn.c
+++ b/drivers/clk/st/clkgen-fsyn.c
@@ -255,6 +255,49 @@ static const struct clkgen_quadfs_data st_fs660c32_F_416 = {
.get_rate = clk_fs660c32_dig_get_rate,
};
+static const struct clkgen_quadfs_data st_fs660c32_C_407 = {
+ .nrst_present = true,
+ .nrst = { CLKGEN_FIELD(0x2f0, 0x1, 0),
+ CLKGEN_FIELD(0x2f0, 0x1, 1),
+ CLKGEN_FIELD(0x2f0, 0x1, 2),
+ CLKGEN_FIELD(0x2f0, 0x1, 3) },
+ .npda = CLKGEN_FIELD(0x2f0, 0x1, 12),
+ .nsb = { CLKGEN_FIELD(0x2f0, 0x1, 8),
+ CLKGEN_FIELD(0x2f0, 0x1, 9),
+ CLKGEN_FIELD(0x2f0, 0x1, 10),
+ CLKGEN_FIELD(0x2f0, 0x1, 11) },
+ .nsdiv_present = true,
+ .nsdiv = { CLKGEN_FIELD(0x304, 0x1, 24),
+ CLKGEN_FIELD(0x308, 0x1, 24),
+ CLKGEN_FIELD(0x30c, 0x1, 24),
+ CLKGEN_FIELD(0x310, 0x1, 24) },
+ .mdiv = { CLKGEN_FIELD(0x304, 0x1f, 15),
+ CLKGEN_FIELD(0x308, 0x1f, 15),
+ CLKGEN_FIELD(0x30c, 0x1f, 15),
+ CLKGEN_FIELD(0x310, 0x1f, 15) },
+ .en = { CLKGEN_FIELD(0x2fc, 0x1, 0),
+ CLKGEN_FIELD(0x2fc, 0x1, 1),
+ CLKGEN_FIELD(0x2fc, 0x1, 2),
+ CLKGEN_FIELD(0x2fc, 0x1, 3) },
+ .ndiv = CLKGEN_FIELD(0x2f4, 0x7, 16),
+ .pe = { CLKGEN_FIELD(0x304, 0x7fff, 0),
+ CLKGEN_FIELD(0x308, 0x7fff, 0),
+ CLKGEN_FIELD(0x30c, 0x7fff, 0),
+ CLKGEN_FIELD(0x310, 0x7fff, 0) },
+ .sdiv = { CLKGEN_FIELD(0x304, 0xf, 20),
+ CLKGEN_FIELD(0x308, 0xf, 20),
+ CLKGEN_FIELD(0x30c, 0xf, 20),
+ CLKGEN_FIELD(0x310, 0xf, 20) },
+ .lockstatus_present = true,
+ .lock_status = CLKGEN_FIELD(0x2A0, 0x1, 24),
+ .powerup_polarity = 1,
+ .standby_polarity = 1,
+ .pll_ops = &st_quadfs_pll_c32_ops,
+ .rtbl = fs660c32_rtbl,
+ .rtbl_cnt = ARRAY_SIZE(fs660c32_rtbl),
+ .get_rate = clk_fs660c32_dig_get_rate,
+};
+
/**
* DOC: A Frequency Synthesizer that multiples its input clock by a fixed factor
*
@@ -938,6 +981,10 @@ static struct of_device_id quadfs_of_match[] = {
.compatible = "st,stih416-quadfs660-F",
.data = (void *)&st_fs660c32_F_416
},
+ {
+ .compatible = "st,stih407-quadfs660-C",
+ .data = (void *)&st_fs660c32_C_407
+ },
{}
};
diff --git a/drivers/clk/st/clkgen-pll.c b/drivers/clk/st/clkgen-pll.c
index d4ef4f4..5327a74 100644
--- a/drivers/clk/st/clkgen-pll.c
+++ b/drivers/clk/st/clkgen-pll.c
@@ -192,6 +192,30 @@ static const struct clkgen_pll_data st_pll3200c32_407_a0 = {
.ops = &stm_pll3200c32_ops,
};
+static const struct clkgen_pll_data st_pll3200c32_407_c0_0 = {
+ /* 407 C0 PLL0 */
+ .pdn_status = CLKGEN_FIELD(0x2a0, 0x1, 8),
+ .locked_status = CLKGEN_FIELD(0x2a0, 0x1, 24),
+ .ndiv = CLKGEN_FIELD(0x2a4, C32_NDIV_MASK, 16),
+ .idf = CLKGEN_FIELD(0x2a4, C32_IDF_MASK, 0x0),
+ .num_odfs = 1,
+ .odf = { CLKGEN_FIELD(0x2b4, C32_ODF_MASK, 0) },
+ .odf_gate = { CLKGEN_FIELD(0x2b4, 0x1, 6) },
+ .ops = &stm_pll3200c32_ops,
+};
+
+static const struct clkgen_pll_data st_pll3200c32_407_c0_1 = {
+ /* 407 C0 PLL1 */
+ .pdn_status = CLKGEN_FIELD(0x2c8, 0x1, 8),
+ .locked_status = CLKGEN_FIELD(0x2c8, 0x1, 24),
+ .ndiv = CLKGEN_FIELD(0x2cc, C32_NDIV_MASK, 16),
+ .idf = CLKGEN_FIELD(0x2cc, C32_IDF_MASK, 0x0),
+ .num_odfs = 1,
+ .odf = { CLKGEN_FIELD(0x2dc, C32_ODF_MASK, 0) },
+ .odf_gate = { CLKGEN_FIELD(0x2dc, 0x1, 6) },
+ .ops = &stm_pll3200c32_ops,
+};
+
/**
* DOC: Clock Generated by PLL, rate set and enabled by bootloader
*
@@ -586,6 +610,14 @@ static struct of_device_id c32_pll_of_match[] = {
.compatible = "st,stih407-plls-c32-a0",
.data = &st_pll3200c32_407_a0,
},
+ {
+ .compatible = "st,stih407-plls-c32-c0_0",
+ .data = &st_pll3200c32_407_c0_0,
+ },
+ {
+ .compatible = "st,stih407-plls-c32-c0_1",
+ .data = &st_pll3200c32_407_c0_1,
+ },
{}
};
--
1.9.1
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [PATCH v2 10/14] drivers: clk: st: STiH407: Support for clockgenC0
@ 2014-06-27 13:25 ` Gabriel FERNANDEZ
0 siblings, 0 replies; 49+ messages in thread
From: Gabriel FERNANDEZ @ 2014-06-27 13:25 UTC (permalink / raw)
To: linux-arm-kernel
The patch added support for DT registration of ClockGenC0
It includes 2 c32 type PLL and a 660 Quadfs.
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org>
Signed-off-by: Olivier Bideau <olivier.bideau@st.com>
Acked-by: Peter Griffin <peter.griffin@linaro.org>
---
drivers/clk/st/clkgen-fsyn.c | 47 ++++++++++++++++++++++++++++++++++++++++++++
drivers/clk/st/clkgen-pll.c | 32 ++++++++++++++++++++++++++++++
2 files changed, 79 insertions(+)
diff --git a/drivers/clk/st/clkgen-fsyn.c b/drivers/clk/st/clkgen-fsyn.c
index b2b73f4..0e0d5f9 100644
--- a/drivers/clk/st/clkgen-fsyn.c
+++ b/drivers/clk/st/clkgen-fsyn.c
@@ -255,6 +255,49 @@ static const struct clkgen_quadfs_data st_fs660c32_F_416 = {
.get_rate = clk_fs660c32_dig_get_rate,
};
+static const struct clkgen_quadfs_data st_fs660c32_C_407 = {
+ .nrst_present = true,
+ .nrst = { CLKGEN_FIELD(0x2f0, 0x1, 0),
+ CLKGEN_FIELD(0x2f0, 0x1, 1),
+ CLKGEN_FIELD(0x2f0, 0x1, 2),
+ CLKGEN_FIELD(0x2f0, 0x1, 3) },
+ .npda = CLKGEN_FIELD(0x2f0, 0x1, 12),
+ .nsb = { CLKGEN_FIELD(0x2f0, 0x1, 8),
+ CLKGEN_FIELD(0x2f0, 0x1, 9),
+ CLKGEN_FIELD(0x2f0, 0x1, 10),
+ CLKGEN_FIELD(0x2f0, 0x1, 11) },
+ .nsdiv_present = true,
+ .nsdiv = { CLKGEN_FIELD(0x304, 0x1, 24),
+ CLKGEN_FIELD(0x308, 0x1, 24),
+ CLKGEN_FIELD(0x30c, 0x1, 24),
+ CLKGEN_FIELD(0x310, 0x1, 24) },
+ .mdiv = { CLKGEN_FIELD(0x304, 0x1f, 15),
+ CLKGEN_FIELD(0x308, 0x1f, 15),
+ CLKGEN_FIELD(0x30c, 0x1f, 15),
+ CLKGEN_FIELD(0x310, 0x1f, 15) },
+ .en = { CLKGEN_FIELD(0x2fc, 0x1, 0),
+ CLKGEN_FIELD(0x2fc, 0x1, 1),
+ CLKGEN_FIELD(0x2fc, 0x1, 2),
+ CLKGEN_FIELD(0x2fc, 0x1, 3) },
+ .ndiv = CLKGEN_FIELD(0x2f4, 0x7, 16),
+ .pe = { CLKGEN_FIELD(0x304, 0x7fff, 0),
+ CLKGEN_FIELD(0x308, 0x7fff, 0),
+ CLKGEN_FIELD(0x30c, 0x7fff, 0),
+ CLKGEN_FIELD(0x310, 0x7fff, 0) },
+ .sdiv = { CLKGEN_FIELD(0x304, 0xf, 20),
+ CLKGEN_FIELD(0x308, 0xf, 20),
+ CLKGEN_FIELD(0x30c, 0xf, 20),
+ CLKGEN_FIELD(0x310, 0xf, 20) },
+ .lockstatus_present = true,
+ .lock_status = CLKGEN_FIELD(0x2A0, 0x1, 24),
+ .powerup_polarity = 1,
+ .standby_polarity = 1,
+ .pll_ops = &st_quadfs_pll_c32_ops,
+ .rtbl = fs660c32_rtbl,
+ .rtbl_cnt = ARRAY_SIZE(fs660c32_rtbl),
+ .get_rate = clk_fs660c32_dig_get_rate,
+};
+
/**
* DOC: A Frequency Synthesizer that multiples its input clock by a fixed factor
*
@@ -938,6 +981,10 @@ static struct of_device_id quadfs_of_match[] = {
.compatible = "st,stih416-quadfs660-F",
.data = (void *)&st_fs660c32_F_416
},
+ {
+ .compatible = "st,stih407-quadfs660-C",
+ .data = (void *)&st_fs660c32_C_407
+ },
{}
};
diff --git a/drivers/clk/st/clkgen-pll.c b/drivers/clk/st/clkgen-pll.c
index d4ef4f4..5327a74 100644
--- a/drivers/clk/st/clkgen-pll.c
+++ b/drivers/clk/st/clkgen-pll.c
@@ -192,6 +192,30 @@ static const struct clkgen_pll_data st_pll3200c32_407_a0 = {
.ops = &stm_pll3200c32_ops,
};
+static const struct clkgen_pll_data st_pll3200c32_407_c0_0 = {
+ /* 407 C0 PLL0 */
+ .pdn_status = CLKGEN_FIELD(0x2a0, 0x1, 8),
+ .locked_status = CLKGEN_FIELD(0x2a0, 0x1, 24),
+ .ndiv = CLKGEN_FIELD(0x2a4, C32_NDIV_MASK, 16),
+ .idf = CLKGEN_FIELD(0x2a4, C32_IDF_MASK, 0x0),
+ .num_odfs = 1,
+ .odf = { CLKGEN_FIELD(0x2b4, C32_ODF_MASK, 0) },
+ .odf_gate = { CLKGEN_FIELD(0x2b4, 0x1, 6) },
+ .ops = &stm_pll3200c32_ops,
+};
+
+static const struct clkgen_pll_data st_pll3200c32_407_c0_1 = {
+ /* 407 C0 PLL1 */
+ .pdn_status = CLKGEN_FIELD(0x2c8, 0x1, 8),
+ .locked_status = CLKGEN_FIELD(0x2c8, 0x1, 24),
+ .ndiv = CLKGEN_FIELD(0x2cc, C32_NDIV_MASK, 16),
+ .idf = CLKGEN_FIELD(0x2cc, C32_IDF_MASK, 0x0),
+ .num_odfs = 1,
+ .odf = { CLKGEN_FIELD(0x2dc, C32_ODF_MASK, 0) },
+ .odf_gate = { CLKGEN_FIELD(0x2dc, 0x1, 6) },
+ .ops = &stm_pll3200c32_ops,
+};
+
/**
* DOC: Clock Generated by PLL, rate set and enabled by bootloader
*
@@ -586,6 +610,14 @@ static struct of_device_id c32_pll_of_match[] = {
.compatible = "st,stih407-plls-c32-a0",
.data = &st_pll3200c32_407_a0,
},
+ {
+ .compatible = "st,stih407-plls-c32-c0_0",
+ .data = &st_pll3200c32_407_c0_0,
+ },
+ {
+ .compatible = "st,stih407-plls-c32-c0_1",
+ .data = &st_pll3200c32_407_c0_1,
+ },
{}
};
--
1.9.1
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [PATCH v2 11/14] drivers: clk: st: STiH407: Support for clockgenD0/D2/D3
2014-06-27 13:24 ` Gabriel FERNANDEZ
@ 2014-06-27 13:25 ` Gabriel FERNANDEZ
-1 siblings, 0 replies; 49+ messages in thread
From: Gabriel FERNANDEZ @ 2014-06-27 13:25 UTC (permalink / raw)
To: mturquette, robh+dt, pawel.moll, mark.rutland, ijc+devicetree, galak
Cc: devicetree, linux-doc, linux-kernel, linux-arm-kernel, kernel,
Lee Jones, Gabriel Fernandez, Olivier Bideau
The patch added support for ClockGenD0/D2/D3
It includes one 660 Quadfs.
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org>
Signed-off-by: Olivier Bideau <olivier.bideau@st.com>
Acked-by: Peter Griffin <peter.griffin@linaro.org>
---
drivers/clk/st/clkgen-fsyn.c | 46 ++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 46 insertions(+)
diff --git a/drivers/clk/st/clkgen-fsyn.c b/drivers/clk/st/clkgen-fsyn.c
index 0e0d5f9..2b6cb1c 100644
--- a/drivers/clk/st/clkgen-fsyn.c
+++ b/drivers/clk/st/clkgen-fsyn.c
@@ -298,6 +298,48 @@ static const struct clkgen_quadfs_data st_fs660c32_C_407 = {
.get_rate = clk_fs660c32_dig_get_rate,
};
+static const struct clkgen_quadfs_data st_fs660c32_D_407 = {
+ .nrst_present = true,
+ .nrst = { CLKGEN_FIELD(0x2a0, 0x1, 0),
+ CLKGEN_FIELD(0x2a0, 0x1, 1),
+ CLKGEN_FIELD(0x2a0, 0x1, 2),
+ CLKGEN_FIELD(0x2a0, 0x1, 3) },
+ .ndiv = CLKGEN_FIELD(0x2a4, 0x7, 16),
+ .pe = { CLKGEN_FIELD(0x2b4, 0x7fff, 0),
+ CLKGEN_FIELD(0x2b8, 0x7fff, 0),
+ CLKGEN_FIELD(0x2bc, 0x7fff, 0),
+ CLKGEN_FIELD(0x2c0, 0x7fff, 0) },
+ .sdiv = { CLKGEN_FIELD(0x2b4, 0xf, 20),
+ CLKGEN_FIELD(0x2b8, 0xf, 20),
+ CLKGEN_FIELD(0x2bc, 0xf, 20),
+ CLKGEN_FIELD(0x2c0, 0xf, 20) },
+ .npda = CLKGEN_FIELD(0x2a0, 0x1, 12),
+ .nsb = { CLKGEN_FIELD(0x2a0, 0x1, 8),
+ CLKGEN_FIELD(0x2a0, 0x1, 9),
+ CLKGEN_FIELD(0x2a0, 0x1, 10),
+ CLKGEN_FIELD(0x2a0, 0x1, 11) },
+ .nsdiv_present = true,
+ .nsdiv = { CLKGEN_FIELD(0x2b4, 0x1, 24),
+ CLKGEN_FIELD(0x2b8, 0x1, 24),
+ CLKGEN_FIELD(0x2bc, 0x1, 24),
+ CLKGEN_FIELD(0x2c0, 0x1, 24) },
+ .mdiv = { CLKGEN_FIELD(0x2b4, 0x1f, 15),
+ CLKGEN_FIELD(0x2b8, 0x1f, 15),
+ CLKGEN_FIELD(0x2bc, 0x1f, 15),
+ CLKGEN_FIELD(0x2c0, 0x1f, 15) },
+ .en = { CLKGEN_FIELD(0x2ac, 0x1, 0),
+ CLKGEN_FIELD(0x2ac, 0x1, 1),
+ CLKGEN_FIELD(0x2ac, 0x1, 2),
+ CLKGEN_FIELD(0x2ac, 0x1, 3) },
+ .lockstatus_present = true,
+ .lock_status = CLKGEN_FIELD(0x2A0, 0x1, 24),
+ .powerup_polarity = 1,
+ .standby_polarity = 1,
+ .pll_ops = &st_quadfs_pll_c32_ops,
+ .rtbl = fs660c32_rtbl,
+ .rtbl_cnt = ARRAY_SIZE(fs660c32_rtbl),
+ .get_rate = clk_fs660c32_dig_get_rate,};
+
/**
* DOC: A Frequency Synthesizer that multiples its input clock by a fixed factor
*
@@ -985,6 +1027,10 @@ static struct of_device_id quadfs_of_match[] = {
.compatible = "st,stih407-quadfs660-C",
.data = (void *)&st_fs660c32_C_407
},
+ {
+ .compatible = "st,stih407-quadfs660-D",
+ .data = (void *)&st_fs660c32_D_407
+ },
{}
};
--
1.9.1
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [PATCH v2 11/14] drivers: clk: st: STiH407: Support for clockgenD0/D2/D3
@ 2014-06-27 13:25 ` Gabriel FERNANDEZ
0 siblings, 0 replies; 49+ messages in thread
From: Gabriel FERNANDEZ @ 2014-06-27 13:25 UTC (permalink / raw)
To: linux-arm-kernel
The patch added support for ClockGenD0/D2/D3
It includes one 660 Quadfs.
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org>
Signed-off-by: Olivier Bideau <olivier.bideau@st.com>
Acked-by: Peter Griffin <peter.griffin@linaro.org>
---
drivers/clk/st/clkgen-fsyn.c | 46 ++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 46 insertions(+)
diff --git a/drivers/clk/st/clkgen-fsyn.c b/drivers/clk/st/clkgen-fsyn.c
index 0e0d5f9..2b6cb1c 100644
--- a/drivers/clk/st/clkgen-fsyn.c
+++ b/drivers/clk/st/clkgen-fsyn.c
@@ -298,6 +298,48 @@ static const struct clkgen_quadfs_data st_fs660c32_C_407 = {
.get_rate = clk_fs660c32_dig_get_rate,
};
+static const struct clkgen_quadfs_data st_fs660c32_D_407 = {
+ .nrst_present = true,
+ .nrst = { CLKGEN_FIELD(0x2a0, 0x1, 0),
+ CLKGEN_FIELD(0x2a0, 0x1, 1),
+ CLKGEN_FIELD(0x2a0, 0x1, 2),
+ CLKGEN_FIELD(0x2a0, 0x1, 3) },
+ .ndiv = CLKGEN_FIELD(0x2a4, 0x7, 16),
+ .pe = { CLKGEN_FIELD(0x2b4, 0x7fff, 0),
+ CLKGEN_FIELD(0x2b8, 0x7fff, 0),
+ CLKGEN_FIELD(0x2bc, 0x7fff, 0),
+ CLKGEN_FIELD(0x2c0, 0x7fff, 0) },
+ .sdiv = { CLKGEN_FIELD(0x2b4, 0xf, 20),
+ CLKGEN_FIELD(0x2b8, 0xf, 20),
+ CLKGEN_FIELD(0x2bc, 0xf, 20),
+ CLKGEN_FIELD(0x2c0, 0xf, 20) },
+ .npda = CLKGEN_FIELD(0x2a0, 0x1, 12),
+ .nsb = { CLKGEN_FIELD(0x2a0, 0x1, 8),
+ CLKGEN_FIELD(0x2a0, 0x1, 9),
+ CLKGEN_FIELD(0x2a0, 0x1, 10),
+ CLKGEN_FIELD(0x2a0, 0x1, 11) },
+ .nsdiv_present = true,
+ .nsdiv = { CLKGEN_FIELD(0x2b4, 0x1, 24),
+ CLKGEN_FIELD(0x2b8, 0x1, 24),
+ CLKGEN_FIELD(0x2bc, 0x1, 24),
+ CLKGEN_FIELD(0x2c0, 0x1, 24) },
+ .mdiv = { CLKGEN_FIELD(0x2b4, 0x1f, 15),
+ CLKGEN_FIELD(0x2b8, 0x1f, 15),
+ CLKGEN_FIELD(0x2bc, 0x1f, 15),
+ CLKGEN_FIELD(0x2c0, 0x1f, 15) },
+ .en = { CLKGEN_FIELD(0x2ac, 0x1, 0),
+ CLKGEN_FIELD(0x2ac, 0x1, 1),
+ CLKGEN_FIELD(0x2ac, 0x1, 2),
+ CLKGEN_FIELD(0x2ac, 0x1, 3) },
+ .lockstatus_present = true,
+ .lock_status = CLKGEN_FIELD(0x2A0, 0x1, 24),
+ .powerup_polarity = 1,
+ .standby_polarity = 1,
+ .pll_ops = &st_quadfs_pll_c32_ops,
+ .rtbl = fs660c32_rtbl,
+ .rtbl_cnt = ARRAY_SIZE(fs660c32_rtbl),
+ .get_rate = clk_fs660c32_dig_get_rate,};
+
/**
* DOC: A Frequency Synthesizer that multiples its input clock by a fixed factor
*
@@ -985,6 +1027,10 @@ static struct of_device_id quadfs_of_match[] = {
.compatible = "st,stih407-quadfs660-C",
.data = (void *)&st_fs660c32_C_407
},
+ {
+ .compatible = "st,stih407-quadfs660-D",
+ .data = (void *)&st_fs660c32_D_407
+ },
{}
};
--
1.9.1
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [PATCH v2 12/14] drivers: clk: st: STiH407: Support for clockgenA9
2014-06-27 13:24 ` Gabriel FERNANDEZ
@ 2014-06-27 13:25 ` Gabriel FERNANDEZ
-1 siblings, 0 replies; 49+ messages in thread
From: Gabriel FERNANDEZ @ 2014-06-27 13:25 UTC (permalink / raw)
To: mturquette, robh+dt, pawel.moll, mark.rutland, ijc+devicetree, galak
Cc: devicetree, linux-doc, linux-kernel, linux-arm-kernel, kernel,
Lee Jones, Gabriel Fernandez, Olivier Bideau
The patch added support for DT registration of ClockGenA9
It includes c32 type PLL.
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org>
Signed-off-by: Olivier Bideau <olivier.bideau@st.com>
Acked-by: Peter Griffin <peter.griffin@linaro.org>
---
drivers/clk/st/clkgen-pll.c | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/drivers/clk/st/clkgen-pll.c b/drivers/clk/st/clkgen-pll.c
index 5327a74..29769d7 100644
--- a/drivers/clk/st/clkgen-pll.c
+++ b/drivers/clk/st/clkgen-pll.c
@@ -216,6 +216,18 @@ static const struct clkgen_pll_data st_pll3200c32_407_c0_1 = {
.ops = &stm_pll3200c32_ops,
};
+static const struct clkgen_pll_data st_pll3200c32_407_a9 = {
+ /* 407 A9 */
+ .pdn_status = CLKGEN_FIELD(0x1a8, 0x1, 0),
+ .locked_status = CLKGEN_FIELD(0x87c, 0x1, 0),
+ .ndiv = CLKGEN_FIELD(0x1b0, C32_NDIV_MASK, 0),
+ .idf = CLKGEN_FIELD(0x1a8, C32_IDF_MASK, 25),
+ .num_odfs = 1,
+ .odf = { CLKGEN_FIELD(0x1b0, C32_ODF_MASK, 8) },
+ .odf_gate = { CLKGEN_FIELD(0x1ac, 0x1, 28) },
+ .ops = &stm_pll3200c32_ops,
+};
+
/**
* DOC: Clock Generated by PLL, rate set and enabled by bootloader
*
@@ -618,6 +630,10 @@ static struct of_device_id c32_pll_of_match[] = {
.compatible = "st,stih407-plls-c32-c0_1",
.data = &st_pll3200c32_407_c0_1,
},
+ {
+ .compatible = "st,stih407-plls-c32-a9",
+ .data = &st_pll3200c32_407_a9,
+ },
{}
};
--
1.9.1
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [PATCH v2 12/14] drivers: clk: st: STiH407: Support for clockgenA9
@ 2014-06-27 13:25 ` Gabriel FERNANDEZ
0 siblings, 0 replies; 49+ messages in thread
From: Gabriel FERNANDEZ @ 2014-06-27 13:25 UTC (permalink / raw)
To: linux-arm-kernel
The patch added support for DT registration of ClockGenA9
It includes c32 type PLL.
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org>
Signed-off-by: Olivier Bideau <olivier.bideau@st.com>
Acked-by: Peter Griffin <peter.griffin@linaro.org>
---
drivers/clk/st/clkgen-pll.c | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/drivers/clk/st/clkgen-pll.c b/drivers/clk/st/clkgen-pll.c
index 5327a74..29769d7 100644
--- a/drivers/clk/st/clkgen-pll.c
+++ b/drivers/clk/st/clkgen-pll.c
@@ -216,6 +216,18 @@ static const struct clkgen_pll_data st_pll3200c32_407_c0_1 = {
.ops = &stm_pll3200c32_ops,
};
+static const struct clkgen_pll_data st_pll3200c32_407_a9 = {
+ /* 407 A9 */
+ .pdn_status = CLKGEN_FIELD(0x1a8, 0x1, 0),
+ .locked_status = CLKGEN_FIELD(0x87c, 0x1, 0),
+ .ndiv = CLKGEN_FIELD(0x1b0, C32_NDIV_MASK, 0),
+ .idf = CLKGEN_FIELD(0x1a8, C32_IDF_MASK, 25),
+ .num_odfs = 1,
+ .odf = { CLKGEN_FIELD(0x1b0, C32_ODF_MASK, 8) },
+ .odf_gate = { CLKGEN_FIELD(0x1ac, 0x1, 28) },
+ .ops = &stm_pll3200c32_ops,
+};
+
/**
* DOC: Clock Generated by PLL, rate set and enabled by bootloader
*
@@ -618,6 +630,10 @@ static struct of_device_id c32_pll_of_match[] = {
.compatible = "st,stih407-plls-c32-c0_1",
.data = &st_pll3200c32_407_c0_1,
},
+ {
+ .compatible = "st,stih407-plls-c32-a9",
+ .data = &st_pll3200c32_407_a9,
+ },
{}
};
--
1.9.1
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [PATCH v2 13/14] drivers: clk: st: Update frequency tables for fs660c32 and fs432c65
2014-06-27 13:24 ` Gabriel FERNANDEZ
@ 2014-06-27 13:25 ` Gabriel FERNANDEZ
-1 siblings, 0 replies; 49+ messages in thread
From: Gabriel FERNANDEZ @ 2014-06-27 13:25 UTC (permalink / raw)
To: mturquette, robh+dt, pawel.moll, mark.rutland, ijc+devicetree, galak
Cc: devicetree, linux-doc, linux-kernel, linux-arm-kernel, kernel,
Lee Jones, Gabriel Fernandez
This patch extend the range of possible frequencies of the fs432c65
and fs660c32 Quad frequency synthesizers.
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org>
Acked-by: Peter Griffin <peter.griffin@linaro.org>
---
drivers/clk/st/clkgen-fsyn.c | 67 ++++++++++++++++++++++++++++++++++++++------
1 file changed, 59 insertions(+), 8 deletions(-)
diff --git a/drivers/clk/st/clkgen-fsyn.c b/drivers/clk/st/clkgen-fsyn.c
index 2b6cb1c..b4a3e50 100644
--- a/drivers/clk/st/clkgen-fsyn.c
+++ b/drivers/clk/st/clkgen-fsyn.c
@@ -50,17 +50,68 @@ static const struct stm_fs fs216c65_rtbl[] = {
};
static const struct stm_fs fs432c65_rtbl[] = {
- { .mdiv = 0x1f, .pe = 0x0, .sdiv = 0x7, .nsdiv = 0 }, /* 625 Khz */
- { .mdiv = 0x11, .pe = 0x1c72, .sdiv = 0x2, .nsdiv = 1 }, /* 108 MHz */
- { .mdiv = 0x19, .pe = 0x121a, .sdiv = 0x0, .nsdiv = 1 }, /* 297 MHz */
+ { .mdiv = 0x1f, .pe = 0x0, .sdiv = 0x7, .nsdiv = 0 }, /* 625 Khz */
+ { .mdiv = 0x13, .pe = 0x777c, .sdiv = 0x4, .nsdiv = 1 }, /* 25.175 MHz */
+ { .mdiv = 0x19, .pe = 0x4d35, .sdiv = 0x2, .nsdiv = 0 }, /* 25.200 MHz */
+ { .mdiv = 0x11, .pe = 0x1c72, .sdiv = 0x4, .nsdiv = 1 }, /* 27.000 MHz */
+ { .mdiv = 0x17, .pe = 0x28f5, .sdiv = 0x2, .nsdiv = 0 }, /* 27.027 MHz */
+ { .mdiv = 0x16, .pe = 0x3359, .sdiv = 0x2, .nsdiv = 0 }, /* 28.320 MHz */
+ { .mdiv = 0x1f, .pe = 0x2083, .sdiv = 0x3, .nsdiv = 1 }, /* 30.240 MHz */
+ { .mdiv = 0x1e, .pe = 0x430d, .sdiv = 0x3, .nsdiv = 1 }, /* 31.500 MHz */
+ { .mdiv = 0x17, .pe = 0x0, .sdiv = 0x3, .nsdiv = 1 }, /* 40.000 MHz */
+ { .mdiv = 0x19, .pe = 0x121a, .sdiv = 0x1, .nsdiv = 0 }, /* 49.500 MHz */
+ { .mdiv = 0x13, .pe = 0x6667, .sdiv = 0x3, .nsdiv = 1 }, /* 50.000 MHz */
+ { .mdiv = 0x10, .pe = 0x1ee6, .sdiv = 0x3, .nsdiv = 1 }, /* 57.284 MHz */
+ { .mdiv = 0x1d, .pe = 0x3b14, .sdiv = 0x2, .nsdiv = 1 }, /* 65.000 MHz */
+ { .mdiv = 0x12, .pe = 0x7c65, .sdiv = 0x1, .nsdiv = 0 }, /* 71.000 MHz */
+ { .mdiv = 0x19, .pe = 0xecd, .sdiv = 0x2, .nsdiv = 1 }, /* 74.176 MHz */
+ { .mdiv = 0x19, .pe = 0x121a, .sdiv = 0x2, .nsdiv = 1 }, /* 74.250 MHz */
+ { .mdiv = 0x19, .pe = 0x3334, .sdiv = 0x2, .nsdiv = 1 }, /* 75.000 MHz */
+ { .mdiv = 0x18, .pe = 0x5138, .sdiv = 0x2, .nsdiv = 1 }, /* 78.800 MHz */
+ { .mdiv = 0x1d, .pe = 0x77d, .sdiv = 0x0, .nsdiv = 0 }, /* 85.500 MHz */
+ { .mdiv = 0x1c, .pe = 0x13d5, .sdiv = 0x0, .nsdiv = 0 }, /* 88.750 MHz */
+ { .mdiv = 0x11, .pe = 0x1c72, .sdiv = 0x2, .nsdiv = 1 }, /* 108.000 MHz */
+ { .mdiv = 0x17, .pe = 0x28f5, .sdiv = 0x0, .nsdiv = 0 }, /* 108.108 MHz */
+ { .mdiv = 0x10, .pe = 0x6e26, .sdiv = 0x2, .nsdiv = 1 }, /* 118.963 MHz */
+ { .mdiv = 0x15, .pe = 0x3e63, .sdiv = 0x0, .nsdiv = 0 }, /* 119.000 MHz */
+ { .mdiv = 0x1c, .pe = 0x471d, .sdiv = 0x1, .nsdiv = 1 }, /* 135.000 MHz */
+ { .mdiv = 0x19, .pe = 0xecd, .sdiv = 0x1, .nsdiv = 1 }, /* 148.352 MHz */
+ { .mdiv = 0x19, .pe = 0x121a, .sdiv = 0x1, .nsdiv = 1 }, /* 148.500 MHz */
+ { .mdiv = 0x19, .pe = 0x121a, .sdiv = 0x0, .nsdiv = 1 }, /* 297 MHz */
};
static const struct stm_fs fs660c32_rtbl[] = {
- { .mdiv = 0x01, .pe = 0x2aaa, .sdiv = 0x8, .nsdiv = 0 }, /* 600 KHz */
- { .mdiv = 0x02, .pe = 0x3d33, .sdiv = 0x0, .nsdiv = 0 }, /* 148.5 Mhz */
- { .mdiv = 0x13, .pe = 0x5bcc, .sdiv = 0x0, .nsdiv = 1 }, /* 297 Mhz */
- { .mdiv = 0x0e, .pe = 0x1025, .sdiv = 0x0, .nsdiv = 1 }, /* 333 Mhz */
- { .mdiv = 0x0b, .pe = 0x715f, .sdiv = 0x0, .nsdiv = 1 }, /* 350 Mhz */
+ { .mdiv = 0x14, .pe = 0x376b, .sdiv = 0x4, .nsdiv = 1 }, /* 25.175 MHz */
+ { .mdiv = 0x14, .pe = 0x30c3, .sdiv = 0x4, .nsdiv = 1 }, /* 25.200 MHz */
+ { .mdiv = 0x10, .pe = 0x71c7, .sdiv = 0x4, .nsdiv = 1 }, /* 27.000 MHz */
+ { .mdiv = 0x00, .pe = 0x47af, .sdiv = 0x3, .nsdiv = 0 }, /* 27.027 MHz */
+ { .mdiv = 0x0e, .pe = 0x4e1a, .sdiv = 0x4, .nsdiv = 1 }, /* 28.320 MHz */
+ { .mdiv = 0x0b, .pe = 0x534d, .sdiv = 0x4, .nsdiv = 1 }, /* 30.240 MHz */
+ { .mdiv = 0x17, .pe = 0x6fbf, .sdiv = 0x2, .nsdiv = 0 }, /* 31.500 MHz */
+ { .mdiv = 0x01, .pe = 0x0, .sdiv = 0x4, .nsdiv = 1 }, /* 40.000 MHz */
+ { .mdiv = 0x15, .pe = 0x2aab, .sdiv = 0x3, .nsdiv = 1 }, /* 49.500 MHz */
+ { .mdiv = 0x14, .pe = 0x6666, .sdiv = 0x3, .nsdiv = 1 }, /* 50.000 MHz */
+ { .mdiv = 0x1d, .pe = 0x395f, .sdiv = 0x1, .nsdiv = 0 }, /* 57.284 MHz */
+ { .mdiv = 0x08, .pe = 0x4ec5, .sdiv = 0x3, .nsdiv = 1 }, /* 65.000 MHz */
+ { .mdiv = 0x05, .pe = 0x1770, .sdiv = 0x3, .nsdiv = 1 }, /* 71.000 MHz */
+ { .mdiv = 0x03, .pe = 0x4ba7, .sdiv = 0x3, .nsdiv = 1 }, /* 74.176 MHz */
+ { .mdiv = 0x0f, .pe = 0x3426, .sdiv = 0x1, .nsdiv = 0 }, /* 74.250 MHz */
+ { .mdiv = 0x0e, .pe = 0x7777, .sdiv = 0x1, .nsdiv = 0 }, /* 75.000 MHz */
+ { .mdiv = 0x01, .pe = 0x4053, .sdiv = 0x3, .nsdiv = 1 }, /* 78.800 MHz */
+ { .mdiv = 0x09, .pe = 0x15b5, .sdiv = 0x1, .nsdiv = 0 }, /* 85.500 MHz */
+ { .mdiv = 0x1b, .pe = 0x3f19, .sdiv = 0x2, .nsdiv = 1 }, /* 88.750 MHz */
+ { .mdiv = 0x10, .pe = 0x71c7, .sdiv = 0x2, .nsdiv = 1 }, /* 108.000 MHz */
+ { .mdiv = 0x00, .pe = 0x47af, .sdiv = 0x1, .nsdiv = 0 }, /* 108.108 MHz */
+ { .mdiv = 0x0c, .pe = 0x3118, .sdiv = 0x2, .nsdiv = 1 }, /* 118.963 MHz */
+ { .mdiv = 0x0c, .pe = 0x2f54, .sdiv = 0x2, .nsdiv = 1 }, /* 119.000 MHz */
+ { .mdiv = 0x07, .pe = 0xe39, .sdiv = 0x2, .nsdiv = 1 }, /* 135.000 MHz */
+ { .mdiv = 0x03, .pe = 0x4ba7, .sdiv = 0x2, .nsdiv = 1 }, /* 148.352 MHz */
+ { .mdiv = 0x0f, .pe = 0x3426, .sdiv = 0x0, .nsdiv = 0 }, /* 148.500 MHz */
+ { .mdiv = 0x03, .pe = 0x4ba7, .sdiv = 0x1, .nsdiv = 1 }, /* 296.704 MHz */
+ { .mdiv = 0x03, .pe = 0x471c, .sdiv = 0x1, .nsdiv = 1 }, /* 297.000 MHz */
+ { .mdiv = 0x00, .pe = 0x295f, .sdiv = 0x1, .nsdiv = 1 }, /* 326.700 MHz */
+ { .mdiv = 0x1f, .pe = 0x3633, .sdiv = 0x0, .nsdiv = 1 }, /* 333.000 MHz */
+ { .mdiv = 0x1c, .pe = 0x0, .sdiv = 0x0, .nsdiv = 1 }, /* 352.000 Mhz */
};
struct clkgen_quadfs_data {
--
1.9.1
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [PATCH v2 13/14] drivers: clk: st: Update frequency tables for fs660c32 and fs432c65
@ 2014-06-27 13:25 ` Gabriel FERNANDEZ
0 siblings, 0 replies; 49+ messages in thread
From: Gabriel FERNANDEZ @ 2014-06-27 13:25 UTC (permalink / raw)
To: linux-arm-kernel
This patch extend the range of possible frequencies of the fs432c65
and fs660c32 Quad frequency synthesizers.
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org>
Acked-by: Peter Griffin <peter.griffin@linaro.org>
---
drivers/clk/st/clkgen-fsyn.c | 67 ++++++++++++++++++++++++++++++++++++++------
1 file changed, 59 insertions(+), 8 deletions(-)
diff --git a/drivers/clk/st/clkgen-fsyn.c b/drivers/clk/st/clkgen-fsyn.c
index 2b6cb1c..b4a3e50 100644
--- a/drivers/clk/st/clkgen-fsyn.c
+++ b/drivers/clk/st/clkgen-fsyn.c
@@ -50,17 +50,68 @@ static const struct stm_fs fs216c65_rtbl[] = {
};
static const struct stm_fs fs432c65_rtbl[] = {
- { .mdiv = 0x1f, .pe = 0x0, .sdiv = 0x7, .nsdiv = 0 }, /* 625 Khz */
- { .mdiv = 0x11, .pe = 0x1c72, .sdiv = 0x2, .nsdiv = 1 }, /* 108 MHz */
- { .mdiv = 0x19, .pe = 0x121a, .sdiv = 0x0, .nsdiv = 1 }, /* 297 MHz */
+ { .mdiv = 0x1f, .pe = 0x0, .sdiv = 0x7, .nsdiv = 0 }, /* 625 Khz */
+ { .mdiv = 0x13, .pe = 0x777c, .sdiv = 0x4, .nsdiv = 1 }, /* 25.175 MHz */
+ { .mdiv = 0x19, .pe = 0x4d35, .sdiv = 0x2, .nsdiv = 0 }, /* 25.200 MHz */
+ { .mdiv = 0x11, .pe = 0x1c72, .sdiv = 0x4, .nsdiv = 1 }, /* 27.000 MHz */
+ { .mdiv = 0x17, .pe = 0x28f5, .sdiv = 0x2, .nsdiv = 0 }, /* 27.027 MHz */
+ { .mdiv = 0x16, .pe = 0x3359, .sdiv = 0x2, .nsdiv = 0 }, /* 28.320 MHz */
+ { .mdiv = 0x1f, .pe = 0x2083, .sdiv = 0x3, .nsdiv = 1 }, /* 30.240 MHz */
+ { .mdiv = 0x1e, .pe = 0x430d, .sdiv = 0x3, .nsdiv = 1 }, /* 31.500 MHz */
+ { .mdiv = 0x17, .pe = 0x0, .sdiv = 0x3, .nsdiv = 1 }, /* 40.000 MHz */
+ { .mdiv = 0x19, .pe = 0x121a, .sdiv = 0x1, .nsdiv = 0 }, /* 49.500 MHz */
+ { .mdiv = 0x13, .pe = 0x6667, .sdiv = 0x3, .nsdiv = 1 }, /* 50.000 MHz */
+ { .mdiv = 0x10, .pe = 0x1ee6, .sdiv = 0x3, .nsdiv = 1 }, /* 57.284 MHz */
+ { .mdiv = 0x1d, .pe = 0x3b14, .sdiv = 0x2, .nsdiv = 1 }, /* 65.000 MHz */
+ { .mdiv = 0x12, .pe = 0x7c65, .sdiv = 0x1, .nsdiv = 0 }, /* 71.000 MHz */
+ { .mdiv = 0x19, .pe = 0xecd, .sdiv = 0x2, .nsdiv = 1 }, /* 74.176 MHz */
+ { .mdiv = 0x19, .pe = 0x121a, .sdiv = 0x2, .nsdiv = 1 }, /* 74.250 MHz */
+ { .mdiv = 0x19, .pe = 0x3334, .sdiv = 0x2, .nsdiv = 1 }, /* 75.000 MHz */
+ { .mdiv = 0x18, .pe = 0x5138, .sdiv = 0x2, .nsdiv = 1 }, /* 78.800 MHz */
+ { .mdiv = 0x1d, .pe = 0x77d, .sdiv = 0x0, .nsdiv = 0 }, /* 85.500 MHz */
+ { .mdiv = 0x1c, .pe = 0x13d5, .sdiv = 0x0, .nsdiv = 0 }, /* 88.750 MHz */
+ { .mdiv = 0x11, .pe = 0x1c72, .sdiv = 0x2, .nsdiv = 1 }, /* 108.000 MHz */
+ { .mdiv = 0x17, .pe = 0x28f5, .sdiv = 0x0, .nsdiv = 0 }, /* 108.108 MHz */
+ { .mdiv = 0x10, .pe = 0x6e26, .sdiv = 0x2, .nsdiv = 1 }, /* 118.963 MHz */
+ { .mdiv = 0x15, .pe = 0x3e63, .sdiv = 0x0, .nsdiv = 0 }, /* 119.000 MHz */
+ { .mdiv = 0x1c, .pe = 0x471d, .sdiv = 0x1, .nsdiv = 1 }, /* 135.000 MHz */
+ { .mdiv = 0x19, .pe = 0xecd, .sdiv = 0x1, .nsdiv = 1 }, /* 148.352 MHz */
+ { .mdiv = 0x19, .pe = 0x121a, .sdiv = 0x1, .nsdiv = 1 }, /* 148.500 MHz */
+ { .mdiv = 0x19, .pe = 0x121a, .sdiv = 0x0, .nsdiv = 1 }, /* 297 MHz */
};
static const struct stm_fs fs660c32_rtbl[] = {
- { .mdiv = 0x01, .pe = 0x2aaa, .sdiv = 0x8, .nsdiv = 0 }, /* 600 KHz */
- { .mdiv = 0x02, .pe = 0x3d33, .sdiv = 0x0, .nsdiv = 0 }, /* 148.5 Mhz */
- { .mdiv = 0x13, .pe = 0x5bcc, .sdiv = 0x0, .nsdiv = 1 }, /* 297 Mhz */
- { .mdiv = 0x0e, .pe = 0x1025, .sdiv = 0x0, .nsdiv = 1 }, /* 333 Mhz */
- { .mdiv = 0x0b, .pe = 0x715f, .sdiv = 0x0, .nsdiv = 1 }, /* 350 Mhz */
+ { .mdiv = 0x14, .pe = 0x376b, .sdiv = 0x4, .nsdiv = 1 }, /* 25.175 MHz */
+ { .mdiv = 0x14, .pe = 0x30c3, .sdiv = 0x4, .nsdiv = 1 }, /* 25.200 MHz */
+ { .mdiv = 0x10, .pe = 0x71c7, .sdiv = 0x4, .nsdiv = 1 }, /* 27.000 MHz */
+ { .mdiv = 0x00, .pe = 0x47af, .sdiv = 0x3, .nsdiv = 0 }, /* 27.027 MHz */
+ { .mdiv = 0x0e, .pe = 0x4e1a, .sdiv = 0x4, .nsdiv = 1 }, /* 28.320 MHz */
+ { .mdiv = 0x0b, .pe = 0x534d, .sdiv = 0x4, .nsdiv = 1 }, /* 30.240 MHz */
+ { .mdiv = 0x17, .pe = 0x6fbf, .sdiv = 0x2, .nsdiv = 0 }, /* 31.500 MHz */
+ { .mdiv = 0x01, .pe = 0x0, .sdiv = 0x4, .nsdiv = 1 }, /* 40.000 MHz */
+ { .mdiv = 0x15, .pe = 0x2aab, .sdiv = 0x3, .nsdiv = 1 }, /* 49.500 MHz */
+ { .mdiv = 0x14, .pe = 0x6666, .sdiv = 0x3, .nsdiv = 1 }, /* 50.000 MHz */
+ { .mdiv = 0x1d, .pe = 0x395f, .sdiv = 0x1, .nsdiv = 0 }, /* 57.284 MHz */
+ { .mdiv = 0x08, .pe = 0x4ec5, .sdiv = 0x3, .nsdiv = 1 }, /* 65.000 MHz */
+ { .mdiv = 0x05, .pe = 0x1770, .sdiv = 0x3, .nsdiv = 1 }, /* 71.000 MHz */
+ { .mdiv = 0x03, .pe = 0x4ba7, .sdiv = 0x3, .nsdiv = 1 }, /* 74.176 MHz */
+ { .mdiv = 0x0f, .pe = 0x3426, .sdiv = 0x1, .nsdiv = 0 }, /* 74.250 MHz */
+ { .mdiv = 0x0e, .pe = 0x7777, .sdiv = 0x1, .nsdiv = 0 }, /* 75.000 MHz */
+ { .mdiv = 0x01, .pe = 0x4053, .sdiv = 0x3, .nsdiv = 1 }, /* 78.800 MHz */
+ { .mdiv = 0x09, .pe = 0x15b5, .sdiv = 0x1, .nsdiv = 0 }, /* 85.500 MHz */
+ { .mdiv = 0x1b, .pe = 0x3f19, .sdiv = 0x2, .nsdiv = 1 }, /* 88.750 MHz */
+ { .mdiv = 0x10, .pe = 0x71c7, .sdiv = 0x2, .nsdiv = 1 }, /* 108.000 MHz */
+ { .mdiv = 0x00, .pe = 0x47af, .sdiv = 0x1, .nsdiv = 0 }, /* 108.108 MHz */
+ { .mdiv = 0x0c, .pe = 0x3118, .sdiv = 0x2, .nsdiv = 1 }, /* 118.963 MHz */
+ { .mdiv = 0x0c, .pe = 0x2f54, .sdiv = 0x2, .nsdiv = 1 }, /* 119.000 MHz */
+ { .mdiv = 0x07, .pe = 0xe39, .sdiv = 0x2, .nsdiv = 1 }, /* 135.000 MHz */
+ { .mdiv = 0x03, .pe = 0x4ba7, .sdiv = 0x2, .nsdiv = 1 }, /* 148.352 MHz */
+ { .mdiv = 0x0f, .pe = 0x3426, .sdiv = 0x0, .nsdiv = 0 }, /* 148.500 MHz */
+ { .mdiv = 0x03, .pe = 0x4ba7, .sdiv = 0x1, .nsdiv = 1 }, /* 296.704 MHz */
+ { .mdiv = 0x03, .pe = 0x471c, .sdiv = 0x1, .nsdiv = 1 }, /* 297.000 MHz */
+ { .mdiv = 0x00, .pe = 0x295f, .sdiv = 0x1, .nsdiv = 1 }, /* 326.700 MHz */
+ { .mdiv = 0x1f, .pe = 0x3633, .sdiv = 0x0, .nsdiv = 1 }, /* 333.000 MHz */
+ { .mdiv = 0x1c, .pe = 0x0, .sdiv = 0x0, .nsdiv = 1 }, /* 352.000 Mhz */
};
struct clkgen_quadfs_data {
--
1.9.1
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [PATCH v2 14/14] drivers: clk: st: Use round to closest divider flag
2014-06-27 13:24 ` Gabriel FERNANDEZ
@ 2014-06-27 13:25 ` Gabriel FERNANDEZ
-1 siblings, 0 replies; 49+ messages in thread
From: Gabriel FERNANDEZ @ 2014-06-27 13:25 UTC (permalink / raw)
To: mturquette, robh+dt, pawel.moll, mark.rutland, ijc+devicetree, galak
Cc: devicetree, linux-doc, linux-kernel, linux-arm-kernel, kernel,
Lee Jones, Gabriel Fernandez
This patch uses CLK_DIVIDER_ROUND_CLOSEST flag to specify
the divider has to round to closest div.
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org>
Acked-by: Peter Griffin <peter.griffin@linaro.org>
---
drivers/clk/st/clkgen-mux.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/st/clkgen-mux.c b/drivers/clk/st/clkgen-mux.c
index 9bdedc8..79dc40b 100644
--- a/drivers/clk/st/clkgen-mux.c
+++ b/drivers/clk/st/clkgen-mux.c
@@ -774,7 +774,8 @@ void __init st_of_clkgen_vcc_setup(struct device_node *np)
div->reg = reg + VCC_DIV_OFFSET;
div->shift = 2 * i;
div->width = 2;
- div->flags = CLK_DIVIDER_POWER_OF_TWO;
+ div->flags = CLK_DIVIDER_POWER_OF_TWO |
+ CLK_DIVIDER_ROUND_CLOSEST;
mux->reg = reg + VCC_MUX_OFFSET;
mux->shift = 2 * i;
--
1.9.1
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [PATCH v2 14/14] drivers: clk: st: Use round to closest divider flag
@ 2014-06-27 13:25 ` Gabriel FERNANDEZ
0 siblings, 0 replies; 49+ messages in thread
From: Gabriel FERNANDEZ @ 2014-06-27 13:25 UTC (permalink / raw)
To: linux-arm-kernel
This patch uses CLK_DIVIDER_ROUND_CLOSEST flag to specify
the divider has to round to closest div.
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org>
Acked-by: Peter Griffin <peter.griffin@linaro.org>
---
drivers/clk/st/clkgen-mux.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/st/clkgen-mux.c b/drivers/clk/st/clkgen-mux.c
index 9bdedc8..79dc40b 100644
--- a/drivers/clk/st/clkgen-mux.c
+++ b/drivers/clk/st/clkgen-mux.c
@@ -774,7 +774,8 @@ void __init st_of_clkgen_vcc_setup(struct device_node *np)
div->reg = reg + VCC_DIV_OFFSET;
div->shift = 2 * i;
div->width = 2;
- div->flags = CLK_DIVIDER_POWER_OF_TWO;
+ div->flags = CLK_DIVIDER_POWER_OF_TWO |
+ CLK_DIVIDER_ROUND_CLOSEST;
mux->reg = reg + VCC_MUX_OFFSET;
mux->shift = 2 * i;
--
1.9.1
^ permalink raw reply related [flat|nested] 49+ messages in thread
* Re: [PATCH v2 01/14] clk: st: Update ST clock binding documentation
2014-06-27 13:24 ` Gabriel FERNANDEZ
(?)
@ 2014-06-30 9:23 ` Mark Rutland
-1 siblings, 0 replies; 49+ messages in thread
From: Mark Rutland @ 2014-06-30 9:23 UTC (permalink / raw)
To: Gabriel FERNANDEZ
Cc: mturquette, robh+dt, Pawel Moll, ijc+devicetree, galak,
devicetree, linux-doc, linux-kernel, linux-arm-kernel, kernel,
Lee Jones, Gabriel Fernandez
On Fri, Jun 27, 2014 at 02:24:58PM +0100, Gabriel FERNANDEZ wrote:
> This patch adds new compatibilities to support STiH407 SoC.
This doesn't seem to match the patch, which seems to relabel nodes,
rename nodes, change clock-output-names, _and_ adds some new compatible
strings.
Therefore this commit message is completely inappropriate for the patch.
It doesn't match the diff and it doesn't tell me why you are making the
changes below.
NAK until that is fixed.
Mark.
>
> Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org>
> Acked-by: Peter Griffin <peter.griffin@linaro.org>
> ---
> .../bindings/clock/st/st,clkgen-divmux.txt | 28 +++++------
> .../devicetree/bindings/clock/st/st,clkgen-mux.txt | 6 +--
> .../devicetree/bindings/clock/st/st,clkgen-pll.txt | 17 ++++---
> .../bindings/clock/st/st,clkgen-prediv.txt | 8 ++--
> .../devicetree/bindings/clock/st/st,clkgen-vcc.txt | 34 ++++++++------
> .../devicetree/bindings/clock/st/st,clkgen.txt | 54 +++++++++++++---------
> .../devicetree/bindings/clock/st/st,quadfs.txt | 15 +++---
> 7 files changed, 94 insertions(+), 68 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/clock/st/st,clkgen-divmux.txt b/Documentation/devicetree/bindings/clock/st/st,clkgen-divmux.txt
> index ae56315..6247652 100644
> --- a/Documentation/devicetree/bindings/clock/st/st,clkgen-divmux.txt
> +++ b/Documentation/devicetree/bindings/clock/st/st,clkgen-divmux.txt
> @@ -24,26 +24,26 @@ Required properties:
>
> Example:
>
> - clockgenA@fd345000 {
> + clockgen-a@fd345000 {
> reg = <0xfd345000 0xb50>;
>
> - CLK_M_A1_DIV1: CLK_M_A1_DIV1 {
> + clk_m_a1_div1: clk-m-a1-div1 {
> #clock-cells = <1>;
> compatible = "st,clkgena-divmux-c32-odf1",
> "st,clkgena-divmux";
>
> - clocks = <&CLK_M_A1_OSC_PREDIV>,
> - <&CLK_M_A1_PLL0 1>, /* PLL0 PHI1 */
> - <&CLK_M_A1_PLL1 1>; /* PLL1 PHI1 */
> -
> - clock-output-names = "CLK_M_RX_ICN_TS",
> - "CLK_M_RX_ICN_VDP_0",
> - "", /* Unused */
> - "CLK_M_PRV_T1_BUS",
> - "CLK_M_ICN_REG_12",
> - "CLK_M_ICN_REG_10",
> - "", /* Unused */
> - "CLK_M_ICN_ST231";
> + clocks = <&clk_m_a1_osc_prediv>,
> + <&clk_m_a1_pll0 1>, /* PLL0 PHI1 */
> + <&clk_m_a1_pll1 1>; /* PLL1 PHI1 */
> +
> + clock-output-names = "clk-m-rx-icn-ts",
> + "clk-m-rx-icn-vdp-0",
> + "", /* unused */
> + "clk-m-prv-t1-bus",
> + "clk-m-icn-reg-12",
> + "clk-m-icn-reg-10",
> + "", /* unused */
> + "clk-m-icn-st231";
> };
> };
>
> diff --git a/Documentation/devicetree/bindings/clock/st/st,clkgen-mux.txt b/Documentation/devicetree/bindings/clock/st/st,clkgen-mux.txt
> index 943e080..f1fa91c 100644
> --- a/Documentation/devicetree/bindings/clock/st/st,clkgen-mux.txt
> +++ b/Documentation/devicetree/bindings/clock/st/st,clkgen-mux.txt
> @@ -17,7 +17,7 @@ Required properties:
> "st,stih416-clkgenf-vcc-sd", "st,clkgen-mux"
> "st,stih415-clkgen-a9-mux", "st,clkgen-mux"
> "st,stih416-clkgen-a9-mux", "st,clkgen-mux"
> -
> + "st,stih407-clkgen-a9-mux", "st,clkgen-mux"
>
> - #clock-cells : from common clock binding; shall be set to 0.
>
> @@ -27,10 +27,10 @@ Required properties:
>
> Example:
>
> - CLK_M_HVA: CLK_M_HVA {
> + clk_m_hva: clk-m-hva@fd690868 {
> #clock-cells = <0>;
> compatible = "st,stih416-clkgenf-vcc-hva", "st,clkgen-mux";
> reg = <0xfd690868 4>;
>
> - clocks = <&CLOCKGEN_F 1>, <&CLK_M_A1_DIV0 3>;
> + clocks = <&clockgen_f 1>, <&clk_m_a1_div0 3>;
> };
> diff --git a/Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt b/Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt
> index 81eb385..efb51cf 100644
> --- a/Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt
> +++ b/Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt
> @@ -19,11 +19,14 @@ Required properties:
> "st,stih415-plls-c32-ddr", "st,clkgen-plls-c32"
> "st,stih416-plls-c32-a9", "st,clkgen-plls-c32"
> "st,stih416-plls-c32-ddr", "st,clkgen-plls-c32"
> + "st,stih407-plls-c32-a0", "st,clkgen-plls-c32"
> + "st,stih407-plls-c32-a9", "st,clkgen-plls-c32"
> + "st,stih407-plls-c32-c0_0", "st,clkgen-plls-c32"
> + "st,stih407-plls-c32-c0_1", "st,clkgen-plls-c32"
>
> "st,stih415-gpu-pll-c32", "st,clkgengpu-pll-c32"
> "st,stih416-gpu-pll-c32", "st,clkgengpu-pll-c32"
>
> -
> - #clock-cells : From common clock binding; shall be set to 1.
>
> - clocks : From common clock binding
> @@ -32,17 +35,17 @@ Required properties:
>
> Example:
>
> - clockgenA@fee62000 {
> + clockgen-a@fee62000 {
> reg = <0xfee62000 0xb48>;
>
> - CLK_S_A0_PLL: CLK_S_A0_PLL {
> + clk_s_a0_pll: clk-s-a0-pll {
> #clock-cells = <1>;
> compatible = "st,clkgena-plls-c65";
>
> - clocks = <&CLK_SYSIN>;
> + clocks = <&clk_sysin>;
>
> - clock-output-names = "CLK_S_A0_PLL0_HS",
> - "CLK_S_A0_PLL0_LS",
> - "CLK_S_A0_PLL1";
> + clock-output-names = "clk-s-a0-pll0-hs",
> + "clk-s-a0-pll0-ls",
> + "clk-s-a0-pll1";
> };
> };
> diff --git a/Documentation/devicetree/bindings/clock/st/st,clkgen-prediv.txt b/Documentation/devicetree/bindings/clock/st/st,clkgen-prediv.txt
> index 566c9d7..604766c 100644
> --- a/Documentation/devicetree/bindings/clock/st/st,clkgen-prediv.txt
> +++ b/Documentation/devicetree/bindings/clock/st/st,clkgen-prediv.txt
> @@ -20,17 +20,17 @@ Required properties:
>
> Example:
>
> - clockgenA@fd345000 {
> + clockgen-a@fd345000 {
> reg = <0xfd345000 0xb50>;
>
> - CLK_M_A2_OSC_PREDIV: CLK_M_A2_OSC_PREDIV {
> + clk_m_a2_osc_prediv: clk-m-a2-osc-prediv {
> #clock-cells = <0>;
> compatible = "st,clkgena-prediv-c32",
> "st,clkgena-prediv";
>
> - clocks = <&CLK_SYSIN>;
> + clocks = <&clk_sysin>;
>
> - clock-output-names = "CLK_M_A2_OSC_PREDIV";
> + clock-output-names = "clk-m-a2-osc-prediv";
> };
> };
>
> diff --git a/Documentation/devicetree/bindings/clock/st/st,clkgen-vcc.txt b/Documentation/devicetree/bindings/clock/st/st,clkgen-vcc.txt
> index 4e3ff28..109b3ed 100644
> --- a/Documentation/devicetree/bindings/clock/st/st,clkgen-vcc.txt
> +++ b/Documentation/devicetree/bindings/clock/st/st,clkgen-vcc.txt
> @@ -32,22 +32,30 @@ Required properties:
>
> Example:
>
> - CLOCKGEN_C_VCC: CLOCKGEN_C_VCC {
> + clockgen_c_vcc: clockgen-c-vcc@0xfe8308ac {
> #clock-cells = <1>;
> compatible = "st,stih416-clkgenc", "st,clkgen-vcc";
> reg = <0xfe8308ac 12>;
>
> - clocks = <&CLK_S_VCC_HD>, <&CLOCKGEN_C 1>,
> - <&CLK_S_TMDS_FROMPHY>, <&CLOCKGEN_C 2>;
> -
> - clock-output-names =
> - "CLK_S_PIX_HDMI", "CLK_S_PIX_DVO",
> - "CLK_S_OUT_DVO", "CLK_S_PIX_HD",
> - "CLK_S_HDDAC", "CLK_S_DENC",
> - "CLK_S_SDDAC", "CLK_S_PIX_MAIN",
> - "CLK_S_PIX_AUX", "CLK_S_STFE_FRC_0",
> - "CLK_S_REF_MCRU", "CLK_S_SLAVE_MCRU",
> - "CLK_S_TMDS_HDMI", "CLK_S_HDMI_REJECT_PLL",
> - "CLK_S_THSENS";
> + clocks = <&clk_s_vcc_hd>,
> + <&clockgen_c 1>,
> + <&clk_s_tmds_fromphy>,
> + <&clockgen_c 2>;
> +
> + clock-output-names = "clk-s-pix-hdmi",
> + "clk-s-pix-dvo",
> + "clk-s-out-dvo",
> + "clk-s-pix-hd",
> + "clk-s-hddac",
> + "clk-s-denc",
> + "clk-s-sddac",
> + "clk-s-pix-main",
> + "clk-s-pix-aux",
> + "clk-s-stfe-frc-0",
> + "clk-s-ref-mcru",
> + "clk-s-slave-mcru",
> + "clk-s-tmds-hdmi",
> + "clk-s-hdmi-reject-pll",
> + "clk-s-thsens";
> };
>
> diff --git a/Documentation/devicetree/bindings/clock/st/st,clkgen.txt b/Documentation/devicetree/bindings/clock/st/st,clkgen.txt
> index 49ec5ae..427bad8 100644
> --- a/Documentation/devicetree/bindings/clock/st/st,clkgen.txt
> +++ b/Documentation/devicetree/bindings/clock/st/st,clkgen.txt
> @@ -24,60 +24,72 @@ address is common of all subnode.
> quadfs_node {
> ...
> };
> +
> + mux_node {
> + ...
> + };
> +
> + vcc_node {
> + ...
> + };
> ...
> };
>
> This binding uses the common clock binding[1].
> -Each subnode should use the binding discribe in [2]..[4]
> +Each subnode should use the binding discribe in [2]..[7]
>
> [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
> -[2] Documentation/devicetree/bindings/clock/st,quadfs.txt
> -[3] Documentation/devicetree/bindings/clock/st,quadfs.txt
> -[4] Documentation/devicetree/bindings/clock/st,quadfs.txt
> +[2] Documentation/devicetree/bindings/clock/st,clkgen-divmux.txt
> +[3] Documentation/devicetree/bindings/clock/st,clkgen-mux.txt
> +[4] Documentation/devicetree/bindings/clock/st,clkgen-pll.txt
> +[5] Documentation/devicetree/bindings/clock/st,clkgen-prediv.txt
> +[6] Documentation/devicetree/bindings/clock/st,vcc.txt
> +[7] Documentation/devicetree/bindings/clock/st,quadfs.txt
> +
>
> Required properties:
> - reg : A Base address and length of the register set.
>
> Example:
>
> - clockgenA@fee62000 {
> + clockgen-a@fee62000 {
>
> reg = <0xfee62000 0xb48>;
>
> - CLK_S_A0_PLL: CLK_S_A0_PLL {
> + clk_s_a0_pll: clk-s-a0-pll {
> #clock-cells = <1>;
> compatible = "st,clkgena-plls-c65";
>
> - clocks = <&CLK_SYSIN>;
> + clocks = <&clk-sysin>;
>
> - clock-output-names = "CLK_S_A0_PLL0_HS",
> - "CLK_S_A0_PLL0_LS",
> - "CLK_S_A0_PLL1";
> + clock-output-names = "clk-s-a0-pll0-hs",
> + "clk-s-a0-pll0-ls",
> + "clk-s-a0-pll1";
> };
>
> - CLK_S_A0_OSC_PREDIV: CLK_S_A0_OSC_PREDIV {
> + clk_s_a0_osc_prediv: clk-s-a0-osc-prediv {
> #clock-cells = <0>;
> compatible = "st,clkgena-prediv-c65",
> "st,clkgena-prediv";
>
> - clocks = <&CLK_SYSIN>;
> + clocks = <&clk_sysin>;
>
> - clock-output-names = "CLK_S_A0_OSC_PREDIV";
> + clock-output-names = "clk-s-a0-osc-prediv";
> };
>
> - CLK_S_A0_HS: CLK_S_A0_HS {
> + clk_s_a0_hs: clk-s-a0-hs {
> #clock-cells = <1>;
> compatible = "st,clkgena-divmux-c65-hs",
> "st,clkgena-divmux";
>
> - clocks = <&CLK_S_A0_OSC_PREDIV>,
> - <&CLK_S_A0_PLL 0>, /* PLL0 HS */
> - <&CLK_S_A0_PLL 2>; /* PLL1 */
> + clocks = <&clk-s_a0_osc_prediv>,
> + <&clk-s_a0_pll 0>, /* pll0 hs */
> + <&clk-s_a0_pll 2>; /* pll1 */
>
> - clock-output-names = "CLK_S_FDMA_0",
> - "CLK_S_FDMA_1",
> - ""; /* CLK_S_JIT_SENSE */
> - /* Fourth output unused */
> + clock-output-names = "clk-s-fdma-0",
> + "clk-s-fdma-1",
> + ""; /* clk-s-jit-sense */
> + /* fourth output unused */
> };
> };
>
> diff --git a/Documentation/devicetree/bindings/clock/st/st,quadfs.txt b/Documentation/devicetree/bindings/clock/st/st,quadfs.txt
> index ec86d62..cedeb9c 100644
> --- a/Documentation/devicetree/bindings/clock/st/st,quadfs.txt
> +++ b/Documentation/devicetree/bindings/clock/st/st,quadfs.txt
> @@ -15,6 +15,9 @@ Required properties:
> "st,stih416-quadfs432", "st,quadfs"
> "st,stih416-quadfs660-E", "st,quadfs"
> "st,stih416-quadfs660-F", "st,quadfs"
> + "st,stih407-quadfs660-C", "st,quadfs"
> + "st,stih407-quadfs660-D", "st,quadfs"
> +
>
> - #clock-cells : from common clock binding; shall be set to 1.
>
> @@ -32,14 +35,14 @@ Required properties:
>
> Example:
>
> - CLOCKGEN_E: CLOCKGEN_E {
> + clockgen_e: clockgen-e@fd3208bc {
> #clock-cells = <1>;
> compatible = "st,stih416-quadfs660-E", "st,quadfs";
> reg = <0xfd3208bc 0xB0>;
>
> - clocks = <&CLK_SYSIN>;
> - clock-output-names = "CLK_M_PIX_MDTP_0",
> - "CLK_M_PIX_MDTP_1",
> - "CLK_M_PIX_MDTP_2",
> - "CLK_M_MPELPC";
> + clocks = <&clk_sysin>;
> + clock-output-names = "clk-m-pix-mdtp-0",
> + "clk-m-pix-mdtp-1",
> + "clk-m-pix-mdtp-2",
> + "clk-m-mpelpc";
> };
> --
> 1.9.1
>
>
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PATCH v2 01/14] clk: st: Update ST clock binding documentation
@ 2014-06-30 9:23 ` Mark Rutland
0 siblings, 0 replies; 49+ messages in thread
From: Mark Rutland @ 2014-06-30 9:23 UTC (permalink / raw)
To: Gabriel FERNANDEZ
Cc: mturquette, robh+dt, Pawel Moll, ijc+devicetree, galak,
devicetree, linux-doc, linux-kernel, linux-arm-kernel, kernel,
Lee Jones, Gabriel Fernandez
On Fri, Jun 27, 2014 at 02:24:58PM +0100, Gabriel FERNANDEZ wrote:
> This patch adds new compatibilities to support STiH407 SoC.
This doesn't seem to match the patch, which seems to relabel nodes,
rename nodes, change clock-output-names, _and_ adds some new compatible
strings.
Therefore this commit message is completely inappropriate for the patch.
It doesn't match the diff and it doesn't tell me why you are making the
changes below.
NAK until that is fixed.
Mark.
>
> Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org>
> Acked-by: Peter Griffin <peter.griffin@linaro.org>
> ---
> .../bindings/clock/st/st,clkgen-divmux.txt | 28 +++++------
> .../devicetree/bindings/clock/st/st,clkgen-mux.txt | 6 +--
> .../devicetree/bindings/clock/st/st,clkgen-pll.txt | 17 ++++---
> .../bindings/clock/st/st,clkgen-prediv.txt | 8 ++--
> .../devicetree/bindings/clock/st/st,clkgen-vcc.txt | 34 ++++++++------
> .../devicetree/bindings/clock/st/st,clkgen.txt | 54 +++++++++++++---------
> .../devicetree/bindings/clock/st/st,quadfs.txt | 15 +++---
> 7 files changed, 94 insertions(+), 68 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/clock/st/st,clkgen-divmux.txt b/Documentation/devicetree/bindings/clock/st/st,clkgen-divmux.txt
> index ae56315..6247652 100644
> --- a/Documentation/devicetree/bindings/clock/st/st,clkgen-divmux.txt
> +++ b/Documentation/devicetree/bindings/clock/st/st,clkgen-divmux.txt
> @@ -24,26 +24,26 @@ Required properties:
>
> Example:
>
> - clockgenA@fd345000 {
> + clockgen-a@fd345000 {
> reg = <0xfd345000 0xb50>;
>
> - CLK_M_A1_DIV1: CLK_M_A1_DIV1 {
> + clk_m_a1_div1: clk-m-a1-div1 {
> #clock-cells = <1>;
> compatible = "st,clkgena-divmux-c32-odf1",
> "st,clkgena-divmux";
>
> - clocks = <&CLK_M_A1_OSC_PREDIV>,
> - <&CLK_M_A1_PLL0 1>, /* PLL0 PHI1 */
> - <&CLK_M_A1_PLL1 1>; /* PLL1 PHI1 */
> -
> - clock-output-names = "CLK_M_RX_ICN_TS",
> - "CLK_M_RX_ICN_VDP_0",
> - "", /* Unused */
> - "CLK_M_PRV_T1_BUS",
> - "CLK_M_ICN_REG_12",
> - "CLK_M_ICN_REG_10",
> - "", /* Unused */
> - "CLK_M_ICN_ST231";
> + clocks = <&clk_m_a1_osc_prediv>,
> + <&clk_m_a1_pll0 1>, /* PLL0 PHI1 */
> + <&clk_m_a1_pll1 1>; /* PLL1 PHI1 */
> +
> + clock-output-names = "clk-m-rx-icn-ts",
> + "clk-m-rx-icn-vdp-0",
> + "", /* unused */
> + "clk-m-prv-t1-bus",
> + "clk-m-icn-reg-12",
> + "clk-m-icn-reg-10",
> + "", /* unused */
> + "clk-m-icn-st231";
> };
> };
>
> diff --git a/Documentation/devicetree/bindings/clock/st/st,clkgen-mux.txt b/Documentation/devicetree/bindings/clock/st/st,clkgen-mux.txt
> index 943e080..f1fa91c 100644
> --- a/Documentation/devicetree/bindings/clock/st/st,clkgen-mux.txt
> +++ b/Documentation/devicetree/bindings/clock/st/st,clkgen-mux.txt
> @@ -17,7 +17,7 @@ Required properties:
> "st,stih416-clkgenf-vcc-sd", "st,clkgen-mux"
> "st,stih415-clkgen-a9-mux", "st,clkgen-mux"
> "st,stih416-clkgen-a9-mux", "st,clkgen-mux"
> -
> + "st,stih407-clkgen-a9-mux", "st,clkgen-mux"
>
> - #clock-cells : from common clock binding; shall be set to 0.
>
> @@ -27,10 +27,10 @@ Required properties:
>
> Example:
>
> - CLK_M_HVA: CLK_M_HVA {
> + clk_m_hva: clk-m-hva@fd690868 {
> #clock-cells = <0>;
> compatible = "st,stih416-clkgenf-vcc-hva", "st,clkgen-mux";
> reg = <0xfd690868 4>;
>
> - clocks = <&CLOCKGEN_F 1>, <&CLK_M_A1_DIV0 3>;
> + clocks = <&clockgen_f 1>, <&clk_m_a1_div0 3>;
> };
> diff --git a/Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt b/Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt
> index 81eb385..efb51cf 100644
> --- a/Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt
> +++ b/Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt
> @@ -19,11 +19,14 @@ Required properties:
> "st,stih415-plls-c32-ddr", "st,clkgen-plls-c32"
> "st,stih416-plls-c32-a9", "st,clkgen-plls-c32"
> "st,stih416-plls-c32-ddr", "st,clkgen-plls-c32"
> + "st,stih407-plls-c32-a0", "st,clkgen-plls-c32"
> + "st,stih407-plls-c32-a9", "st,clkgen-plls-c32"
> + "st,stih407-plls-c32-c0_0", "st,clkgen-plls-c32"
> + "st,stih407-plls-c32-c0_1", "st,clkgen-plls-c32"
>
> "st,stih415-gpu-pll-c32", "st,clkgengpu-pll-c32"
> "st,stih416-gpu-pll-c32", "st,clkgengpu-pll-c32"
>
> -
> - #clock-cells : From common clock binding; shall be set to 1.
>
> - clocks : From common clock binding
> @@ -32,17 +35,17 @@ Required properties:
>
> Example:
>
> - clockgenA@fee62000 {
> + clockgen-a@fee62000 {
> reg = <0xfee62000 0xb48>;
>
> - CLK_S_A0_PLL: CLK_S_A0_PLL {
> + clk_s_a0_pll: clk-s-a0-pll {
> #clock-cells = <1>;
> compatible = "st,clkgena-plls-c65";
>
> - clocks = <&CLK_SYSIN>;
> + clocks = <&clk_sysin>;
>
> - clock-output-names = "CLK_S_A0_PLL0_HS",
> - "CLK_S_A0_PLL0_LS",
> - "CLK_S_A0_PLL1";
> + clock-output-names = "clk-s-a0-pll0-hs",
> + "clk-s-a0-pll0-ls",
> + "clk-s-a0-pll1";
> };
> };
> diff --git a/Documentation/devicetree/bindings/clock/st/st,clkgen-prediv.txt b/Documentation/devicetree/bindings/clock/st/st,clkgen-prediv.txt
> index 566c9d7..604766c 100644
> --- a/Documentation/devicetree/bindings/clock/st/st,clkgen-prediv.txt
> +++ b/Documentation/devicetree/bindings/clock/st/st,clkgen-prediv.txt
> @@ -20,17 +20,17 @@ Required properties:
>
> Example:
>
> - clockgenA@fd345000 {
> + clockgen-a@fd345000 {
> reg = <0xfd345000 0xb50>;
>
> - CLK_M_A2_OSC_PREDIV: CLK_M_A2_OSC_PREDIV {
> + clk_m_a2_osc_prediv: clk-m-a2-osc-prediv {
> #clock-cells = <0>;
> compatible = "st,clkgena-prediv-c32",
> "st,clkgena-prediv";
>
> - clocks = <&CLK_SYSIN>;
> + clocks = <&clk_sysin>;
>
> - clock-output-names = "CLK_M_A2_OSC_PREDIV";
> + clock-output-names = "clk-m-a2-osc-prediv";
> };
> };
>
> diff --git a/Documentation/devicetree/bindings/clock/st/st,clkgen-vcc.txt b/Documentation/devicetree/bindings/clock/st/st,clkgen-vcc.txt
> index 4e3ff28..109b3ed 100644
> --- a/Documentation/devicetree/bindings/clock/st/st,clkgen-vcc.txt
> +++ b/Documentation/devicetree/bindings/clock/st/st,clkgen-vcc.txt
> @@ -32,22 +32,30 @@ Required properties:
>
> Example:
>
> - CLOCKGEN_C_VCC: CLOCKGEN_C_VCC {
> + clockgen_c_vcc: clockgen-c-vcc@0xfe8308ac {
> #clock-cells = <1>;
> compatible = "st,stih416-clkgenc", "st,clkgen-vcc";
> reg = <0xfe8308ac 12>;
>
> - clocks = <&CLK_S_VCC_HD>, <&CLOCKGEN_C 1>,
> - <&CLK_S_TMDS_FROMPHY>, <&CLOCKGEN_C 2>;
> -
> - clock-output-names =
> - "CLK_S_PIX_HDMI", "CLK_S_PIX_DVO",
> - "CLK_S_OUT_DVO", "CLK_S_PIX_HD",
> - "CLK_S_HDDAC", "CLK_S_DENC",
> - "CLK_S_SDDAC", "CLK_S_PIX_MAIN",
> - "CLK_S_PIX_AUX", "CLK_S_STFE_FRC_0",
> - "CLK_S_REF_MCRU", "CLK_S_SLAVE_MCRU",
> - "CLK_S_TMDS_HDMI", "CLK_S_HDMI_REJECT_PLL",
> - "CLK_S_THSENS";
> + clocks = <&clk_s_vcc_hd>,
> + <&clockgen_c 1>,
> + <&clk_s_tmds_fromphy>,
> + <&clockgen_c 2>;
> +
> + clock-output-names = "clk-s-pix-hdmi",
> + "clk-s-pix-dvo",
> + "clk-s-out-dvo",
> + "clk-s-pix-hd",
> + "clk-s-hddac",
> + "clk-s-denc",
> + "clk-s-sddac",
> + "clk-s-pix-main",
> + "clk-s-pix-aux",
> + "clk-s-stfe-frc-0",
> + "clk-s-ref-mcru",
> + "clk-s-slave-mcru",
> + "clk-s-tmds-hdmi",
> + "clk-s-hdmi-reject-pll",
> + "clk-s-thsens";
> };
>
> diff --git a/Documentation/devicetree/bindings/clock/st/st,clkgen.txt b/Documentation/devicetree/bindings/clock/st/st,clkgen.txt
> index 49ec5ae..427bad8 100644
> --- a/Documentation/devicetree/bindings/clock/st/st,clkgen.txt
> +++ b/Documentation/devicetree/bindings/clock/st/st,clkgen.txt
> @@ -24,60 +24,72 @@ address is common of all subnode.
> quadfs_node {
> ...
> };
> +
> + mux_node {
> + ...
> + };
> +
> + vcc_node {
> + ...
> + };
> ...
> };
>
> This binding uses the common clock binding[1].
> -Each subnode should use the binding discribe in [2]..[4]
> +Each subnode should use the binding discribe in [2]..[7]
>
> [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
> -[2] Documentation/devicetree/bindings/clock/st,quadfs.txt
> -[3] Documentation/devicetree/bindings/clock/st,quadfs.txt
> -[4] Documentation/devicetree/bindings/clock/st,quadfs.txt
> +[2] Documentation/devicetree/bindings/clock/st,clkgen-divmux.txt
> +[3] Documentation/devicetree/bindings/clock/st,clkgen-mux.txt
> +[4] Documentation/devicetree/bindings/clock/st,clkgen-pll.txt
> +[5] Documentation/devicetree/bindings/clock/st,clkgen-prediv.txt
> +[6] Documentation/devicetree/bindings/clock/st,vcc.txt
> +[7] Documentation/devicetree/bindings/clock/st,quadfs.txt
> +
>
> Required properties:
> - reg : A Base address and length of the register set.
>
> Example:
>
> - clockgenA@fee62000 {
> + clockgen-a@fee62000 {
>
> reg = <0xfee62000 0xb48>;
>
> - CLK_S_A0_PLL: CLK_S_A0_PLL {
> + clk_s_a0_pll: clk-s-a0-pll {
> #clock-cells = <1>;
> compatible = "st,clkgena-plls-c65";
>
> - clocks = <&CLK_SYSIN>;
> + clocks = <&clk-sysin>;
>
> - clock-output-names = "CLK_S_A0_PLL0_HS",
> - "CLK_S_A0_PLL0_LS",
> - "CLK_S_A0_PLL1";
> + clock-output-names = "clk-s-a0-pll0-hs",
> + "clk-s-a0-pll0-ls",
> + "clk-s-a0-pll1";
> };
>
> - CLK_S_A0_OSC_PREDIV: CLK_S_A0_OSC_PREDIV {
> + clk_s_a0_osc_prediv: clk-s-a0-osc-prediv {
> #clock-cells = <0>;
> compatible = "st,clkgena-prediv-c65",
> "st,clkgena-prediv";
>
> - clocks = <&CLK_SYSIN>;
> + clocks = <&clk_sysin>;
>
> - clock-output-names = "CLK_S_A0_OSC_PREDIV";
> + clock-output-names = "clk-s-a0-osc-prediv";
> };
>
> - CLK_S_A0_HS: CLK_S_A0_HS {
> + clk_s_a0_hs: clk-s-a0-hs {
> #clock-cells = <1>;
> compatible = "st,clkgena-divmux-c65-hs",
> "st,clkgena-divmux";
>
> - clocks = <&CLK_S_A0_OSC_PREDIV>,
> - <&CLK_S_A0_PLL 0>, /* PLL0 HS */
> - <&CLK_S_A0_PLL 2>; /* PLL1 */
> + clocks = <&clk-s_a0_osc_prediv>,
> + <&clk-s_a0_pll 0>, /* pll0 hs */
> + <&clk-s_a0_pll 2>; /* pll1 */
>
> - clock-output-names = "CLK_S_FDMA_0",
> - "CLK_S_FDMA_1",
> - ""; /* CLK_S_JIT_SENSE */
> - /* Fourth output unused */
> + clock-output-names = "clk-s-fdma-0",
> + "clk-s-fdma-1",
> + ""; /* clk-s-jit-sense */
> + /* fourth output unused */
> };
> };
>
> diff --git a/Documentation/devicetree/bindings/clock/st/st,quadfs.txt b/Documentation/devicetree/bindings/clock/st/st,quadfs.txt
> index ec86d62..cedeb9c 100644
> --- a/Documentation/devicetree/bindings/clock/st/st,quadfs.txt
> +++ b/Documentation/devicetree/bindings/clock/st/st,quadfs.txt
> @@ -15,6 +15,9 @@ Required properties:
> "st,stih416-quadfs432", "st,quadfs"
> "st,stih416-quadfs660-E", "st,quadfs"
> "st,stih416-quadfs660-F", "st,quadfs"
> + "st,stih407-quadfs660-C", "st,quadfs"
> + "st,stih407-quadfs660-D", "st,quadfs"
> +
>
> - #clock-cells : from common clock binding; shall be set to 1.
>
> @@ -32,14 +35,14 @@ Required properties:
>
> Example:
>
> - CLOCKGEN_E: CLOCKGEN_E {
> + clockgen_e: clockgen-e@fd3208bc {
> #clock-cells = <1>;
> compatible = "st,stih416-quadfs660-E", "st,quadfs";
> reg = <0xfd3208bc 0xB0>;
>
> - clocks = <&CLK_SYSIN>;
> - clock-output-names = "CLK_M_PIX_MDTP_0",
> - "CLK_M_PIX_MDTP_1",
> - "CLK_M_PIX_MDTP_2",
> - "CLK_M_MPELPC";
> + clocks = <&clk_sysin>;
> + clock-output-names = "clk-m-pix-mdtp-0",
> + "clk-m-pix-mdtp-1",
> + "clk-m-pix-mdtp-2",
> + "clk-m-mpelpc";
> };
> --
> 1.9.1
>
>
^ permalink raw reply [flat|nested] 49+ messages in thread
* [PATCH v2 01/14] clk: st: Update ST clock binding documentation
@ 2014-06-30 9:23 ` Mark Rutland
0 siblings, 0 replies; 49+ messages in thread
From: Mark Rutland @ 2014-06-30 9:23 UTC (permalink / raw)
To: linux-arm-kernel
On Fri, Jun 27, 2014 at 02:24:58PM +0100, Gabriel FERNANDEZ wrote:
> This patch adds new compatibilities to support STiH407 SoC.
This doesn't seem to match the patch, which seems to relabel nodes,
rename nodes, change clock-output-names, _and_ adds some new compatible
strings.
Therefore this commit message is completely inappropriate for the patch.
It doesn't match the diff and it doesn't tell me why you are making the
changes below.
NAK until that is fixed.
Mark.
>
> Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org>
> Acked-by: Peter Griffin <peter.griffin@linaro.org>
> ---
> .../bindings/clock/st/st,clkgen-divmux.txt | 28 +++++------
> .../devicetree/bindings/clock/st/st,clkgen-mux.txt | 6 +--
> .../devicetree/bindings/clock/st/st,clkgen-pll.txt | 17 ++++---
> .../bindings/clock/st/st,clkgen-prediv.txt | 8 ++--
> .../devicetree/bindings/clock/st/st,clkgen-vcc.txt | 34 ++++++++------
> .../devicetree/bindings/clock/st/st,clkgen.txt | 54 +++++++++++++---------
> .../devicetree/bindings/clock/st/st,quadfs.txt | 15 +++---
> 7 files changed, 94 insertions(+), 68 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/clock/st/st,clkgen-divmux.txt b/Documentation/devicetree/bindings/clock/st/st,clkgen-divmux.txt
> index ae56315..6247652 100644
> --- a/Documentation/devicetree/bindings/clock/st/st,clkgen-divmux.txt
> +++ b/Documentation/devicetree/bindings/clock/st/st,clkgen-divmux.txt
> @@ -24,26 +24,26 @@ Required properties:
>
> Example:
>
> - clockgenA at fd345000 {
> + clockgen-a at fd345000 {
> reg = <0xfd345000 0xb50>;
>
> - CLK_M_A1_DIV1: CLK_M_A1_DIV1 {
> + clk_m_a1_div1: clk-m-a1-div1 {
> #clock-cells = <1>;
> compatible = "st,clkgena-divmux-c32-odf1",
> "st,clkgena-divmux";
>
> - clocks = <&CLK_M_A1_OSC_PREDIV>,
> - <&CLK_M_A1_PLL0 1>, /* PLL0 PHI1 */
> - <&CLK_M_A1_PLL1 1>; /* PLL1 PHI1 */
> -
> - clock-output-names = "CLK_M_RX_ICN_TS",
> - "CLK_M_RX_ICN_VDP_0",
> - "", /* Unused */
> - "CLK_M_PRV_T1_BUS",
> - "CLK_M_ICN_REG_12",
> - "CLK_M_ICN_REG_10",
> - "", /* Unused */
> - "CLK_M_ICN_ST231";
> + clocks = <&clk_m_a1_osc_prediv>,
> + <&clk_m_a1_pll0 1>, /* PLL0 PHI1 */
> + <&clk_m_a1_pll1 1>; /* PLL1 PHI1 */
> +
> + clock-output-names = "clk-m-rx-icn-ts",
> + "clk-m-rx-icn-vdp-0",
> + "", /* unused */
> + "clk-m-prv-t1-bus",
> + "clk-m-icn-reg-12",
> + "clk-m-icn-reg-10",
> + "", /* unused */
> + "clk-m-icn-st231";
> };
> };
>
> diff --git a/Documentation/devicetree/bindings/clock/st/st,clkgen-mux.txt b/Documentation/devicetree/bindings/clock/st/st,clkgen-mux.txt
> index 943e080..f1fa91c 100644
> --- a/Documentation/devicetree/bindings/clock/st/st,clkgen-mux.txt
> +++ b/Documentation/devicetree/bindings/clock/st/st,clkgen-mux.txt
> @@ -17,7 +17,7 @@ Required properties:
> "st,stih416-clkgenf-vcc-sd", "st,clkgen-mux"
> "st,stih415-clkgen-a9-mux", "st,clkgen-mux"
> "st,stih416-clkgen-a9-mux", "st,clkgen-mux"
> -
> + "st,stih407-clkgen-a9-mux", "st,clkgen-mux"
>
> - #clock-cells : from common clock binding; shall be set to 0.
>
> @@ -27,10 +27,10 @@ Required properties:
>
> Example:
>
> - CLK_M_HVA: CLK_M_HVA {
> + clk_m_hva: clk-m-hva at fd690868 {
> #clock-cells = <0>;
> compatible = "st,stih416-clkgenf-vcc-hva", "st,clkgen-mux";
> reg = <0xfd690868 4>;
>
> - clocks = <&CLOCKGEN_F 1>, <&CLK_M_A1_DIV0 3>;
> + clocks = <&clockgen_f 1>, <&clk_m_a1_div0 3>;
> };
> diff --git a/Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt b/Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt
> index 81eb385..efb51cf 100644
> --- a/Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt
> +++ b/Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt
> @@ -19,11 +19,14 @@ Required properties:
> "st,stih415-plls-c32-ddr", "st,clkgen-plls-c32"
> "st,stih416-plls-c32-a9", "st,clkgen-plls-c32"
> "st,stih416-plls-c32-ddr", "st,clkgen-plls-c32"
> + "st,stih407-plls-c32-a0", "st,clkgen-plls-c32"
> + "st,stih407-plls-c32-a9", "st,clkgen-plls-c32"
> + "st,stih407-plls-c32-c0_0", "st,clkgen-plls-c32"
> + "st,stih407-plls-c32-c0_1", "st,clkgen-plls-c32"
>
> "st,stih415-gpu-pll-c32", "st,clkgengpu-pll-c32"
> "st,stih416-gpu-pll-c32", "st,clkgengpu-pll-c32"
>
> -
> - #clock-cells : From common clock binding; shall be set to 1.
>
> - clocks : From common clock binding
> @@ -32,17 +35,17 @@ Required properties:
>
> Example:
>
> - clockgenA at fee62000 {
> + clockgen-a at fee62000 {
> reg = <0xfee62000 0xb48>;
>
> - CLK_S_A0_PLL: CLK_S_A0_PLL {
> + clk_s_a0_pll: clk-s-a0-pll {
> #clock-cells = <1>;
> compatible = "st,clkgena-plls-c65";
>
> - clocks = <&CLK_SYSIN>;
> + clocks = <&clk_sysin>;
>
> - clock-output-names = "CLK_S_A0_PLL0_HS",
> - "CLK_S_A0_PLL0_LS",
> - "CLK_S_A0_PLL1";
> + clock-output-names = "clk-s-a0-pll0-hs",
> + "clk-s-a0-pll0-ls",
> + "clk-s-a0-pll1";
> };
> };
> diff --git a/Documentation/devicetree/bindings/clock/st/st,clkgen-prediv.txt b/Documentation/devicetree/bindings/clock/st/st,clkgen-prediv.txt
> index 566c9d7..604766c 100644
> --- a/Documentation/devicetree/bindings/clock/st/st,clkgen-prediv.txt
> +++ b/Documentation/devicetree/bindings/clock/st/st,clkgen-prediv.txt
> @@ -20,17 +20,17 @@ Required properties:
>
> Example:
>
> - clockgenA at fd345000 {
> + clockgen-a at fd345000 {
> reg = <0xfd345000 0xb50>;
>
> - CLK_M_A2_OSC_PREDIV: CLK_M_A2_OSC_PREDIV {
> + clk_m_a2_osc_prediv: clk-m-a2-osc-prediv {
> #clock-cells = <0>;
> compatible = "st,clkgena-prediv-c32",
> "st,clkgena-prediv";
>
> - clocks = <&CLK_SYSIN>;
> + clocks = <&clk_sysin>;
>
> - clock-output-names = "CLK_M_A2_OSC_PREDIV";
> + clock-output-names = "clk-m-a2-osc-prediv";
> };
> };
>
> diff --git a/Documentation/devicetree/bindings/clock/st/st,clkgen-vcc.txt b/Documentation/devicetree/bindings/clock/st/st,clkgen-vcc.txt
> index 4e3ff28..109b3ed 100644
> --- a/Documentation/devicetree/bindings/clock/st/st,clkgen-vcc.txt
> +++ b/Documentation/devicetree/bindings/clock/st/st,clkgen-vcc.txt
> @@ -32,22 +32,30 @@ Required properties:
>
> Example:
>
> - CLOCKGEN_C_VCC: CLOCKGEN_C_VCC {
> + clockgen_c_vcc: clockgen-c-vcc at 0xfe8308ac {
> #clock-cells = <1>;
> compatible = "st,stih416-clkgenc", "st,clkgen-vcc";
> reg = <0xfe8308ac 12>;
>
> - clocks = <&CLK_S_VCC_HD>, <&CLOCKGEN_C 1>,
> - <&CLK_S_TMDS_FROMPHY>, <&CLOCKGEN_C 2>;
> -
> - clock-output-names =
> - "CLK_S_PIX_HDMI", "CLK_S_PIX_DVO",
> - "CLK_S_OUT_DVO", "CLK_S_PIX_HD",
> - "CLK_S_HDDAC", "CLK_S_DENC",
> - "CLK_S_SDDAC", "CLK_S_PIX_MAIN",
> - "CLK_S_PIX_AUX", "CLK_S_STFE_FRC_0",
> - "CLK_S_REF_MCRU", "CLK_S_SLAVE_MCRU",
> - "CLK_S_TMDS_HDMI", "CLK_S_HDMI_REJECT_PLL",
> - "CLK_S_THSENS";
> + clocks = <&clk_s_vcc_hd>,
> + <&clockgen_c 1>,
> + <&clk_s_tmds_fromphy>,
> + <&clockgen_c 2>;
> +
> + clock-output-names = "clk-s-pix-hdmi",
> + "clk-s-pix-dvo",
> + "clk-s-out-dvo",
> + "clk-s-pix-hd",
> + "clk-s-hddac",
> + "clk-s-denc",
> + "clk-s-sddac",
> + "clk-s-pix-main",
> + "clk-s-pix-aux",
> + "clk-s-stfe-frc-0",
> + "clk-s-ref-mcru",
> + "clk-s-slave-mcru",
> + "clk-s-tmds-hdmi",
> + "clk-s-hdmi-reject-pll",
> + "clk-s-thsens";
> };
>
> diff --git a/Documentation/devicetree/bindings/clock/st/st,clkgen.txt b/Documentation/devicetree/bindings/clock/st/st,clkgen.txt
> index 49ec5ae..427bad8 100644
> --- a/Documentation/devicetree/bindings/clock/st/st,clkgen.txt
> +++ b/Documentation/devicetree/bindings/clock/st/st,clkgen.txt
> @@ -24,60 +24,72 @@ address is common of all subnode.
> quadfs_node {
> ...
> };
> +
> + mux_node {
> + ...
> + };
> +
> + vcc_node {
> + ...
> + };
> ...
> };
>
> This binding uses the common clock binding[1].
> -Each subnode should use the binding discribe in [2]..[4]
> +Each subnode should use the binding discribe in [2]..[7]
>
> [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
> -[2] Documentation/devicetree/bindings/clock/st,quadfs.txt
> -[3] Documentation/devicetree/bindings/clock/st,quadfs.txt
> -[4] Documentation/devicetree/bindings/clock/st,quadfs.txt
> +[2] Documentation/devicetree/bindings/clock/st,clkgen-divmux.txt
> +[3] Documentation/devicetree/bindings/clock/st,clkgen-mux.txt
> +[4] Documentation/devicetree/bindings/clock/st,clkgen-pll.txt
> +[5] Documentation/devicetree/bindings/clock/st,clkgen-prediv.txt
> +[6] Documentation/devicetree/bindings/clock/st,vcc.txt
> +[7] Documentation/devicetree/bindings/clock/st,quadfs.txt
> +
>
> Required properties:
> - reg : A Base address and length of the register set.
>
> Example:
>
> - clockgenA at fee62000 {
> + clockgen-a at fee62000 {
>
> reg = <0xfee62000 0xb48>;
>
> - CLK_S_A0_PLL: CLK_S_A0_PLL {
> + clk_s_a0_pll: clk-s-a0-pll {
> #clock-cells = <1>;
> compatible = "st,clkgena-plls-c65";
>
> - clocks = <&CLK_SYSIN>;
> + clocks = <&clk-sysin>;
>
> - clock-output-names = "CLK_S_A0_PLL0_HS",
> - "CLK_S_A0_PLL0_LS",
> - "CLK_S_A0_PLL1";
> + clock-output-names = "clk-s-a0-pll0-hs",
> + "clk-s-a0-pll0-ls",
> + "clk-s-a0-pll1";
> };
>
> - CLK_S_A0_OSC_PREDIV: CLK_S_A0_OSC_PREDIV {
> + clk_s_a0_osc_prediv: clk-s-a0-osc-prediv {
> #clock-cells = <0>;
> compatible = "st,clkgena-prediv-c65",
> "st,clkgena-prediv";
>
> - clocks = <&CLK_SYSIN>;
> + clocks = <&clk_sysin>;
>
> - clock-output-names = "CLK_S_A0_OSC_PREDIV";
> + clock-output-names = "clk-s-a0-osc-prediv";
> };
>
> - CLK_S_A0_HS: CLK_S_A0_HS {
> + clk_s_a0_hs: clk-s-a0-hs {
> #clock-cells = <1>;
> compatible = "st,clkgena-divmux-c65-hs",
> "st,clkgena-divmux";
>
> - clocks = <&CLK_S_A0_OSC_PREDIV>,
> - <&CLK_S_A0_PLL 0>, /* PLL0 HS */
> - <&CLK_S_A0_PLL 2>; /* PLL1 */
> + clocks = <&clk-s_a0_osc_prediv>,
> + <&clk-s_a0_pll 0>, /* pll0 hs */
> + <&clk-s_a0_pll 2>; /* pll1 */
>
> - clock-output-names = "CLK_S_FDMA_0",
> - "CLK_S_FDMA_1",
> - ""; /* CLK_S_JIT_SENSE */
> - /* Fourth output unused */
> + clock-output-names = "clk-s-fdma-0",
> + "clk-s-fdma-1",
> + ""; /* clk-s-jit-sense */
> + /* fourth output unused */
> };
> };
>
> diff --git a/Documentation/devicetree/bindings/clock/st/st,quadfs.txt b/Documentation/devicetree/bindings/clock/st/st,quadfs.txt
> index ec86d62..cedeb9c 100644
> --- a/Documentation/devicetree/bindings/clock/st/st,quadfs.txt
> +++ b/Documentation/devicetree/bindings/clock/st/st,quadfs.txt
> @@ -15,6 +15,9 @@ Required properties:
> "st,stih416-quadfs432", "st,quadfs"
> "st,stih416-quadfs660-E", "st,quadfs"
> "st,stih416-quadfs660-F", "st,quadfs"
> + "st,stih407-quadfs660-C", "st,quadfs"
> + "st,stih407-quadfs660-D", "st,quadfs"
> +
>
> - #clock-cells : from common clock binding; shall be set to 1.
>
> @@ -32,14 +35,14 @@ Required properties:
>
> Example:
>
> - CLOCKGEN_E: CLOCKGEN_E {
> + clockgen_e: clockgen-e at fd3208bc {
> #clock-cells = <1>;
> compatible = "st,stih416-quadfs660-E", "st,quadfs";
> reg = <0xfd3208bc 0xB0>;
>
> - clocks = <&CLK_SYSIN>;
> - clock-output-names = "CLK_M_PIX_MDTP_0",
> - "CLK_M_PIX_MDTP_1",
> - "CLK_M_PIX_MDTP_2",
> - "CLK_M_MPELPC";
> + clocks = <&clk_sysin>;
> + clock-output-names = "clk-m-pix-mdtp-0",
> + "clk-m-pix-mdtp-1",
> + "clk-m-pix-mdtp-2",
> + "clk-m-mpelpc";
> };
> --
> 1.9.1
>
>
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PATCH v2 04/14] clk: st: Adds Flexgen clock binding
2014-06-27 13:25 ` Gabriel FERNANDEZ
(?)
@ 2014-06-30 9:26 ` Mark Rutland
-1 siblings, 0 replies; 49+ messages in thread
From: Mark Rutland @ 2014-06-30 9:26 UTC (permalink / raw)
To: Gabriel FERNANDEZ
Cc: mturquette, robh+dt, Pawel Moll, ijc+devicetree, galak,
devicetree, linux-doc, linux-kernel, linux-arm-kernel, kernel,
Lee Jones, Gabriel Fernandez
On Fri, Jun 27, 2014 at 02:25:01PM +0100, Gabriel FERNANDEZ wrote:
> A Flexgen structure is composed by:
> - a clock cross bar (represented by a mux element)
> - a pre and final dividers (represented by a divider and gate elements)
>
> Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org>
> Acked-by: Peter Griffin <peter.griffin@linaro.org>
> ---
> .../devicetree/bindings/clock/st/st,clkgen.txt | 5 +++
> .../devicetree/bindings/clock/st/st,flexgen.txt | 48 ++++++++++++++++++++++
> 2 files changed, 53 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/clock/st/st,flexgen.txt
>
> diff --git a/Documentation/devicetree/bindings/clock/st/st,clkgen.txt b/Documentation/devicetree/bindings/clock/st/st,clkgen.txt
> index 427bad8..78978f1 100644
> --- a/Documentation/devicetree/bindings/clock/st/st,clkgen.txt
> +++ b/Documentation/devicetree/bindings/clock/st/st,clkgen.txt
> @@ -32,6 +32,10 @@ address is common of all subnode.
> vcc_node {
> ...
> };
> +
> + flexgen_node {
> + ...
> + };
> ...
> };
>
> @@ -45,6 +49,7 @@ Each subnode should use the binding discribe in [2]..[7]
> [5] Documentation/devicetree/bindings/clock/st,clkgen-prediv.txt
> [6] Documentation/devicetree/bindings/clock/st,vcc.txt
> [7] Documentation/devicetree/bindings/clock/st,quadfs.txt
> +[8] Documentation/devicetree/bindings/clock/st,flexgen.txt
>
>
> Required properties:
> diff --git a/Documentation/devicetree/bindings/clock/st/st,flexgen.txt b/Documentation/devicetree/bindings/clock/st/st,flexgen.txt
> new file mode 100644
> index 0000000..f2d4333
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/st/st,flexgen.txt
> @@ -0,0 +1,48 @@
> +Binding for a type of flexgen structure found on certain
> +STMicroelectronics consumer electronics SoC devices
> +
> +This structure includes:
> +- a clock cross bar (represented by a mux element)
> +- a pre and final dividers (represented by a divider and gate elements)
> +
> +This binding uses the common clock binding[1].
> +
> +[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
> +
> +Required properties:
> +- compatible : shall be:
> + "st,flexgen"
That looks very vague. Is this a sub-node of a larger block?
Might there be a future flexgen revision that looks different?
> +- #clock-cells : from common clock binding; shall be set to 1.
what does the clock cell represent? Is it just a linear index from 0?
> +- clocks : from common clock binding
This is a completely useless description.
Which clock inputs do you expect clocks for? How many? Are they named?
> +
> +- clock-output-names : From common clock binding. The block has 4
> + clock outputs but not all of them in a specific instance
> + have to be used in the SoC. If a clock name is left as
> + an empty string then no clock will be created for the
> + output associated with that string index. If fewer than
> + 4 strings are provided then no clocks will be created
> + for the remaining outputs.
That's a Linux-internal detail, surely?
Why do we even do that?
Mark.
> +
> +Example:
> +
> + clockgen-d2@x9106000 {
> + compatible = "st,clkgen-c32";
> + reg = <0x9106000 0x1000>;
> +
> + clk_s_d2_flexgen: clk-s-d2-flexgen {
> + compatible = "st,flexgen";
> +
> + #clock-cells = <1>;
> + clocks = <&clk_s_d2_quadfs 0>,
> + <&clk_s_d2_quadfs 1>,
> + <&clk_s_d2_quadfs 2>,
> + <&clk_s_d2_quadfs 3>;
> +
> + clock-output-names = "clk-pix-main-disp",
> + "clk-pix-pip",
> + "clk-pix-gdp1",
> + "clk-pix-gdp2";
> + };
> + };
> --
> 1.9.1
>
>
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PATCH v2 04/14] clk: st: Adds Flexgen clock binding
@ 2014-06-30 9:26 ` Mark Rutland
0 siblings, 0 replies; 49+ messages in thread
From: Mark Rutland @ 2014-06-30 9:26 UTC (permalink / raw)
To: Gabriel FERNANDEZ
Cc: mturquette, robh+dt, Pawel Moll, ijc+devicetree, galak,
devicetree, linux-doc, linux-kernel, linux-arm-kernel, kernel,
Lee Jones, Gabriel Fernandez
On Fri, Jun 27, 2014 at 02:25:01PM +0100, Gabriel FERNANDEZ wrote:
> A Flexgen structure is composed by:
> - a clock cross bar (represented by a mux element)
> - a pre and final dividers (represented by a divider and gate elements)
>
> Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org>
> Acked-by: Peter Griffin <peter.griffin@linaro.org>
> ---
> .../devicetree/bindings/clock/st/st,clkgen.txt | 5 +++
> .../devicetree/bindings/clock/st/st,flexgen.txt | 48 ++++++++++++++++++++++
> 2 files changed, 53 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/clock/st/st,flexgen.txt
>
> diff --git a/Documentation/devicetree/bindings/clock/st/st,clkgen.txt b/Documentation/devicetree/bindings/clock/st/st,clkgen.txt
> index 427bad8..78978f1 100644
> --- a/Documentation/devicetree/bindings/clock/st/st,clkgen.txt
> +++ b/Documentation/devicetree/bindings/clock/st/st,clkgen.txt
> @@ -32,6 +32,10 @@ address is common of all subnode.
> vcc_node {
> ...
> };
> +
> + flexgen_node {
> + ...
> + };
> ...
> };
>
> @@ -45,6 +49,7 @@ Each subnode should use the binding discribe in [2]..[7]
> [5] Documentation/devicetree/bindings/clock/st,clkgen-prediv.txt
> [6] Documentation/devicetree/bindings/clock/st,vcc.txt
> [7] Documentation/devicetree/bindings/clock/st,quadfs.txt
> +[8] Documentation/devicetree/bindings/clock/st,flexgen.txt
>
>
> Required properties:
> diff --git a/Documentation/devicetree/bindings/clock/st/st,flexgen.txt b/Documentation/devicetree/bindings/clock/st/st,flexgen.txt
> new file mode 100644
> index 0000000..f2d4333
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/st/st,flexgen.txt
> @@ -0,0 +1,48 @@
> +Binding for a type of flexgen structure found on certain
> +STMicroelectronics consumer electronics SoC devices
> +
> +This structure includes:
> +- a clock cross bar (represented by a mux element)
> +- a pre and final dividers (represented by a divider and gate elements)
> +
> +This binding uses the common clock binding[1].
> +
> +[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
> +
> +Required properties:
> +- compatible : shall be:
> + "st,flexgen"
That looks very vague. Is this a sub-node of a larger block?
Might there be a future flexgen revision that looks different?
> +- #clock-cells : from common clock binding; shall be set to 1.
what does the clock cell represent? Is it just a linear index from 0?
> +- clocks : from common clock binding
This is a completely useless description.
Which clock inputs do you expect clocks for? How many? Are they named?
> +
> +- clock-output-names : From common clock binding. The block has 4
> + clock outputs but not all of them in a specific instance
> + have to be used in the SoC. If a clock name is left as
> + an empty string then no clock will be created for the
> + output associated with that string index. If fewer than
> + 4 strings are provided then no clocks will be created
> + for the remaining outputs.
That's a Linux-internal detail, surely?
Why do we even do that?
Mark.
> +
> +Example:
> +
> + clockgen-d2@x9106000 {
> + compatible = "st,clkgen-c32";
> + reg = <0x9106000 0x1000>;
> +
> + clk_s_d2_flexgen: clk-s-d2-flexgen {
> + compatible = "st,flexgen";
> +
> + #clock-cells = <1>;
> + clocks = <&clk_s_d2_quadfs 0>,
> + <&clk_s_d2_quadfs 1>,
> + <&clk_s_d2_quadfs 2>,
> + <&clk_s_d2_quadfs 3>;
> +
> + clock-output-names = "clk-pix-main-disp",
> + "clk-pix-pip",
> + "clk-pix-gdp1",
> + "clk-pix-gdp2";
> + };
> + };
> --
> 1.9.1
>
>
^ permalink raw reply [flat|nested] 49+ messages in thread
* [PATCH v2 04/14] clk: st: Adds Flexgen clock binding
@ 2014-06-30 9:26 ` Mark Rutland
0 siblings, 0 replies; 49+ messages in thread
From: Mark Rutland @ 2014-06-30 9:26 UTC (permalink / raw)
To: linux-arm-kernel
On Fri, Jun 27, 2014 at 02:25:01PM +0100, Gabriel FERNANDEZ wrote:
> A Flexgen structure is composed by:
> - a clock cross bar (represented by a mux element)
> - a pre and final dividers (represented by a divider and gate elements)
>
> Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org>
> Acked-by: Peter Griffin <peter.griffin@linaro.org>
> ---
> .../devicetree/bindings/clock/st/st,clkgen.txt | 5 +++
> .../devicetree/bindings/clock/st/st,flexgen.txt | 48 ++++++++++++++++++++++
> 2 files changed, 53 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/clock/st/st,flexgen.txt
>
> diff --git a/Documentation/devicetree/bindings/clock/st/st,clkgen.txt b/Documentation/devicetree/bindings/clock/st/st,clkgen.txt
> index 427bad8..78978f1 100644
> --- a/Documentation/devicetree/bindings/clock/st/st,clkgen.txt
> +++ b/Documentation/devicetree/bindings/clock/st/st,clkgen.txt
> @@ -32,6 +32,10 @@ address is common of all subnode.
> vcc_node {
> ...
> };
> +
> + flexgen_node {
> + ...
> + };
> ...
> };
>
> @@ -45,6 +49,7 @@ Each subnode should use the binding discribe in [2]..[7]
> [5] Documentation/devicetree/bindings/clock/st,clkgen-prediv.txt
> [6] Documentation/devicetree/bindings/clock/st,vcc.txt
> [7] Documentation/devicetree/bindings/clock/st,quadfs.txt
> +[8] Documentation/devicetree/bindings/clock/st,flexgen.txt
>
>
> Required properties:
> diff --git a/Documentation/devicetree/bindings/clock/st/st,flexgen.txt b/Documentation/devicetree/bindings/clock/st/st,flexgen.txt
> new file mode 100644
> index 0000000..f2d4333
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/st/st,flexgen.txt
> @@ -0,0 +1,48 @@
> +Binding for a type of flexgen structure found on certain
> +STMicroelectronics consumer electronics SoC devices
> +
> +This structure includes:
> +- a clock cross bar (represented by a mux element)
> +- a pre and final dividers (represented by a divider and gate elements)
> +
> +This binding uses the common clock binding[1].
> +
> +[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
> +
> +Required properties:
> +- compatible : shall be:
> + "st,flexgen"
That looks very vague. Is this a sub-node of a larger block?
Might there be a future flexgen revision that looks different?
> +- #clock-cells : from common clock binding; shall be set to 1.
what does the clock cell represent? Is it just a linear index from 0?
> +- clocks : from common clock binding
This is a completely useless description.
Which clock inputs do you expect clocks for? How many? Are they named?
> +
> +- clock-output-names : From common clock binding. The block has 4
> + clock outputs but not all of them in a specific instance
> + have to be used in the SoC. If a clock name is left as
> + an empty string then no clock will be created for the
> + output associated with that string index. If fewer than
> + 4 strings are provided then no clocks will be created
> + for the remaining outputs.
That's a Linux-internal detail, surely?
Why do we even do that?
Mark.
> +
> +Example:
> +
> + clockgen-d2 at x9106000 {
> + compatible = "st,clkgen-c32";
> + reg = <0x9106000 0x1000>;
> +
> + clk_s_d2_flexgen: clk-s-d2-flexgen {
> + compatible = "st,flexgen";
> +
> + #clock-cells = <1>;
> + clocks = <&clk_s_d2_quadfs 0>,
> + <&clk_s_d2_quadfs 1>,
> + <&clk_s_d2_quadfs 2>,
> + <&clk_s_d2_quadfs 3>;
> +
> + clock-output-names = "clk-pix-main-disp",
> + "clk-pix-pip",
> + "clk-pix-gdp1",
> + "clk-pix-gdp2";
> + };
> + };
> --
> 1.9.1
>
>
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PATCH v2 10/14] drivers: clk: st: STiH407: Support for clockgenC0
2014-06-27 13:25 ` Gabriel FERNANDEZ
(?)
@ 2014-06-30 9:30 ` Mark Rutland
-1 siblings, 0 replies; 49+ messages in thread
From: Mark Rutland @ 2014-06-30 9:30 UTC (permalink / raw)
To: Gabriel FERNANDEZ
Cc: mturquette, robh+dt, Pawel Moll, ijc+devicetree, galak,
devicetree, linux-doc, linux-kernel, linux-arm-kernel, kernel,
Lee Jones, Gabriel Fernandez, Olivier Bideau
On Fri, Jun 27, 2014 at 02:25:07PM +0100, Gabriel FERNANDEZ wrote:
> The patch added support for DT registration of ClockGenC0
> It includes 2 c32 type PLL and a 660 Quadfs.
>
> Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org>
> Signed-off-by: Olivier Bideau <olivier.bideau@st.com>
> Acked-by: Peter Griffin <peter.griffin@linaro.org>
> ---
> drivers/clk/st/clkgen-fsyn.c | 47 ++++++++++++++++++++++++++++++++++++++++++++
> drivers/clk/st/clkgen-pll.c | 32 ++++++++++++++++++++++++++++++
> 2 files changed, 79 insertions(+)
>
> diff --git a/drivers/clk/st/clkgen-fsyn.c b/drivers/clk/st/clkgen-fsyn.c
> index b2b73f4..0e0d5f9 100644
> --- a/drivers/clk/st/clkgen-fsyn.c
> +++ b/drivers/clk/st/clkgen-fsyn.c
> @@ -255,6 +255,49 @@ static const struct clkgen_quadfs_data st_fs660c32_F_416 = {
> .get_rate = clk_fs660c32_dig_get_rate,
> };
>
> +static const struct clkgen_quadfs_data st_fs660c32_C_407 = {
> + .nrst_present = true,
> + .nrst = { CLKGEN_FIELD(0x2f0, 0x1, 0),
> + CLKGEN_FIELD(0x2f0, 0x1, 1),
> + CLKGEN_FIELD(0x2f0, 0x1, 2),
> + CLKGEN_FIELD(0x2f0, 0x1, 3) },
> + .npda = CLKGEN_FIELD(0x2f0, 0x1, 12),
> + .nsb = { CLKGEN_FIELD(0x2f0, 0x1, 8),
> + CLKGEN_FIELD(0x2f0, 0x1, 9),
> + CLKGEN_FIELD(0x2f0, 0x1, 10),
> + CLKGEN_FIELD(0x2f0, 0x1, 11) },
> + .nsdiv_present = true,
> + .nsdiv = { CLKGEN_FIELD(0x304, 0x1, 24),
> + CLKGEN_FIELD(0x308, 0x1, 24),
> + CLKGEN_FIELD(0x30c, 0x1, 24),
> + CLKGEN_FIELD(0x310, 0x1, 24) },
> + .mdiv = { CLKGEN_FIELD(0x304, 0x1f, 15),
> + CLKGEN_FIELD(0x308, 0x1f, 15),
> + CLKGEN_FIELD(0x30c, 0x1f, 15),
> + CLKGEN_FIELD(0x310, 0x1f, 15) },
> + .en = { CLKGEN_FIELD(0x2fc, 0x1, 0),
> + CLKGEN_FIELD(0x2fc, 0x1, 1),
> + CLKGEN_FIELD(0x2fc, 0x1, 2),
> + CLKGEN_FIELD(0x2fc, 0x1, 3) },
> + .ndiv = CLKGEN_FIELD(0x2f4, 0x7, 16),
> + .pe = { CLKGEN_FIELD(0x304, 0x7fff, 0),
> + CLKGEN_FIELD(0x308, 0x7fff, 0),
> + CLKGEN_FIELD(0x30c, 0x7fff, 0),
> + CLKGEN_FIELD(0x310, 0x7fff, 0) },
> + .sdiv = { CLKGEN_FIELD(0x304, 0xf, 20),
> + CLKGEN_FIELD(0x308, 0xf, 20),
> + CLKGEN_FIELD(0x30c, 0xf, 20),
> + CLKGEN_FIELD(0x310, 0xf, 20) },
> + .lockstatus_present = true,
> + .lock_status = CLKGEN_FIELD(0x2A0, 0x1, 24),
> + .powerup_polarity = 1,
> + .standby_polarity = 1,
> + .pll_ops = &st_quadfs_pll_c32_ops,
> + .rtbl = fs660c32_rtbl,
> + .rtbl_cnt = ARRAY_SIZE(fs660c32_rtbl),
> + .get_rate = clk_fs660c32_dig_get_rate,
> +};
> +
> /**
> * DOC: A Frequency Synthesizer that multiples its input clock by a fixed factor
> *
> @@ -938,6 +981,10 @@ static struct of_device_id quadfs_of_match[] = {
> .compatible = "st,stih416-quadfs660-F",
> .data = (void *)&st_fs660c32_F_416
> },
> + {
> + .compatible = "st,stih407-quadfs660-C",
> + .data = (void *)&st_fs660c32_C_407
Surely a (void*) cast isn't necessary?
Mark.
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PATCH v2 10/14] drivers: clk: st: STiH407: Support for clockgenC0
@ 2014-06-30 9:30 ` Mark Rutland
0 siblings, 0 replies; 49+ messages in thread
From: Mark Rutland @ 2014-06-30 9:30 UTC (permalink / raw)
To: Gabriel FERNANDEZ
Cc: mturquette, robh+dt, Pawel Moll, ijc+devicetree, galak,
devicetree, linux-doc, linux-kernel, linux-arm-kernel, kernel,
Lee Jones, Gabriel Fernandez, Olivier Bideau
On Fri, Jun 27, 2014 at 02:25:07PM +0100, Gabriel FERNANDEZ wrote:
> The patch added support for DT registration of ClockGenC0
> It includes 2 c32 type PLL and a 660 Quadfs.
>
> Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org>
> Signed-off-by: Olivier Bideau <olivier.bideau@st.com>
> Acked-by: Peter Griffin <peter.griffin@linaro.org>
> ---
> drivers/clk/st/clkgen-fsyn.c | 47 ++++++++++++++++++++++++++++++++++++++++++++
> drivers/clk/st/clkgen-pll.c | 32 ++++++++++++++++++++++++++++++
> 2 files changed, 79 insertions(+)
>
> diff --git a/drivers/clk/st/clkgen-fsyn.c b/drivers/clk/st/clkgen-fsyn.c
> index b2b73f4..0e0d5f9 100644
> --- a/drivers/clk/st/clkgen-fsyn.c
> +++ b/drivers/clk/st/clkgen-fsyn.c
> @@ -255,6 +255,49 @@ static const struct clkgen_quadfs_data st_fs660c32_F_416 = {
> .get_rate = clk_fs660c32_dig_get_rate,
> };
>
> +static const struct clkgen_quadfs_data st_fs660c32_C_407 = {
> + .nrst_present = true,
> + .nrst = { CLKGEN_FIELD(0x2f0, 0x1, 0),
> + CLKGEN_FIELD(0x2f0, 0x1, 1),
> + CLKGEN_FIELD(0x2f0, 0x1, 2),
> + CLKGEN_FIELD(0x2f0, 0x1, 3) },
> + .npda = CLKGEN_FIELD(0x2f0, 0x1, 12),
> + .nsb = { CLKGEN_FIELD(0x2f0, 0x1, 8),
> + CLKGEN_FIELD(0x2f0, 0x1, 9),
> + CLKGEN_FIELD(0x2f0, 0x1, 10),
> + CLKGEN_FIELD(0x2f0, 0x1, 11) },
> + .nsdiv_present = true,
> + .nsdiv = { CLKGEN_FIELD(0x304, 0x1, 24),
> + CLKGEN_FIELD(0x308, 0x1, 24),
> + CLKGEN_FIELD(0x30c, 0x1, 24),
> + CLKGEN_FIELD(0x310, 0x1, 24) },
> + .mdiv = { CLKGEN_FIELD(0x304, 0x1f, 15),
> + CLKGEN_FIELD(0x308, 0x1f, 15),
> + CLKGEN_FIELD(0x30c, 0x1f, 15),
> + CLKGEN_FIELD(0x310, 0x1f, 15) },
> + .en = { CLKGEN_FIELD(0x2fc, 0x1, 0),
> + CLKGEN_FIELD(0x2fc, 0x1, 1),
> + CLKGEN_FIELD(0x2fc, 0x1, 2),
> + CLKGEN_FIELD(0x2fc, 0x1, 3) },
> + .ndiv = CLKGEN_FIELD(0x2f4, 0x7, 16),
> + .pe = { CLKGEN_FIELD(0x304, 0x7fff, 0),
> + CLKGEN_FIELD(0x308, 0x7fff, 0),
> + CLKGEN_FIELD(0x30c, 0x7fff, 0),
> + CLKGEN_FIELD(0x310, 0x7fff, 0) },
> + .sdiv = { CLKGEN_FIELD(0x304, 0xf, 20),
> + CLKGEN_FIELD(0x308, 0xf, 20),
> + CLKGEN_FIELD(0x30c, 0xf, 20),
> + CLKGEN_FIELD(0x310, 0xf, 20) },
> + .lockstatus_present = true,
> + .lock_status = CLKGEN_FIELD(0x2A0, 0x1, 24),
> + .powerup_polarity = 1,
> + .standby_polarity = 1,
> + .pll_ops = &st_quadfs_pll_c32_ops,
> + .rtbl = fs660c32_rtbl,
> + .rtbl_cnt = ARRAY_SIZE(fs660c32_rtbl),
> + .get_rate = clk_fs660c32_dig_get_rate,
> +};
> +
> /**
> * DOC: A Frequency Synthesizer that multiples its input clock by a fixed factor
> *
> @@ -938,6 +981,10 @@ static struct of_device_id quadfs_of_match[] = {
> .compatible = "st,stih416-quadfs660-F",
> .data = (void *)&st_fs660c32_F_416
> },
> + {
> + .compatible = "st,stih407-quadfs660-C",
> + .data = (void *)&st_fs660c32_C_407
Surely a (void*) cast isn't necessary?
Mark.
^ permalink raw reply [flat|nested] 49+ messages in thread
* [PATCH v2 10/14] drivers: clk: st: STiH407: Support for clockgenC0
@ 2014-06-30 9:30 ` Mark Rutland
0 siblings, 0 replies; 49+ messages in thread
From: Mark Rutland @ 2014-06-30 9:30 UTC (permalink / raw)
To: linux-arm-kernel
On Fri, Jun 27, 2014 at 02:25:07PM +0100, Gabriel FERNANDEZ wrote:
> The patch added support for DT registration of ClockGenC0
> It includes 2 c32 type PLL and a 660 Quadfs.
>
> Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org>
> Signed-off-by: Olivier Bideau <olivier.bideau@st.com>
> Acked-by: Peter Griffin <peter.griffin@linaro.org>
> ---
> drivers/clk/st/clkgen-fsyn.c | 47 ++++++++++++++++++++++++++++++++++++++++++++
> drivers/clk/st/clkgen-pll.c | 32 ++++++++++++++++++++++++++++++
> 2 files changed, 79 insertions(+)
>
> diff --git a/drivers/clk/st/clkgen-fsyn.c b/drivers/clk/st/clkgen-fsyn.c
> index b2b73f4..0e0d5f9 100644
> --- a/drivers/clk/st/clkgen-fsyn.c
> +++ b/drivers/clk/st/clkgen-fsyn.c
> @@ -255,6 +255,49 @@ static const struct clkgen_quadfs_data st_fs660c32_F_416 = {
> .get_rate = clk_fs660c32_dig_get_rate,
> };
>
> +static const struct clkgen_quadfs_data st_fs660c32_C_407 = {
> + .nrst_present = true,
> + .nrst = { CLKGEN_FIELD(0x2f0, 0x1, 0),
> + CLKGEN_FIELD(0x2f0, 0x1, 1),
> + CLKGEN_FIELD(0x2f0, 0x1, 2),
> + CLKGEN_FIELD(0x2f0, 0x1, 3) },
> + .npda = CLKGEN_FIELD(0x2f0, 0x1, 12),
> + .nsb = { CLKGEN_FIELD(0x2f0, 0x1, 8),
> + CLKGEN_FIELD(0x2f0, 0x1, 9),
> + CLKGEN_FIELD(0x2f0, 0x1, 10),
> + CLKGEN_FIELD(0x2f0, 0x1, 11) },
> + .nsdiv_present = true,
> + .nsdiv = { CLKGEN_FIELD(0x304, 0x1, 24),
> + CLKGEN_FIELD(0x308, 0x1, 24),
> + CLKGEN_FIELD(0x30c, 0x1, 24),
> + CLKGEN_FIELD(0x310, 0x1, 24) },
> + .mdiv = { CLKGEN_FIELD(0x304, 0x1f, 15),
> + CLKGEN_FIELD(0x308, 0x1f, 15),
> + CLKGEN_FIELD(0x30c, 0x1f, 15),
> + CLKGEN_FIELD(0x310, 0x1f, 15) },
> + .en = { CLKGEN_FIELD(0x2fc, 0x1, 0),
> + CLKGEN_FIELD(0x2fc, 0x1, 1),
> + CLKGEN_FIELD(0x2fc, 0x1, 2),
> + CLKGEN_FIELD(0x2fc, 0x1, 3) },
> + .ndiv = CLKGEN_FIELD(0x2f4, 0x7, 16),
> + .pe = { CLKGEN_FIELD(0x304, 0x7fff, 0),
> + CLKGEN_FIELD(0x308, 0x7fff, 0),
> + CLKGEN_FIELD(0x30c, 0x7fff, 0),
> + CLKGEN_FIELD(0x310, 0x7fff, 0) },
> + .sdiv = { CLKGEN_FIELD(0x304, 0xf, 20),
> + CLKGEN_FIELD(0x308, 0xf, 20),
> + CLKGEN_FIELD(0x30c, 0xf, 20),
> + CLKGEN_FIELD(0x310, 0xf, 20) },
> + .lockstatus_present = true,
> + .lock_status = CLKGEN_FIELD(0x2A0, 0x1, 24),
> + .powerup_polarity = 1,
> + .standby_polarity = 1,
> + .pll_ops = &st_quadfs_pll_c32_ops,
> + .rtbl = fs660c32_rtbl,
> + .rtbl_cnt = ARRAY_SIZE(fs660c32_rtbl),
> + .get_rate = clk_fs660c32_dig_get_rate,
> +};
> +
> /**
> * DOC: A Frequency Synthesizer that multiples its input clock by a fixed factor
> *
> @@ -938,6 +981,10 @@ static struct of_device_id quadfs_of_match[] = {
> .compatible = "st,stih416-quadfs660-F",
> .data = (void *)&st_fs660c32_F_416
> },
> + {
> + .compatible = "st,stih407-quadfs660-C",
> + .data = (void *)&st_fs660c32_C_407
Surely a (void*) cast isn't necessary?
Mark.
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PATCH v2 01/14] clk: st: Update ST clock binding documentation
2014-06-30 9:23 ` Mark Rutland
(?)
@ 2014-07-01 12:11 ` Gabriel Fernandez
-1 siblings, 0 replies; 49+ messages in thread
From: Gabriel Fernandez @ 2014-07-01 12:11 UTC (permalink / raw)
To: Mark Rutland
Cc: Gabriel FERNANDEZ, mturquette, robh+dt, Pawel Moll,
ijc+devicetree, galak, devicetree, linux-doc, linux-kernel,
linux-arm-kernel, kernel, Lee Jones
Hi Mark,
yes i agree.
Thanks.
Gabriel
On 30 June 2014 11:23, Mark Rutland <mark.rutland@arm.com> wrote:
> On Fri, Jun 27, 2014 at 02:24:58PM +0100, Gabriel FERNANDEZ wrote:
>> This patch adds new compatibilities to support STiH407 SoC.
>
> This doesn't seem to match the patch, which seems to relabel nodes,
> rename nodes, change clock-output-names, _and_ adds some new compatible
> strings.
>
> Therefore this commit message is completely inappropriate for the patch.
> It doesn't match the diff and it doesn't tell me why you are making the
> changes below.
>
> NAK until that is fixed.
>
> Mark.
>
>>
>> Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org>
>> Acked-by: Peter Griffin <peter.griffin@linaro.org>
>> ---
>> .../bindings/clock/st/st,clkgen-divmux.txt | 28 +++++------
>> .../devicetree/bindings/clock/st/st,clkgen-mux.txt | 6 +--
>> .../devicetree/bindings/clock/st/st,clkgen-pll.txt | 17 ++++---
>> .../bindings/clock/st/st,clkgen-prediv.txt | 8 ++--
>> .../devicetree/bindings/clock/st/st,clkgen-vcc.txt | 34 ++++++++------
>> .../devicetree/bindings/clock/st/st,clkgen.txt | 54 +++++++++++++---------
>> .../devicetree/bindings/clock/st/st,quadfs.txt | 15 +++---
>> 7 files changed, 94 insertions(+), 68 deletions(-)
>>
>> diff --git a/Documentation/devicetree/bindings/clock/st/st,clkgen-divmux.txt b/Documentation/devicetree/bindings/clock/st/st,clkgen-divmux.txt
>> index ae56315..6247652 100644
>> --- a/Documentation/devicetree/bindings/clock/st/st,clkgen-divmux.txt
>> +++ b/Documentation/devicetree/bindings/clock/st/st,clkgen-divmux.txt
>> @@ -24,26 +24,26 @@ Required properties:
>>
>> Example:
>>
>> - clockgenA@fd345000 {
>> + clockgen-a@fd345000 {
>> reg = <0xfd345000 0xb50>;
>>
>> - CLK_M_A1_DIV1: CLK_M_A1_DIV1 {
>> + clk_m_a1_div1: clk-m-a1-div1 {
>> #clock-cells = <1>;
>> compatible = "st,clkgena-divmux-c32-odf1",
>> "st,clkgena-divmux";
>>
>> - clocks = <&CLK_M_A1_OSC_PREDIV>,
>> - <&CLK_M_A1_PLL0 1>, /* PLL0 PHI1 */
>> - <&CLK_M_A1_PLL1 1>; /* PLL1 PHI1 */
>> -
>> - clock-output-names = "CLK_M_RX_ICN_TS",
>> - "CLK_M_RX_ICN_VDP_0",
>> - "", /* Unused */
>> - "CLK_M_PRV_T1_BUS",
>> - "CLK_M_ICN_REG_12",
>> - "CLK_M_ICN_REG_10",
>> - "", /* Unused */
>> - "CLK_M_ICN_ST231";
>> + clocks = <&clk_m_a1_osc_prediv>,
>> + <&clk_m_a1_pll0 1>, /* PLL0 PHI1 */
>> + <&clk_m_a1_pll1 1>; /* PLL1 PHI1 */
>> +
>> + clock-output-names = "clk-m-rx-icn-ts",
>> + "clk-m-rx-icn-vdp-0",
>> + "", /* unused */
>> + "clk-m-prv-t1-bus",
>> + "clk-m-icn-reg-12",
>> + "clk-m-icn-reg-10",
>> + "", /* unused */
>> + "clk-m-icn-st231";
>> };
>> };
>>
>> diff --git a/Documentation/devicetree/bindings/clock/st/st,clkgen-mux.txt b/Documentation/devicetree/bindings/clock/st/st,clkgen-mux.txt
>> index 943e080..f1fa91c 100644
>> --- a/Documentation/devicetree/bindings/clock/st/st,clkgen-mux.txt
>> +++ b/Documentation/devicetree/bindings/clock/st/st,clkgen-mux.txt
>> @@ -17,7 +17,7 @@ Required properties:
>> "st,stih416-clkgenf-vcc-sd", "st,clkgen-mux"
>> "st,stih415-clkgen-a9-mux", "st,clkgen-mux"
>> "st,stih416-clkgen-a9-mux", "st,clkgen-mux"
>> -
>> + "st,stih407-clkgen-a9-mux", "st,clkgen-mux"
>>
>> - #clock-cells : from common clock binding; shall be set to 0.
>>
>> @@ -27,10 +27,10 @@ Required properties:
>>
>> Example:
>>
>> - CLK_M_HVA: CLK_M_HVA {
>> + clk_m_hva: clk-m-hva@fd690868 {
>> #clock-cells = <0>;
>> compatible = "st,stih416-clkgenf-vcc-hva", "st,clkgen-mux";
>> reg = <0xfd690868 4>;
>>
>> - clocks = <&CLOCKGEN_F 1>, <&CLK_M_A1_DIV0 3>;
>> + clocks = <&clockgen_f 1>, <&clk_m_a1_div0 3>;
>> };
>> diff --git a/Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt b/Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt
>> index 81eb385..efb51cf 100644
>> --- a/Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt
>> +++ b/Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt
>> @@ -19,11 +19,14 @@ Required properties:
>> "st,stih415-plls-c32-ddr", "st,clkgen-plls-c32"
>> "st,stih416-plls-c32-a9", "st,clkgen-plls-c32"
>> "st,stih416-plls-c32-ddr", "st,clkgen-plls-c32"
>> + "st,stih407-plls-c32-a0", "st,clkgen-plls-c32"
>> + "st,stih407-plls-c32-a9", "st,clkgen-plls-c32"
>> + "st,stih407-plls-c32-c0_0", "st,clkgen-plls-c32"
>> + "st,stih407-plls-c32-c0_1", "st,clkgen-plls-c32"
>>
>> "st,stih415-gpu-pll-c32", "st,clkgengpu-pll-c32"
>> "st,stih416-gpu-pll-c32", "st,clkgengpu-pll-c32"
>>
>> -
>> - #clock-cells : From common clock binding; shall be set to 1.
>>
>> - clocks : From common clock binding
>> @@ -32,17 +35,17 @@ Required properties:
>>
>> Example:
>>
>> - clockgenA@fee62000 {
>> + clockgen-a@fee62000 {
>> reg = <0xfee62000 0xb48>;
>>
>> - CLK_S_A0_PLL: CLK_S_A0_PLL {
>> + clk_s_a0_pll: clk-s-a0-pll {
>> #clock-cells = <1>;
>> compatible = "st,clkgena-plls-c65";
>>
>> - clocks = <&CLK_SYSIN>;
>> + clocks = <&clk_sysin>;
>>
>> - clock-output-names = "CLK_S_A0_PLL0_HS",
>> - "CLK_S_A0_PLL0_LS",
>> - "CLK_S_A0_PLL1";
>> + clock-output-names = "clk-s-a0-pll0-hs",
>> + "clk-s-a0-pll0-ls",
>> + "clk-s-a0-pll1";
>> };
>> };
>> diff --git a/Documentation/devicetree/bindings/clock/st/st,clkgen-prediv.txt b/Documentation/devicetree/bindings/clock/st/st,clkgen-prediv.txt
>> index 566c9d7..604766c 100644
>> --- a/Documentation/devicetree/bindings/clock/st/st,clkgen-prediv.txt
>> +++ b/Documentation/devicetree/bindings/clock/st/st,clkgen-prediv.txt
>> @@ -20,17 +20,17 @@ Required properties:
>>
>> Example:
>>
>> - clockgenA@fd345000 {
>> + clockgen-a@fd345000 {
>> reg = <0xfd345000 0xb50>;
>>
>> - CLK_M_A2_OSC_PREDIV: CLK_M_A2_OSC_PREDIV {
>> + clk_m_a2_osc_prediv: clk-m-a2-osc-prediv {
>> #clock-cells = <0>;
>> compatible = "st,clkgena-prediv-c32",
>> "st,clkgena-prediv";
>>
>> - clocks = <&CLK_SYSIN>;
>> + clocks = <&clk_sysin>;
>>
>> - clock-output-names = "CLK_M_A2_OSC_PREDIV";
>> + clock-output-names = "clk-m-a2-osc-prediv";
>> };
>> };
>>
>> diff --git a/Documentation/devicetree/bindings/clock/st/st,clkgen-vcc.txt b/Documentation/devicetree/bindings/clock/st/st,clkgen-vcc.txt
>> index 4e3ff28..109b3ed 100644
>> --- a/Documentation/devicetree/bindings/clock/st/st,clkgen-vcc.txt
>> +++ b/Documentation/devicetree/bindings/clock/st/st,clkgen-vcc.txt
>> @@ -32,22 +32,30 @@ Required properties:
>>
>> Example:
>>
>> - CLOCKGEN_C_VCC: CLOCKGEN_C_VCC {
>> + clockgen_c_vcc: clockgen-c-vcc@0xfe8308ac {
>> #clock-cells = <1>;
>> compatible = "st,stih416-clkgenc", "st,clkgen-vcc";
>> reg = <0xfe8308ac 12>;
>>
>> - clocks = <&CLK_S_VCC_HD>, <&CLOCKGEN_C 1>,
>> - <&CLK_S_TMDS_FROMPHY>, <&CLOCKGEN_C 2>;
>> -
>> - clock-output-names =
>> - "CLK_S_PIX_HDMI", "CLK_S_PIX_DVO",
>> - "CLK_S_OUT_DVO", "CLK_S_PIX_HD",
>> - "CLK_S_HDDAC", "CLK_S_DENC",
>> - "CLK_S_SDDAC", "CLK_S_PIX_MAIN",
>> - "CLK_S_PIX_AUX", "CLK_S_STFE_FRC_0",
>> - "CLK_S_REF_MCRU", "CLK_S_SLAVE_MCRU",
>> - "CLK_S_TMDS_HDMI", "CLK_S_HDMI_REJECT_PLL",
>> - "CLK_S_THSENS";
>> + clocks = <&clk_s_vcc_hd>,
>> + <&clockgen_c 1>,
>> + <&clk_s_tmds_fromphy>,
>> + <&clockgen_c 2>;
>> +
>> + clock-output-names = "clk-s-pix-hdmi",
>> + "clk-s-pix-dvo",
>> + "clk-s-out-dvo",
>> + "clk-s-pix-hd",
>> + "clk-s-hddac",
>> + "clk-s-denc",
>> + "clk-s-sddac",
>> + "clk-s-pix-main",
>> + "clk-s-pix-aux",
>> + "clk-s-stfe-frc-0",
>> + "clk-s-ref-mcru",
>> + "clk-s-slave-mcru",
>> + "clk-s-tmds-hdmi",
>> + "clk-s-hdmi-reject-pll",
>> + "clk-s-thsens";
>> };
>>
>> diff --git a/Documentation/devicetree/bindings/clock/st/st,clkgen.txt b/Documentation/devicetree/bindings/clock/st/st,clkgen.txt
>> index 49ec5ae..427bad8 100644
>> --- a/Documentation/devicetree/bindings/clock/st/st,clkgen.txt
>> +++ b/Documentation/devicetree/bindings/clock/st/st,clkgen.txt
>> @@ -24,60 +24,72 @@ address is common of all subnode.
>> quadfs_node {
>> ...
>> };
>> +
>> + mux_node {
>> + ...
>> + };
>> +
>> + vcc_node {
>> + ...
>> + };
>> ...
>> };
>>
>> This binding uses the common clock binding[1].
>> -Each subnode should use the binding discribe in [2]..[4]
>> +Each subnode should use the binding discribe in [2]..[7]
>>
>> [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
>> -[2] Documentation/devicetree/bindings/clock/st,quadfs.txt
>> -[3] Documentation/devicetree/bindings/clock/st,quadfs.txt
>> -[4] Documentation/devicetree/bindings/clock/st,quadfs.txt
>> +[2] Documentation/devicetree/bindings/clock/st,clkgen-divmux.txt
>> +[3] Documentation/devicetree/bindings/clock/st,clkgen-mux.txt
>> +[4] Documentation/devicetree/bindings/clock/st,clkgen-pll.txt
>> +[5] Documentation/devicetree/bindings/clock/st,clkgen-prediv.txt
>> +[6] Documentation/devicetree/bindings/clock/st,vcc.txt
>> +[7] Documentation/devicetree/bindings/clock/st,quadfs.txt
>> +
>>
>> Required properties:
>> - reg : A Base address and length of the register set.
>>
>> Example:
>>
>> - clockgenA@fee62000 {
>> + clockgen-a@fee62000 {
>>
>> reg = <0xfee62000 0xb48>;
>>
>> - CLK_S_A0_PLL: CLK_S_A0_PLL {
>> + clk_s_a0_pll: clk-s-a0-pll {
>> #clock-cells = <1>;
>> compatible = "st,clkgena-plls-c65";
>>
>> - clocks = <&CLK_SYSIN>;
>> + clocks = <&clk-sysin>;
>>
>> - clock-output-names = "CLK_S_A0_PLL0_HS",
>> - "CLK_S_A0_PLL0_LS",
>> - "CLK_S_A0_PLL1";
>> + clock-output-names = "clk-s-a0-pll0-hs",
>> + "clk-s-a0-pll0-ls",
>> + "clk-s-a0-pll1";
>> };
>>
>> - CLK_S_A0_OSC_PREDIV: CLK_S_A0_OSC_PREDIV {
>> + clk_s_a0_osc_prediv: clk-s-a0-osc-prediv {
>> #clock-cells = <0>;
>> compatible = "st,clkgena-prediv-c65",
>> "st,clkgena-prediv";
>>
>> - clocks = <&CLK_SYSIN>;
>> + clocks = <&clk_sysin>;
>>
>> - clock-output-names = "CLK_S_A0_OSC_PREDIV";
>> + clock-output-names = "clk-s-a0-osc-prediv";
>> };
>>
>> - CLK_S_A0_HS: CLK_S_A0_HS {
>> + clk_s_a0_hs: clk-s-a0-hs {
>> #clock-cells = <1>;
>> compatible = "st,clkgena-divmux-c65-hs",
>> "st,clkgena-divmux";
>>
>> - clocks = <&CLK_S_A0_OSC_PREDIV>,
>> - <&CLK_S_A0_PLL 0>, /* PLL0 HS */
>> - <&CLK_S_A0_PLL 2>; /* PLL1 */
>> + clocks = <&clk-s_a0_osc_prediv>,
>> + <&clk-s_a0_pll 0>, /* pll0 hs */
>> + <&clk-s_a0_pll 2>; /* pll1 */
>>
>> - clock-output-names = "CLK_S_FDMA_0",
>> - "CLK_S_FDMA_1",
>> - ""; /* CLK_S_JIT_SENSE */
>> - /* Fourth output unused */
>> + clock-output-names = "clk-s-fdma-0",
>> + "clk-s-fdma-1",
>> + ""; /* clk-s-jit-sense */
>> + /* fourth output unused */
>> };
>> };
>>
>> diff --git a/Documentation/devicetree/bindings/clock/st/st,quadfs.txt b/Documentation/devicetree/bindings/clock/st/st,quadfs.txt
>> index ec86d62..cedeb9c 100644
>> --- a/Documentation/devicetree/bindings/clock/st/st,quadfs.txt
>> +++ b/Documentation/devicetree/bindings/clock/st/st,quadfs.txt
>> @@ -15,6 +15,9 @@ Required properties:
>> "st,stih416-quadfs432", "st,quadfs"
>> "st,stih416-quadfs660-E", "st,quadfs"
>> "st,stih416-quadfs660-F", "st,quadfs"
>> + "st,stih407-quadfs660-C", "st,quadfs"
>> + "st,stih407-quadfs660-D", "st,quadfs"
>> +
>>
>> - #clock-cells : from common clock binding; shall be set to 1.
>>
>> @@ -32,14 +35,14 @@ Required properties:
>>
>> Example:
>>
>> - CLOCKGEN_E: CLOCKGEN_E {
>> + clockgen_e: clockgen-e@fd3208bc {
>> #clock-cells = <1>;
>> compatible = "st,stih416-quadfs660-E", "st,quadfs";
>> reg = <0xfd3208bc 0xB0>;
>>
>> - clocks = <&CLK_SYSIN>;
>> - clock-output-names = "CLK_M_PIX_MDTP_0",
>> - "CLK_M_PIX_MDTP_1",
>> - "CLK_M_PIX_MDTP_2",
>> - "CLK_M_MPELPC";
>> + clocks = <&clk_sysin>;
>> + clock-output-names = "clk-m-pix-mdtp-0",
>> + "clk-m-pix-mdtp-1",
>> + "clk-m-pix-mdtp-2",
>> + "clk-m-mpelpc";
>> };
>> --
>> 1.9.1
>>
>>
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PATCH v2 01/14] clk: st: Update ST clock binding documentation
@ 2014-07-01 12:11 ` Gabriel Fernandez
0 siblings, 0 replies; 49+ messages in thread
From: Gabriel Fernandez @ 2014-07-01 12:11 UTC (permalink / raw)
To: Mark Rutland
Cc: Gabriel FERNANDEZ, mturquette, robh+dt, Pawel Moll,
ijc+devicetree, galak, devicetree, linux-doc, linux-kernel,
linux-arm-kernel, kernel, Lee Jones
Hi Mark,
yes i agree.
Thanks.
Gabriel
On 30 June 2014 11:23, Mark Rutland <mark.rutland@arm.com> wrote:
> On Fri, Jun 27, 2014 at 02:24:58PM +0100, Gabriel FERNANDEZ wrote:
>> This patch adds new compatibilities to support STiH407 SoC.
>
> This doesn't seem to match the patch, which seems to relabel nodes,
> rename nodes, change clock-output-names, _and_ adds some new compatible
> strings.
>
> Therefore this commit message is completely inappropriate for the patch.
> It doesn't match the diff and it doesn't tell me why you are making the
> changes below.
>
> NAK until that is fixed.
>
> Mark.
>
>>
>> Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org>
>> Acked-by: Peter Griffin <peter.griffin@linaro.org>
>> ---
>> .../bindings/clock/st/st,clkgen-divmux.txt | 28 +++++------
>> .../devicetree/bindings/clock/st/st,clkgen-mux.txt | 6 +--
>> .../devicetree/bindings/clock/st/st,clkgen-pll.txt | 17 ++++---
>> .../bindings/clock/st/st,clkgen-prediv.txt | 8 ++--
>> .../devicetree/bindings/clock/st/st,clkgen-vcc.txt | 34 ++++++++------
>> .../devicetree/bindings/clock/st/st,clkgen.txt | 54 +++++++++++++---------
>> .../devicetree/bindings/clock/st/st,quadfs.txt | 15 +++---
>> 7 files changed, 94 insertions(+), 68 deletions(-)
>>
>> diff --git a/Documentation/devicetree/bindings/clock/st/st,clkgen-divmux.txt b/Documentation/devicetree/bindings/clock/st/st,clkgen-divmux.txt
>> index ae56315..6247652 100644
>> --- a/Documentation/devicetree/bindings/clock/st/st,clkgen-divmux.txt
>> +++ b/Documentation/devicetree/bindings/clock/st/st,clkgen-divmux.txt
>> @@ -24,26 +24,26 @@ Required properties:
>>
>> Example:
>>
>> - clockgenA@fd345000 {
>> + clockgen-a@fd345000 {
>> reg = <0xfd345000 0xb50>;
>>
>> - CLK_M_A1_DIV1: CLK_M_A1_DIV1 {
>> + clk_m_a1_div1: clk-m-a1-div1 {
>> #clock-cells = <1>;
>> compatible = "st,clkgena-divmux-c32-odf1",
>> "st,clkgena-divmux";
>>
>> - clocks = <&CLK_M_A1_OSC_PREDIV>,
>> - <&CLK_M_A1_PLL0 1>, /* PLL0 PHI1 */
>> - <&CLK_M_A1_PLL1 1>; /* PLL1 PHI1 */
>> -
>> - clock-output-names = "CLK_M_RX_ICN_TS",
>> - "CLK_M_RX_ICN_VDP_0",
>> - "", /* Unused */
>> - "CLK_M_PRV_T1_BUS",
>> - "CLK_M_ICN_REG_12",
>> - "CLK_M_ICN_REG_10",
>> - "", /* Unused */
>> - "CLK_M_ICN_ST231";
>> + clocks = <&clk_m_a1_osc_prediv>,
>> + <&clk_m_a1_pll0 1>, /* PLL0 PHI1 */
>> + <&clk_m_a1_pll1 1>; /* PLL1 PHI1 */
>> +
>> + clock-output-names = "clk-m-rx-icn-ts",
>> + "clk-m-rx-icn-vdp-0",
>> + "", /* unused */
>> + "clk-m-prv-t1-bus",
>> + "clk-m-icn-reg-12",
>> + "clk-m-icn-reg-10",
>> + "", /* unused */
>> + "clk-m-icn-st231";
>> };
>> };
>>
>> diff --git a/Documentation/devicetree/bindings/clock/st/st,clkgen-mux.txt b/Documentation/devicetree/bindings/clock/st/st,clkgen-mux.txt
>> index 943e080..f1fa91c 100644
>> --- a/Documentation/devicetree/bindings/clock/st/st,clkgen-mux.txt
>> +++ b/Documentation/devicetree/bindings/clock/st/st,clkgen-mux.txt
>> @@ -17,7 +17,7 @@ Required properties:
>> "st,stih416-clkgenf-vcc-sd", "st,clkgen-mux"
>> "st,stih415-clkgen-a9-mux", "st,clkgen-mux"
>> "st,stih416-clkgen-a9-mux", "st,clkgen-mux"
>> -
>> + "st,stih407-clkgen-a9-mux", "st,clkgen-mux"
>>
>> - #clock-cells : from common clock binding; shall be set to 0.
>>
>> @@ -27,10 +27,10 @@ Required properties:
>>
>> Example:
>>
>> - CLK_M_HVA: CLK_M_HVA {
>> + clk_m_hva: clk-m-hva@fd690868 {
>> #clock-cells = <0>;
>> compatible = "st,stih416-clkgenf-vcc-hva", "st,clkgen-mux";
>> reg = <0xfd690868 4>;
>>
>> - clocks = <&CLOCKGEN_F 1>, <&CLK_M_A1_DIV0 3>;
>> + clocks = <&clockgen_f 1>, <&clk_m_a1_div0 3>;
>> };
>> diff --git a/Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt b/Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt
>> index 81eb385..efb51cf 100644
>> --- a/Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt
>> +++ b/Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt
>> @@ -19,11 +19,14 @@ Required properties:
>> "st,stih415-plls-c32-ddr", "st,clkgen-plls-c32"
>> "st,stih416-plls-c32-a9", "st,clkgen-plls-c32"
>> "st,stih416-plls-c32-ddr", "st,clkgen-plls-c32"
>> + "st,stih407-plls-c32-a0", "st,clkgen-plls-c32"
>> + "st,stih407-plls-c32-a9", "st,clkgen-plls-c32"
>> + "st,stih407-plls-c32-c0_0", "st,clkgen-plls-c32"
>> + "st,stih407-plls-c32-c0_1", "st,clkgen-plls-c32"
>>
>> "st,stih415-gpu-pll-c32", "st,clkgengpu-pll-c32"
>> "st,stih416-gpu-pll-c32", "st,clkgengpu-pll-c32"
>>
>> -
>> - #clock-cells : From common clock binding; shall be set to 1.
>>
>> - clocks : From common clock binding
>> @@ -32,17 +35,17 @@ Required properties:
>>
>> Example:
>>
>> - clockgenA@fee62000 {
>> + clockgen-a@fee62000 {
>> reg = <0xfee62000 0xb48>;
>>
>> - CLK_S_A0_PLL: CLK_S_A0_PLL {
>> + clk_s_a0_pll: clk-s-a0-pll {
>> #clock-cells = <1>;
>> compatible = "st,clkgena-plls-c65";
>>
>> - clocks = <&CLK_SYSIN>;
>> + clocks = <&clk_sysin>;
>>
>> - clock-output-names = "CLK_S_A0_PLL0_HS",
>> - "CLK_S_A0_PLL0_LS",
>> - "CLK_S_A0_PLL1";
>> + clock-output-names = "clk-s-a0-pll0-hs",
>> + "clk-s-a0-pll0-ls",
>> + "clk-s-a0-pll1";
>> };
>> };
>> diff --git a/Documentation/devicetree/bindings/clock/st/st,clkgen-prediv.txt b/Documentation/devicetree/bindings/clock/st/st,clkgen-prediv.txt
>> index 566c9d7..604766c 100644
>> --- a/Documentation/devicetree/bindings/clock/st/st,clkgen-prediv.txt
>> +++ b/Documentation/devicetree/bindings/clock/st/st,clkgen-prediv.txt
>> @@ -20,17 +20,17 @@ Required properties:
>>
>> Example:
>>
>> - clockgenA@fd345000 {
>> + clockgen-a@fd345000 {
>> reg = <0xfd345000 0xb50>;
>>
>> - CLK_M_A2_OSC_PREDIV: CLK_M_A2_OSC_PREDIV {
>> + clk_m_a2_osc_prediv: clk-m-a2-osc-prediv {
>> #clock-cells = <0>;
>> compatible = "st,clkgena-prediv-c32",
>> "st,clkgena-prediv";
>>
>> - clocks = <&CLK_SYSIN>;
>> + clocks = <&clk_sysin>;
>>
>> - clock-output-names = "CLK_M_A2_OSC_PREDIV";
>> + clock-output-names = "clk-m-a2-osc-prediv";
>> };
>> };
>>
>> diff --git a/Documentation/devicetree/bindings/clock/st/st,clkgen-vcc.txt b/Documentation/devicetree/bindings/clock/st/st,clkgen-vcc.txt
>> index 4e3ff28..109b3ed 100644
>> --- a/Documentation/devicetree/bindings/clock/st/st,clkgen-vcc.txt
>> +++ b/Documentation/devicetree/bindings/clock/st/st,clkgen-vcc.txt
>> @@ -32,22 +32,30 @@ Required properties:
>>
>> Example:
>>
>> - CLOCKGEN_C_VCC: CLOCKGEN_C_VCC {
>> + clockgen_c_vcc: clockgen-c-vcc@0xfe8308ac {
>> #clock-cells = <1>;
>> compatible = "st,stih416-clkgenc", "st,clkgen-vcc";
>> reg = <0xfe8308ac 12>;
>>
>> - clocks = <&CLK_S_VCC_HD>, <&CLOCKGEN_C 1>,
>> - <&CLK_S_TMDS_FROMPHY>, <&CLOCKGEN_C 2>;
>> -
>> - clock-output-names =
>> - "CLK_S_PIX_HDMI", "CLK_S_PIX_DVO",
>> - "CLK_S_OUT_DVO", "CLK_S_PIX_HD",
>> - "CLK_S_HDDAC", "CLK_S_DENC",
>> - "CLK_S_SDDAC", "CLK_S_PIX_MAIN",
>> - "CLK_S_PIX_AUX", "CLK_S_STFE_FRC_0",
>> - "CLK_S_REF_MCRU", "CLK_S_SLAVE_MCRU",
>> - "CLK_S_TMDS_HDMI", "CLK_S_HDMI_REJECT_PLL",
>> - "CLK_S_THSENS";
>> + clocks = <&clk_s_vcc_hd>,
>> + <&clockgen_c 1>,
>> + <&clk_s_tmds_fromphy>,
>> + <&clockgen_c 2>;
>> +
>> + clock-output-names = "clk-s-pix-hdmi",
>> + "clk-s-pix-dvo",
>> + "clk-s-out-dvo",
>> + "clk-s-pix-hd",
>> + "clk-s-hddac",
>> + "clk-s-denc",
>> + "clk-s-sddac",
>> + "clk-s-pix-main",
>> + "clk-s-pix-aux",
>> + "clk-s-stfe-frc-0",
>> + "clk-s-ref-mcru",
>> + "clk-s-slave-mcru",
>> + "clk-s-tmds-hdmi",
>> + "clk-s-hdmi-reject-pll",
>> + "clk-s-thsens";
>> };
>>
>> diff --git a/Documentation/devicetree/bindings/clock/st/st,clkgen.txt b/Documentation/devicetree/bindings/clock/st/st,clkgen.txt
>> index 49ec5ae..427bad8 100644
>> --- a/Documentation/devicetree/bindings/clock/st/st,clkgen.txt
>> +++ b/Documentation/devicetree/bindings/clock/st/st,clkgen.txt
>> @@ -24,60 +24,72 @@ address is common of all subnode.
>> quadfs_node {
>> ...
>> };
>> +
>> + mux_node {
>> + ...
>> + };
>> +
>> + vcc_node {
>> + ...
>> + };
>> ...
>> };
>>
>> This binding uses the common clock binding[1].
>> -Each subnode should use the binding discribe in [2]..[4]
>> +Each subnode should use the binding discribe in [2]..[7]
>>
>> [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
>> -[2] Documentation/devicetree/bindings/clock/st,quadfs.txt
>> -[3] Documentation/devicetree/bindings/clock/st,quadfs.txt
>> -[4] Documentation/devicetree/bindings/clock/st,quadfs.txt
>> +[2] Documentation/devicetree/bindings/clock/st,clkgen-divmux.txt
>> +[3] Documentation/devicetree/bindings/clock/st,clkgen-mux.txt
>> +[4] Documentation/devicetree/bindings/clock/st,clkgen-pll.txt
>> +[5] Documentation/devicetree/bindings/clock/st,clkgen-prediv.txt
>> +[6] Documentation/devicetree/bindings/clock/st,vcc.txt
>> +[7] Documentation/devicetree/bindings/clock/st,quadfs.txt
>> +
>>
>> Required properties:
>> - reg : A Base address and length of the register set.
>>
>> Example:
>>
>> - clockgenA@fee62000 {
>> + clockgen-a@fee62000 {
>>
>> reg = <0xfee62000 0xb48>;
>>
>> - CLK_S_A0_PLL: CLK_S_A0_PLL {
>> + clk_s_a0_pll: clk-s-a0-pll {
>> #clock-cells = <1>;
>> compatible = "st,clkgena-plls-c65";
>>
>> - clocks = <&CLK_SYSIN>;
>> + clocks = <&clk-sysin>;
>>
>> - clock-output-names = "CLK_S_A0_PLL0_HS",
>> - "CLK_S_A0_PLL0_LS",
>> - "CLK_S_A0_PLL1";
>> + clock-output-names = "clk-s-a0-pll0-hs",
>> + "clk-s-a0-pll0-ls",
>> + "clk-s-a0-pll1";
>> };
>>
>> - CLK_S_A0_OSC_PREDIV: CLK_S_A0_OSC_PREDIV {
>> + clk_s_a0_osc_prediv: clk-s-a0-osc-prediv {
>> #clock-cells = <0>;
>> compatible = "st,clkgena-prediv-c65",
>> "st,clkgena-prediv";
>>
>> - clocks = <&CLK_SYSIN>;
>> + clocks = <&clk_sysin>;
>>
>> - clock-output-names = "CLK_S_A0_OSC_PREDIV";
>> + clock-output-names = "clk-s-a0-osc-prediv";
>> };
>>
>> - CLK_S_A0_HS: CLK_S_A0_HS {
>> + clk_s_a0_hs: clk-s-a0-hs {
>> #clock-cells = <1>;
>> compatible = "st,clkgena-divmux-c65-hs",
>> "st,clkgena-divmux";
>>
>> - clocks = <&CLK_S_A0_OSC_PREDIV>,
>> - <&CLK_S_A0_PLL 0>, /* PLL0 HS */
>> - <&CLK_S_A0_PLL 2>; /* PLL1 */
>> + clocks = <&clk-s_a0_osc_prediv>,
>> + <&clk-s_a0_pll 0>, /* pll0 hs */
>> + <&clk-s_a0_pll 2>; /* pll1 */
>>
>> - clock-output-names = "CLK_S_FDMA_0",
>> - "CLK_S_FDMA_1",
>> - ""; /* CLK_S_JIT_SENSE */
>> - /* Fourth output unused */
>> + clock-output-names = "clk-s-fdma-0",
>> + "clk-s-fdma-1",
>> + ""; /* clk-s-jit-sense */
>> + /* fourth output unused */
>> };
>> };
>>
>> diff --git a/Documentation/devicetree/bindings/clock/st/st,quadfs.txt b/Documentation/devicetree/bindings/clock/st/st,quadfs.txt
>> index ec86d62..cedeb9c 100644
>> --- a/Documentation/devicetree/bindings/clock/st/st,quadfs.txt
>> +++ b/Documentation/devicetree/bindings/clock/st/st,quadfs.txt
>> @@ -15,6 +15,9 @@ Required properties:
>> "st,stih416-quadfs432", "st,quadfs"
>> "st,stih416-quadfs660-E", "st,quadfs"
>> "st,stih416-quadfs660-F", "st,quadfs"
>> + "st,stih407-quadfs660-C", "st,quadfs"
>> + "st,stih407-quadfs660-D", "st,quadfs"
>> +
>>
>> - #clock-cells : from common clock binding; shall be set to 1.
>>
>> @@ -32,14 +35,14 @@ Required properties:
>>
>> Example:
>>
>> - CLOCKGEN_E: CLOCKGEN_E {
>> + clockgen_e: clockgen-e@fd3208bc {
>> #clock-cells = <1>;
>> compatible = "st,stih416-quadfs660-E", "st,quadfs";
>> reg = <0xfd3208bc 0xB0>;
>>
>> - clocks = <&CLK_SYSIN>;
>> - clock-output-names = "CLK_M_PIX_MDTP_0",
>> - "CLK_M_PIX_MDTP_1",
>> - "CLK_M_PIX_MDTP_2",
>> - "CLK_M_MPELPC";
>> + clocks = <&clk_sysin>;
>> + clock-output-names = "clk-m-pix-mdtp-0",
>> + "clk-m-pix-mdtp-1",
>> + "clk-m-pix-mdtp-2",
>> + "clk-m-mpelpc";
>> };
>> --
>> 1.9.1
>>
>>
^ permalink raw reply [flat|nested] 49+ messages in thread
* [PATCH v2 01/14] clk: st: Update ST clock binding documentation
@ 2014-07-01 12:11 ` Gabriel Fernandez
0 siblings, 0 replies; 49+ messages in thread
From: Gabriel Fernandez @ 2014-07-01 12:11 UTC (permalink / raw)
To: linux-arm-kernel
Hi Mark,
yes i agree.
Thanks.
Gabriel
On 30 June 2014 11:23, Mark Rutland <mark.rutland@arm.com> wrote:
> On Fri, Jun 27, 2014 at 02:24:58PM +0100, Gabriel FERNANDEZ wrote:
>> This patch adds new compatibilities to support STiH407 SoC.
>
> This doesn't seem to match the patch, which seems to relabel nodes,
> rename nodes, change clock-output-names, _and_ adds some new compatible
> strings.
>
> Therefore this commit message is completely inappropriate for the patch.
> It doesn't match the diff and it doesn't tell me why you are making the
> changes below.
>
> NAK until that is fixed.
>
> Mark.
>
>>
>> Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org>
>> Acked-by: Peter Griffin <peter.griffin@linaro.org>
>> ---
>> .../bindings/clock/st/st,clkgen-divmux.txt | 28 +++++------
>> .../devicetree/bindings/clock/st/st,clkgen-mux.txt | 6 +--
>> .../devicetree/bindings/clock/st/st,clkgen-pll.txt | 17 ++++---
>> .../bindings/clock/st/st,clkgen-prediv.txt | 8 ++--
>> .../devicetree/bindings/clock/st/st,clkgen-vcc.txt | 34 ++++++++------
>> .../devicetree/bindings/clock/st/st,clkgen.txt | 54 +++++++++++++---------
>> .../devicetree/bindings/clock/st/st,quadfs.txt | 15 +++---
>> 7 files changed, 94 insertions(+), 68 deletions(-)
>>
>> diff --git a/Documentation/devicetree/bindings/clock/st/st,clkgen-divmux.txt b/Documentation/devicetree/bindings/clock/st/st,clkgen-divmux.txt
>> index ae56315..6247652 100644
>> --- a/Documentation/devicetree/bindings/clock/st/st,clkgen-divmux.txt
>> +++ b/Documentation/devicetree/bindings/clock/st/st,clkgen-divmux.txt
>> @@ -24,26 +24,26 @@ Required properties:
>>
>> Example:
>>
>> - clockgenA at fd345000 {
>> + clockgen-a at fd345000 {
>> reg = <0xfd345000 0xb50>;
>>
>> - CLK_M_A1_DIV1: CLK_M_A1_DIV1 {
>> + clk_m_a1_div1: clk-m-a1-div1 {
>> #clock-cells = <1>;
>> compatible = "st,clkgena-divmux-c32-odf1",
>> "st,clkgena-divmux";
>>
>> - clocks = <&CLK_M_A1_OSC_PREDIV>,
>> - <&CLK_M_A1_PLL0 1>, /* PLL0 PHI1 */
>> - <&CLK_M_A1_PLL1 1>; /* PLL1 PHI1 */
>> -
>> - clock-output-names = "CLK_M_RX_ICN_TS",
>> - "CLK_M_RX_ICN_VDP_0",
>> - "", /* Unused */
>> - "CLK_M_PRV_T1_BUS",
>> - "CLK_M_ICN_REG_12",
>> - "CLK_M_ICN_REG_10",
>> - "", /* Unused */
>> - "CLK_M_ICN_ST231";
>> + clocks = <&clk_m_a1_osc_prediv>,
>> + <&clk_m_a1_pll0 1>, /* PLL0 PHI1 */
>> + <&clk_m_a1_pll1 1>; /* PLL1 PHI1 */
>> +
>> + clock-output-names = "clk-m-rx-icn-ts",
>> + "clk-m-rx-icn-vdp-0",
>> + "", /* unused */
>> + "clk-m-prv-t1-bus",
>> + "clk-m-icn-reg-12",
>> + "clk-m-icn-reg-10",
>> + "", /* unused */
>> + "clk-m-icn-st231";
>> };
>> };
>>
>> diff --git a/Documentation/devicetree/bindings/clock/st/st,clkgen-mux.txt b/Documentation/devicetree/bindings/clock/st/st,clkgen-mux.txt
>> index 943e080..f1fa91c 100644
>> --- a/Documentation/devicetree/bindings/clock/st/st,clkgen-mux.txt
>> +++ b/Documentation/devicetree/bindings/clock/st/st,clkgen-mux.txt
>> @@ -17,7 +17,7 @@ Required properties:
>> "st,stih416-clkgenf-vcc-sd", "st,clkgen-mux"
>> "st,stih415-clkgen-a9-mux", "st,clkgen-mux"
>> "st,stih416-clkgen-a9-mux", "st,clkgen-mux"
>> -
>> + "st,stih407-clkgen-a9-mux", "st,clkgen-mux"
>>
>> - #clock-cells : from common clock binding; shall be set to 0.
>>
>> @@ -27,10 +27,10 @@ Required properties:
>>
>> Example:
>>
>> - CLK_M_HVA: CLK_M_HVA {
>> + clk_m_hva: clk-m-hva at fd690868 {
>> #clock-cells = <0>;
>> compatible = "st,stih416-clkgenf-vcc-hva", "st,clkgen-mux";
>> reg = <0xfd690868 4>;
>>
>> - clocks = <&CLOCKGEN_F 1>, <&CLK_M_A1_DIV0 3>;
>> + clocks = <&clockgen_f 1>, <&clk_m_a1_div0 3>;
>> };
>> diff --git a/Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt b/Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt
>> index 81eb385..efb51cf 100644
>> --- a/Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt
>> +++ b/Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt
>> @@ -19,11 +19,14 @@ Required properties:
>> "st,stih415-plls-c32-ddr", "st,clkgen-plls-c32"
>> "st,stih416-plls-c32-a9", "st,clkgen-plls-c32"
>> "st,stih416-plls-c32-ddr", "st,clkgen-plls-c32"
>> + "st,stih407-plls-c32-a0", "st,clkgen-plls-c32"
>> + "st,stih407-plls-c32-a9", "st,clkgen-plls-c32"
>> + "st,stih407-plls-c32-c0_0", "st,clkgen-plls-c32"
>> + "st,stih407-plls-c32-c0_1", "st,clkgen-plls-c32"
>>
>> "st,stih415-gpu-pll-c32", "st,clkgengpu-pll-c32"
>> "st,stih416-gpu-pll-c32", "st,clkgengpu-pll-c32"
>>
>> -
>> - #clock-cells : From common clock binding; shall be set to 1.
>>
>> - clocks : From common clock binding
>> @@ -32,17 +35,17 @@ Required properties:
>>
>> Example:
>>
>> - clockgenA at fee62000 {
>> + clockgen-a at fee62000 {
>> reg = <0xfee62000 0xb48>;
>>
>> - CLK_S_A0_PLL: CLK_S_A0_PLL {
>> + clk_s_a0_pll: clk-s-a0-pll {
>> #clock-cells = <1>;
>> compatible = "st,clkgena-plls-c65";
>>
>> - clocks = <&CLK_SYSIN>;
>> + clocks = <&clk_sysin>;
>>
>> - clock-output-names = "CLK_S_A0_PLL0_HS",
>> - "CLK_S_A0_PLL0_LS",
>> - "CLK_S_A0_PLL1";
>> + clock-output-names = "clk-s-a0-pll0-hs",
>> + "clk-s-a0-pll0-ls",
>> + "clk-s-a0-pll1";
>> };
>> };
>> diff --git a/Documentation/devicetree/bindings/clock/st/st,clkgen-prediv.txt b/Documentation/devicetree/bindings/clock/st/st,clkgen-prediv.txt
>> index 566c9d7..604766c 100644
>> --- a/Documentation/devicetree/bindings/clock/st/st,clkgen-prediv.txt
>> +++ b/Documentation/devicetree/bindings/clock/st/st,clkgen-prediv.txt
>> @@ -20,17 +20,17 @@ Required properties:
>>
>> Example:
>>
>> - clockgenA at fd345000 {
>> + clockgen-a at fd345000 {
>> reg = <0xfd345000 0xb50>;
>>
>> - CLK_M_A2_OSC_PREDIV: CLK_M_A2_OSC_PREDIV {
>> + clk_m_a2_osc_prediv: clk-m-a2-osc-prediv {
>> #clock-cells = <0>;
>> compatible = "st,clkgena-prediv-c32",
>> "st,clkgena-prediv";
>>
>> - clocks = <&CLK_SYSIN>;
>> + clocks = <&clk_sysin>;
>>
>> - clock-output-names = "CLK_M_A2_OSC_PREDIV";
>> + clock-output-names = "clk-m-a2-osc-prediv";
>> };
>> };
>>
>> diff --git a/Documentation/devicetree/bindings/clock/st/st,clkgen-vcc.txt b/Documentation/devicetree/bindings/clock/st/st,clkgen-vcc.txt
>> index 4e3ff28..109b3ed 100644
>> --- a/Documentation/devicetree/bindings/clock/st/st,clkgen-vcc.txt
>> +++ b/Documentation/devicetree/bindings/clock/st/st,clkgen-vcc.txt
>> @@ -32,22 +32,30 @@ Required properties:
>>
>> Example:
>>
>> - CLOCKGEN_C_VCC: CLOCKGEN_C_VCC {
>> + clockgen_c_vcc: clockgen-c-vcc at 0xfe8308ac {
>> #clock-cells = <1>;
>> compatible = "st,stih416-clkgenc", "st,clkgen-vcc";
>> reg = <0xfe8308ac 12>;
>>
>> - clocks = <&CLK_S_VCC_HD>, <&CLOCKGEN_C 1>,
>> - <&CLK_S_TMDS_FROMPHY>, <&CLOCKGEN_C 2>;
>> -
>> - clock-output-names =
>> - "CLK_S_PIX_HDMI", "CLK_S_PIX_DVO",
>> - "CLK_S_OUT_DVO", "CLK_S_PIX_HD",
>> - "CLK_S_HDDAC", "CLK_S_DENC",
>> - "CLK_S_SDDAC", "CLK_S_PIX_MAIN",
>> - "CLK_S_PIX_AUX", "CLK_S_STFE_FRC_0",
>> - "CLK_S_REF_MCRU", "CLK_S_SLAVE_MCRU",
>> - "CLK_S_TMDS_HDMI", "CLK_S_HDMI_REJECT_PLL",
>> - "CLK_S_THSENS";
>> + clocks = <&clk_s_vcc_hd>,
>> + <&clockgen_c 1>,
>> + <&clk_s_tmds_fromphy>,
>> + <&clockgen_c 2>;
>> +
>> + clock-output-names = "clk-s-pix-hdmi",
>> + "clk-s-pix-dvo",
>> + "clk-s-out-dvo",
>> + "clk-s-pix-hd",
>> + "clk-s-hddac",
>> + "clk-s-denc",
>> + "clk-s-sddac",
>> + "clk-s-pix-main",
>> + "clk-s-pix-aux",
>> + "clk-s-stfe-frc-0",
>> + "clk-s-ref-mcru",
>> + "clk-s-slave-mcru",
>> + "clk-s-tmds-hdmi",
>> + "clk-s-hdmi-reject-pll",
>> + "clk-s-thsens";
>> };
>>
>> diff --git a/Documentation/devicetree/bindings/clock/st/st,clkgen.txt b/Documentation/devicetree/bindings/clock/st/st,clkgen.txt
>> index 49ec5ae..427bad8 100644
>> --- a/Documentation/devicetree/bindings/clock/st/st,clkgen.txt
>> +++ b/Documentation/devicetree/bindings/clock/st/st,clkgen.txt
>> @@ -24,60 +24,72 @@ address is common of all subnode.
>> quadfs_node {
>> ...
>> };
>> +
>> + mux_node {
>> + ...
>> + };
>> +
>> + vcc_node {
>> + ...
>> + };
>> ...
>> };
>>
>> This binding uses the common clock binding[1].
>> -Each subnode should use the binding discribe in [2]..[4]
>> +Each subnode should use the binding discribe in [2]..[7]
>>
>> [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
>> -[2] Documentation/devicetree/bindings/clock/st,quadfs.txt
>> -[3] Documentation/devicetree/bindings/clock/st,quadfs.txt
>> -[4] Documentation/devicetree/bindings/clock/st,quadfs.txt
>> +[2] Documentation/devicetree/bindings/clock/st,clkgen-divmux.txt
>> +[3] Documentation/devicetree/bindings/clock/st,clkgen-mux.txt
>> +[4] Documentation/devicetree/bindings/clock/st,clkgen-pll.txt
>> +[5] Documentation/devicetree/bindings/clock/st,clkgen-prediv.txt
>> +[6] Documentation/devicetree/bindings/clock/st,vcc.txt
>> +[7] Documentation/devicetree/bindings/clock/st,quadfs.txt
>> +
>>
>> Required properties:
>> - reg : A Base address and length of the register set.
>>
>> Example:
>>
>> - clockgenA at fee62000 {
>> + clockgen-a at fee62000 {
>>
>> reg = <0xfee62000 0xb48>;
>>
>> - CLK_S_A0_PLL: CLK_S_A0_PLL {
>> + clk_s_a0_pll: clk-s-a0-pll {
>> #clock-cells = <1>;
>> compatible = "st,clkgena-plls-c65";
>>
>> - clocks = <&CLK_SYSIN>;
>> + clocks = <&clk-sysin>;
>>
>> - clock-output-names = "CLK_S_A0_PLL0_HS",
>> - "CLK_S_A0_PLL0_LS",
>> - "CLK_S_A0_PLL1";
>> + clock-output-names = "clk-s-a0-pll0-hs",
>> + "clk-s-a0-pll0-ls",
>> + "clk-s-a0-pll1";
>> };
>>
>> - CLK_S_A0_OSC_PREDIV: CLK_S_A0_OSC_PREDIV {
>> + clk_s_a0_osc_prediv: clk-s-a0-osc-prediv {
>> #clock-cells = <0>;
>> compatible = "st,clkgena-prediv-c65",
>> "st,clkgena-prediv";
>>
>> - clocks = <&CLK_SYSIN>;
>> + clocks = <&clk_sysin>;
>>
>> - clock-output-names = "CLK_S_A0_OSC_PREDIV";
>> + clock-output-names = "clk-s-a0-osc-prediv";
>> };
>>
>> - CLK_S_A0_HS: CLK_S_A0_HS {
>> + clk_s_a0_hs: clk-s-a0-hs {
>> #clock-cells = <1>;
>> compatible = "st,clkgena-divmux-c65-hs",
>> "st,clkgena-divmux";
>>
>> - clocks = <&CLK_S_A0_OSC_PREDIV>,
>> - <&CLK_S_A0_PLL 0>, /* PLL0 HS */
>> - <&CLK_S_A0_PLL 2>; /* PLL1 */
>> + clocks = <&clk-s_a0_osc_prediv>,
>> + <&clk-s_a0_pll 0>, /* pll0 hs */
>> + <&clk-s_a0_pll 2>; /* pll1 */
>>
>> - clock-output-names = "CLK_S_FDMA_0",
>> - "CLK_S_FDMA_1",
>> - ""; /* CLK_S_JIT_SENSE */
>> - /* Fourth output unused */
>> + clock-output-names = "clk-s-fdma-0",
>> + "clk-s-fdma-1",
>> + ""; /* clk-s-jit-sense */
>> + /* fourth output unused */
>> };
>> };
>>
>> diff --git a/Documentation/devicetree/bindings/clock/st/st,quadfs.txt b/Documentation/devicetree/bindings/clock/st/st,quadfs.txt
>> index ec86d62..cedeb9c 100644
>> --- a/Documentation/devicetree/bindings/clock/st/st,quadfs.txt
>> +++ b/Documentation/devicetree/bindings/clock/st/st,quadfs.txt
>> @@ -15,6 +15,9 @@ Required properties:
>> "st,stih416-quadfs432", "st,quadfs"
>> "st,stih416-quadfs660-E", "st,quadfs"
>> "st,stih416-quadfs660-F", "st,quadfs"
>> + "st,stih407-quadfs660-C", "st,quadfs"
>> + "st,stih407-quadfs660-D", "st,quadfs"
>> +
>>
>> - #clock-cells : from common clock binding; shall be set to 1.
>>
>> @@ -32,14 +35,14 @@ Required properties:
>>
>> Example:
>>
>> - CLOCKGEN_E: CLOCKGEN_E {
>> + clockgen_e: clockgen-e at fd3208bc {
>> #clock-cells = <1>;
>> compatible = "st,stih416-quadfs660-E", "st,quadfs";
>> reg = <0xfd3208bc 0xB0>;
>>
>> - clocks = <&CLK_SYSIN>;
>> - clock-output-names = "CLK_M_PIX_MDTP_0",
>> - "CLK_M_PIX_MDTP_1",
>> - "CLK_M_PIX_MDTP_2",
>> - "CLK_M_MPELPC";
>> + clocks = <&clk_sysin>;
>> + clock-output-names = "clk-m-pix-mdtp-0",
>> + "clk-m-pix-mdtp-1",
>> + "clk-m-pix-mdtp-2",
>> + "clk-m-mpelpc";
>> };
>> --
>> 1.9.1
>>
>>
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PATCH v2 10/14] drivers: clk: st: STiH407: Support for clockgenC0
2014-06-30 9:30 ` Mark Rutland
(?)
@ 2014-07-01 12:11 ` Gabriel Fernandez
-1 siblings, 0 replies; 49+ messages in thread
From: Gabriel Fernandez @ 2014-07-01 12:11 UTC (permalink / raw)
To: Mark Rutland
Cc: Gabriel FERNANDEZ, mturquette, robh+dt, Pawel Moll,
ijc+devicetree, galak, devicetree, linux-doc, linux-kernel,
linux-arm-kernel, kernel, Lee Jones, Olivier Bideau
On 30 June 2014 11:30, Mark Rutland <mark.rutland@arm.com> wrote:
> On Fri, Jun 27, 2014 at 02:25:07PM +0100, Gabriel FERNANDEZ wrote:
>> The patch added support for DT registration of ClockGenC0
>> It includes 2 c32 type PLL and a 660 Quadfs.
>>
>> Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org>
>> Signed-off-by: Olivier Bideau <olivier.bideau@st.com>
>> Acked-by: Peter Griffin <peter.griffin@linaro.org>
>> ---
>> drivers/clk/st/clkgen-fsyn.c | 47 ++++++++++++++++++++++++++++++++++++++++++++
>> drivers/clk/st/clkgen-pll.c | 32 ++++++++++++++++++++++++++++++
>> 2 files changed, 79 insertions(+)
>>
>> diff --git a/drivers/clk/st/clkgen-fsyn.c b/drivers/clk/st/clkgen-fsyn.c
>> index b2b73f4..0e0d5f9 100644
>> --- a/drivers/clk/st/clkgen-fsyn.c
>> +++ b/drivers/clk/st/clkgen-fsyn.c
>> @@ -255,6 +255,49 @@ static const struct clkgen_quadfs_data st_fs660c32_F_416 = {
>> .get_rate = clk_fs660c32_dig_get_rate,
>> };
>>
>> +static const struct clkgen_quadfs_data st_fs660c32_C_407 = {
>> + .nrst_present = true,
>> + .nrst = { CLKGEN_FIELD(0x2f0, 0x1, 0),
>> + CLKGEN_FIELD(0x2f0, 0x1, 1),
>> + CLKGEN_FIELD(0x2f0, 0x1, 2),
>> + CLKGEN_FIELD(0x2f0, 0x1, 3) },
>> + .npda = CLKGEN_FIELD(0x2f0, 0x1, 12),
>> + .nsb = { CLKGEN_FIELD(0x2f0, 0x1, 8),
>> + CLKGEN_FIELD(0x2f0, 0x1, 9),
>> + CLKGEN_FIELD(0x2f0, 0x1, 10),
>> + CLKGEN_FIELD(0x2f0, 0x1, 11) },
>> + .nsdiv_present = true,
>> + .nsdiv = { CLKGEN_FIELD(0x304, 0x1, 24),
>> + CLKGEN_FIELD(0x308, 0x1, 24),
>> + CLKGEN_FIELD(0x30c, 0x1, 24),
>> + CLKGEN_FIELD(0x310, 0x1, 24) },
>> + .mdiv = { CLKGEN_FIELD(0x304, 0x1f, 15),
>> + CLKGEN_FIELD(0x308, 0x1f, 15),
>> + CLKGEN_FIELD(0x30c, 0x1f, 15),
>> + CLKGEN_FIELD(0x310, 0x1f, 15) },
>> + .en = { CLKGEN_FIELD(0x2fc, 0x1, 0),
>> + CLKGEN_FIELD(0x2fc, 0x1, 1),
>> + CLKGEN_FIELD(0x2fc, 0x1, 2),
>> + CLKGEN_FIELD(0x2fc, 0x1, 3) },
>> + .ndiv = CLKGEN_FIELD(0x2f4, 0x7, 16),
>> + .pe = { CLKGEN_FIELD(0x304, 0x7fff, 0),
>> + CLKGEN_FIELD(0x308, 0x7fff, 0),
>> + CLKGEN_FIELD(0x30c, 0x7fff, 0),
>> + CLKGEN_FIELD(0x310, 0x7fff, 0) },
>> + .sdiv = { CLKGEN_FIELD(0x304, 0xf, 20),
>> + CLKGEN_FIELD(0x308, 0xf, 20),
>> + CLKGEN_FIELD(0x30c, 0xf, 20),
>> + CLKGEN_FIELD(0x310, 0xf, 20) },
>> + .lockstatus_present = true,
>> + .lock_status = CLKGEN_FIELD(0x2A0, 0x1, 24),
>> + .powerup_polarity = 1,
>> + .standby_polarity = 1,
>> + .pll_ops = &st_quadfs_pll_c32_ops,
>> + .rtbl = fs660c32_rtbl,
>> + .rtbl_cnt = ARRAY_SIZE(fs660c32_rtbl),
>> + .get_rate = clk_fs660c32_dig_get_rate,
>> +};
>> +
>> /**
>> * DOC: A Frequency Synthesizer that multiples its input clock by a fixed factor
>> *
>> @@ -938,6 +981,10 @@ static struct of_device_id quadfs_of_match[] = {
>> .compatible = "st,stih416-quadfs660-F",
>> .data = (void *)&st_fs660c32_F_416
>> },
>> + {
>> + .compatible = "st,stih407-quadfs660-C",
>> + .data = (void *)&st_fs660c32_C_407
>
> Surely a (void*) cast isn't necessary?
Ok
Thanks Mark
Gabriel
>
> Mark.
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PATCH v2 10/14] drivers: clk: st: STiH407: Support for clockgenC0
@ 2014-07-01 12:11 ` Gabriel Fernandez
0 siblings, 0 replies; 49+ messages in thread
From: Gabriel Fernandez @ 2014-07-01 12:11 UTC (permalink / raw)
To: Mark Rutland
Cc: Gabriel FERNANDEZ, mturquette, robh+dt, Pawel Moll,
ijc+devicetree, galak, devicetree, linux-doc, linux-kernel,
linux-arm-kernel, kernel, Lee Jones, Olivier Bideau
On 30 June 2014 11:30, Mark Rutland <mark.rutland@arm.com> wrote:
> On Fri, Jun 27, 2014 at 02:25:07PM +0100, Gabriel FERNANDEZ wrote:
>> The patch added support for DT registration of ClockGenC0
>> It includes 2 c32 type PLL and a 660 Quadfs.
>>
>> Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org>
>> Signed-off-by: Olivier Bideau <olivier.bideau@st.com>
>> Acked-by: Peter Griffin <peter.griffin@linaro.org>
>> ---
>> drivers/clk/st/clkgen-fsyn.c | 47 ++++++++++++++++++++++++++++++++++++++++++++
>> drivers/clk/st/clkgen-pll.c | 32 ++++++++++++++++++++++++++++++
>> 2 files changed, 79 insertions(+)
>>
>> diff --git a/drivers/clk/st/clkgen-fsyn.c b/drivers/clk/st/clkgen-fsyn.c
>> index b2b73f4..0e0d5f9 100644
>> --- a/drivers/clk/st/clkgen-fsyn.c
>> +++ b/drivers/clk/st/clkgen-fsyn.c
>> @@ -255,6 +255,49 @@ static const struct clkgen_quadfs_data st_fs660c32_F_416 = {
>> .get_rate = clk_fs660c32_dig_get_rate,
>> };
>>
>> +static const struct clkgen_quadfs_data st_fs660c32_C_407 = {
>> + .nrst_present = true,
>> + .nrst = { CLKGEN_FIELD(0x2f0, 0x1, 0),
>> + CLKGEN_FIELD(0x2f0, 0x1, 1),
>> + CLKGEN_FIELD(0x2f0, 0x1, 2),
>> + CLKGEN_FIELD(0x2f0, 0x1, 3) },
>> + .npda = CLKGEN_FIELD(0x2f0, 0x1, 12),
>> + .nsb = { CLKGEN_FIELD(0x2f0, 0x1, 8),
>> + CLKGEN_FIELD(0x2f0, 0x1, 9),
>> + CLKGEN_FIELD(0x2f0, 0x1, 10),
>> + CLKGEN_FIELD(0x2f0, 0x1, 11) },
>> + .nsdiv_present = true,
>> + .nsdiv = { CLKGEN_FIELD(0x304, 0x1, 24),
>> + CLKGEN_FIELD(0x308, 0x1, 24),
>> + CLKGEN_FIELD(0x30c, 0x1, 24),
>> + CLKGEN_FIELD(0x310, 0x1, 24) },
>> + .mdiv = { CLKGEN_FIELD(0x304, 0x1f, 15),
>> + CLKGEN_FIELD(0x308, 0x1f, 15),
>> + CLKGEN_FIELD(0x30c, 0x1f, 15),
>> + CLKGEN_FIELD(0x310, 0x1f, 15) },
>> + .en = { CLKGEN_FIELD(0x2fc, 0x1, 0),
>> + CLKGEN_FIELD(0x2fc, 0x1, 1),
>> + CLKGEN_FIELD(0x2fc, 0x1, 2),
>> + CLKGEN_FIELD(0x2fc, 0x1, 3) },
>> + .ndiv = CLKGEN_FIELD(0x2f4, 0x7, 16),
>> + .pe = { CLKGEN_FIELD(0x304, 0x7fff, 0),
>> + CLKGEN_FIELD(0x308, 0x7fff, 0),
>> + CLKGEN_FIELD(0x30c, 0x7fff, 0),
>> + CLKGEN_FIELD(0x310, 0x7fff, 0) },
>> + .sdiv = { CLKGEN_FIELD(0x304, 0xf, 20),
>> + CLKGEN_FIELD(0x308, 0xf, 20),
>> + CLKGEN_FIELD(0x30c, 0xf, 20),
>> + CLKGEN_FIELD(0x310, 0xf, 20) },
>> + .lockstatus_present = true,
>> + .lock_status = CLKGEN_FIELD(0x2A0, 0x1, 24),
>> + .powerup_polarity = 1,
>> + .standby_polarity = 1,
>> + .pll_ops = &st_quadfs_pll_c32_ops,
>> + .rtbl = fs660c32_rtbl,
>> + .rtbl_cnt = ARRAY_SIZE(fs660c32_rtbl),
>> + .get_rate = clk_fs660c32_dig_get_rate,
>> +};
>> +
>> /**
>> * DOC: A Frequency Synthesizer that multiples its input clock by a fixed factor
>> *
>> @@ -938,6 +981,10 @@ static struct of_device_id quadfs_of_match[] = {
>> .compatible = "st,stih416-quadfs660-F",
>> .data = (void *)&st_fs660c32_F_416
>> },
>> + {
>> + .compatible = "st,stih407-quadfs660-C",
>> + .data = (void *)&st_fs660c32_C_407
>
> Surely a (void*) cast isn't necessary?
Ok
Thanks Mark
Gabriel
>
> Mark.
^ permalink raw reply [flat|nested] 49+ messages in thread
* [PATCH v2 10/14] drivers: clk: st: STiH407: Support for clockgenC0
@ 2014-07-01 12:11 ` Gabriel Fernandez
0 siblings, 0 replies; 49+ messages in thread
From: Gabriel Fernandez @ 2014-07-01 12:11 UTC (permalink / raw)
To: linux-arm-kernel
On 30 June 2014 11:30, Mark Rutland <mark.rutland@arm.com> wrote:
> On Fri, Jun 27, 2014 at 02:25:07PM +0100, Gabriel FERNANDEZ wrote:
>> The patch added support for DT registration of ClockGenC0
>> It includes 2 c32 type PLL and a 660 Quadfs.
>>
>> Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org>
>> Signed-off-by: Olivier Bideau <olivier.bideau@st.com>
>> Acked-by: Peter Griffin <peter.griffin@linaro.org>
>> ---
>> drivers/clk/st/clkgen-fsyn.c | 47 ++++++++++++++++++++++++++++++++++++++++++++
>> drivers/clk/st/clkgen-pll.c | 32 ++++++++++++++++++++++++++++++
>> 2 files changed, 79 insertions(+)
>>
>> diff --git a/drivers/clk/st/clkgen-fsyn.c b/drivers/clk/st/clkgen-fsyn.c
>> index b2b73f4..0e0d5f9 100644
>> --- a/drivers/clk/st/clkgen-fsyn.c
>> +++ b/drivers/clk/st/clkgen-fsyn.c
>> @@ -255,6 +255,49 @@ static const struct clkgen_quadfs_data st_fs660c32_F_416 = {
>> .get_rate = clk_fs660c32_dig_get_rate,
>> };
>>
>> +static const struct clkgen_quadfs_data st_fs660c32_C_407 = {
>> + .nrst_present = true,
>> + .nrst = { CLKGEN_FIELD(0x2f0, 0x1, 0),
>> + CLKGEN_FIELD(0x2f0, 0x1, 1),
>> + CLKGEN_FIELD(0x2f0, 0x1, 2),
>> + CLKGEN_FIELD(0x2f0, 0x1, 3) },
>> + .npda = CLKGEN_FIELD(0x2f0, 0x1, 12),
>> + .nsb = { CLKGEN_FIELD(0x2f0, 0x1, 8),
>> + CLKGEN_FIELD(0x2f0, 0x1, 9),
>> + CLKGEN_FIELD(0x2f0, 0x1, 10),
>> + CLKGEN_FIELD(0x2f0, 0x1, 11) },
>> + .nsdiv_present = true,
>> + .nsdiv = { CLKGEN_FIELD(0x304, 0x1, 24),
>> + CLKGEN_FIELD(0x308, 0x1, 24),
>> + CLKGEN_FIELD(0x30c, 0x1, 24),
>> + CLKGEN_FIELD(0x310, 0x1, 24) },
>> + .mdiv = { CLKGEN_FIELD(0x304, 0x1f, 15),
>> + CLKGEN_FIELD(0x308, 0x1f, 15),
>> + CLKGEN_FIELD(0x30c, 0x1f, 15),
>> + CLKGEN_FIELD(0x310, 0x1f, 15) },
>> + .en = { CLKGEN_FIELD(0x2fc, 0x1, 0),
>> + CLKGEN_FIELD(0x2fc, 0x1, 1),
>> + CLKGEN_FIELD(0x2fc, 0x1, 2),
>> + CLKGEN_FIELD(0x2fc, 0x1, 3) },
>> + .ndiv = CLKGEN_FIELD(0x2f4, 0x7, 16),
>> + .pe = { CLKGEN_FIELD(0x304, 0x7fff, 0),
>> + CLKGEN_FIELD(0x308, 0x7fff, 0),
>> + CLKGEN_FIELD(0x30c, 0x7fff, 0),
>> + CLKGEN_FIELD(0x310, 0x7fff, 0) },
>> + .sdiv = { CLKGEN_FIELD(0x304, 0xf, 20),
>> + CLKGEN_FIELD(0x308, 0xf, 20),
>> + CLKGEN_FIELD(0x30c, 0xf, 20),
>> + CLKGEN_FIELD(0x310, 0xf, 20) },
>> + .lockstatus_present = true,
>> + .lock_status = CLKGEN_FIELD(0x2A0, 0x1, 24),
>> + .powerup_polarity = 1,
>> + .standby_polarity = 1,
>> + .pll_ops = &st_quadfs_pll_c32_ops,
>> + .rtbl = fs660c32_rtbl,
>> + .rtbl_cnt = ARRAY_SIZE(fs660c32_rtbl),
>> + .get_rate = clk_fs660c32_dig_get_rate,
>> +};
>> +
>> /**
>> * DOC: A Frequency Synthesizer that multiples its input clock by a fixed factor
>> *
>> @@ -938,6 +981,10 @@ static struct of_device_id quadfs_of_match[] = {
>> .compatible = "st,stih416-quadfs660-F",
>> .data = (void *)&st_fs660c32_F_416
>> },
>> + {
>> + .compatible = "st,stih407-quadfs660-C",
>> + .data = (void *)&st_fs660c32_C_407
>
> Surely a (void*) cast isn't necessary?
Ok
Thanks Mark
Gabriel
>
> Mark.
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PATCH v2 04/14] clk: st: Adds Flexgen clock binding
2014-06-30 9:26 ` Mark Rutland
(?)
@ 2014-07-01 12:11 ` Gabriel Fernandez
-1 siblings, 0 replies; 49+ messages in thread
From: Gabriel Fernandez @ 2014-07-01 12:11 UTC (permalink / raw)
To: Mark Rutland
Cc: Gabriel FERNANDEZ, mturquette, robh+dt, Pawel Moll,
ijc+devicetree, galak, devicetree, linux-doc, linux-kernel,
linux-arm-kernel, kernel, Lee Jones
Thanks for the review Mark,
I'll rework this documentation to answer all these questions
Thanks
Gabriel
On 30 June 2014 11:26, Mark Rutland <mark.rutland@arm.com> wrote:
> On Fri, Jun 27, 2014 at 02:25:01PM +0100, Gabriel FERNANDEZ wrote:
>> A Flexgen structure is composed by:
>> - a clock cross bar (represented by a mux element)
>> - a pre and final dividers (represented by a divider and gate elements)
>>
>> Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org>
>> Acked-by: Peter Griffin <peter.griffin@linaro.org>
>> ---
>> .../devicetree/bindings/clock/st/st,clkgen.txt | 5 +++
>> .../devicetree/bindings/clock/st/st,flexgen.txt | 48 ++++++++++++++++++++++
>> 2 files changed, 53 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/clock/st/st,flexgen.txt
>>
>> diff --git a/Documentation/devicetree/bindings/clock/st/st,clkgen.txt b/Documentation/devicetree/bindings/clock/st/st,clkgen.txt
>> index 427bad8..78978f1 100644
>> --- a/Documentation/devicetree/bindings/clock/st/st,clkgen.txt
>> +++ b/Documentation/devicetree/bindings/clock/st/st,clkgen.txt
>> @@ -32,6 +32,10 @@ address is common of all subnode.
>> vcc_node {
>> ...
>> };
>> +
>> + flexgen_node {
>> + ...
>> + };
>> ...
>> };
>>
>> @@ -45,6 +49,7 @@ Each subnode should use the binding discribe in [2]..[7]
>> [5] Documentation/devicetree/bindings/clock/st,clkgen-prediv.txt
>> [6] Documentation/devicetree/bindings/clock/st,vcc.txt
>> [7] Documentation/devicetree/bindings/clock/st,quadfs.txt
>> +[8] Documentation/devicetree/bindings/clock/st,flexgen.txt
>>
>>
>> Required properties:
>> diff --git a/Documentation/devicetree/bindings/clock/st/st,flexgen.txt b/Documentation/devicetree/bindings/clock/st/st,flexgen.txt
>> new file mode 100644
>> index 0000000..f2d4333
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/clock/st/st,flexgen.txt
>> @@ -0,0 +1,48 @@
>> +Binding for a type of flexgen structure found on certain
>> +STMicroelectronics consumer electronics SoC devices
>> +
>> +This structure includes:
>> +- a clock cross bar (represented by a mux element)
>> +- a pre and final dividers (represented by a divider and gate elements)
>> +
>> +This binding uses the common clock binding[1].
>> +
>> +[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
>> +
>> +Required properties:
>> +- compatible : shall be:
>> + "st,flexgen"
>
> That looks very vague. Is this a sub-node of a larger block?
>
> Might there be a future flexgen revision that looks different?
>
>> +- #clock-cells : from common clock binding; shall be set to 1.
>
> what does the clock cell represent? Is it just a linear index from 0?
>
>> +- clocks : from common clock binding
>
> This is a completely useless description.
>
> Which clock inputs do you expect clocks for? How many? Are they named?
>
>> +
>> +- clock-output-names : From common clock binding. The block has 4
>> + clock outputs but not all of them in a specific instance
>> + have to be used in the SoC. If a clock name is left as
>> + an empty string then no clock will be created for the
>> + output associated with that string index. If fewer than
>> + 4 strings are provided then no clocks will be created
>> + for the remaining outputs.
>
> That's a Linux-internal detail, surely?
>
> Why do we even do that?
>
> Mark.
>
>> +
>> +Example:
>> +
>> + clockgen-d2@x9106000 {
>> + compatible = "st,clkgen-c32";
>> + reg = <0x9106000 0x1000>;
>> +
>> + clk_s_d2_flexgen: clk-s-d2-flexgen {
>> + compatible = "st,flexgen";
>> +
>> + #clock-cells = <1>;
>> + clocks = <&clk_s_d2_quadfs 0>,
>> + <&clk_s_d2_quadfs 1>,
>> + <&clk_s_d2_quadfs 2>,
>> + <&clk_s_d2_quadfs 3>;
>> +
>> + clock-output-names = "clk-pix-main-disp",
>> + "clk-pix-pip",
>> + "clk-pix-gdp1",
>> + "clk-pix-gdp2";
>> + };
>> + };
>> --
>> 1.9.1
>>
>>
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PATCH v2 04/14] clk: st: Adds Flexgen clock binding
@ 2014-07-01 12:11 ` Gabriel Fernandez
0 siblings, 0 replies; 49+ messages in thread
From: Gabriel Fernandez @ 2014-07-01 12:11 UTC (permalink / raw)
To: Mark Rutland
Cc: Gabriel FERNANDEZ, mturquette, robh+dt, Pawel Moll,
ijc+devicetree, galak, devicetree, linux-doc, linux-kernel,
linux-arm-kernel, kernel, Lee Jones
Thanks for the review Mark,
I'll rework this documentation to answer all these questions
Thanks
Gabriel
On 30 June 2014 11:26, Mark Rutland <mark.rutland@arm.com> wrote:
> On Fri, Jun 27, 2014 at 02:25:01PM +0100, Gabriel FERNANDEZ wrote:
>> A Flexgen structure is composed by:
>> - a clock cross bar (represented by a mux element)
>> - a pre and final dividers (represented by a divider and gate elements)
>>
>> Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org>
>> Acked-by: Peter Griffin <peter.griffin@linaro.org>
>> ---
>> .../devicetree/bindings/clock/st/st,clkgen.txt | 5 +++
>> .../devicetree/bindings/clock/st/st,flexgen.txt | 48 ++++++++++++++++++++++
>> 2 files changed, 53 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/clock/st/st,flexgen.txt
>>
>> diff --git a/Documentation/devicetree/bindings/clock/st/st,clkgen.txt b/Documentation/devicetree/bindings/clock/st/st,clkgen.txt
>> index 427bad8..78978f1 100644
>> --- a/Documentation/devicetree/bindings/clock/st/st,clkgen.txt
>> +++ b/Documentation/devicetree/bindings/clock/st/st,clkgen.txt
>> @@ -32,6 +32,10 @@ address is common of all subnode.
>> vcc_node {
>> ...
>> };
>> +
>> + flexgen_node {
>> + ...
>> + };
>> ...
>> };
>>
>> @@ -45,6 +49,7 @@ Each subnode should use the binding discribe in [2]..[7]
>> [5] Documentation/devicetree/bindings/clock/st,clkgen-prediv.txt
>> [6] Documentation/devicetree/bindings/clock/st,vcc.txt
>> [7] Documentation/devicetree/bindings/clock/st,quadfs.txt
>> +[8] Documentation/devicetree/bindings/clock/st,flexgen.txt
>>
>>
>> Required properties:
>> diff --git a/Documentation/devicetree/bindings/clock/st/st,flexgen.txt b/Documentation/devicetree/bindings/clock/st/st,flexgen.txt
>> new file mode 100644
>> index 0000000..f2d4333
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/clock/st/st,flexgen.txt
>> @@ -0,0 +1,48 @@
>> +Binding for a type of flexgen structure found on certain
>> +STMicroelectronics consumer electronics SoC devices
>> +
>> +This structure includes:
>> +- a clock cross bar (represented by a mux element)
>> +- a pre and final dividers (represented by a divider and gate elements)
>> +
>> +This binding uses the common clock binding[1].
>> +
>> +[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
>> +
>> +Required properties:
>> +- compatible : shall be:
>> + "st,flexgen"
>
> That looks very vague. Is this a sub-node of a larger block?
>
> Might there be a future flexgen revision that looks different?
>
>> +- #clock-cells : from common clock binding; shall be set to 1.
>
> what does the clock cell represent? Is it just a linear index from 0?
>
>> +- clocks : from common clock binding
>
> This is a completely useless description.
>
> Which clock inputs do you expect clocks for? How many? Are they named?
>
>> +
>> +- clock-output-names : From common clock binding. The block has 4
>> + clock outputs but not all of them in a specific instance
>> + have to be used in the SoC. If a clock name is left as
>> + an empty string then no clock will be created for the
>> + output associated with that string index. If fewer than
>> + 4 strings are provided then no clocks will be created
>> + for the remaining outputs.
>
> That's a Linux-internal detail, surely?
>
> Why do we even do that?
>
> Mark.
>
>> +
>> +Example:
>> +
>> + clockgen-d2@x9106000 {
>> + compatible = "st,clkgen-c32";
>> + reg = <0x9106000 0x1000>;
>> +
>> + clk_s_d2_flexgen: clk-s-d2-flexgen {
>> + compatible = "st,flexgen";
>> +
>> + #clock-cells = <1>;
>> + clocks = <&clk_s_d2_quadfs 0>,
>> + <&clk_s_d2_quadfs 1>,
>> + <&clk_s_d2_quadfs 2>,
>> + <&clk_s_d2_quadfs 3>;
>> +
>> + clock-output-names = "clk-pix-main-disp",
>> + "clk-pix-pip",
>> + "clk-pix-gdp1",
>> + "clk-pix-gdp2";
>> + };
>> + };
>> --
>> 1.9.1
>>
>>
^ permalink raw reply [flat|nested] 49+ messages in thread
* [PATCH v2 04/14] clk: st: Adds Flexgen clock binding
@ 2014-07-01 12:11 ` Gabriel Fernandez
0 siblings, 0 replies; 49+ messages in thread
From: Gabriel Fernandez @ 2014-07-01 12:11 UTC (permalink / raw)
To: linux-arm-kernel
Thanks for the review Mark,
I'll rework this documentation to answer all these questions
Thanks
Gabriel
On 30 June 2014 11:26, Mark Rutland <mark.rutland@arm.com> wrote:
> On Fri, Jun 27, 2014 at 02:25:01PM +0100, Gabriel FERNANDEZ wrote:
>> A Flexgen structure is composed by:
>> - a clock cross bar (represented by a mux element)
>> - a pre and final dividers (represented by a divider and gate elements)
>>
>> Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org>
>> Acked-by: Peter Griffin <peter.griffin@linaro.org>
>> ---
>> .../devicetree/bindings/clock/st/st,clkgen.txt | 5 +++
>> .../devicetree/bindings/clock/st/st,flexgen.txt | 48 ++++++++++++++++++++++
>> 2 files changed, 53 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/clock/st/st,flexgen.txt
>>
>> diff --git a/Documentation/devicetree/bindings/clock/st/st,clkgen.txt b/Documentation/devicetree/bindings/clock/st/st,clkgen.txt
>> index 427bad8..78978f1 100644
>> --- a/Documentation/devicetree/bindings/clock/st/st,clkgen.txt
>> +++ b/Documentation/devicetree/bindings/clock/st/st,clkgen.txt
>> @@ -32,6 +32,10 @@ address is common of all subnode.
>> vcc_node {
>> ...
>> };
>> +
>> + flexgen_node {
>> + ...
>> + };
>> ...
>> };
>>
>> @@ -45,6 +49,7 @@ Each subnode should use the binding discribe in [2]..[7]
>> [5] Documentation/devicetree/bindings/clock/st,clkgen-prediv.txt
>> [6] Documentation/devicetree/bindings/clock/st,vcc.txt
>> [7] Documentation/devicetree/bindings/clock/st,quadfs.txt
>> +[8] Documentation/devicetree/bindings/clock/st,flexgen.txt
>>
>>
>> Required properties:
>> diff --git a/Documentation/devicetree/bindings/clock/st/st,flexgen.txt b/Documentation/devicetree/bindings/clock/st/st,flexgen.txt
>> new file mode 100644
>> index 0000000..f2d4333
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/clock/st/st,flexgen.txt
>> @@ -0,0 +1,48 @@
>> +Binding for a type of flexgen structure found on certain
>> +STMicroelectronics consumer electronics SoC devices
>> +
>> +This structure includes:
>> +- a clock cross bar (represented by a mux element)
>> +- a pre and final dividers (represented by a divider and gate elements)
>> +
>> +This binding uses the common clock binding[1].
>> +
>> +[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
>> +
>> +Required properties:
>> +- compatible : shall be:
>> + "st,flexgen"
>
> That looks very vague. Is this a sub-node of a larger block?
>
> Might there be a future flexgen revision that looks different?
>
>> +- #clock-cells : from common clock binding; shall be set to 1.
>
> what does the clock cell represent? Is it just a linear index from 0?
>
>> +- clocks : from common clock binding
>
> This is a completely useless description.
>
> Which clock inputs do you expect clocks for? How many? Are they named?
>
>> +
>> +- clock-output-names : From common clock binding. The block has 4
>> + clock outputs but not all of them in a specific instance
>> + have to be used in the SoC. If a clock name is left as
>> + an empty string then no clock will be created for the
>> + output associated with that string index. If fewer than
>> + 4 strings are provided then no clocks will be created
>> + for the remaining outputs.
>
> That's a Linux-internal detail, surely?
>
> Why do we even do that?
>
> Mark.
>
>> +
>> +Example:
>> +
>> + clockgen-d2 at x9106000 {
>> + compatible = "st,clkgen-c32";
>> + reg = <0x9106000 0x1000>;
>> +
>> + clk_s_d2_flexgen: clk-s-d2-flexgen {
>> + compatible = "st,flexgen";
>> +
>> + #clock-cells = <1>;
>> + clocks = <&clk_s_d2_quadfs 0>,
>> + <&clk_s_d2_quadfs 1>,
>> + <&clk_s_d2_quadfs 2>,
>> + <&clk_s_d2_quadfs 3>;
>> +
>> + clock-output-names = "clk-pix-main-disp",
>> + "clk-pix-pip",
>> + "clk-pix-gdp1",
>> + "clk-pix-gdp2";
>> + };
>> + };
>> --
>> 1.9.1
>>
>>
^ permalink raw reply [flat|nested] 49+ messages in thread
end of thread, other threads:[~2014-07-01 12:11 UTC | newest]
Thread overview: 49+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2014-06-27 13:24 [PATCH v2 00/14] Add Flexgen Clock support Gabriel FERNANDEZ
2014-06-27 13:24 ` Gabriel FERNANDEZ
2014-06-27 13:24 ` [PATCH v2 01/14] clk: st: Update ST clock binding documentation Gabriel FERNANDEZ
2014-06-27 13:24 ` Gabriel FERNANDEZ
2014-06-30 9:23 ` Mark Rutland
2014-06-30 9:23 ` Mark Rutland
2014-06-30 9:23 ` Mark Rutland
2014-07-01 12:11 ` Gabriel Fernandez
2014-07-01 12:11 ` Gabriel Fernandez
2014-07-01 12:11 ` Gabriel Fernandez
2014-06-27 13:24 ` [PATCH v2 02/14] drivers: clk: st: use static const for stm_fs tables Gabriel FERNANDEZ
2014-06-27 13:24 ` Gabriel FERNANDEZ
2014-06-27 13:25 ` [PATCH v2 03/14] drivers: clk: st: use static const for clkgen_pll_data tables Gabriel FERNANDEZ
2014-06-27 13:25 ` Gabriel FERNANDEZ
2014-06-27 13:25 ` [PATCH v2 04/14] clk: st: Adds Flexgen clock binding Gabriel FERNANDEZ
2014-06-27 13:25 ` Gabriel FERNANDEZ
2014-06-30 9:26 ` Mark Rutland
2014-06-30 9:26 ` Mark Rutland
2014-06-30 9:26 ` Mark Rutland
2014-07-01 12:11 ` Gabriel Fernandez
2014-07-01 12:11 ` Gabriel Fernandez
2014-07-01 12:11 ` Gabriel Fernandez
2014-06-27 13:25 ` [PATCH v2 05/14] drivers: clk: st: STiH407: Support for Flexgen Clocks Gabriel FERNANDEZ
2014-06-27 13:25 ` Gabriel FERNANDEZ
2014-06-27 13:25 ` Gabriel FERNANDEZ
2014-06-27 13:25 ` [PATCH v2 06/14] drivers: clk: st: STiH407: Support for A9 MUX Clocks Gabriel FERNANDEZ
2014-06-27 13:25 ` Gabriel FERNANDEZ
2014-06-27 13:25 ` [PATCH v2 07/14] drivers: clk: st: STiH407: Support for clockgenA0 Gabriel FERNANDEZ
2014-06-27 13:25 ` Gabriel FERNANDEZ
2014-06-27 13:25 ` [PATCH v2 08/14] drivers: clk: st: Add polarity bit indication Gabriel FERNANDEZ
2014-06-27 13:25 ` Gabriel FERNANDEZ
2014-06-27 13:25 ` [PATCH v2 09/14] drivers: clk: st: Add quadfs reset handling Gabriel FERNANDEZ
2014-06-27 13:25 ` Gabriel FERNANDEZ
2014-06-27 13:25 ` [PATCH v2 10/14] drivers: clk: st: STiH407: Support for clockgenC0 Gabriel FERNANDEZ
2014-06-27 13:25 ` Gabriel FERNANDEZ
2014-06-30 9:30 ` Mark Rutland
2014-06-30 9:30 ` Mark Rutland
2014-06-30 9:30 ` Mark Rutland
2014-07-01 12:11 ` Gabriel Fernandez
2014-07-01 12:11 ` Gabriel Fernandez
2014-07-01 12:11 ` Gabriel Fernandez
2014-06-27 13:25 ` [PATCH v2 11/14] drivers: clk: st: STiH407: Support for clockgenD0/D2/D3 Gabriel FERNANDEZ
2014-06-27 13:25 ` Gabriel FERNANDEZ
2014-06-27 13:25 ` [PATCH v2 12/14] drivers: clk: st: STiH407: Support for clockgenA9 Gabriel FERNANDEZ
2014-06-27 13:25 ` Gabriel FERNANDEZ
2014-06-27 13:25 ` [PATCH v2 13/14] drivers: clk: st: Update frequency tables for fs660c32 and fs432c65 Gabriel FERNANDEZ
2014-06-27 13:25 ` Gabriel FERNANDEZ
2014-06-27 13:25 ` [PATCH v2 14/14] drivers: clk: st: Use round to closest divider flag Gabriel FERNANDEZ
2014-06-27 13:25 ` Gabriel FERNANDEZ
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