From: Chen-Yu Tsai <wens@csie.org> To: Boris BREZILLON <boris.brezillon@free-electrons.com> Cc: "Randy Dunlap" <rdunlap@infradead.org>, "Maxime Ripard" <maxime.ripard@free-electrons.com>, "Emilio López" <emilio@elopez.com.ar>, "Mike Turquette" <mturquette@linaro.org>, "Linus Walleij" <linus.walleij@linaro.org>, devicetree <devicetree@vger.kernel.org>, linux-kernel <linux-kernel@vger.kernel.org>, linux-arm-kernel <linux-arm-kernel@lists.infradead.org>, linux-doc@vger.kernel.org Subject: Re: [PATCH 06/15] clk: sunxi: add A31 APB0 gates compatible string to the documentation Date: Wed, 9 Apr 2014 21:59:02 +0800 [thread overview] Message-ID: <CAGb2v645Yu_1ODQhVcQjjFf1M0uf3aHBfRw4F_uhoYk9RozcOA@mail.gmail.com> (raw) In-Reply-To: <1397051478-4113-7-git-send-email-boris.brezillon@free-electrons.com> Hi, On Wed, Apr 9, 2014 at 9:51 PM, Boris BREZILLON <boris.brezillon@free-electrons.com> wrote: > Add the new "allwinner,sun6i-a31-apb0-gates-clk" compatible string to the > sunxi clock documentation. > > Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com> > --- > Documentation/devicetree/bindings/clock/sunxi.txt | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt b/Documentation/devicetree/bindings/clock/sunxi.txt > index c2cb762..bc30387 100644 > --- a/Documentation/devicetree/bindings/clock/sunxi.txt > +++ b/Documentation/devicetree/bindings/clock/sunxi.txt > @@ -25,6 +25,7 @@ Required properties: > "allwinner,sun4i-apb0-gates-clk" - for the APB0 gates on A10 > "allwinner,sun5i-a13-apb0-gates-clk" - for the APB0 gates on A13 > "allwinner,sun5i-a10s-apb0-gates-clk" - for the APB0 gates on A10s > + "allwinner,sun6i-a31-apb0-gates-clk" - for the APB0 gates on A10s ^^^^ Copy paste error here. ChenYu > "allwinner,sun7i-a20-apb0-gates-clk" - for the APB0 gates on A20 > "allwinner,sun4i-apb1-clk" - for the APB1 clock > "allwinner,sun4i-apb1-mux-clk" - for the APB1 clock muxing
WARNING: multiple messages have this Message-ID (diff)
From: wens@csie.org (Chen-Yu Tsai) To: linux-arm-kernel@lists.infradead.org Subject: [PATCH 06/15] clk: sunxi: add A31 APB0 gates compatible string to the documentation Date: Wed, 9 Apr 2014 21:59:02 +0800 [thread overview] Message-ID: <CAGb2v645Yu_1ODQhVcQjjFf1M0uf3aHBfRw4F_uhoYk9RozcOA@mail.gmail.com> (raw) In-Reply-To: <1397051478-4113-7-git-send-email-boris.brezillon@free-electrons.com> Hi, On Wed, Apr 9, 2014 at 9:51 PM, Boris BREZILLON <boris.brezillon@free-electrons.com> wrote: > Add the new "allwinner,sun6i-a31-apb0-gates-clk" compatible string to the > sunxi clock documentation. > > Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com> > --- > Documentation/devicetree/bindings/clock/sunxi.txt | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt b/Documentation/devicetree/bindings/clock/sunxi.txt > index c2cb762..bc30387 100644 > --- a/Documentation/devicetree/bindings/clock/sunxi.txt > +++ b/Documentation/devicetree/bindings/clock/sunxi.txt > @@ -25,6 +25,7 @@ Required properties: > "allwinner,sun4i-apb0-gates-clk" - for the APB0 gates on A10 > "allwinner,sun5i-a13-apb0-gates-clk" - for the APB0 gates on A13 > "allwinner,sun5i-a10s-apb0-gates-clk" - for the APB0 gates on A10s > + "allwinner,sun6i-a31-apb0-gates-clk" - for the APB0 gates on A10s ^^^^ Copy paste error here. ChenYu > "allwinner,sun7i-a20-apb0-gates-clk" - for the APB0 gates on A20 > "allwinner,sun4i-apb1-clk" - for the APB1 clock > "allwinner,sun4i-apb1-mux-clk" - for the APB1 clock muxing
next prev parent reply other threads:[~2014-04-09 13:59 UTC|newest] Thread overview: 91+ messages / expand[flat|nested] mbox.gz Atom feed top 2014-04-09 13:51 [PATCH 00/15] ARM: sunxi: add A31 PL pins support Boris BREZILLON 2014-04-09 13:51 ` Boris BREZILLON 2014-04-09 13:51 ` [PATCH 01/15] ARM: sunxi: dt: list all pinctrl compatible strings Boris BREZILLON 2014-04-09 13:51 ` Boris BREZILLON 2014-04-09 14:43 ` Maxime Ripard 2014-04-09 14:43 ` Maxime Ripard 2014-04-09 14:43 ` Maxime Ripard 2014-04-09 13:51 ` [PATCH 02/15] ARM: sunxi: dt: document pinctrl clock related properties Boris BREZILLON 2014-04-09 13:51 ` Boris BREZILLON 2014-04-09 14:45 ` Maxime Ripard 2014-04-09 14:45 ` Maxime Ripard 2014-04-09 13:51 ` [PATCH 03/15] ARM: sunxi: dt: add pinctrl clock-names properties Boris BREZILLON 2014-04-09 13:51 ` Boris BREZILLON 2014-04-09 13:51 ` [PATCH 04/15] pinctrl: sunxi: specify clk name when retrieving pinctrl pio clk Boris BREZILLON 2014-04-09 13:51 ` Boris BREZILLON 2014-04-10 18:14 ` Linus Walleij 2014-04-10 18:14 ` Linus Walleij 2014-04-10 18:14 ` Linus Walleij 2014-04-10 18:16 ` Linus Walleij 2014-04-10 18:16 ` Linus Walleij 2014-04-10 21:17 ` Boris BREZILLON 2014-04-10 21:17 ` Boris BREZILLON 2014-04-09 13:51 ` [PATCH 05/15] clk: sunxi: add A31 APB0 clk gate defintions Boris BREZILLON 2014-04-09 13:51 ` Boris BREZILLON 2014-04-09 13:51 ` Boris BREZILLON 2014-04-09 14:49 ` Maxime Ripard 2014-04-09 14:49 ` Maxime Ripard 2014-04-09 13:51 ` [PATCH 06/15] clk: sunxi: add A31 APB0 gates compatible string to the documentation Boris BREZILLON 2014-04-09 13:51 ` Boris BREZILLON 2014-04-09 13:51 ` Boris BREZILLON 2014-04-09 13:59 ` Chen-Yu Tsai [this message] 2014-04-09 13:59 ` Chen-Yu Tsai 2014-04-09 14:45 ` Boris BREZILLON 2014-04-09 14:45 ` Boris BREZILLON 2014-04-09 14:51 ` Maxime Ripard 2014-04-09 14:51 ` Maxime Ripard 2014-04-09 13:51 ` [PATCH 07/15] ARM: sunxi: dt: define A31's APB0 clk gates node Boris BREZILLON 2014-04-09 13:51 ` Boris BREZILLON 2014-04-09 13:51 ` Boris BREZILLON 2014-04-09 14:06 ` Emilio López 2014-04-09 14:06 ` Emilio López 2014-04-09 14:43 ` Boris BREZILLON 2014-04-09 14:43 ` Boris BREZILLON 2014-04-09 15:08 ` Maxime Ripard 2014-04-09 15:08 ` Maxime Ripard 2014-04-09 13:51 ` [PATCH 08/15] reset: sunxi: document sunxi's reset controllers bindings Boris BREZILLON 2014-04-09 13:51 ` Boris BREZILLON 2014-04-09 13:51 ` [PATCH 09/15] clk: sunxi: add A31 APB0 reset line defintions Boris BREZILLON 2014-04-09 13:51 ` Boris BREZILLON 2014-04-09 13:51 ` Boris BREZILLON 2014-04-09 13:51 ` [PATCH 10/15] pinctrl: sunxi: add PL pin definitions Boris BREZILLON 2014-04-09 13:51 ` Boris BREZILLON 2014-04-09 13:51 ` [PATCH 11/15] pinctrl: sunxi: add support for A31 PL pins Boris BREZILLON 2014-04-09 13:51 ` Boris BREZILLON 2014-04-09 13:51 ` [PATCH 12/15] pinctrl: sunxi: retrieve and enable PL clk gate for A31 SoC Boris BREZILLON 2014-04-09 13:51 ` Boris BREZILLON 2014-04-09 15:33 ` Maxime Ripard 2014-04-09 15:33 ` Maxime Ripard 2014-04-09 13:51 ` [PATCH 13/15] pinctrl: sunxi: retrieve and enable PL reset line " Boris BREZILLON 2014-04-09 13:51 ` Boris BREZILLON 2014-04-09 13:51 ` Boris BREZILLON 2014-04-09 15:34 ` Maxime Ripard 2014-04-09 15:34 ` Maxime Ripard 2014-04-09 15:34 ` Maxime Ripard 2014-04-09 13:51 ` [PATCH 14/15] pinctrl: sunxi: define A31 PL0/PL1 pins Boris BREZILLON 2014-04-09 13:51 ` Boris BREZILLON 2014-04-09 13:51 ` Boris BREZILLON 2014-04-09 15:38 ` Maxime Ripard 2014-04-09 15:38 ` Maxime Ripard 2014-04-09 13:51 ` [PATCH 15/15] ARM: sunxi: dt: add support for A31's PL pins Boris BREZILLON 2014-04-09 13:51 ` Boris BREZILLON 2014-04-09 14:53 ` [PATCH 00/15] ARM: sunxi: add A31 PL pins support Chen-Yu Tsai 2014-04-09 14:53 ` Chen-Yu Tsai 2014-04-09 15:17 ` Maxime Ripard 2014-04-09 15:17 ` Maxime Ripard 2014-04-09 15:45 ` Maxime Ripard 2014-04-09 15:45 ` Maxime Ripard 2014-04-09 16:27 ` Chen-Yu Tsai 2014-04-09 16:27 ` Chen-Yu Tsai 2014-04-10 8:10 ` Maxime Ripard 2014-04-10 8:10 ` Maxime Ripard 2014-04-10 9:56 ` Chen-Yu Tsai 2014-04-10 9:56 ` Chen-Yu Tsai 2014-04-09 16:14 ` Boris BREZILLON 2014-04-09 16:14 ` Boris BREZILLON 2014-04-09 17:14 ` Chen-Yu Tsai 2014-04-09 17:14 ` Chen-Yu Tsai 2014-04-09 18:04 ` Boris BREZILLON 2014-04-09 18:04 ` Boris BREZILLON 2014-04-10 8:16 ` Maxime Ripard 2014-04-10 8:16 ` Maxime Ripard
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