[PATCH v2 0/8] arm: sunxi: rename DT clock node names to clk@N

[PATCH v2 0/8] arm: sunxi: rename DT clock node names to clk@N

[Chen-Yu Tsai]

This is v2 of the clock node renaming patch series, which renames
the clock nodes in sunxi dts to conform to device tree naming
conventions, i.e. clk at N. Dummy clocks that will be renamed/removed
later, or clocks sharing registers are not renamed.

Renamed clock nodes have clock-output-names properties added to
desginate their names. Support for this is added in the first
patch.

The last patch, which enables i2c controllers on Cubietruck, is
not related to the clocks. Just submitting them together.

Changes since v1:

  * Fixed pll5, pll6 divs clock name handling 

Cheers
ChenYu


Chen-Yu Tsai (8):
  clk: sunxi: add clock-output-names dt property support
  clk: sunxi: choose correct name for multiple output factor clocks
  clk: sunxi: get divs parent clock name from parent factor clock
  arm: dts: sun4i: rename clock node names to clk at N
  arm: dts: sun5i: rename clock node names to clk at N
  arm: dts: sun6i: rename clock node names to clk at N
  arm: dts: sun7i: rename clock node names to clk at N
  arm: sun7i: cubietruck: Enable the i2c controllers

 arch/arm/boot/dts/sun4i-a10.dtsi           | 26 +++++++++++++++-----------
 arch/arm/boot/dts/sun5i-a10s.dtsi          | 26 +++++++++++++++-----------
 arch/arm/boot/dts/sun5i-a13.dtsi           | 26 +++++++++++++++-----------
 arch/arm/boot/dts/sun6i-a31.dtsi           | 12 +++++++-----
 arch/arm/boot/dts/sun7i-a20-cubietruck.dts | 18 ++++++++++++++++++
 arch/arm/boot/dts/sun7i-a20.dtsi           | 21 ++++++++++++---------
 drivers/clk/sunxi/clk-sunxi.c              | 27 +++++++++++++++++----------
 7 files changed, 99 insertions(+), 57 deletions(-)

-- 
1.8.5.2

[PATCH v2 1/8] clk: sunxi: add clock-output-names dt property support

[Chen-Yu Tsai]

sunxi clock drivers use dt node name as clock name, but clock
nodes should be named clk at X, so the names would be the same.
Let the drivers read clock names from dt clock-output-names
property.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---
 drivers/clk/sunxi/clk-sunxi.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
index 19d9e9e..14a3774 100644
--- a/drivers/clk/sunxi/clk-sunxi.c
+++ b/drivers/clk/sunxi/clk-sunxi.c
@@ -53,6 +53,8 @@ static void __init sun4i_osc_clk_setup(struct device_node *node)
 	if (of_property_read_u32(node, "clock-frequency", &rate))
 		return;
 
+	of_property_read_string(node, "clock-output-names", &clk_name);
+
 	/* set up gate and fixed rate properties */
 	gate->reg = of_iomap(node, 0);
 	gate->bit_idx = SUNXI_OSC24M_GATE;
@@ -595,6 +597,8 @@ static void __init sunxi_mux_clk_setup(struct device_node *node,
 	       (parents[i] = of_clk_get_parent_name(node, i)) != NULL)
 		i++;
 
+	of_property_read_string(node, "clock-output-names", &clk_name);
+
 	clk = clk_register_mux(NULL, clk_name, parents, i,
 			       CLK_SET_RATE_NO_REPARENT, reg,
 			       data->shift, SUNXI_MUX_GATE_WIDTH,
@@ -654,6 +658,8 @@ static void __init sunxi_divider_clk_setup(struct device_node *node,
 
 	clk_parent = of_clk_get_parent_name(node, 0);
 
+	of_property_read_string(node, "clock-output-names", &clk_name);
+
 	clk = clk_register_divider(NULL, clk_name, clk_parent, 0,
 				   reg, data->shift, data->width,
 				   data->pow ? CLK_DIVIDER_POWER_OF_TWO : 0,
-- 
1.8.5.2

[PATCH v2 2/8] clk: sunxi: choose correct name for multiple output factor clocks

[Chen-Yu Tsai]

Some factor clocks, such as the parent clock of pll5 and pll6, have
multiple output names. Use the last name as the name for the clock
itself.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---
 drivers/clk/sunxi/clk-sunxi.c | 18 +++++++++---------
 1 file changed, 9 insertions(+), 9 deletions(-)

diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
index 14a3774..7ce7e1c 100644
--- a/drivers/clk/sunxi/clk-sunxi.c
+++ b/drivers/clk/sunxi/clk-sunxi.c
@@ -484,7 +484,7 @@ static struct clk * __init sunxi_factors_clk_setup(struct device_node *node,
 	const char *clk_name = node->name;
 	const char *parents[SUNXI_MAX_PARENTS];
 	void *reg;
-	int i = 0;
+	int j, i = 0;
 
 	reg = of_iomap(node, 0);
 
@@ -493,14 +493,14 @@ static struct clk * __init sunxi_factors_clk_setup(struct device_node *node,
 	       (parents[i] = of_clk_get_parent_name(node, i)) != NULL)
 		i++;
 
-	/* Nodes should be providing the name via clock-output-names
-	 * but originally our dts didn't, and so we used node->name.
-	 * The new, better nodes look like clk at deadbeef, so we pull the
-	 * name just in this case */
-	if (!strcmp("clk", clk_name)) {
-		of_property_read_string_index(node, "clock-output-names",
-					      0, &clk_name);
-	}
+	/*
+	 * factor clocks, such as pll5 and pll6, may have multiple outputs
+	 * Use the last clock output name as this clock's name.
+	 * This matches the behavior of of_clk_get_parent_name()
+	 */
+	j = of_property_count_strings(node, "clock-output-names");
+	of_property_read_string_index(node, "clock-output-names", j - 1,
+				      &clk_name);
 
 	factors = kzalloc(sizeof(struct clk_factors), GFP_KERNEL);
 	if (!factors)
-- 
1.8.5.2

[PATCH v2 3/8] clk: sunxi: get divs parent clock name from parent factor clock

[Chen-Yu Tsai]

Divs clocks consist of a parent factor clock with multiple outputs,
and seperate clocks for each output. Get the name of the parent
clock from the parent factor clock, instead of the DT node name.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---
 drivers/clk/sunxi/clk-sunxi.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
index 7ce7e1c..6c51828 100644
--- a/drivers/clk/sunxi/clk-sunxi.c
+++ b/drivers/clk/sunxi/clk-sunxi.c
@@ -854,7 +854,7 @@ static void __init sunxi_divs_clk_setup(struct device_node *node,
 					struct divs_data *data)
 {
 	struct clk_onecell_data *clk_data;
-	const char *parent  = node->name;
+	const char *parent;
 	const char *clk_name;
 	struct clk **clks, *pclk;
 	struct clk_hw *gate_hw, *rate_hw;
@@ -868,6 +868,7 @@ static void __init sunxi_divs_clk_setup(struct device_node *node,
 
 	/* Set up factor clock that we will be dividing */
 	pclk = sunxi_factors_clk_setup(node, data->factors);
+	parent = __clk_get_name(pclk);
 
 	reg = of_iomap(node, 0);
 
-- 
1.8.5.2

[PATCH v2 4/8] arm: dts: sun4i: rename clock node names to clk@N

[Chen-Yu Tsai]

Device tree naming conventions state that node names should match
node function. Change fully functioning clock nodes to match.

Also add the output name for pll5 to use as the clock name.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---
 arch/arm/boot/dts/sun4i-a10.dtsi | 26 +++++++++++++++-----------
 1 file changed, 15 insertions(+), 11 deletions(-)

diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi
index 3ba2b46..45d5283 100644
--- a/arch/arm/boot/dts/sun4i-a10.dtsi
+++ b/arch/arm/boot/dts/sun4i-a10.dtsi
@@ -50,42 +50,46 @@
 			clock-frequency = <0>;
 		};
 
-		osc24M: osc24M at 01c20050 {
+		osc24M: clk at 01c20050 {
 			#clock-cells = <0>;
 			compatible = "allwinner,sun4i-osc-clk";
 			reg = <0x01c20050 0x4>;
 			clock-frequency = <24000000>;
+			clock-output-names = "osc24M";
 		};
 
-		osc32k: osc32k {
+		osc32k: clk at 0 {
 			#clock-cells = <0>;
 			compatible = "fixed-clock";
 			clock-frequency = <32768>;
+			clock-output-names = "osc32k";
 		};
 
-		pll1: pll1 at 01c20000 {
+		pll1: clk at 01c20000 {
 			#clock-cells = <0>;
 			compatible = "allwinner,sun4i-pll1-clk";
 			reg = <0x01c20000 0x4>;
 			clocks = <&osc24M>;
+			clock-output-names = "pll1";
 		};
 
-		pll4: pll4 at 01c20018 {
+		pll4: clk at 01c20018 {
 			#clock-cells = <0>;
 			compatible = "allwinner,sun4i-pll1-clk";
 			reg = <0x01c20018 0x4>;
 			clocks = <&osc24M>;
+			clock-output-names = "pll4";
 		};
 
-		pll5: pll5 at 01c20020 {
+		pll5: clk at 01c20020 {
 			#clock-cells = <1>;
 			compatible = "allwinner,sun4i-pll5-clk";
 			reg = <0x01c20020 0x4>;
 			clocks = <&osc24M>;
-			clock-output-names = "pll5_ddr", "pll5_other";
+			clock-output-names = "pll5_ddr", "pll5_other", "pll5";
 		};
 
-		pll6: pll6 at 01c20028 {
+		pll6: clk at 01c20028 {
 			#clock-cells = <1>;
 			compatible = "allwinner,sun4i-pll6-clk";
 			reg = <0x01c20028 0x4>;
@@ -108,7 +112,7 @@
 			clocks = <&cpu>;
 		};
 
-		axi_gates: axi_gates at 01c2005c {
+		axi_gates: clk at 01c2005c {
 			#clock-cells = <1>;
 			compatible = "allwinner,sun4i-axi-gates-clk";
 			reg = <0x01c2005c 0x4>;
@@ -123,7 +127,7 @@
 			clocks = <&axi>;
 		};
 
-		ahb_gates: ahb_gates at 01c20060 {
+		ahb_gates: clk at 01c20060 {
 			#clock-cells = <1>;
 			compatible = "allwinner,sun4i-ahb-gates-clk";
 			reg = <0x01c20060 0x8>;
@@ -148,7 +152,7 @@
 			clocks = <&ahb>;
 		};
 
-		apb0_gates: apb0_gates at 01c20068 {
+		apb0_gates: clk at 01c20068 {
 			#clock-cells = <1>;
 			compatible = "allwinner,sun4i-apb0-gates-clk";
 			reg = <0x01c20068 0x4>;
@@ -172,7 +176,7 @@
 			clocks = <&apb1_mux>;
 		};
 
-		apb1_gates: apb1_gates at 01c2006c {
+		apb1_gates: clk at 01c2006c {
 			#clock-cells = <1>;
 			compatible = "allwinner,sun4i-apb1-gates-clk";
 			reg = <0x01c2006c 0x4>;
-- 
1.8.5.2

[PATCH v2 5/8] arm: dts: sun5i: rename clock node names to clk@N

[Chen-Yu Tsai]

Device tree naming conventions state that node names should match
node function. Change fully functioning clock nodes to match.

Also add the output name for pll5 to use as the clock name.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---
 arch/arm/boot/dts/sun5i-a10s.dtsi | 26 +++++++++++++++-----------
 arch/arm/boot/dts/sun5i-a13.dtsi  | 26 +++++++++++++++-----------
 2 files changed, 30 insertions(+), 22 deletions(-)

diff --git a/arch/arm/boot/dts/sun5i-a10s.dtsi b/arch/arm/boot/dts/sun5i-a10s.dtsi
index 78360b3..b67553b 100644
--- a/arch/arm/boot/dts/sun5i-a10s.dtsi
+++ b/arch/arm/boot/dts/sun5i-a10s.dtsi
@@ -47,42 +47,46 @@
 			clock-frequency = <0>;
 		};
 
-		osc24M: osc24M at 01c20050 {
+		osc24M: clk at 01c20050 {
 			#clock-cells = <0>;
 			compatible = "allwinner,sun4i-osc-clk";
 			reg = <0x01c20050 0x4>;
 			clock-frequency = <24000000>;
+			clock-output-names = "osc24M";
 		};
 
-		osc32k: osc32k {
+		osc32k: clk at 0 {
 			#clock-cells = <0>;
 			compatible = "fixed-clock";
 			clock-frequency = <32768>;
+			clock-output-names = "osc32k";
 		};
 
-		pll1: pll1 at 01c20000 {
+		pll1: clk at 01c20000 {
 			#clock-cells = <0>;
 			compatible = "allwinner,sun4i-pll1-clk";
 			reg = <0x01c20000 0x4>;
 			clocks = <&osc24M>;
+			clock-output-names = "pll1";
 		};
 
-		pll4: pll4 at 01c20018 {
+		pll4: clk at 01c20018 {
 			#clock-cells = <0>;
 			compatible = "allwinner,sun4i-pll1-clk";
 			reg = <0x01c20018 0x4>;
 			clocks = <&osc24M>;
+			clock-output-names = "pll4";
 		};
 
-		pll5: pll5 at 01c20020 {
+		pll5: clk at 01c20020 {
 			#clock-cells = <1>;
 			compatible = "allwinner,sun4i-pll5-clk";
 			reg = <0x01c20020 0x4>;
 			clocks = <&osc24M>;
-			clock-output-names = "pll5_ddr", "pll5_other";
+			clock-output-names = "pll5_ddr", "pll5_other", "pll5";
 		};
 
-		pll6: pll6 at 01c20028 {
+		pll6: clk at 01c20028 {
 			#clock-cells = <1>;
 			compatible = "allwinner,sun4i-pll6-clk";
 			reg = <0x01c20028 0x4>;
@@ -105,7 +109,7 @@
 			clocks = <&cpu>;
 		};
 
-		axi_gates: axi_gates at 01c2005c {
+		axi_gates: clk at 01c2005c {
 			#clock-cells = <1>;
 			compatible = "allwinner,sun4i-axi-gates-clk";
 			reg = <0x01c2005c 0x4>;
@@ -120,7 +124,7 @@
 			clocks = <&axi>;
 		};
 
-		ahb_gates: ahb_gates at 01c20060 {
+		ahb_gates: clk at 01c20060 {
 			#clock-cells = <1>;
 			compatible = "allwinner,sun5i-a10s-ahb-gates-clk";
 			reg = <0x01c20060 0x8>;
@@ -141,7 +145,7 @@
 			clocks = <&ahb>;
 		};
 
-		apb0_gates: apb0_gates at 01c20068 {
+		apb0_gates: clk at 01c20068 {
 			#clock-cells = <1>;
 			compatible = "allwinner,sun5i-a10s-apb0-gates-clk";
 			reg = <0x01c20068 0x4>;
@@ -164,7 +168,7 @@
 			clocks = <&apb1_mux>;
 		};
 
-		apb1_gates: apb1_gates at 01c2006c {
+		apb1_gates: clk at 01c2006c {
 			#clock-cells = <1>;
 			compatible = "allwinner,sun5i-a10s-apb1-gates-clk";
 			reg = <0x01c2006c 0x4>;
diff --git a/arch/arm/boot/dts/sun5i-a13.dtsi b/arch/arm/boot/dts/sun5i-a13.dtsi
index 2f37ca5..76d6f7a 100644
--- a/arch/arm/boot/dts/sun5i-a13.dtsi
+++ b/arch/arm/boot/dts/sun5i-a13.dtsi
@@ -47,42 +47,46 @@
 			clock-frequency = <0>;
 		};
 
-		osc24M: osc24M at 01c20050 {
+		osc24M: clk at 01c20050 {
 			#clock-cells = <0>;
 			compatible = "allwinner,sun4i-osc-clk";
 			reg = <0x01c20050 0x4>;
 			clock-frequency = <24000000>;
+			clock-output-names = "osc24M";
 		};
 
-		osc32k: osc32k {
+		osc32k: clk at 0 {
 			#clock-cells = <0>;
 			compatible = "fixed-clock";
 			clock-frequency = <32768>;
+			clock-output-names = "osc32k";
 		};
 
-		pll1: pll1 at 01c20000 {
+		pll1: clk at 01c20000 {
 			#clock-cells = <0>;
 			compatible = "allwinner,sun4i-pll1-clk";
 			reg = <0x01c20000 0x4>;
 			clocks = <&osc24M>;
+			clock-output-names = "pll1";
 		};
 
-		pll4: pll4 at 01c20018 {
+		pll4: clk at 01c20018 {
 			#clock-cells = <0>;
 			compatible = "allwinner,sun4i-pll1-clk";
 			reg = <0x01c20018 0x4>;
 			clocks = <&osc24M>;
+			clock-output-names = "pll4";
 		};
 
-		pll5: pll5 at 01c20020 {
+		pll5: clk at 01c20020 {
 			#clock-cells = <1>;
 			compatible = "allwinner,sun4i-pll5-clk";
 			reg = <0x01c20020 0x4>;
 			clocks = <&osc24M>;
-			clock-output-names = "pll5_ddr", "pll5_other";
+			clock-output-names = "pll5_ddr", "pll5_other", "pll5";
 		};
 
-		pll6: pll6 at 01c20028 {
+		pll6: clk at 01c20028 {
 			#clock-cells = <1>;
 			compatible = "allwinner,sun4i-pll6-clk";
 			reg = <0x01c20028 0x4>;
@@ -105,7 +109,7 @@
 			clocks = <&cpu>;
 		};
 
-		axi_gates: axi_gates at 01c2005c {
+		axi_gates: clk at 01c2005c {
 			#clock-cells = <1>;
 			compatible = "allwinner,sun4i-axi-gates-clk";
 			reg = <0x01c2005c 0x4>;
@@ -120,7 +124,7 @@
 			clocks = <&axi>;
 		};
 
-		ahb_gates: ahb_gates at 01c20060 {
+		ahb_gates: clk at 01c20060 {
 			#clock-cells = <1>;
 			compatible = "allwinner,sun5i-a13-ahb-gates-clk";
 			reg = <0x01c20060 0x8>;
@@ -140,7 +144,7 @@
 			clocks = <&ahb>;
 		};
 
-		apb0_gates: apb0_gates at 01c20068 {
+		apb0_gates: clk at 01c20068 {
 			#clock-cells = <1>;
 			compatible = "allwinner,sun5i-a13-apb0-gates-clk";
 			reg = <0x01c20068 0x4>;
@@ -162,7 +166,7 @@
 			clocks = <&apb1_mux>;
 		};
 
-		apb1_gates: apb1_gates at 01c2006c {
+		apb1_gates: clk at 01c2006c {
 			#clock-cells = <1>;
 			compatible = "allwinner,sun5i-a13-apb1-gates-clk";
 			reg = <0x01c2006c 0x4>;
-- 
1.8.5.2

[PATCH v2 6/8] arm: dts: sun6i: rename clock node names to clk@N

[Chen-Yu Tsai]

Device tree naming conventions state that node names should match
node function. Change fully functioning clock nodes to match.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---
 arch/arm/boot/dts/sun6i-a31.dtsi | 12 +++++++-----
 1 file changed, 7 insertions(+), 5 deletions(-)

diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi
index 5256ad9..a1f5193 100644
--- a/arch/arm/boot/dts/sun6i-a31.dtsi
+++ b/arch/arm/boot/dts/sun6i-a31.dtsi
@@ -60,17 +60,19 @@
 			clock-frequency = <24000000>;
 		};
 
-		osc32k: osc32k {
+		osc32k: clk at 0 {
 			#clock-cells = <0>;
 			compatible = "fixed-clock";
 			clock-frequency = <32768>;
+			clock-output-names = "osc32k";
 		};
 
-		pll1: pll1 at 01c20000 {
+		pll1: clk at 01c20000 {
 			#clock-cells = <0>;
 			compatible = "allwinner,sun6i-a31-pll1-clk";
 			reg = <0x01c20000 0x4>;
 			clocks = <&osc24M>;
+			clock-output-names = "pll1";
 		};
 
 		/*
@@ -120,7 +122,7 @@
 			clocks = <&ahb1_mux>;
 		};
 
-		ahb1_gates: ahb1_gates at 01c20060 {
+		ahb1_gates: clk at 01c20060 {
 			#clock-cells = <1>;
 			compatible = "allwinner,sun6i-a31-ahb1-gates-clk";
 			reg = <0x01c20060 0x8>;
@@ -148,7 +150,7 @@
 			clocks = <&ahb1>;
 		};
 
-		apb1_gates: apb1_gates at 01c20060 {
+		apb1_gates: clk at 01c20068 {
 			#clock-cells = <1>;
 			compatible = "allwinner,sun6i-a31-apb1-gates-clk";
 			reg = <0x01c20068 0x4>;
@@ -172,7 +174,7 @@
 			clocks = <&apb2_mux>;
 		};
 
-		apb2_gates: apb2_gates at 01c2006c {
+		apb2_gates: clk at 01c2006c {
 			#clock-cells = <1>;
 			compatible = "allwinner,sun6i-a31-apb2-gates-clk";
 			reg = <0x01c2006c 0x4>;
-- 
1.8.5.2

[PATCH v2 7/8] arm: dts: sun7i: rename clock node names to clk@N

[Chen-Yu Tsai]

Device tree naming conventions state that node names should match
node function. Change fully functioning clock nodes to match.

Also add the output name for pll5 to use as the clock name.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---
 arch/arm/boot/dts/sun7i-a20.dtsi | 21 ++++++++++++---------
 1 file changed, 12 insertions(+), 9 deletions(-)

diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
index 0062811..3808f1b 100644
--- a/arch/arm/boot/dts/sun7i-a20.dtsi
+++ b/arch/arm/boot/dts/sun7i-a20.dtsi
@@ -46,11 +46,12 @@
 		#size-cells = <1>;
 		ranges;
 
-		osc24M: osc24M at 01c20050 {
+		osc24M: clk at 01c20050 {
 			#clock-cells = <0>;
 			compatible = "allwinner,sun4i-osc-clk";
 			reg = <0x01c20050 0x4>;
 			clock-frequency = <24000000>;
+			clock-output-names = "osc24M";
 		};
 
 		osc32k: clk at 0 {
@@ -60,29 +61,31 @@
 			clock-output-names = "osc32k";
 		};
 
-		pll1: pll1 at 01c20000 {
+		pll1: clk at 01c20000 {
 			#clock-cells = <0>;
 			compatible = "allwinner,sun4i-pll1-clk";
 			reg = <0x01c20000 0x4>;
 			clocks = <&osc24M>;
+			clock-output-names = "pll1";
 		};
 
-		pll4: pll4 at 01c20018 {
+		pll4: clk at 01c20018 {
 			#clock-cells = <0>;
 			compatible = "allwinner,sun4i-pll1-clk";
 			reg = <0x01c20018 0x4>;
 			clocks = <&osc24M>;
+			clock-output-names = "pll4";
 		};
 
-		pll5: pll5 at 01c20020 {
+		pll5: clk at 01c20020 {
 			#clock-cells = <1>;
 			compatible = "allwinner,sun4i-pll5-clk";
 			reg = <0x01c20020 0x4>;
 			clocks = <&osc24M>;
-			clock-output-names = "pll5_ddr", "pll5_other";
+			clock-output-names = "pll5_ddr", "pll5_other", "pll5";
 		};
 
-		pll6: pll6 at 01c20028 {
+		pll6: clk at 01c20028 {
 			#clock-cells = <1>;
 			compatible = "allwinner,sun4i-pll6-clk";
 			reg = <0x01c20028 0x4>;
@@ -111,7 +114,7 @@
 			clocks = <&axi>;
 		};
 
-		ahb_gates: ahb_gates at 01c20060 {
+		ahb_gates: clk at 01c20060 {
 			#clock-cells = <1>;
 			compatible = "allwinner,sun7i-a20-ahb-gates-clk";
 			reg = <0x01c20060 0x8>;
@@ -138,7 +141,7 @@
 			clocks = <&ahb>;
 		};
 
-		apb0_gates: apb0_gates at 01c20068 {
+		apb0_gates: clk at 01c20068 {
 			#clock-cells = <1>;
 			compatible = "allwinner,sun7i-a20-apb0-gates-clk";
 			reg = <0x01c20068 0x4>;
@@ -163,7 +166,7 @@
 			clocks = <&apb1_mux>;
 		};
 
-		apb1_gates: apb1_gates at 01c2006c {
+		apb1_gates: clk at 01c2006c {
 			#clock-cells = <1>;
 			compatible = "allwinner,sun7i-a20-apb1-gates-clk";
 			reg = <0x01c2006c 0x4>;
-- 
1.8.5.2

[PATCH v2 8/8] arm: sun7i: cubietruck: Enable the i2c controllers

[Chen-Yu Tsai]

The Cubietruck makes use of the first three i2c controllers found on the
Allwinner A20; i2c-0 is used internally for the PMIC, i2c-1 is exposed on
the board headers, and i2c-2 is used for DDC on the VGA connector. This
patch enables them in the device tree.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---
 arch/arm/boot/dts/sun7i-a20-cubietruck.dts | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)

diff --git a/arch/arm/boot/dts/sun7i-a20-cubietruck.dts b/arch/arm/boot/dts/sun7i-a20-cubietruck.dts
index 8a1009d..f9dcb61 100644
--- a/arch/arm/boot/dts/sun7i-a20-cubietruck.dts
+++ b/arch/arm/boot/dts/sun7i-a20-cubietruck.dts
@@ -33,6 +33,24 @@
 			pinctrl-0 = <&uart0_pins_a>;
 			status = "okay";
 		};
+
+		i2c0: i2c at 01c2ac00 {
+			pinctrl-names = "default";
+			pinctrl-0 = <&i2c0_pins_a>;
+			status = "okay";
+		};
+
+		i2c1: i2c at 01c2b000 {
+			pinctrl-names = "default";
+			pinctrl-0 = <&i2c1_pins_a>;
+			status = "okay";
+		};
+
+		i2c2: i2c at 01c2b400 {
+			pinctrl-names = "default";
+			pinctrl-0 = <&i2c2_pins_a>;
+			status = "okay";
+		};
 	};
 
 	leds {
-- 
1.8.5.2

[PATCH v2 1/8] clk: sunxi: add clock-output-names dt property support

[Maxime Ripard]

Hi Chen-Yu,

On Mon, Jan 06, 2014 at 01:58:05PM +0800, Chen-Yu Tsai wrote:
> sunxi clock drivers use dt node name as clock name, but clock
> nodes should be named clk at X, so the names would be the same.
> Let the drivers read clock names from dt clock-output-names
> property.
> 
> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
> ---
>  drivers/clk/sunxi/clk-sunxi.c | 6 ++++++
>  1 file changed, 6 insertions(+)
> 
> diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
> index 19d9e9e..14a3774 100644
> --- a/drivers/clk/sunxi/clk-sunxi.c
> +++ b/drivers/clk/sunxi/clk-sunxi.c
> @@ -53,6 +53,8 @@ static void __init sun4i_osc_clk_setup(struct device_node *node)
>  	if (of_property_read_u32(node, "clock-frequency", &rate))
>  		return;
>  
> +	of_property_read_string(node, "clock-output-names", &clk_name);
> +
>  	/* set up gate and fixed rate properties */
>  	gate->reg = of_iomap(node, 0);
>  	gate->bit_idx = SUNXI_OSC24M_GATE;
> @@ -595,6 +597,8 @@ static void __init sunxi_mux_clk_setup(struct device_node *node,
>  	       (parents[i] = of_clk_get_parent_name(node, i)) != NULL)
>  		i++;
>  
> +	of_property_read_string(node, "clock-output-names", &clk_name);
> +
>  	clk = clk_register_mux(NULL, clk_name, parents, i,
>  			       CLK_SET_RATE_NO_REPARENT, reg,
>  			       data->shift, SUNXI_MUX_GATE_WIDTH,
> @@ -654,6 +658,8 @@ static void __init sunxi_divider_clk_setup(struct device_node *node,
>  
>  	clk_parent = of_clk_get_parent_name(node, 0);
>  
> +	of_property_read_string(node, "clock-output-names", &clk_name);
> +
>  	clk = clk_register_divider(NULL, clk_name, clk_parent, 0,
>  				   reg, data->shift, data->width,
>  				   data->pow ? CLK_DIVIDER_POWER_OF_TWO : 0,
> -- 
> 1.8.5.2
> 

Please document this in Documentation/devicetree/bindings.

Thanks!
Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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[PATCH v2 2/8] clk: sunxi: choose correct name for multiple output factor clocks

[Maxime Ripard]

On Mon, Jan 06, 2014 at 01:58:06PM +0800, Chen-Yu Tsai wrote:
> Some factor clocks, such as the parent clock of pll5 and pll6, have
> multiple output names. Use the last name as the name for the clock
> itself.
> 
> Signed-off-by: Chen-Yu Tsai <wens@csie.org>

Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>

Mike, Emilio,

This changes the clock names with regard to the previous patches
emilio sent that will be merged in 3.14. It would be great if we could
merge this in 3.14 as well.

Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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[PATCH v2 3/8] clk: sunxi: get divs parent clock name from parent factor clock

[Maxime Ripard]

On Mon, Jan 06, 2014 at 01:58:07PM +0800, Chen-Yu Tsai wrote:
> Divs clocks consist of a parent factor clock with multiple outputs,
> and seperate clocks for each output. Get the name of the parent
> clock from the parent factor clock, instead of the DT node name.
> 
> Signed-off-by: Chen-Yu Tsai <wens@csie.org>

Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>

Thanks!
Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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[PATCH v2 4/8] arm: dts: sun4i: rename clock node names to clk@N

[Maxime Ripard]

On Mon, Jan 06, 2014 at 01:58:08PM +0800, Chen-Yu Tsai wrote:
> Device tree naming conventions state that node names should match
> node function. Change fully functioning clock nodes to match.
> 
> Also add the output name for pll5 to use as the clock name.
> 
> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
> ---
>  arch/arm/boot/dts/sun4i-a10.dtsi | 26 +++++++++++++++-----------
>  1 file changed, 15 insertions(+), 11 deletions(-)
> 
> diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi
> index 3ba2b46..45d5283 100644
> --- a/arch/arm/boot/dts/sun4i-a10.dtsi
> +++ b/arch/arm/boot/dts/sun4i-a10.dtsi
> @@ -50,42 +50,46 @@
>  			clock-frequency = <0>;
>  		};
>  
> -		osc24M: osc24M at 01c20050 {
> +		osc24M: clk at 01c20050 {
>  			#clock-cells = <0>;
>  			compatible = "allwinner,sun4i-osc-clk";
>  			reg = <0x01c20050 0x4>;
>  			clock-frequency = <24000000>;
> +			clock-output-names = "osc24M";
>  		};
>  
> -		osc32k: osc32k {
> +		osc32k: clk at 0 {
>  			#clock-cells = <0>;
>  			compatible = "fixed-clock";
>  			clock-frequency = <32768>;
> +			clock-output-names = "osc32k";
>  		};
>  
> -		pll1: pll1 at 01c20000 {
> +		pll1: clk at 01c20000 {
>  			#clock-cells = <0>;
>  			compatible = "allwinner,sun4i-pll1-clk";
>  			reg = <0x01c20000 0x4>;
>  			clocks = <&osc24M>;
> +			clock-output-names = "pll1";
>  		};
>  
> -		pll4: pll4 at 01c20018 {
> +		pll4: clk at 01c20018 {
>  			#clock-cells = <0>;
>  			compatible = "allwinner,sun4i-pll1-clk";
>  			reg = <0x01c20018 0x4>;
>  			clocks = <&osc24M>;
> +			clock-output-names = "pll4";
>  		};
>  
> -		pll5: pll5 at 01c20020 {
> +		pll5: clk at 01c20020 {
>  			#clock-cells = <1>;
>  			compatible = "allwinner,sun4i-pll5-clk";
>  			reg = <0x01c20020 0x4>;
>  			clocks = <&osc24M>;
> -			clock-output-names = "pll5_ddr", "pll5_other";
> +			clock-output-names = "pll5_ddr", "pll5_other", "pll5";

Hmmm, I don't really like that bit too much.

This "pll5" clock doesn't actually exist at the hardware point of
view, which is not really what the DT is used for.

I can think of two ways to do what you want withouth this: 
  - either hardcode the name, since we have a compatible of our own here
  - or use strchr to take anyhing until '_' and use that as a name


-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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[PATCH v2 8/8] arm: sun7i: cubietruck: Enable the i2c controllers

[Maxime Ripard]

Hi,

On Mon, Jan 06, 2014 at 01:58:12PM +0800, Chen-Yu Tsai wrote:
> The Cubietruck makes use of the first three i2c controllers found on the
> Allwinner A20; i2c-0 is used internally for the PMIC, i2c-1 is exposed on
> the board headers, and i2c-2 is used for DDC on the VGA connector. This
> patch enables them in the device tree.
> 
> Signed-off-by: Chen-Yu Tsai <wens@csie.org>

It's not really related to the rest of the patches, so I would have
prefered it being send as a separate patch.

Anyway, it's merged now :)

Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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[PATCH v2 2/8] clk: sunxi: choose correct name for multiple output factor clocks

[Maxime Ripard]

On Tue, Jan 07, 2014 at 11:16:46PM +0100, Maxime Ripard wrote:
> On Mon, Jan 06, 2014 at 01:58:06PM +0800, Chen-Yu Tsai wrote:
> > Some factor clocks, such as the parent clock of pll5 and pll6, have
> > multiple output names. Use the last name as the name for the clock
> > itself.
> > 
> > Signed-off-by: Chen-Yu Tsai <wens@csie.org>
> 
> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
> 
> Mike, Emilio,
> 
> This changes the clock names with regard to the previous patches
> emilio sent that will be merged in 3.14. It would be great if we could
> merge this in 3.14 as well.

I've spoken a bit too fast on this, and I'm not really fond of the
patch 7 i've commented on, that depends on what is done in this patch.

We'll see what the outcome of the discussion is.

Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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[PATCH v2 4/8] arm: dts: sun4i: rename clock node names to clk@N

[Chen-Yu Tsai]

On Wed, Jan 8, 2014 at 6:38 AM, Maxime Ripard
<maxime.ripard@free-electrons.com> wrote:
> On Mon, Jan 06, 2014 at 01:58:08PM +0800, Chen-Yu Tsai wrote:
>> Device tree naming conventions state that node names should match
>> node function. Change fully functioning clock nodes to match.
>>
>> Also add the output name for pll5 to use as the clock name.
>>
>> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
>> ---
>>  arch/arm/boot/dts/sun4i-a10.dtsi | 26 +++++++++++++++-----------
>>  1 file changed, 15 insertions(+), 11 deletions(-)
>>
>> diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi
>> index 3ba2b46..45d5283 100644
>> --- a/arch/arm/boot/dts/sun4i-a10.dtsi
>> +++ b/arch/arm/boot/dts/sun4i-a10.dtsi
>> @@ -50,42 +50,46 @@
>>                       clock-frequency = <0>;
>>               };
>>
>> -             osc24M: osc24M at 01c20050 {
>> +             osc24M: clk at 01c20050 {
>>                       #clock-cells = <0>;
>>                       compatible = "allwinner,sun4i-osc-clk";
>>                       reg = <0x01c20050 0x4>;
>>                       clock-frequency = <24000000>;
>> +                     clock-output-names = "osc24M";
>>               };
>>
>> -             osc32k: osc32k {
>> +             osc32k: clk at 0 {
>>                       #clock-cells = <0>;
>>                       compatible = "fixed-clock";
>>                       clock-frequency = <32768>;
>> +                     clock-output-names = "osc32k";
>>               };
>>
>> -             pll1: pll1 at 01c20000 {
>> +             pll1: clk at 01c20000 {
>>                       #clock-cells = <0>;
>>                       compatible = "allwinner,sun4i-pll1-clk";
>>                       reg = <0x01c20000 0x4>;
>>                       clocks = <&osc24M>;
>> +                     clock-output-names = "pll1";
>>               };
>>
>> -             pll4: pll4 at 01c20018 {
>> +             pll4: clk at 01c20018 {
>>                       #clock-cells = <0>;
>>                       compatible = "allwinner,sun4i-pll1-clk";
>>                       reg = <0x01c20018 0x4>;
>>                       clocks = <&osc24M>;
>> +                     clock-output-names = "pll4";
>>               };
>>
>> -             pll5: pll5 at 01c20020 {
>> +             pll5: clk at 01c20020 {
>>                       #clock-cells = <1>;
>>                       compatible = "allwinner,sun4i-pll5-clk";
>>                       reg = <0x01c20020 0x4>;
>>                       clocks = <&osc24M>;
>> -                     clock-output-names = "pll5_ddr", "pll5_other";
>> +                     clock-output-names = "pll5_ddr", "pll5_other", "pll5";
>
> Hmmm, I don't really like that bit too much.
>
> This "pll5" clock doesn't actually exist at the hardware point of
> view, which is not really what the DT is used for.

You are right. pll5 only has 2 outputs. I was matching the format of
pll6, which I'd like to include in this discussion.

Does pll6 actually have 3 outputs? or are we just using the third
output as a shortcut for mbus input of pll6*2 ?

> I can think of two ways to do what you want withouth this:
>   - either hardcode the name, since we have a compatible of our own here

Since we have seperate compatibles for pll5 and pll6, I would prefer
to add a .name to clk_factors_config, instead of adding it in the code.
Emilio, is that okay with you?

>   - or use strchr to take anyhing until '_' and use that as a name

Thanks
ChenYu

[linux-sunxi] Re: [PATCH v2 1/8] clk: sunxi: add clock-output-names dt property support

[Chen-Yu Tsai]

Hi,

On Wed, Jan 8, 2014 at 6:14 AM, Maxime Ripard
<maxime.ripard@free-electrons.com> wrote:
> Hi Chen-Yu,
>
> On Mon, Jan 06, 2014 at 01:58:05PM +0800, Chen-Yu Tsai wrote:
>> sunxi clock drivers use dt node name as clock name, but clock
>> nodes should be named clk at X, so the names would be the same.
>> Let the drivers read clock names from dt clock-output-names
>> property.
>>
>> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
>
> Please document this in Documentation/devicetree/bindings.
>

Do you want them in the same patch, or separate?

I think someone asked about this yesterday, but don't remember
the conclusion.


Thanks
ChenYu

[PATCH v2 4/8] arm: dts: sun4i: rename clock node names to clk@N

[Maxime Ripard]

On Wed, Jan 08, 2014 at 09:38:52AM +0800, Chen-Yu Tsai wrote:
> On Wed, Jan 8, 2014 at 6:38 AM, Maxime Ripard
> <maxime.ripard@free-electrons.com> wrote:
> > On Mon, Jan 06, 2014 at 01:58:08PM +0800, Chen-Yu Tsai wrote:
> >> Device tree naming conventions state that node names should match
> >> node function. Change fully functioning clock nodes to match.
> >>
> >> Also add the output name for pll5 to use as the clock name.
> >>
> >> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
> >> ---
> >>  arch/arm/boot/dts/sun4i-a10.dtsi | 26 +++++++++++++++-----------
> >>  1 file changed, 15 insertions(+), 11 deletions(-)
> >>
> >> diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi
> >> index 3ba2b46..45d5283 100644
> >> --- a/arch/arm/boot/dts/sun4i-a10.dtsi
> >> +++ b/arch/arm/boot/dts/sun4i-a10.dtsi
> >> @@ -50,42 +50,46 @@
> >>                       clock-frequency = <0>;
> >>               };
> >>
> >> -             osc24M: osc24M at 01c20050 {
> >> +             osc24M: clk at 01c20050 {
> >>                       #clock-cells = <0>;
> >>                       compatible = "allwinner,sun4i-osc-clk";
> >>                       reg = <0x01c20050 0x4>;
> >>                       clock-frequency = <24000000>;
> >> +                     clock-output-names = "osc24M";
> >>               };
> >>
> >> -             osc32k: osc32k {
> >> +             osc32k: clk at 0 {
> >>                       #clock-cells = <0>;
> >>                       compatible = "fixed-clock";
> >>                       clock-frequency = <32768>;
> >> +                     clock-output-names = "osc32k";
> >>               };
> >>
> >> -             pll1: pll1 at 01c20000 {
> >> +             pll1: clk at 01c20000 {
> >>                       #clock-cells = <0>;
> >>                       compatible = "allwinner,sun4i-pll1-clk";
> >>                       reg = <0x01c20000 0x4>;
> >>                       clocks = <&osc24M>;
> >> +                     clock-output-names = "pll1";
> >>               };
> >>
> >> -             pll4: pll4 at 01c20018 {
> >> +             pll4: clk at 01c20018 {
> >>                       #clock-cells = <0>;
> >>                       compatible = "allwinner,sun4i-pll1-clk";
> >>                       reg = <0x01c20018 0x4>;
> >>                       clocks = <&osc24M>;
> >> +                     clock-output-names = "pll4";
> >>               };
> >>
> >> -             pll5: pll5 at 01c20020 {
> >> +             pll5: clk at 01c20020 {
> >>                       #clock-cells = <1>;
> >>                       compatible = "allwinner,sun4i-pll5-clk";
> >>                       reg = <0x01c20020 0x4>;
> >>                       clocks = <&osc24M>;
> >> -                     clock-output-names = "pll5_ddr", "pll5_other";
> >> +                     clock-output-names = "pll5_ddr", "pll5_other", "pll5";
> >
> > Hmmm, I don't really like that bit too much.
> >
> > This "pll5" clock doesn't actually exist at the hardware point of
> > view, which is not really what the DT is used for.
> 
> You are right. pll5 only has 2 outputs. I was matching the format of
> pll6, which I'd like to include in this discussion.
> 
> Does pll6 actually have 3 outputs? or are we just using the third
> output as a shortcut for mbus input of pll6*2 ?

Hmmm, indeed. I don't really get why pll6 has a third output
either. Emilio?

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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[PATCH v2 4/8] arm: dts: sun4i: rename clock node names to clk@N

[Emilio López]

Hi,

2014/1/9 Maxime Ripard <maxime.ripard@free-electrons.com>:
>> You are right. pll5 only has 2 outputs. I was matching the format of
>> pll6, which I'd like to include in this discussion.
>>
>> Does pll6 actually have 3 outputs? or are we just using the third
>> output as a shortcut for mbus input of pll6*2 ?
>
> Hmmm, indeed. I don't really get why pll6 has a third output
> either. Emilio?

Citing the A20 user manual (my comments on the right)

-----8<------
For SATA, the output =(24MHz*N*K)/M/6 <-- we call this pll6_sata
If the SATA is on, the clock output should be equal to 100MHz;
For other module, the clock output = (24MHz*N*K)/2 <-- we call this pll6_other
PLL6*2 = 24MHz*N*K <-- this would be the third output, which we call pll6
-----8<------

This last output is used by things like mbus and LCD

Now, pll5 says

-----8<------
The PLL5 output for DDR = (24MHz*N*K)/M. <-- we call this pll5_ddr
The PLL5 output for other module =(24MHz*N*K)/P. <-- we call this pll5_other
-----8<------

There does not seem to be anything connected to "pll5" with a rate of
24MHz*N*K, but personally I would not be opposed to adding it to the
DT for consistency with pll6. After all, it actually is the common
ancestor of pll5_ddr and pll5_other.

There's also some ASCII art on the code to visualize these clocks better

http://git.linaro.org/people/mike.turquette/linux.git/blob/refs/heads/clk-next:/drivers/clk/sunxi/clk-sunxi.c#l842

I hope this clarifies things.

Cheers,

Emilio

[linux-sunxi] Re: [PATCH v2 4/8] arm: dts: sun4i: rename clock node names to clk@N

[Chen-Yu Tsai]

Hi,

On Thu, Jan 9, 2014 at 11:47 PM, Emilio L?pez <emilio@elopez.com.ar> wrote:
> Hi,
>
> 2014/1/9 Maxime Ripard <maxime.ripard@free-electrons.com>:
>>> You are right. pll5 only has 2 outputs. I was matching the format of
>>> pll6, which I'd like to include in this discussion.
>>>
>>> Does pll6 actually have 3 outputs? or are we just using the third
>>> output as a shortcut for mbus input of pll6*2 ?
>>
>> Hmmm, indeed. I don't really get why pll6 has a third output
>> either. Emilio?
>
> Citing the A20 user manual (my comments on the right)
>
> -----8<------
> For SATA, the output =(24MHz*N*K)/M/6 <-- we call this pll6_sata
> If the SATA is on, the clock output should be equal to 100MHz;
> For other module, the clock output = (24MHz*N*K)/2 <-- we call this pll6_other
> PLL6*2 = 24MHz*N*K <-- this would be the third output, which we call pll6
> -----8<------
>
> This last output is used by things like mbus and LCD

A wild guess, maybe those modules have a frequency doubler after the
PLL6 input?  Though pll6 direct output seems more reasonable.

Do we want to match the hardware exactly? If so we might want to ask Allwinner.

> Now, pll5 says
>
> -----8<------
> The PLL5 output for DDR = (24MHz*N*K)/M. <-- we call this pll5_ddr
> The PLL5 output for other module =(24MHz*N*K)/P. <-- we call this pll5_other
> -----8<------
>
> There does not seem to be anything connected to "pll5" with a rate of
> 24MHz*N*K, but personally I would not be opposed to adding it to the
> DT for consistency with pll6. After all, it actually is the common
> ancestor of pll5_ddr and pll5_other.

I already posted a version without adding "pll5". The names are coded into
factors_data instead.


Cheers,
ChenYu

> There's also some ASCII art on the code to visualize these clocks better
>
> http://git.linaro.org/people/mike.turquette/linux.git/blob/refs/heads/clk-next:/drivers/clk/sunxi/clk-sunxi.c#l842
>
> I hope this clarifies things.
>
> Cheers,
>
> Emilio