[PATCH net-next v3] net: stmmac: add platform init/exit for Altera's ARM socfpga

[PATCH net-next v3] net: stmmac: add platform init/exit for Altera's ARM socfpga

[Vince Bridgers]

This patch adds platform init/exit functions and modifications to support
suspend/resume for the Altera Cyclone 5 SOC Ethernet controller. The platform
exit function puts the controller into reset using the socfpga reset
controller driver. The platform init function sets up the Synopsys mac by
first making sure the Ethernet controller is held in reset, programming the
phy mode through external support logic, then deasserts reset through
the socfpga reset manager driver.

Signed-off-by: Vince Bridgers <vbridgers2013@gmail.com>
---
V3: respin for net-next after phy_suspend was exported by libphy
    per suggestion from Florian. No changes to patch from V2 -> V3.
V2: Address review comments - add line break before structure decl
---
 .../net/ethernet/stmicro/stmmac/dwmac-socfpga.c    |   69 ++++++++++++++++++++
 drivers/net/ethernet/stmicro/stmmac/stmmac_main.c  |    4 ++
 2 files changed, 73 insertions(+)

diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c
index fd8a217..ec632e6 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c
@@ -20,7 +20,9 @@
 #include <linux/of_net.h>
 #include <linux/phy.h>
 #include <linux/regmap.h>
+#include <linux/reset.h>
 #include <linux/stmmac.h>
+#include "stmmac.h"
 
 #define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII 0x0
 #define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII 0x1
@@ -34,6 +36,7 @@ struct socfpga_dwmac {
 	u32	reg_shift;
 	struct	device *dev;
 	struct regmap *sys_mgr_base_addr;
+	struct reset_control *stmmac_rst;
 };
 
 static int socfpga_dwmac_parse_data(struct socfpga_dwmac *dwmac, struct device *dev)
@@ -43,6 +46,13 @@ static int socfpga_dwmac_parse_data(struct socfpga_dwmac *dwmac, struct device *
 	u32 reg_offset, reg_shift;
 	int ret;
 
+	dwmac->stmmac_rst = devm_reset_control_get(dev,
+						  STMMAC_RESOURCE_NAME);
+	if (IS_ERR(dwmac->stmmac_rst)) {
+		dev_info(dev, "Could not get reset control!\n");
+		return -EINVAL;
+	}
+
 	dwmac->interface = of_get_phy_mode(np);
 
 	sys_mgr_base_addr = syscon_regmap_lookup_by_phandle(np, "altr,sysmgr-syscon");
@@ -125,6 +135,65 @@ static void *socfpga_dwmac_probe(struct platform_device *pdev)
 	return dwmac;
 }
 
+static void socfpga_dwmac_exit(struct platform_device *pdev, void *priv)
+{
+	struct socfpga_dwmac	*dwmac = priv;
+
+	/* On socfpga platform exit, assert and hold reset to the
+	 * enet controller - the default state after a hard reset.
+	 */
+	if (dwmac->stmmac_rst)
+		reset_control_assert(dwmac->stmmac_rst);
+}
+
+static int socfpga_dwmac_init(struct platform_device *pdev, void *priv)
+{
+	struct socfpga_dwmac	*dwmac = priv;
+	struct net_device *ndev = platform_get_drvdata(pdev);
+	struct stmmac_priv *stpriv = NULL;
+	int ret = 0;
+
+	if (ndev)
+		stpriv = netdev_priv(ndev);
+
+	/* Assert reset to the enet controller before changing the phy mode */
+	if (dwmac->stmmac_rst)
+		reset_control_assert(dwmac->stmmac_rst);
+
+	/* Setup the phy mode in the system manager registers according to
+	 * devicetree configuration
+	 */
+	ret = socfpga_dwmac_setup(dwmac);
+
+	/* Deassert reset for the phy configuration to be sampled by
+	 * the enet controller, and operation to start in requested mode
+	 */
+	if (dwmac->stmmac_rst)
+		reset_control_deassert(dwmac->stmmac_rst);
+
+	/* Before the enet controller is suspended, the phy is suspended.
+	 * This causes the phy clock to be gated. The enet controller is
+	 * resumed before the phy, so the clock is still gated "off" when
+	 * the enet controller is resumed. This code makes sure the phy
+	 * is "resumed" before reinitializing the enet controller since
+	 * the enet controller depends on an active phy clock to complete
+	 * a DMA reset. A DMA reset will "time out" if executed
+	 * with no phy clock input on the Synopsys enet controller.
+	 * Verified through Synopsys Case #8000711656.
+	 *
+	 * Note that the phy clock is also gated when the phy is isolated.
+	 * Phy "suspend" and "isolate" controls are located in phy basic
+	 * control register 0, and can be modified by the phy driver
+	 * framework.
+	 */
+	if (stpriv && stpriv->phydev)
+		phy_resume(stpriv->phydev);
+
+	return ret;
+}
+
 const struct stmmac_of_data socfpga_gmac_data = {
 	.setup = socfpga_dwmac_probe,
+	.init = socfpga_dwmac_init,
+	.exit = socfpga_dwmac_exit,
 };
diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
index 057a120..18315f3 100644
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
@@ -2878,6 +2878,10 @@ int stmmac_suspend(struct net_device *ndev)
 		clk_disable_unprepare(priv->stmmac_clk);
 	}
 	spin_unlock_irqrestore(&priv->lock, flags);
+
+	priv->oldlink = 0;
+	priv->speed = 0;
+	priv->oldduplex = -1;
 	return 0;
 }
 
-- 
1.7.9.5

Re: [PATCH net-next v3] net: stmmac: add platform init/exit for Altera's ARM socfpga

[David Miller]

From: Vince Bridgers <vbridgers2013@gmail.com>
Date: Mon, 28 Jul 2014 14:07:58 -0500

> This patch adds platform init/exit functions and modifications to support
> suspend/resume for the Altera Cyclone 5 SOC Ethernet controller. The platform
> exit function puts the controller into reset using the socfpga reset
> controller driver. The platform init function sets up the Synopsys mac by
> first making sure the Ethernet controller is held in reset, programming the
> phy mode through external support logic, then deasserts reset through
> the socfpga reset manager driver.
> 
> Signed-off-by: Vince Bridgers <vbridgers2013@gmail.com>
> ---
> V3: respin for net-next after phy_suspend was exported by libphy
>     per suggestion from Florian. No changes to patch from V2 -> V3.
> V2: Address review comments - add line break before structure decl

Applied, thank you.

Re: [PATCH net-next v3] net: stmmac: add platform init/exit for Altera's ARM socfpga

[Chen-Yu Tsai]

Hi,

On Tue, Jul 29, 2014 at 3:07 AM, Vince Bridgers <vbridgers2013@gmail.com> wrote:
> This patch adds platform init/exit functions and modifications to support
> suspend/resume for the Altera Cyclone 5 SOC Ethernet controller. The platform
> exit function puts the controller into reset using the socfpga reset
> controller driver. The platform init function sets up the Synopsys mac by
> first making sure the Ethernet controller is held in reset, programming the
> phy mode through external support logic, then deasserts reset through
> the socfpga reset manager driver.

Sorry for the very late reply after the fact.

Is it possible to assert/deassert the reset in the driver core
suspend/resume functions, before the clock is enabled?

Since the platform hooks are called before the core resume, and after
core suspend, doing it in the core has the same order as you have in your
platform code. And the driver core already supports reset controls,
deasserting them at probe time, and asserting them when removed.

At the same time, phy_suspend/phy_resume could be moved into the driver
core as well.

After that, you only need to keep is socfpga_dwmac_init() calling
socfpga_dwmac_setup().


I did not attempt this when I added the platform code hooks, as I did not
have suspend capable hardware to test it on.

> Signed-off-by: Vince Bridgers <vbridgers2013@gmail.com>
> ---
> V3: respin for net-next after phy_suspend was exported by libphy
>     per suggestion from Florian. No changes to patch from V2 -> V3.
> V2: Address review comments - add line break before structure decl
> ---
>  .../net/ethernet/stmicro/stmmac/dwmac-socfpga.c    |   69 ++++++++++++++++++++
>  drivers/net/ethernet/stmicro/stmmac/stmmac_main.c  |    4 ++
>  2 files changed, 73 insertions(+)
>
[...]


Cheers
ChenYu

Re: [PATCH net-next v3] net: stmmac: add platform init/exit for Altera's ARM socfpga

[Vince Bridgers]

Hi ChenYu,

On Fri, Aug 1, 2014 at 11:06 AM, Chen-Yu Tsai <wens@csie.org> wrote:
> Hi,
>
> On Tue, Jul 29, 2014 at 3:07 AM, Vince Bridgers <vbridgers2013@gmail.com> wrote:
>> This patch adds platform init/exit functions and modifications to support
>> suspend/resume for the Altera Cyclone 5 SOC Ethernet controller. The platform
>> exit function puts the controller into reset using the socfpga reset
>> controller driver. The platform init function sets up the Synopsys mac by
>> first making sure the Ethernet controller is held in reset, programming the
>> phy mode through external support logic, then deasserts reset through
>> the socfpga reset manager driver.
>
> Sorry for the very late reply after the fact.
>
> Is it possible to assert/deassert the reset in the driver core
> suspend/resume functions, before the clock is enabled?

The answer to this question depends on how the Synopsys EMAC is used
in other implementations.

For the suspend - and exit, yes this is possible for the Altera SOC
implementation (but I don't know if this is the case for other EMAC
implementations). For resume - and init, this is platform specific.

For the Altera SOC implementation, the driver code must make sure the
EMAC controller logic is held in reset, set the phy mode selection
input pins to the Synopsys EMAC through a register write, then
deassert the reset. This is further complicated by making sure the
PHY's clock is active before returning from the init function so that
the DMA reset in the EMAC initialization function will be successful -
leading to the addition of phy_resume in the driver's platform
specific init function.

The patch in the platform specific portion of the driver for the
Altera socfpga supports the logic that wraps the EMAC in the Altera
SOC - note this logic could be different for other implementations and
I don't know what all of those look like. If we knew the details of
the other controller implementations then I think we could answer this
question.

>
> Since the platform hooks are called before the core resume, and after
> core suspend, doing it in the core has the same order as you have in your
> platform code. And the driver core already supports reset controls,
> deasserting them at probe time, and asserting them when removed.
>
> At the same time, phy_suspend/phy_resume could be moved into the driver
> core as well.

Only PHY resume is part of the platform specific initialization, the
reason as stated above. In the Altera SOC case, PHY resume could be
moved out of the platform specific initialization and into the driver
core if that's helpful.

>
> After that, you only need to keep is socfpga_dwmac_init() calling
> socfpga_dwmac_setup().
>
>
> I did not attempt this when I added the platform code hooks, as I did not
> have suspend capable hardware to test it on.

The contributors for the other implementations using this driver need
to let us know how this might work for them too before we make any
changes outside of the platform specific code. One suggestion might be
to start a thread requesting those details from the contributors to
the stmmac driver.

Cheers,

Vince

>
>> Signed-off-by: Vince Bridgers <vbridgers2013@gmail.com>
>> ---
>> V3: respin for net-next after phy_suspend was exported by libphy
>>     per suggestion from Florian. No changes to patch from V2 -> V3.
>> V2: Address review comments - add line break before structure decl
>> ---
>>  .../net/ethernet/stmicro/stmmac/dwmac-socfpga.c    |   69 ++++++++++++++++++++
>>  drivers/net/ethernet/stmicro/stmmac/stmmac_main.c  |    4 ++
>>  2 files changed, 73 insertions(+)
>>
> [...]
>
>
> Cheers
> ChenYu