* [PATCH v2 0/4] arm64: Allwinner A64 support based on sunxi-ng @ 2016-09-09 20:10 ` Maxime Ripard 0 siblings, 0 replies; 35+ messages in thread From: Maxime Ripard @ 2016-09-09 20:10 UTC (permalink / raw) To: Mike Turquette, Stephen Boyd, Chen-Yu Tsai, Maxime Ripard Cc: linux-arm-kernel, Andre Przywara, linux-clk, linux-kernel, linux-sunxi Hi, As it was in the first iteration, this is the A64 support based on the new sunxi-ng clock framework. The support for it is quite minimal at the moment, but it should be fairly easy to add new devices, as most of the design is shared with older SoCs. Let me know what you think, Maxime Changes from v1: - Split the A64 CCU support out of the H3 driver - Added the PMU support - Removed the clocks node - Rebased on top of current sunxi/clk-for-4.9 branch Andre Przywara (3): Documentation: devicetree: add vendor prefix for Pine64 arm64: dts: add Allwinner A64 SoC .dtsi arm64: dts: add Pine64 support Maxime Ripard (1): clk: sunxi-ng: Add A64 clocks Documentation/devicetree/bindings/arm/sunxi.txt | 1 + .../devicetree/bindings/clock/sunxi-ccu.txt | 1 + .../devicetree/bindings/vendor-prefixes.txt | 1 + MAINTAINERS | 1 + arch/arm64/boot/dts/Makefile | 1 + arch/arm64/boot/dts/allwinner/Makefile | 5 + .../boot/dts/allwinner/sun50i-a64-pine64-plus.dts | 50 ++ .../arm64/boot/dts/allwinner/sun50i-a64-pine64.dts | 70 ++ arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 279 +++++++ drivers/clk/sunxi-ng/Kconfig | 11 + drivers/clk/sunxi-ng/Makefile | 1 + drivers/clk/sunxi-ng/ccu-sun50i-a64.c | 870 +++++++++++++++++++++ drivers/clk/sunxi-ng/ccu-sun50i-a64.h | 68 ++ include/dt-bindings/clock/sun50i-a64-ccu.h | 132 ++++ include/dt-bindings/reset/sun50i-a64-ccu.h | 97 +++ 15 files changed, 1588 insertions(+) create mode 100644 arch/arm64/boot/dts/allwinner/Makefile create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-plus.dts create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi create mode 100644 drivers/clk/sunxi-ng/ccu-sun50i-a64.c create mode 100644 drivers/clk/sunxi-ng/ccu-sun50i-a64.h create mode 100644 include/dt-bindings/clock/sun50i-a64-ccu.h create mode 100644 include/dt-bindings/reset/sun50i-a64-ccu.h -- 2.9.3 ^ permalink raw reply [flat|nested] 35+ messages in thread
* [PATCH v2 0/4] arm64: Allwinner A64 support based on sunxi-ng @ 2016-09-09 20:10 ` Maxime Ripard 0 siblings, 0 replies; 35+ messages in thread From: Maxime Ripard @ 2016-09-09 20:10 UTC (permalink / raw) To: linux-arm-kernel Hi, As it was in the first iteration, this is the A64 support based on the new sunxi-ng clock framework. The support for it is quite minimal at the moment, but it should be fairly easy to add new devices, as most of the design is shared with older SoCs. Let me know what you think, Maxime Changes from v1: - Split the A64 CCU support out of the H3 driver - Added the PMU support - Removed the clocks node - Rebased on top of current sunxi/clk-for-4.9 branch Andre Przywara (3): Documentation: devicetree: add vendor prefix for Pine64 arm64: dts: add Allwinner A64 SoC .dtsi arm64: dts: add Pine64 support Maxime Ripard (1): clk: sunxi-ng: Add A64 clocks Documentation/devicetree/bindings/arm/sunxi.txt | 1 + .../devicetree/bindings/clock/sunxi-ccu.txt | 1 + .../devicetree/bindings/vendor-prefixes.txt | 1 + MAINTAINERS | 1 + arch/arm64/boot/dts/Makefile | 1 + arch/arm64/boot/dts/allwinner/Makefile | 5 + .../boot/dts/allwinner/sun50i-a64-pine64-plus.dts | 50 ++ .../arm64/boot/dts/allwinner/sun50i-a64-pine64.dts | 70 ++ arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 279 +++++++ drivers/clk/sunxi-ng/Kconfig | 11 + drivers/clk/sunxi-ng/Makefile | 1 + drivers/clk/sunxi-ng/ccu-sun50i-a64.c | 870 +++++++++++++++++++++ drivers/clk/sunxi-ng/ccu-sun50i-a64.h | 68 ++ include/dt-bindings/clock/sun50i-a64-ccu.h | 132 ++++ include/dt-bindings/reset/sun50i-a64-ccu.h | 97 +++ 15 files changed, 1588 insertions(+) create mode 100644 arch/arm64/boot/dts/allwinner/Makefile create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-plus.dts create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi create mode 100644 drivers/clk/sunxi-ng/ccu-sun50i-a64.c create mode 100644 drivers/clk/sunxi-ng/ccu-sun50i-a64.h create mode 100644 include/dt-bindings/clock/sun50i-a64-ccu.h create mode 100644 include/dt-bindings/reset/sun50i-a64-ccu.h -- 2.9.3 ^ permalink raw reply [flat|nested] 35+ messages in thread
* [PATCH v2 1/4] clk: sunxi-ng: Add A64 clocks 2016-09-09 20:10 ` Maxime Ripard @ 2016-09-09 20:10 ` Maxime Ripard -1 siblings, 0 replies; 35+ messages in thread From: Maxime Ripard @ 2016-09-09 20:10 UTC (permalink / raw) To: Mike Turquette, Stephen Boyd, Chen-Yu Tsai, Maxime Ripard Cc: linux-arm-kernel, Andre Przywara, linux-clk, linux-kernel, linux-sunxi Add the A64 CCU clocks set. Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> --- .../devicetree/bindings/clock/sunxi-ccu.txt | 1 + drivers/clk/sunxi-ng/Kconfig | 11 + drivers/clk/sunxi-ng/Makefile | 1 + drivers/clk/sunxi-ng/ccu-sun50i-a64.c | 870 +++++++++++++++++++++ drivers/clk/sunxi-ng/ccu-sun50i-a64.h | 68 ++ include/dt-bindings/clock/sun50i-a64-ccu.h | 132 ++++ include/dt-bindings/reset/sun50i-a64-ccu.h | 97 +++ 7 files changed, 1180 insertions(+) create mode 100644 drivers/clk/sunxi-ng/ccu-sun50i-a64.c create mode 100644 drivers/clk/sunxi-ng/ccu-sun50i-a64.h create mode 100644 include/dt-bindings/clock/sun50i-a64-ccu.h create mode 100644 include/dt-bindings/reset/sun50i-a64-ccu.h diff --git a/Documentation/devicetree/bindings/clock/sunxi-ccu.txt b/Documentation/devicetree/bindings/clock/sunxi-ccu.txt index 3868458a5feb..74d44a4273f2 100644 --- a/Documentation/devicetree/bindings/clock/sunxi-ccu.txt +++ b/Documentation/devicetree/bindings/clock/sunxi-ccu.txt @@ -7,6 +7,7 @@ Required properties : - "allwinner,sun8i-a23-ccu" - "allwinner,sun8i-a33-ccu" - "allwinner,sun8i-h3-ccu" + - "allwinner,sun50i-a64-ccu" - reg: Must contain the registers base address and length - clocks: phandle to the oscillators feeding the CCU. Two are needed: diff --git a/drivers/clk/sunxi-ng/Kconfig b/drivers/clk/sunxi-ng/Kconfig index 254d9526c018..71e0c21c3545 100644 --- a/drivers/clk/sunxi-ng/Kconfig +++ b/drivers/clk/sunxi-ng/Kconfig @@ -101,4 +101,15 @@ config SUN8I_H3_CCU select SUNXI_CCU_PHASE default MACH_SUN8I +config SUN50I_A64_CCU + bool "Support for the Allwinner A64 CCU" + select SUNXI_CCU_DIV + select SUNXI_CCU_NK + select SUNXI_CCU_NKM + select SUNXI_CCU_NKMP + select SUNXI_CCU_NM + select SUNXI_CCU_MP + select SUNXI_CCU_PHASE + default ARM64 && ARCH_SUNXI + endif diff --git a/drivers/clk/sunxi-ng/Makefile b/drivers/clk/sunxi-ng/Makefile index 106cba27c331..964f22091a10 100644 --- a/drivers/clk/sunxi-ng/Makefile +++ b/drivers/clk/sunxi-ng/Makefile @@ -22,3 +22,4 @@ obj-$(CONFIG_SUN6I_A31_CCU) += ccu-sun6i-a31.o obj-$(CONFIG_SUN8I_A23_CCU) += ccu-sun8i-a23.o obj-$(CONFIG_SUN8I_A33_CCU) += ccu-sun8i-a33.o obj-$(CONFIG_SUN8I_H3_CCU) += ccu-sun8i-h3.o +obj-$(CONFIG_SUN50I_A64_CCU) += ccu-sun50i-a64.o diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c new file mode 100644 index 000000000000..d51ee416f515 --- /dev/null +++ b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c @@ -0,0 +1,870 @@ +/* + * Copyright (c) 2016 Maxime Ripard. All rights reserved. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <linux/clk-provider.h> +#include <linux/of_address.h> + +#include "ccu_common.h" +#include "ccu_reset.h" + +#include "ccu_div.h" +#include "ccu_gate.h" +#include "ccu_mp.h" +#include "ccu_mult.h" +#include "ccu_nk.h" +#include "ccu_nkm.h" +#include "ccu_nkmp.h" +#include "ccu_nm.h" +#include "ccu_phase.h" + +#include "ccu-sun50i-a64.h" + +static SUNXI_CCU_NKMP_WITH_GATE_LOCK(pll_cpux_clk, "pll-cpux", + "osc24M", 0x000, + 8, 5, /* N */ + 4, 2, /* K */ + 0, 2, /* M */ + 16, 2, /* P */ + BIT(31), /* gate */ + BIT(28), /* lock */ + 0); + +/* + * The Audio PLL is supposed to have 4 outputs: 3 fixed factors from + * the base (2x, 4x and 8x), and one variable divider (the one true + * pll audio). + * + * We don't have any need for the variable divider for now, so we just + * hardcode it to match with the clock names + */ +#define SUN50I_A64_PLL_AUDIO_REG 0x008 + +static SUNXI_CCU_NM_WITH_GATE_LOCK(pll_audio_base_clk, "pll-audio-base", + "osc24M", 0x008, + 8, 7, /* N */ + 0, 5, /* M */ + BIT(31), /* gate */ + BIT(28), /* lock */ + 0); + +static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video0_clk, "pll-video0", + "osc24M", 0x010, + 8, 7, /* N */ + 0, 4, /* M */ + BIT(24), /* frac enable */ + BIT(25), /* frac select */ + 270000000, /* frac rate 0 */ + 297000000, /* frac rate 1 */ + BIT(31), /* gate */ + BIT(28), /* lock */ + 0); + +static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_ve_clk, "pll-ve", + "osc24M", 0x018, + 8, 7, /* N */ + 0, 4, /* M */ + BIT(24), /* frac enable */ + BIT(25), /* frac select */ + 270000000, /* frac rate 0 */ + 297000000, /* frac rate 1 */ + BIT(31), /* gate */ + BIT(28), /* lock */ + 0); + +static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_ddr0_clk, "pll-ddr0", + "osc24M", 0x020, + 8, 5, /* N */ + 4, 2, /* K */ + 0, 2, /* M */ + BIT(31), /* gate */ + BIT(28), /* lock */ + 0); + +static SUNXI_CCU_NK_WITH_GATE_LOCK_POSTDIV(pll_periph0_clk, "pll-periph0", + "osc24M", 0x028, + 8, 5, /* N */ + 4, 2, /* K */ + BIT(31), /* gate */ + BIT(28), /* lock */ + 2, /* post-div */ + 0); + +static SUNXI_CCU_NK_WITH_GATE_LOCK_POSTDIV(pll_periph1_clk, "pll-periph1", + "osc24M", 0x02c, + 8, 5, /* N */ + 4, 2, /* K */ + BIT(31), /* gate */ + BIT(28), /* lock */ + 2, /* post-div */ + 0); + +static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video1_clk, "pll-video1", + "osc24M", 0x030, + 8, 7, /* N */ + 0, 4, /* M */ + BIT(24), /* frac enable */ + BIT(25), /* frac select */ + 270000000, /* frac rate 0 */ + 297000000, /* frac rate 1 */ + BIT(31), /* gate */ + BIT(28), /* lock */ + 0); + +static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_gpu_clk, "pll-gpu", + "osc24M", 0x038, + 8, 7, /* N */ + 0, 4, /* M */ + BIT(24), /* frac enable */ + BIT(25), /* frac select */ + 270000000, /* frac rate 0 */ + 297000000, /* frac rate 1 */ + BIT(31), /* gate */ + BIT(28), /* lock */ + 0); + +/* + * The output function can be changed to something more complex that + * we do not handle yet. + * + * Hardcode the mode so that we don't fall in that case. + */ +#define SUN50I_A64_PLL_MIPI_REG 0x040 + +static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_mipi_clk, "pll-mipi", + "pll-video0", 0x040, + 8, 4, /* N */ + 4, 2, /* K */ + 0, 4, /* M */ + BIT(31), /* gate */ + BIT(28), /* lock */ + 0); + +static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_hsic_clk, "pll-hsic", + "osc24M", 0x044, + 8, 7, /* N */ + 0, 4, /* M */ + BIT(24), /* frac enable */ + BIT(25), /* frac select */ + 270000000, /* frac rate 0 */ + 297000000, /* frac rate 1 */ + BIT(31), /* gate */ + BIT(28), /* lock */ + 0); + +static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_de_clk, "pll-de", + "osc24M", 0x048, + 8, 7, /* N */ + 0, 4, /* M */ + BIT(24), /* frac enable */ + BIT(25), /* frac select */ + 270000000, /* frac rate 0 */ + 297000000, /* frac rate 1 */ + BIT(31), /* gate */ + BIT(28), /* lock */ + 0); + +static SUNXI_CCU_NM_WITH_GATE_LOCK(pll_ddr1_clk, "pll-ddr1", + "osc24M", 0x04c, + 8, 7, /* N */ + 0, 2, /* M */ + BIT(31), /* gate */ + BIT(28), /* lock */ + 0); + +static const char * const cpux_parents[] = { "osc32k", "osc24M", + "pll-cpux" , "pll-cpux" }; +static SUNXI_CCU_MUX(cpux_clk, "cpux", cpux_parents, + 0x050, 16, 2, CLK_IS_CRITICAL); + +static SUNXI_CCU_M(axi_clk, "axi", "cpux", 0x050, 0, 2, 0); + +static const char * const ahb1_parents[] = { "osc32k", "osc24M", + "axi" , "pll-periph0" }; +static struct ccu_div ahb1_clk = { + .div = _SUNXI_CCU_DIV_FLAGS(4, 2, CLK_DIVIDER_POWER_OF_TWO), + + .mux = { + .shift = 12, + .width = 2, + + .variable_prediv = { + .index = 3, + .shift = 6, + .width = 2, + }, + }, + + .common = { + .reg = 0x054, + .features = CCU_FEATURE_VARIABLE_PREDIV, + .hw.init = CLK_HW_INIT_PARENTS("ahb1", + ahb1_parents, + &ccu_div_ops, + 0), + }, +}; + +static struct clk_div_table apb1_div_table[] = { + { .val = 0, .div = 2 }, + { .val = 1, .div = 2 }, + { .val = 2, .div = 4 }, + { .val = 3, .div = 8 }, + { /* Sentinel */ }, +}; +static SUNXI_CCU_DIV_TABLE(apb1_clk, "apb1", "ahb1", + 0x054, 8, 2, apb1_div_table, 0); + +static const char * const apb2_parents[] = { "osc32k", "osc24M", + "pll-periph0-2x" , + "pll-periph0-2x" }; +static SUNXI_CCU_MP_WITH_MUX(apb2_clk, "apb2", apb2_parents, 0x058, + 0, 5, /* M */ + 16, 2, /* P */ + 24, 2, /* mux */ + 0); + +static const char * const ahb2_parents[] = { "ahb1" , "pll-periph0" }; +static const struct ccu_mux_fixed_prediv ahb2_fixed_predivs[] = { + { .index = 1, .div = 2 }, +}; +static struct ccu_mux ahb2_clk = { + .mux = { + .shift = 0, + .width = 1, + .fixed_predivs = ahb2_fixed_predivs, + .n_predivs = ARRAY_SIZE(ahb2_fixed_predivs), + }, + + .common = { + .reg = 0x05c, + .features = CCU_FEATURE_FIXED_PREDIV, + .hw.init = CLK_HW_INIT_PARENTS("ahb2", + ahb2_parents, + &ccu_mux_ops, + 0), + }, +}; + +static SUNXI_CCU_GATE(bus_mipi_dsi_clk, "bus-mipi-dsi", "ahb1", + 0x060, BIT(1), 0); +static SUNXI_CCU_GATE(bus_ce_clk, "bus-ce", "ahb1", + 0x060, BIT(5), 0); +static SUNXI_CCU_GATE(bus_dma_clk, "bus-dma", "ahb1", + 0x060, BIT(6), 0); +static SUNXI_CCU_GATE(bus_mmc0_clk, "bus-mmc0", "ahb1", + 0x060, BIT(8), 0); +static SUNXI_CCU_GATE(bus_mmc1_clk, "bus-mmc1", "ahb1", + 0x060, BIT(9), 0); +static SUNXI_CCU_GATE(bus_mmc2_clk, "bus-mmc2", "ahb1", + 0x060, BIT(10), 0); +static SUNXI_CCU_GATE(bus_nand_clk, "bus-nand", "ahb1", + 0x060, BIT(13), 0); +static SUNXI_CCU_GATE(bus_dram_clk, "bus-dram", "ahb1", + 0x060, BIT(14), 0); +static SUNXI_CCU_GATE(bus_emac_clk, "bus-emac", "ahb2", + 0x060, BIT(17), 0); +static SUNXI_CCU_GATE(bus_ts_clk, "bus-ts", "ahb1", + 0x060, BIT(18), 0); +static SUNXI_CCU_GATE(bus_hstimer_clk, "bus-hstimer", "ahb1", + 0x060, BIT(19), 0); +static SUNXI_CCU_GATE(bus_spi0_clk, "bus-spi0", "ahb1", + 0x060, BIT(20), 0); +static SUNXI_CCU_GATE(bus_spi1_clk, "bus-spi1", "ahb1", + 0x060, BIT(21), 0); +static SUNXI_CCU_GATE(bus_otg_clk, "bus-otg", "ahb1", + 0x060, BIT(23), 0); +static SUNXI_CCU_GATE(bus_ehci0_clk, "bus-ehci0", "ahb1", + 0x060, BIT(24), 0); +static SUNXI_CCU_GATE(bus_ehci1_clk, "bus-ehci1", "ahb2", + 0x060, BIT(25), 0); +static SUNXI_CCU_GATE(bus_ohci0_clk, "bus-ohci0", "ahb1", + 0x060, BIT(28), 0); +static SUNXI_CCU_GATE(bus_ohci1_clk, "bus-ohci1", "ahb2", + 0x060, BIT(29), 0); + +static SUNXI_CCU_GATE(bus_ve_clk, "bus-ve", "ahb1", + 0x064, BIT(0), 0); +static SUNXI_CCU_GATE(bus_tcon0_clk, "bus-tcon0", "ahb1", + 0x064, BIT(3), 0); +static SUNXI_CCU_GATE(bus_tcon1_clk, "bus-tcon1", "ahb1", + 0x064, BIT(4), 0); +static SUNXI_CCU_GATE(bus_deinterlace_clk, "bus-deinterlace", "ahb1", + 0x064, BIT(5), 0); +static SUNXI_CCU_GATE(bus_csi_clk, "bus-csi", "ahb1", + 0x064, BIT(8), 0); +static SUNXI_CCU_GATE(bus_hdmi_clk, "bus-hdmi", "ahb1", + 0x064, BIT(11), 0); +static SUNXI_CCU_GATE(bus_de_clk, "bus-de", "ahb1", + 0x064, BIT(12), 0); +static SUNXI_CCU_GATE(bus_gpu_clk, "bus-gpu", "ahb1", + 0x064, BIT(20), 0); +static SUNXI_CCU_GATE(bus_msgbox_clk, "bus-msgbox", "ahb1", + 0x064, BIT(21), 0); +static SUNXI_CCU_GATE(bus_spinlock_clk, "bus-spinlock", "ahb1", + 0x064, BIT(22), 0); + +static SUNXI_CCU_GATE(bus_codec_clk, "bus-codec", "apb1", + 0x068, BIT(0), 0); +static SUNXI_CCU_GATE(bus_spdif_clk, "bus-spdif", "apb1", + 0x068, BIT(1), 0); +static SUNXI_CCU_GATE(bus_pio_clk, "bus-pio", "apb1", + 0x068, BIT(5), 0); +static SUNXI_CCU_GATE(bus_ths_clk, "bus-ths", "apb1", + 0x068, BIT(8), 0); +static SUNXI_CCU_GATE(bus_i2s0_clk, "bus-i2s0", "apb1", + 0x068, BIT(12), 0); +static SUNXI_CCU_GATE(bus_i2s1_clk, "bus-i2s1", "apb1", + 0x068, BIT(13), 0); +static SUNXI_CCU_GATE(bus_i2s2_clk, "bus-i2s2", "apb1", + 0x068, BIT(14), 0); + +static SUNXI_CCU_GATE(bus_i2c0_clk, "bus-i2c0", "apb2", + 0x06c, BIT(0), 0); +static SUNXI_CCU_GATE(bus_i2c1_clk, "bus-i2c1", "apb2", + 0x06c, BIT(1), 0); +static SUNXI_CCU_GATE(bus_i2c2_clk, "bus-i2c2", "apb2", + 0x06c, BIT(2), 0); +static SUNXI_CCU_GATE(bus_scr_clk, "bus-scr", "apb2", + 0x06c, BIT(5), 0); +static SUNXI_CCU_GATE(bus_uart0_clk, "bus-uart0", "apb2", + 0x06c, BIT(16), 0); +static SUNXI_CCU_GATE(bus_uart1_clk, "bus-uart1", "apb2", + 0x06c, BIT(17), 0); +static SUNXI_CCU_GATE(bus_uart2_clk, "bus-uart2", "apb2", + 0x06c, BIT(18), 0); +static SUNXI_CCU_GATE(bus_uart3_clk, "bus-uart3", "apb2", + 0x06c, BIT(19), 0); +static SUNXI_CCU_GATE(bus_uart4_clk, "bus-uart4", "apb2", + 0x06c, BIT(20), 0); + +static SUNXI_CCU_GATE(bus_dbg_clk, "bus-dbg", "ahb1", + 0x070, BIT(7), 0); + +static struct clk_div_table ths_div_table[] = { + { .val = 0, .div = 1 }, + { .val = 1, .div = 2 }, + { .val = 2, .div = 4 }, + { .val = 3, .div = 6 }, +}; +static SUNXI_CCU_DIV_TABLE_WITH_GATE(ths_clk, "ths", "osc24M", + 0x074, 0, 2, ths_div_table, BIT(31), 0); + +static const char * const mod0_default_parents[] = { "osc24M", "pll-periph0", + "pll-periph1" }; +static SUNXI_CCU_MP_WITH_MUX_GATE(nand_clk, "nand", mod0_default_parents, 0x080, + 0, 4, /* M */ + 16, 2, /* P */ + 24, 2, /* mux */ + BIT(31), /* gate */ + 0); + +static const char * const mmc_default_parents[] = { "osc24M", "pll-periph0-2x", + "pll-periph1-2x" }; +static SUNXI_CCU_MP_WITH_MUX_GATE(mmc0_clk, "mmc0", mmc_default_parents, 0x088, + 0, 4, /* M */ + 16, 2, /* P */ + 24, 2, /* mux */ + BIT(31), /* gate */ + 0); + +static SUNXI_CCU_MP_WITH_MUX_GATE(mmc1_clk, "mmc1", mmc_default_parents, 0x08c, + 0, 4, /* M */ + 16, 2, /* P */ + 24, 2, /* mux */ + BIT(31), /* gate */ + 0); + +static SUNXI_CCU_MP_WITH_MUX_GATE(mmc2_clk, "mmc2", mmc_default_parents, 0x090, + 0, 4, /* M */ + 16, 2, /* P */ + 24, 2, /* mux */ + BIT(31), /* gate */ + 0); + +static const char * const ts_parents[] = { "osc24M", "pll-periph0", }; +static SUNXI_CCU_MP_WITH_MUX_GATE(ts_clk, "ts", ts_parents, 0x098, + 0, 4, /* M */ + 16, 2, /* P */ + 24, 2, /* mux */ + BIT(31), /* gate */ + 0); + +static SUNXI_CCU_MP_WITH_MUX_GATE(ce_clk, "ce", mmc_default_parents, 0x09c, + 0, 4, /* M */ + 16, 2, /* P */ + 24, 2, /* mux */ + BIT(31), /* gate */ + 0); + + +static SUNXI_CCU_MP_WITH_MUX_GATE(spi0_clk, "spi0", mod0_default_parents, 0x0a0, + 0, 4, /* M */ + 16, 2, /* P */ + 24, 2, /* mux */ + BIT(31), /* gate */ + 0); + +static SUNXI_CCU_MP_WITH_MUX_GATE(spi1_clk, "spi1", mod0_default_parents, 0x0a4, + 0, 4, /* M */ + 16, 2, /* P */ + 24, 2, /* mux */ + BIT(31), /* gate */ + 0); + +static const char * const i2s_parents[] = { "pll-audio-8x", "pll-audio-4x", + "pll-audio-2x", "pll-audio" }; +static SUNXI_CCU_MUX_WITH_GATE(i2s0_clk, "i2s0", i2s_parents, + 0x0b0, 16, 2, BIT(31), 0); + +static SUNXI_CCU_MUX_WITH_GATE(i2s1_clk, "i2s1", i2s_parents, + 0x0b4, 16, 2, BIT(31), 0); + +static SUNXI_CCU_MUX_WITH_GATE(i2s2_clk, "i2s2", i2s_parents, + 0x0b8, 16, 2, BIT(31), 0); + +static SUNXI_CCU_M_WITH_GATE(spdif_clk, "spdif", "pll-audio", + 0x0c0, 0, 4, BIT(31), 0); + +static SUNXI_CCU_GATE(usb_phy0_clk, "usb-phy0", "osc24M", + 0x0cc, BIT(8), 0); +static SUNXI_CCU_GATE(usb_phy1_clk, "usb-phy1", "osc24M", + 0x0cc, BIT(9), 0); +static SUNXI_CCU_GATE(usb_hsic_clk, "usb-hsic", "pll-hsic", + 0x0cc, BIT(10), 0); +static SUNXI_CCU_GATE(usb_hsic_12m_clk, "usb-hsic-12M", "osc12M", + 0x0cc, BIT(11), 0); +static SUNXI_CCU_GATE(usb_ohci0_clk, "usb-ohci0", "osc12M", + 0x0cc, BIT(16), 0); +static SUNXI_CCU_GATE(usb_ohci1_clk, "usb-ohci1", "usb-ohci0", + 0x0cc, BIT(17), 0); + +static const char * const dram_parents[] = { "pll-ddr0", "pll-ddr1" }; +static SUNXI_CCU_M_WITH_MUX(dram_clk, "dram", dram_parents, + 0x0f4, 0, 4, 20, 2, CLK_IS_CRITICAL); + +static SUNXI_CCU_GATE(dram_ve_clk, "dram-ve", "dram", + 0x100, BIT(0), 0); +static SUNXI_CCU_GATE(dram_csi_clk, "dram-csi", "dram", + 0x100, BIT(1), 0); +static SUNXI_CCU_GATE(dram_deinterlace_clk, "dram-deinterlace", "dram", + 0x100, BIT(2), 0); +static SUNXI_CCU_GATE(dram_ts_clk, "dram-ts", "dram", + 0x100, BIT(3), 0); + +static const char * const de_parents[] = { "pll-periph0-2x", "pll-de" }; +static SUNXI_CCU_M_WITH_MUX_GATE(de_clk, "de", de_parents, + 0x104, 0, 4, 24, 3, BIT(31), 0); + +static const char * const tcon0_parents[] = { "pll-mipi", "pll-video0-2x" }; +static const u8 tcon0_table[] = { 0, 2, }; +static SUNXI_CCU_MUX_TABLE_WITH_GATE(tcon0_clk, "tcon0", tcon0_parents, + tcon0_table, 0x118, 24, 3, BIT(31), 0); + +static const char * const tcon1_parents[] = { "pll-video0", "pll-video1" }; +static const u8 tcon1_table[] = { 0, 2, }; +struct ccu_div tcon1_clk = { + .enable = BIT(31), + .div = _SUNXI_CCU_DIV(0, 4), + .mux = _SUNXI_CCU_MUX_TABLE(24, 3, tcon1_table), + .common = { + .reg = 0x11c, + .hw.init = CLK_HW_INIT_PARENTS("tcon1", + tcon1_parents, + &ccu_div_ops, + 0), + }, +}; + +static const char * const deinterlace_parents[] = { "pll-periph0", "pll-periph1" }; +static SUNXI_CCU_M_WITH_MUX_GATE(deinterlace_clk, "deinterlace", deinterlace_parents, + 0x124, 0, 4, 24, 3, BIT(31), 0); + +static SUNXI_CCU_GATE(csi_misc_clk, "csi-misc", "osc24M", + 0x130, BIT(31), 0); + +static const char * const csi_sclk_parents[] = { "pll-periph0", "pll-periph1" }; +static SUNXI_CCU_M_WITH_MUX_GATE(csi_sclk_clk, "csi-sclk", csi_sclk_parents, + 0x134, 16, 4, 24, 3, BIT(31), 0); + +static const char * const csi_mclk_parents[] = { "osc24M", "pll-video1", "pll-periph1" }; +static SUNXI_CCU_M_WITH_MUX_GATE(csi_mclk_clk, "csi-mclk", csi_mclk_parents, + 0x134, 0, 5, 8, 3, BIT(15), 0); + +static SUNXI_CCU_M_WITH_GATE(ve_clk, "ve", "pll-ve", + 0x13c, 16, 3, BIT(31), 0); + +static SUNXI_CCU_GATE(ac_dig_clk, "ac-dig", "pll-audio", + 0x140, BIT(31), 0); + +static SUNXI_CCU_GATE(ac_dig_4x_clk, "ac-dig-4x", "pll-audio-4x", + 0x140, BIT(30), 0); + +static SUNXI_CCU_GATE(avs_clk, "avs", "osc24M", + 0x144, BIT(31), 0); + +static const char * const hdmi_parents[] = { "pll-video0", "pll-video1" }; +static SUNXI_CCU_M_WITH_MUX_GATE(hdmi_clk, "hdmi", hdmi_parents, + 0x150, 0, 4, 24, 2, BIT(31), 0); + +static SUNXI_CCU_GATE(hdmi_ddc_clk, "hdmi-ddc", "osc24M", + 0x154, BIT(31), 0); + +static const char * const mbus_parents[] = { "osc24M", "pll-periph0-2x", + "pll-ddr0", "pll-ddr1" }; +static SUNXI_CCU_M_WITH_MUX_GATE(mbus_clk, "mbus", mbus_parents, + 0x15c, 0, 3, 24, 2, BIT(31), CLK_IS_CRITICAL); + +static const char * const dsi_dphy_parents[] = { "pll-video0", "pll-periph0" }; +static SUNXI_CCU_M_WITH_MUX_GATE(dsi_dphy_clk, "dsi-dphy", dsi_dphy_parents, + 0x168, 0, 3, 24, 2, BIT(31), 0); + +static SUNXI_CCU_M_WITH_GATE(gpu_clk, "gpu", "pll-gpu", + 0x1a0, 0, 3, BIT(31), 0); + +/* Fixed Factor clocks */ +static CLK_FIXED_FACTOR(osc12M_clk, "osc12M", "osc24M", 1, 2, 0); + +/* We hardcode the divider to 4 for now */ +static CLK_FIXED_FACTOR(pll_audio_clk, "pll-audio", + "pll-audio-base", 4, 1, CLK_SET_RATE_PARENT); +static CLK_FIXED_FACTOR(pll_audio_2x_clk, "pll-audio-2x", + "pll-audio-base", 2, 1, CLK_SET_RATE_PARENT); +static CLK_FIXED_FACTOR(pll_audio_4x_clk, "pll-audio-4x", + "pll-audio-base", 1, 1, CLK_SET_RATE_PARENT); +static CLK_FIXED_FACTOR(pll_audio_8x_clk, "pll-audio-8x", + "pll-audio-base", 1, 2, CLK_SET_RATE_PARENT); +static CLK_FIXED_FACTOR(pll_periph0_2x_clk, "pll-periph0-2x", + "pll-periph0", 1, 2, 0); +static CLK_FIXED_FACTOR(pll_periph1_2x_clk, "pll-periph1-2x", + "pll-periph1", 1, 2, 0); +static CLK_FIXED_FACTOR(pll_video0_2x_clk, "pll-video0-2x", + "pll-video0", 1, 2, 0); + +static struct ccu_common *sun50i_a64_ccu_clks[] = { + &pll_cpux_clk.common, + &pll_audio_base_clk.common, + &pll_video0_clk.common, + &pll_ve_clk.common, + &pll_ddr0_clk.common, + &pll_periph0_clk.common, + &pll_periph1_clk.common, + &pll_video1_clk.common, + &pll_gpu_clk.common, + &pll_mipi_clk.common, + &pll_hsic_clk.common, + &pll_de_clk.common, + &pll_ddr1_clk.common, + &cpux_clk.common, + &axi_clk.common, + &ahb1_clk.common, + &apb1_clk.common, + &apb2_clk.common, + &ahb2_clk.common, + &bus_mipi_dsi_clk.common, + &bus_ce_clk.common, + &bus_dma_clk.common, + &bus_mmc0_clk.common, + &bus_mmc1_clk.common, + &bus_mmc2_clk.common, + &bus_nand_clk.common, + &bus_dram_clk.common, + &bus_emac_clk.common, + &bus_ts_clk.common, + &bus_hstimer_clk.common, + &bus_spi0_clk.common, + &bus_spi1_clk.common, + &bus_otg_clk.common, + &bus_ehci0_clk.common, + &bus_ehci1_clk.common, + &bus_ohci0_clk.common, + &bus_ohci1_clk.common, + &bus_ve_clk.common, + &bus_tcon0_clk.common, + &bus_tcon1_clk.common, + &bus_deinterlace_clk.common, + &bus_csi_clk.common, + &bus_hdmi_clk.common, + &bus_de_clk.common, + &bus_gpu_clk.common, + &bus_msgbox_clk.common, + &bus_spinlock_clk.common, + &bus_codec_clk.common, + &bus_spdif_clk.common, + &bus_pio_clk.common, + &bus_ths_clk.common, + &bus_i2s0_clk.common, + &bus_i2s1_clk.common, + &bus_i2s2_clk.common, + &bus_i2c0_clk.common, + &bus_i2c1_clk.common, + &bus_i2c2_clk.common, + &bus_scr_clk.common, + &bus_uart0_clk.common, + &bus_uart1_clk.common, + &bus_uart2_clk.common, + &bus_uart3_clk.common, + &bus_uart4_clk.common, + &bus_dbg_clk.common, + &ths_clk.common, + &nand_clk.common, + &mmc0_clk.common, + &mmc1_clk.common, + &mmc2_clk.common, + &ts_clk.common, + &ce_clk.common, + &spi0_clk.common, + &spi1_clk.common, + &i2s0_clk.common, + &i2s1_clk.common, + &i2s2_clk.common, + &spdif_clk.common, + &usb_phy0_clk.common, + &usb_phy1_clk.common, + &usb_hsic_clk.common, + &usb_hsic_12m_clk.common, + &usb_ohci0_clk.common, + &usb_ohci1_clk.common, + &dram_clk.common, + &dram_ve_clk.common, + &dram_csi_clk.common, + &dram_deinterlace_clk.common, + &dram_ts_clk.common, + &de_clk.common, + &tcon0_clk.common, + &tcon1_clk.common, + &deinterlace_clk.common, + &csi_misc_clk.common, + &csi_sclk_clk.common, + &csi_mclk_clk.common, + &ve_clk.common, + &ac_dig_clk.common, + &ac_dig_4x_clk.common, + &avs_clk.common, + &hdmi_clk.common, + &hdmi_ddc_clk.common, + &mbus_clk.common, + &dsi_dphy_clk.common, + &gpu_clk.common, +}; + +static struct clk_hw_onecell_data sun50i_a64_hw_clks = { + .hws = { + [CLK_OSC_12M] = &osc12M_clk.hw, + [CLK_PLL_CPUX] = &pll_cpux_clk.common.hw, + [CLK_PLL_AUDIO_BASE] = &pll_audio_base_clk.common.hw, + [CLK_PLL_AUDIO] = &pll_audio_clk.hw, + [CLK_PLL_AUDIO_2X] = &pll_audio_2x_clk.hw, + [CLK_PLL_AUDIO_4X] = &pll_audio_4x_clk.hw, + [CLK_PLL_AUDIO_8X] = &pll_audio_8x_clk.hw, + [CLK_PLL_VIDEO0] = &pll_video0_clk.common.hw, + [CLK_PLL_VIDEO0_2X] = &pll_video0_2x_clk.hw, + [CLK_PLL_VE] = &pll_ve_clk.common.hw, + [CLK_PLL_DDR0] = &pll_ddr0_clk.common.hw, + [CLK_PLL_PERIPH0] = &pll_periph0_clk.common.hw, + [CLK_PLL_PERIPH0_2X] = &pll_periph0_2x_clk.hw, + [CLK_PLL_PERIPH1] = &pll_periph1_clk.common.hw, + [CLK_PLL_PERIPH1_2X] = &pll_periph1_2x_clk.hw, + [CLK_PLL_VIDEO1] = &pll_video1_clk.common.hw, + [CLK_PLL_GPU] = &pll_gpu_clk.common.hw, + [CLK_PLL_MIPI] = &pll_mipi_clk.common.hw, + [CLK_PLL_HSIC] = &pll_hsic_clk.common.hw, + [CLK_PLL_DE] = &pll_de_clk.common.hw, + [CLK_PLL_DDR1] = &pll_ddr1_clk.common.hw, + [CLK_CPUX] = &cpux_clk.common.hw, + [CLK_AXI] = &axi_clk.common.hw, + [CLK_AHB1] = &ahb1_clk.common.hw, + [CLK_APB1] = &apb1_clk.common.hw, + [CLK_APB2] = &apb2_clk.common.hw, + [CLK_AHB2] = &ahb2_clk.common.hw, + [CLK_BUS_MIPI_DSI] = &bus_mipi_dsi_clk.common.hw, + [CLK_BUS_CE] = &bus_ce_clk.common.hw, + [CLK_BUS_DMA] = &bus_dma_clk.common.hw, + [CLK_BUS_MMC0] = &bus_mmc0_clk.common.hw, + [CLK_BUS_MMC1] = &bus_mmc1_clk.common.hw, + [CLK_BUS_MMC2] = &bus_mmc2_clk.common.hw, + [CLK_BUS_NAND] = &bus_nand_clk.common.hw, + [CLK_BUS_DRAM] = &bus_dram_clk.common.hw, + [CLK_BUS_EMAC] = &bus_emac_clk.common.hw, + [CLK_BUS_TS] = &bus_ts_clk.common.hw, + [CLK_BUS_HSTIMER] = &bus_hstimer_clk.common.hw, + [CLK_BUS_SPI0] = &bus_spi0_clk.common.hw, + [CLK_BUS_SPI1] = &bus_spi1_clk.common.hw, + [CLK_BUS_OTG] = &bus_otg_clk.common.hw, + [CLK_BUS_EHCI0] = &bus_ehci0_clk.common.hw, + [CLK_BUS_EHCI1] = &bus_ehci1_clk.common.hw, + [CLK_BUS_OHCI0] = &bus_ohci0_clk.common.hw, + [CLK_BUS_OHCI1] = &bus_ohci1_clk.common.hw, + [CLK_BUS_VE] = &bus_ve_clk.common.hw, + [CLK_BUS_TCON0] = &bus_tcon0_clk.common.hw, + [CLK_BUS_TCON1] = &bus_tcon1_clk.common.hw, + [CLK_BUS_DEINTERLACE] = &bus_deinterlace_clk.common.hw, + [CLK_BUS_CSI] = &bus_csi_clk.common.hw, + [CLK_BUS_HDMI] = &bus_hdmi_clk.common.hw, + [CLK_BUS_DE] = &bus_de_clk.common.hw, + [CLK_BUS_GPU] = &bus_gpu_clk.common.hw, + [CLK_BUS_MSGBOX] = &bus_msgbox_clk.common.hw, + [CLK_BUS_SPINLOCK] = &bus_spinlock_clk.common.hw, + [CLK_BUS_CODEC] = &bus_codec_clk.common.hw, + [CLK_BUS_SPDIF] = &bus_spdif_clk.common.hw, + [CLK_BUS_PIO] = &bus_pio_clk.common.hw, + [CLK_BUS_THS] = &bus_ths_clk.common.hw, + [CLK_BUS_I2S0] = &bus_i2s0_clk.common.hw, + [CLK_BUS_I2S1] = &bus_i2s1_clk.common.hw, + [CLK_BUS_I2S2] = &bus_i2s2_clk.common.hw, + [CLK_BUS_I2C0] = &bus_i2c0_clk.common.hw, + [CLK_BUS_I2C1] = &bus_i2c1_clk.common.hw, + [CLK_BUS_I2C2] = &bus_i2c2_clk.common.hw, + [CLK_BUS_UART0] = &bus_uart0_clk.common.hw, + [CLK_BUS_UART1] = &bus_uart1_clk.common.hw, + [CLK_BUS_UART2] = &bus_uart2_clk.common.hw, + [CLK_BUS_UART3] = &bus_uart3_clk.common.hw, + [CLK_BUS_UART4] = &bus_uart4_clk.common.hw, + [CLK_BUS_SCR] = &bus_scr_clk.common.hw, + [CLK_BUS_DBG] = &bus_dbg_clk.common.hw, + [CLK_THS] = &ths_clk.common.hw, + [CLK_NAND] = &nand_clk.common.hw, + [CLK_MMC0] = &mmc0_clk.common.hw, + [CLK_MMC1] = &mmc1_clk.common.hw, + [CLK_MMC2] = &mmc2_clk.common.hw, + [CLK_TS] = &ts_clk.common.hw, + [CLK_CE] = &ce_clk.common.hw, + [CLK_SPI0] = &spi0_clk.common.hw, + [CLK_SPI1] = &spi1_clk.common.hw, + [CLK_I2S0] = &i2s0_clk.common.hw, + [CLK_I2S1] = &i2s1_clk.common.hw, + [CLK_I2S2] = &i2s2_clk.common.hw, + [CLK_SPDIF] = &spdif_clk.common.hw, + [CLK_USB_PHY0] = &usb_phy0_clk.common.hw, + [CLK_USB_PHY1] = &usb_phy1_clk.common.hw, + [CLK_USB_HSIC] = &usb_hsic_clk.common.hw, + [CLK_USB_HSIC_12M] = &usb_hsic_12m_clk.common.hw, + [CLK_USB_OHCI0] = &usb_ohci0_clk.common.hw, + [CLK_USB_OHCI1] = &usb_ohci1_clk.common.hw, + [CLK_DRAM] = &dram_clk.common.hw, + [CLK_DRAM_VE] = &dram_ve_clk.common.hw, + [CLK_DRAM_CSI] = &dram_csi_clk.common.hw, + [CLK_DRAM_DEINTERLACE] = &dram_deinterlace_clk.common.hw, + [CLK_DRAM_TS] = &dram_ts_clk.common.hw, + [CLK_DE] = &de_clk.common.hw, + [CLK_TCON0] = &tcon0_clk.common.hw, + [CLK_TCON1] = &tcon1_clk.common.hw, + [CLK_DEINTERLACE] = &deinterlace_clk.common.hw, + [CLK_CSI_MISC] = &csi_misc_clk.common.hw, + [CLK_CSI_SCLK] = &csi_sclk_clk.common.hw, + [CLK_CSI_MCLK] = &csi_mclk_clk.common.hw, + [CLK_VE] = &ve_clk.common.hw, + [CLK_AC_DIG] = &ac_dig_clk.common.hw, + [CLK_AC_DIG_4X] = &ac_dig_4x_clk.common.hw, + [CLK_AVS] = &avs_clk.common.hw, + [CLK_HDMI] = &hdmi_clk.common.hw, + [CLK_HDMI_DDC] = &hdmi_ddc_clk.common.hw, + [CLK_MBUS] = &mbus_clk.common.hw, + [CLK_DSI_DPHY] = &dsi_dphy_clk.common.hw, + [CLK_GPU] = &gpu_clk.common.hw, + }, + .num = CLK_NUMBER, +}; + +static struct ccu_reset_map sun50i_a64_ccu_resets[] = { + [RST_USB_PHY0] = { 0x0cc, BIT(0) }, + [RST_USB_PHY1] = { 0x0cc, BIT(1) }, + [RST_USB_HSIC] = { 0x0cc, BIT(2) }, + + + [RST_MBUS] = { 0x0fc, BIT(31) }, + + [RST_BUS_MIPI_DSI] = { 0x2c0, BIT(1) }, + [RST_BUS_CE] = { 0x2c0, BIT(5) }, + [RST_BUS_DMA] = { 0x2c0, BIT(6) }, + [RST_BUS_MMC0] = { 0x2c0, BIT(8) }, + [RST_BUS_MMC1] = { 0x2c0, BIT(9) }, + [RST_BUS_MMC2] = { 0x2c0, BIT(10) }, + [RST_BUS_NAND] = { 0x2c0, BIT(13) }, + [RST_BUS_DRAM] = { 0x2c0, BIT(14) }, + [RST_BUS_EMAC] = { 0x2c0, BIT(17) }, + [RST_BUS_TS] = { 0x2c0, BIT(18) }, + [RST_BUS_HSTIMER] = { 0x2c0, BIT(19) }, + [RST_BUS_SPI0] = { 0x2c0, BIT(20) }, + [RST_BUS_SPI1] = { 0x2c0, BIT(21) }, + [RST_BUS_OTG] = { 0x2c0, BIT(23) }, + [RST_BUS_EHCI0] = { 0x2c0, BIT(24) }, + [RST_BUS_EHCI1] = { 0x2c0, BIT(25) }, + [RST_BUS_OHCI0] = { 0x2c0, BIT(28) }, + [RST_BUS_OHCI1] = { 0x2c0, BIT(29) }, + + [RST_BUS_VE] = { 0x2c4, BIT(0) }, + [RST_BUS_TCON0] = { 0x2c4, BIT(3) }, + [RST_BUS_TCON1] = { 0x2c4, BIT(4) }, + [RST_BUS_DEINTERLACE] = { 0x2c4, BIT(5) }, + [RST_BUS_CSI] = { 0x2c4, BIT(8) }, + [RST_BUS_HDMI0] = { 0x2c4, BIT(10) }, + [RST_BUS_HDMI1] = { 0x2c4, BIT(11) }, + [RST_BUS_DE] = { 0x2c4, BIT(12) }, + [RST_BUS_GPU] = { 0x2c4, BIT(20) }, + [RST_BUS_MSGBOX] = { 0x2c4, BIT(21) }, + [RST_BUS_SPINLOCK] = { 0x2c4, BIT(22) }, + [RST_BUS_DBG] = { 0x2c4, BIT(31) }, + + [RST_BUS_LVDS] = { 0x2c8, BIT(0) }, + + [RST_BUS_CODEC] = { 0x2d0, BIT(0) }, + [RST_BUS_SPDIF] = { 0x2d0, BIT(1) }, + [RST_BUS_THS] = { 0x2d0, BIT(8) }, + [RST_BUS_I2S0] = { 0x2d0, BIT(12) }, + [RST_BUS_I2S1] = { 0x2d0, BIT(13) }, + [RST_BUS_I2S2] = { 0x2d0, BIT(14) }, + + [RST_BUS_I2C0] = { 0x2d8, BIT(0) }, + [RST_BUS_I2C1] = { 0x2d8, BIT(1) }, + [RST_BUS_I2C2] = { 0x2d8, BIT(2) }, + [RST_BUS_SCR] = { 0x2d8, BIT(5) }, + [RST_BUS_UART0] = { 0x2d8, BIT(16) }, + [RST_BUS_UART1] = { 0x2d8, BIT(17) }, + [RST_BUS_UART2] = { 0x2d8, BIT(18) }, + [RST_BUS_UART3] = { 0x2d8, BIT(19) }, + [RST_BUS_UART4] = { 0x2d8, BIT(20) }, +}; + +static const struct sunxi_ccu_desc sun50i_a64_ccu_desc = { + .ccu_clks = sun50i_a64_ccu_clks, + .num_ccu_clks = ARRAY_SIZE(sun50i_a64_ccu_clks), + + .hw_clks = &sun50i_a64_hw_clks, + + .resets = sun50i_a64_ccu_resets, + .num_resets = ARRAY_SIZE(sun50i_a64_ccu_resets), +}; + +static void __init sun50i_a64_ccu_setup(struct device_node *node) +{ + void __iomem *reg; + u32 val; + + reg = of_io_request_and_map(node, 0, of_node_full_name(node)); + if (IS_ERR(reg)) { + pr_err("%s: Could not map the clock registers\n", + of_node_full_name(node)); + return; + } + + /* Force the PLL-Audio-1x divider to 4 */ + val = readl(reg + SUN50I_A64_PLL_AUDIO_REG); + val &= ~GENMASK(19, 16); + writel(val | (3 << 16), reg + SUN50I_A64_PLL_AUDIO_REG); + + writel(0x515, reg + SUN50I_A64_PLL_MIPI_REG); + + sunxi_ccu_probe(node, reg, &sun50i_a64_ccu_desc); +} +CLK_OF_DECLARE(sun50i_a64_ccu, "allwinner,sun50i-a64-ccu", + sun50i_a64_ccu_setup); diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-a64.h b/drivers/clk/sunxi-ng/ccu-sun50i-a64.h new file mode 100644 index 000000000000..e3c77d92af1c --- /dev/null +++ b/drivers/clk/sunxi-ng/ccu-sun50i-a64.h @@ -0,0 +1,68 @@ +/* + * Copyright 2016 Maxime Ripard + * + * Maxime Ripard <maxime.ripard@free-electrons.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _CCU_SUN50I_A64_H_ +#define _CCU_SUN50I_A64_H_ + +#include <dt-bindings/clock/sun50i-a64-ccu.h> +#include <dt-bindings/reset/sun50i-a64-ccu.h> + +#define CLK_OSC_12M 0 +#define CLK_PLL_CPUX 1 +#define CLK_PLL_AUDIO_BASE 2 +#define CLK_PLL_AUDIO 3 +#define CLK_PLL_AUDIO_2X 4 +#define CLK_PLL_AUDIO_4X 5 +#define CLK_PLL_AUDIO_8X 6 +#define CLK_PLL_VIDEO0 7 +#define CLK_PLL_VIDEO0_2X 8 +#define CLK_PLL_VE 9 +#define CLK_PLL_DDR0 10 +#define CLK_PLL_PERIPH0 11 +#define CLK_PLL_PERIPH0_2X 12 +#define CLK_PLL_PERIPH1 13 +#define CLK_PLL_PERIPH1_2X 14 +#define CLK_PLL_VIDEO1 15 +#define CLK_PLL_GPU 16 +#define CLK_PLL_MIPI 17 +#define CLK_PLL_HSIC 18 +#define CLK_PLL_DE 19 +#define CLK_PLL_DDR1 20 +#define CLK_CPUX 21 +#define CLK_AXI 22 +#define CLK_APB 23 +#define CLK_AHB1 24 +#define CLK_APB1 25 +#define CLK_APB2 26 +#define CLK_AHB2 27 + +/* All the bus gates are exported */ + +/* The first bunch of module clocks are exported */ + +#define CLK_DRAM 92 + +/* All the DRAM gates are exported */ + +/* Some more module clocks are exported */ + +#define CLK_MBUS 110 + +/* And the DSI and GPU module clock is exported */ + +#define CLK_NUMBER (CLK_GPU + 1) + +#endif /* _CCU_SUN50I_A64_H_ */ diff --git a/include/dt-bindings/clock/sun50i-a64-ccu.h b/include/dt-bindings/clock/sun50i-a64-ccu.h new file mode 100644 index 000000000000..2abcd87c7a2d --- /dev/null +++ b/include/dt-bindings/clock/sun50i-a64-ccu.h @@ -0,0 +1,132 @@ +/* + * Copyright (C) 2016 Maxime Ripard <maxime.ripard@free-electrons.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef _DT_BINDINGS_CLK_SUN50I_A64_H_ +#define _DT_BINDINGS_CLK_SUN50I_A64_H_ + +#define CLK_BUS_MIPI_DSI 28 +#define CLK_BUS_CE 29 +#define CLK_BUS_DMA 30 +#define CLK_BUS_MMC0 31 +#define CLK_BUS_MMC1 32 +#define CLK_BUS_MMC2 33 +#define CLK_BUS_NAND 34 +#define CLK_BUS_DRAM 35 +#define CLK_BUS_EMAC 36 +#define CLK_BUS_TS 37 +#define CLK_BUS_HSTIMER 38 +#define CLK_BUS_SPI0 39 +#define CLK_BUS_SPI1 40 +#define CLK_BUS_OTG 41 +#define CLK_BUS_EHCI0 42 +#define CLK_BUS_EHCI1 43 +#define CLK_BUS_OHCI0 44 +#define CLK_BUS_OHCI1 45 +#define CLK_BUS_VE 46 +#define CLK_BUS_TCON0 47 +#define CLK_BUS_TCON1 48 +#define CLK_BUS_DEINTERLACE 49 +#define CLK_BUS_CSI 50 +#define CLK_BUS_HDMI 51 +#define CLK_BUS_DE 52 +#define CLK_BUS_GPU 53 +#define CLK_BUS_MSGBOX 54 +#define CLK_BUS_SPINLOCK 55 +#define CLK_BUS_CODEC 56 +#define CLK_BUS_SPDIF 57 +#define CLK_BUS_PIO 58 +#define CLK_BUS_THS 59 +#define CLK_BUS_I2S0 60 +#define CLK_BUS_I2S1 61 +#define CLK_BUS_I2S2 62 +#define CLK_BUS_I2C0 63 +#define CLK_BUS_I2C1 64 +#define CLK_BUS_I2C2 65 +#define CLK_BUS_SCR 66 +#define CLK_BUS_UART0 67 +#define CLK_BUS_UART1 68 +#define CLK_BUS_UART2 69 +#define CLK_BUS_UART3 70 +#define CLK_BUS_UART4 71 +#define CLK_BUS_DBG 72 +#define CLK_THS 73 +#define CLK_NAND 74 +#define CLK_MMC0 75 +#define CLK_MMC1 76 +#define CLK_MMC2 77 +#define CLK_TS 78 +#define CLK_CE 79 +#define CLK_SPI0 80 +#define CLK_SPI1 81 +#define CLK_I2S0 82 +#define CLK_I2S1 83 +#define CLK_I2S2 84 +#define CLK_SPDIF 85 +#define CLK_USB_PHY0 86 +#define CLK_USB_PHY1 87 +#define CLK_USB_HSIC 88 +#define CLK_USB_HSIC_12M 89 +#define CLK_USB_OHCI0 90 +#define CLK_USB_OHCI1 91 + +#define CLK_DRAM_VE 93 +#define CLK_DRAM_CSI 94 +#define CLK_DRAM_DEINTERLACE 95 +#define CLK_DRAM_TS 96 +#define CLK_DE 97 +#define CLK_TCON0 98 +#define CLK_TCON1 99 +#define CLK_DEINTERLACE 100 +#define CLK_CSI_MISC 101 +#define CLK_CSI_SCLK 102 +#define CLK_CSI_MCLK 103 +#define CLK_VE 104 +#define CLK_AC_DIG 105 +#define CLK_AC_DIG_4X 106 +#define CLK_AVS 107 +#define CLK_HDMI 108 +#define CLK_HDMI_DDC 109 + +#define CLK_DSI_DPHY 111 +#define CLK_GPU 112 + +#endif /* _DT_BINDINGS_CLK_SUN50I_H_ */ diff --git a/include/dt-bindings/reset/sun50i-a64-ccu.h b/include/dt-bindings/reset/sun50i-a64-ccu.h new file mode 100644 index 000000000000..e61fac294d73 --- /dev/null +++ b/include/dt-bindings/reset/sun50i-a64-ccu.h @@ -0,0 +1,97 @@ +/* + * Copyright (C) 2016 Maxime Ripard <maxime.ripard@free-electrons.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef _DT_BINDINGS_RST_SUN50I_A64_H_ +#define _DT_BINDINGS_RST_SUN50I_A64_H_ + +#define RST_USB_PHY0 0 +#define RST_USB_PHY1 1 +#define RST_USB_HSIC 2 +#define RST_MBUS 3 +#define RST_BUS_MIPI_DSI 4 +#define RST_BUS_CE 5 +#define RST_BUS_DMA 6 +#define RST_BUS_MMC0 7 +#define RST_BUS_MMC1 8 +#define RST_BUS_MMC2 9 +#define RST_BUS_NAND 10 +#define RST_BUS_DRAM 11 +#define RST_BUS_EMAC 12 +#define RST_BUS_TS 13 +#define RST_BUS_HSTIMER 14 +#define RST_BUS_SPI0 15 +#define RST_BUS_SPI1 16 +#define RST_BUS_OTG 17 +#define RST_BUS_EHCI0 18 +#define RST_BUS_EHCI1 19 +#define RST_BUS_OHCI0 20 +#define RST_BUS_OHCI1 21 +#define RST_BUS_VE 22 +#define RST_BUS_TCON0 23 +#define RST_BUS_TCON1 24 +#define RST_BUS_DEINTERLACE 25 +#define RST_BUS_CSI 26 +#define RST_BUS_HDMI0 27 +#define RST_BUS_HDMI1 28 +#define RST_BUS_DE 29 +#define RST_BUS_GPU 30 +#define RST_BUS_MSGBOX 31 +#define RST_BUS_SPINLOCK 32 +#define RST_BUS_DBG 33 +#define RST_BUS_LVDS 34 +#define RST_BUS_CODEC 35 +#define RST_BUS_SPDIF 36 +#define RST_BUS_THS 37 +#define RST_BUS_I2S0 38 +#define RST_BUS_I2S1 39 +#define RST_BUS_I2S2 40 +#define RST_BUS_I2C0 41 +#define RST_BUS_I2C1 42 +#define RST_BUS_I2C2 43 +#define RST_BUS_SCR 44 +#define RST_BUS_UART0 45 +#define RST_BUS_UART1 46 +#define RST_BUS_UART2 47 +#define RST_BUS_UART3 48 +#define RST_BUS_UART4 49 + +#endif /* _DT_BINDINGS_RST_SUN8I_H3_H_ */ -- 2.9.3 ^ permalink raw reply related [flat|nested] 35+ messages in thread
* [PATCH v2 1/4] clk: sunxi-ng: Add A64 clocks @ 2016-09-09 20:10 ` Maxime Ripard 0 siblings, 0 replies; 35+ messages in thread From: Maxime Ripard @ 2016-09-09 20:10 UTC (permalink / raw) To: linux-arm-kernel Add the A64 CCU clocks set. Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> --- .../devicetree/bindings/clock/sunxi-ccu.txt | 1 + drivers/clk/sunxi-ng/Kconfig | 11 + drivers/clk/sunxi-ng/Makefile | 1 + drivers/clk/sunxi-ng/ccu-sun50i-a64.c | 870 +++++++++++++++++++++ drivers/clk/sunxi-ng/ccu-sun50i-a64.h | 68 ++ include/dt-bindings/clock/sun50i-a64-ccu.h | 132 ++++ include/dt-bindings/reset/sun50i-a64-ccu.h | 97 +++ 7 files changed, 1180 insertions(+) create mode 100644 drivers/clk/sunxi-ng/ccu-sun50i-a64.c create mode 100644 drivers/clk/sunxi-ng/ccu-sun50i-a64.h create mode 100644 include/dt-bindings/clock/sun50i-a64-ccu.h create mode 100644 include/dt-bindings/reset/sun50i-a64-ccu.h diff --git a/Documentation/devicetree/bindings/clock/sunxi-ccu.txt b/Documentation/devicetree/bindings/clock/sunxi-ccu.txt index 3868458a5feb..74d44a4273f2 100644 --- a/Documentation/devicetree/bindings/clock/sunxi-ccu.txt +++ b/Documentation/devicetree/bindings/clock/sunxi-ccu.txt @@ -7,6 +7,7 @@ Required properties : - "allwinner,sun8i-a23-ccu" - "allwinner,sun8i-a33-ccu" - "allwinner,sun8i-h3-ccu" + - "allwinner,sun50i-a64-ccu" - reg: Must contain the registers base address and length - clocks: phandle to the oscillators feeding the CCU. Two are needed: diff --git a/drivers/clk/sunxi-ng/Kconfig b/drivers/clk/sunxi-ng/Kconfig index 254d9526c018..71e0c21c3545 100644 --- a/drivers/clk/sunxi-ng/Kconfig +++ b/drivers/clk/sunxi-ng/Kconfig @@ -101,4 +101,15 @@ config SUN8I_H3_CCU select SUNXI_CCU_PHASE default MACH_SUN8I +config SUN50I_A64_CCU + bool "Support for the Allwinner A64 CCU" + select SUNXI_CCU_DIV + select SUNXI_CCU_NK + select SUNXI_CCU_NKM + select SUNXI_CCU_NKMP + select SUNXI_CCU_NM + select SUNXI_CCU_MP + select SUNXI_CCU_PHASE + default ARM64 && ARCH_SUNXI + endif diff --git a/drivers/clk/sunxi-ng/Makefile b/drivers/clk/sunxi-ng/Makefile index 106cba27c331..964f22091a10 100644 --- a/drivers/clk/sunxi-ng/Makefile +++ b/drivers/clk/sunxi-ng/Makefile @@ -22,3 +22,4 @@ obj-$(CONFIG_SUN6I_A31_CCU) += ccu-sun6i-a31.o obj-$(CONFIG_SUN8I_A23_CCU) += ccu-sun8i-a23.o obj-$(CONFIG_SUN8I_A33_CCU) += ccu-sun8i-a33.o obj-$(CONFIG_SUN8I_H3_CCU) += ccu-sun8i-h3.o +obj-$(CONFIG_SUN50I_A64_CCU) += ccu-sun50i-a64.o diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c new file mode 100644 index 000000000000..d51ee416f515 --- /dev/null +++ b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c @@ -0,0 +1,870 @@ +/* + * Copyright (c) 2016 Maxime Ripard. All rights reserved. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <linux/clk-provider.h> +#include <linux/of_address.h> + +#include "ccu_common.h" +#include "ccu_reset.h" + +#include "ccu_div.h" +#include "ccu_gate.h" +#include "ccu_mp.h" +#include "ccu_mult.h" +#include "ccu_nk.h" +#include "ccu_nkm.h" +#include "ccu_nkmp.h" +#include "ccu_nm.h" +#include "ccu_phase.h" + +#include "ccu-sun50i-a64.h" + +static SUNXI_CCU_NKMP_WITH_GATE_LOCK(pll_cpux_clk, "pll-cpux", + "osc24M", 0x000, + 8, 5, /* N */ + 4, 2, /* K */ + 0, 2, /* M */ + 16, 2, /* P */ + BIT(31), /* gate */ + BIT(28), /* lock */ + 0); + +/* + * The Audio PLL is supposed to have 4 outputs: 3 fixed factors from + * the base (2x, 4x and 8x), and one variable divider (the one true + * pll audio). + * + * We don't have any need for the variable divider for now, so we just + * hardcode it to match with the clock names + */ +#define SUN50I_A64_PLL_AUDIO_REG 0x008 + +static SUNXI_CCU_NM_WITH_GATE_LOCK(pll_audio_base_clk, "pll-audio-base", + "osc24M", 0x008, + 8, 7, /* N */ + 0, 5, /* M */ + BIT(31), /* gate */ + BIT(28), /* lock */ + 0); + +static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video0_clk, "pll-video0", + "osc24M", 0x010, + 8, 7, /* N */ + 0, 4, /* M */ + BIT(24), /* frac enable */ + BIT(25), /* frac select */ + 270000000, /* frac rate 0 */ + 297000000, /* frac rate 1 */ + BIT(31), /* gate */ + BIT(28), /* lock */ + 0); + +static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_ve_clk, "pll-ve", + "osc24M", 0x018, + 8, 7, /* N */ + 0, 4, /* M */ + BIT(24), /* frac enable */ + BIT(25), /* frac select */ + 270000000, /* frac rate 0 */ + 297000000, /* frac rate 1 */ + BIT(31), /* gate */ + BIT(28), /* lock */ + 0); + +static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_ddr0_clk, "pll-ddr0", + "osc24M", 0x020, + 8, 5, /* N */ + 4, 2, /* K */ + 0, 2, /* M */ + BIT(31), /* gate */ + BIT(28), /* lock */ + 0); + +static SUNXI_CCU_NK_WITH_GATE_LOCK_POSTDIV(pll_periph0_clk, "pll-periph0", + "osc24M", 0x028, + 8, 5, /* N */ + 4, 2, /* K */ + BIT(31), /* gate */ + BIT(28), /* lock */ + 2, /* post-div */ + 0); + +static SUNXI_CCU_NK_WITH_GATE_LOCK_POSTDIV(pll_periph1_clk, "pll-periph1", + "osc24M", 0x02c, + 8, 5, /* N */ + 4, 2, /* K */ + BIT(31), /* gate */ + BIT(28), /* lock */ + 2, /* post-div */ + 0); + +static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video1_clk, "pll-video1", + "osc24M", 0x030, + 8, 7, /* N */ + 0, 4, /* M */ + BIT(24), /* frac enable */ + BIT(25), /* frac select */ + 270000000, /* frac rate 0 */ + 297000000, /* frac rate 1 */ + BIT(31), /* gate */ + BIT(28), /* lock */ + 0); + +static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_gpu_clk, "pll-gpu", + "osc24M", 0x038, + 8, 7, /* N */ + 0, 4, /* M */ + BIT(24), /* frac enable */ + BIT(25), /* frac select */ + 270000000, /* frac rate 0 */ + 297000000, /* frac rate 1 */ + BIT(31), /* gate */ + BIT(28), /* lock */ + 0); + +/* + * The output function can be changed to something more complex that + * we do not handle yet. + * + * Hardcode the mode so that we don't fall in that case. + */ +#define SUN50I_A64_PLL_MIPI_REG 0x040 + +static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_mipi_clk, "pll-mipi", + "pll-video0", 0x040, + 8, 4, /* N */ + 4, 2, /* K */ + 0, 4, /* M */ + BIT(31), /* gate */ + BIT(28), /* lock */ + 0); + +static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_hsic_clk, "pll-hsic", + "osc24M", 0x044, + 8, 7, /* N */ + 0, 4, /* M */ + BIT(24), /* frac enable */ + BIT(25), /* frac select */ + 270000000, /* frac rate 0 */ + 297000000, /* frac rate 1 */ + BIT(31), /* gate */ + BIT(28), /* lock */ + 0); + +static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_de_clk, "pll-de", + "osc24M", 0x048, + 8, 7, /* N */ + 0, 4, /* M */ + BIT(24), /* frac enable */ + BIT(25), /* frac select */ + 270000000, /* frac rate 0 */ + 297000000, /* frac rate 1 */ + BIT(31), /* gate */ + BIT(28), /* lock */ + 0); + +static SUNXI_CCU_NM_WITH_GATE_LOCK(pll_ddr1_clk, "pll-ddr1", + "osc24M", 0x04c, + 8, 7, /* N */ + 0, 2, /* M */ + BIT(31), /* gate */ + BIT(28), /* lock */ + 0); + +static const char * const cpux_parents[] = { "osc32k", "osc24M", + "pll-cpux" , "pll-cpux" }; +static SUNXI_CCU_MUX(cpux_clk, "cpux", cpux_parents, + 0x050, 16, 2, CLK_IS_CRITICAL); + +static SUNXI_CCU_M(axi_clk, "axi", "cpux", 0x050, 0, 2, 0); + +static const char * const ahb1_parents[] = { "osc32k", "osc24M", + "axi" , "pll-periph0" }; +static struct ccu_div ahb1_clk = { + .div = _SUNXI_CCU_DIV_FLAGS(4, 2, CLK_DIVIDER_POWER_OF_TWO), + + .mux = { + .shift = 12, + .width = 2, + + .variable_prediv = { + .index = 3, + .shift = 6, + .width = 2, + }, + }, + + .common = { + .reg = 0x054, + .features = CCU_FEATURE_VARIABLE_PREDIV, + .hw.init = CLK_HW_INIT_PARENTS("ahb1", + ahb1_parents, + &ccu_div_ops, + 0), + }, +}; + +static struct clk_div_table apb1_div_table[] = { + { .val = 0, .div = 2 }, + { .val = 1, .div = 2 }, + { .val = 2, .div = 4 }, + { .val = 3, .div = 8 }, + { /* Sentinel */ }, +}; +static SUNXI_CCU_DIV_TABLE(apb1_clk, "apb1", "ahb1", + 0x054, 8, 2, apb1_div_table, 0); + +static const char * const apb2_parents[] = { "osc32k", "osc24M", + "pll-periph0-2x" , + "pll-periph0-2x" }; +static SUNXI_CCU_MP_WITH_MUX(apb2_clk, "apb2", apb2_parents, 0x058, + 0, 5, /* M */ + 16, 2, /* P */ + 24, 2, /* mux */ + 0); + +static const char * const ahb2_parents[] = { "ahb1" , "pll-periph0" }; +static const struct ccu_mux_fixed_prediv ahb2_fixed_predivs[] = { + { .index = 1, .div = 2 }, +}; +static struct ccu_mux ahb2_clk = { + .mux = { + .shift = 0, + .width = 1, + .fixed_predivs = ahb2_fixed_predivs, + .n_predivs = ARRAY_SIZE(ahb2_fixed_predivs), + }, + + .common = { + .reg = 0x05c, + .features = CCU_FEATURE_FIXED_PREDIV, + .hw.init = CLK_HW_INIT_PARENTS("ahb2", + ahb2_parents, + &ccu_mux_ops, + 0), + }, +}; + +static SUNXI_CCU_GATE(bus_mipi_dsi_clk, "bus-mipi-dsi", "ahb1", + 0x060, BIT(1), 0); +static SUNXI_CCU_GATE(bus_ce_clk, "bus-ce", "ahb1", + 0x060, BIT(5), 0); +static SUNXI_CCU_GATE(bus_dma_clk, "bus-dma", "ahb1", + 0x060, BIT(6), 0); +static SUNXI_CCU_GATE(bus_mmc0_clk, "bus-mmc0", "ahb1", + 0x060, BIT(8), 0); +static SUNXI_CCU_GATE(bus_mmc1_clk, "bus-mmc1", "ahb1", + 0x060, BIT(9), 0); +static SUNXI_CCU_GATE(bus_mmc2_clk, "bus-mmc2", "ahb1", + 0x060, BIT(10), 0); +static SUNXI_CCU_GATE(bus_nand_clk, "bus-nand", "ahb1", + 0x060, BIT(13), 0); +static SUNXI_CCU_GATE(bus_dram_clk, "bus-dram", "ahb1", + 0x060, BIT(14), 0); +static SUNXI_CCU_GATE(bus_emac_clk, "bus-emac", "ahb2", + 0x060, BIT(17), 0); +static SUNXI_CCU_GATE(bus_ts_clk, "bus-ts", "ahb1", + 0x060, BIT(18), 0); +static SUNXI_CCU_GATE(bus_hstimer_clk, "bus-hstimer", "ahb1", + 0x060, BIT(19), 0); +static SUNXI_CCU_GATE(bus_spi0_clk, "bus-spi0", "ahb1", + 0x060, BIT(20), 0); +static SUNXI_CCU_GATE(bus_spi1_clk, "bus-spi1", "ahb1", + 0x060, BIT(21), 0); +static SUNXI_CCU_GATE(bus_otg_clk, "bus-otg", "ahb1", + 0x060, BIT(23), 0); +static SUNXI_CCU_GATE(bus_ehci0_clk, "bus-ehci0", "ahb1", + 0x060, BIT(24), 0); +static SUNXI_CCU_GATE(bus_ehci1_clk, "bus-ehci1", "ahb2", + 0x060, BIT(25), 0); +static SUNXI_CCU_GATE(bus_ohci0_clk, "bus-ohci0", "ahb1", + 0x060, BIT(28), 0); +static SUNXI_CCU_GATE(bus_ohci1_clk, "bus-ohci1", "ahb2", + 0x060, BIT(29), 0); + +static SUNXI_CCU_GATE(bus_ve_clk, "bus-ve", "ahb1", + 0x064, BIT(0), 0); +static SUNXI_CCU_GATE(bus_tcon0_clk, "bus-tcon0", "ahb1", + 0x064, BIT(3), 0); +static SUNXI_CCU_GATE(bus_tcon1_clk, "bus-tcon1", "ahb1", + 0x064, BIT(4), 0); +static SUNXI_CCU_GATE(bus_deinterlace_clk, "bus-deinterlace", "ahb1", + 0x064, BIT(5), 0); +static SUNXI_CCU_GATE(bus_csi_clk, "bus-csi", "ahb1", + 0x064, BIT(8), 0); +static SUNXI_CCU_GATE(bus_hdmi_clk, "bus-hdmi", "ahb1", + 0x064, BIT(11), 0); +static SUNXI_CCU_GATE(bus_de_clk, "bus-de", "ahb1", + 0x064, BIT(12), 0); +static SUNXI_CCU_GATE(bus_gpu_clk, "bus-gpu", "ahb1", + 0x064, BIT(20), 0); +static SUNXI_CCU_GATE(bus_msgbox_clk, "bus-msgbox", "ahb1", + 0x064, BIT(21), 0); +static SUNXI_CCU_GATE(bus_spinlock_clk, "bus-spinlock", "ahb1", + 0x064, BIT(22), 0); + +static SUNXI_CCU_GATE(bus_codec_clk, "bus-codec", "apb1", + 0x068, BIT(0), 0); +static SUNXI_CCU_GATE(bus_spdif_clk, "bus-spdif", "apb1", + 0x068, BIT(1), 0); +static SUNXI_CCU_GATE(bus_pio_clk, "bus-pio", "apb1", + 0x068, BIT(5), 0); +static SUNXI_CCU_GATE(bus_ths_clk, "bus-ths", "apb1", + 0x068, BIT(8), 0); +static SUNXI_CCU_GATE(bus_i2s0_clk, "bus-i2s0", "apb1", + 0x068, BIT(12), 0); +static SUNXI_CCU_GATE(bus_i2s1_clk, "bus-i2s1", "apb1", + 0x068, BIT(13), 0); +static SUNXI_CCU_GATE(bus_i2s2_clk, "bus-i2s2", "apb1", + 0x068, BIT(14), 0); + +static SUNXI_CCU_GATE(bus_i2c0_clk, "bus-i2c0", "apb2", + 0x06c, BIT(0), 0); +static SUNXI_CCU_GATE(bus_i2c1_clk, "bus-i2c1", "apb2", + 0x06c, BIT(1), 0); +static SUNXI_CCU_GATE(bus_i2c2_clk, "bus-i2c2", "apb2", + 0x06c, BIT(2), 0); +static SUNXI_CCU_GATE(bus_scr_clk, "bus-scr", "apb2", + 0x06c, BIT(5), 0); +static SUNXI_CCU_GATE(bus_uart0_clk, "bus-uart0", "apb2", + 0x06c, BIT(16), 0); +static SUNXI_CCU_GATE(bus_uart1_clk, "bus-uart1", "apb2", + 0x06c, BIT(17), 0); +static SUNXI_CCU_GATE(bus_uart2_clk, "bus-uart2", "apb2", + 0x06c, BIT(18), 0); +static SUNXI_CCU_GATE(bus_uart3_clk, "bus-uart3", "apb2", + 0x06c, BIT(19), 0); +static SUNXI_CCU_GATE(bus_uart4_clk, "bus-uart4", "apb2", + 0x06c, BIT(20), 0); + +static SUNXI_CCU_GATE(bus_dbg_clk, "bus-dbg", "ahb1", + 0x070, BIT(7), 0); + +static struct clk_div_table ths_div_table[] = { + { .val = 0, .div = 1 }, + { .val = 1, .div = 2 }, + { .val = 2, .div = 4 }, + { .val = 3, .div = 6 }, +}; +static SUNXI_CCU_DIV_TABLE_WITH_GATE(ths_clk, "ths", "osc24M", + 0x074, 0, 2, ths_div_table, BIT(31), 0); + +static const char * const mod0_default_parents[] = { "osc24M", "pll-periph0", + "pll-periph1" }; +static SUNXI_CCU_MP_WITH_MUX_GATE(nand_clk, "nand", mod0_default_parents, 0x080, + 0, 4, /* M */ + 16, 2, /* P */ + 24, 2, /* mux */ + BIT(31), /* gate */ + 0); + +static const char * const mmc_default_parents[] = { "osc24M", "pll-periph0-2x", + "pll-periph1-2x" }; +static SUNXI_CCU_MP_WITH_MUX_GATE(mmc0_clk, "mmc0", mmc_default_parents, 0x088, + 0, 4, /* M */ + 16, 2, /* P */ + 24, 2, /* mux */ + BIT(31), /* gate */ + 0); + +static SUNXI_CCU_MP_WITH_MUX_GATE(mmc1_clk, "mmc1", mmc_default_parents, 0x08c, + 0, 4, /* M */ + 16, 2, /* P */ + 24, 2, /* mux */ + BIT(31), /* gate */ + 0); + +static SUNXI_CCU_MP_WITH_MUX_GATE(mmc2_clk, "mmc2", mmc_default_parents, 0x090, + 0, 4, /* M */ + 16, 2, /* P */ + 24, 2, /* mux */ + BIT(31), /* gate */ + 0); + +static const char * const ts_parents[] = { "osc24M", "pll-periph0", }; +static SUNXI_CCU_MP_WITH_MUX_GATE(ts_clk, "ts", ts_parents, 0x098, + 0, 4, /* M */ + 16, 2, /* P */ + 24, 2, /* mux */ + BIT(31), /* gate */ + 0); + +static SUNXI_CCU_MP_WITH_MUX_GATE(ce_clk, "ce", mmc_default_parents, 0x09c, + 0, 4, /* M */ + 16, 2, /* P */ + 24, 2, /* mux */ + BIT(31), /* gate */ + 0); + + +static SUNXI_CCU_MP_WITH_MUX_GATE(spi0_clk, "spi0", mod0_default_parents, 0x0a0, + 0, 4, /* M */ + 16, 2, /* P */ + 24, 2, /* mux */ + BIT(31), /* gate */ + 0); + +static SUNXI_CCU_MP_WITH_MUX_GATE(spi1_clk, "spi1", mod0_default_parents, 0x0a4, + 0, 4, /* M */ + 16, 2, /* P */ + 24, 2, /* mux */ + BIT(31), /* gate */ + 0); + +static const char * const i2s_parents[] = { "pll-audio-8x", "pll-audio-4x", + "pll-audio-2x", "pll-audio" }; +static SUNXI_CCU_MUX_WITH_GATE(i2s0_clk, "i2s0", i2s_parents, + 0x0b0, 16, 2, BIT(31), 0); + +static SUNXI_CCU_MUX_WITH_GATE(i2s1_clk, "i2s1", i2s_parents, + 0x0b4, 16, 2, BIT(31), 0); + +static SUNXI_CCU_MUX_WITH_GATE(i2s2_clk, "i2s2", i2s_parents, + 0x0b8, 16, 2, BIT(31), 0); + +static SUNXI_CCU_M_WITH_GATE(spdif_clk, "spdif", "pll-audio", + 0x0c0, 0, 4, BIT(31), 0); + +static SUNXI_CCU_GATE(usb_phy0_clk, "usb-phy0", "osc24M", + 0x0cc, BIT(8), 0); +static SUNXI_CCU_GATE(usb_phy1_clk, "usb-phy1", "osc24M", + 0x0cc, BIT(9), 0); +static SUNXI_CCU_GATE(usb_hsic_clk, "usb-hsic", "pll-hsic", + 0x0cc, BIT(10), 0); +static SUNXI_CCU_GATE(usb_hsic_12m_clk, "usb-hsic-12M", "osc12M", + 0x0cc, BIT(11), 0); +static SUNXI_CCU_GATE(usb_ohci0_clk, "usb-ohci0", "osc12M", + 0x0cc, BIT(16), 0); +static SUNXI_CCU_GATE(usb_ohci1_clk, "usb-ohci1", "usb-ohci0", + 0x0cc, BIT(17), 0); + +static const char * const dram_parents[] = { "pll-ddr0", "pll-ddr1" }; +static SUNXI_CCU_M_WITH_MUX(dram_clk, "dram", dram_parents, + 0x0f4, 0, 4, 20, 2, CLK_IS_CRITICAL); + +static SUNXI_CCU_GATE(dram_ve_clk, "dram-ve", "dram", + 0x100, BIT(0), 0); +static SUNXI_CCU_GATE(dram_csi_clk, "dram-csi", "dram", + 0x100, BIT(1), 0); +static SUNXI_CCU_GATE(dram_deinterlace_clk, "dram-deinterlace", "dram", + 0x100, BIT(2), 0); +static SUNXI_CCU_GATE(dram_ts_clk, "dram-ts", "dram", + 0x100, BIT(3), 0); + +static const char * const de_parents[] = { "pll-periph0-2x", "pll-de" }; +static SUNXI_CCU_M_WITH_MUX_GATE(de_clk, "de", de_parents, + 0x104, 0, 4, 24, 3, BIT(31), 0); + +static const char * const tcon0_parents[] = { "pll-mipi", "pll-video0-2x" }; +static const u8 tcon0_table[] = { 0, 2, }; +static SUNXI_CCU_MUX_TABLE_WITH_GATE(tcon0_clk, "tcon0", tcon0_parents, + tcon0_table, 0x118, 24, 3, BIT(31), 0); + +static const char * const tcon1_parents[] = { "pll-video0", "pll-video1" }; +static const u8 tcon1_table[] = { 0, 2, }; +struct ccu_div tcon1_clk = { + .enable = BIT(31), + .div = _SUNXI_CCU_DIV(0, 4), + .mux = _SUNXI_CCU_MUX_TABLE(24, 3, tcon1_table), + .common = { + .reg = 0x11c, + .hw.init = CLK_HW_INIT_PARENTS("tcon1", + tcon1_parents, + &ccu_div_ops, + 0), + }, +}; + +static const char * const deinterlace_parents[] = { "pll-periph0", "pll-periph1" }; +static SUNXI_CCU_M_WITH_MUX_GATE(deinterlace_clk, "deinterlace", deinterlace_parents, + 0x124, 0, 4, 24, 3, BIT(31), 0); + +static SUNXI_CCU_GATE(csi_misc_clk, "csi-misc", "osc24M", + 0x130, BIT(31), 0); + +static const char * const csi_sclk_parents[] = { "pll-periph0", "pll-periph1" }; +static SUNXI_CCU_M_WITH_MUX_GATE(csi_sclk_clk, "csi-sclk", csi_sclk_parents, + 0x134, 16, 4, 24, 3, BIT(31), 0); + +static const char * const csi_mclk_parents[] = { "osc24M", "pll-video1", "pll-periph1" }; +static SUNXI_CCU_M_WITH_MUX_GATE(csi_mclk_clk, "csi-mclk", csi_mclk_parents, + 0x134, 0, 5, 8, 3, BIT(15), 0); + +static SUNXI_CCU_M_WITH_GATE(ve_clk, "ve", "pll-ve", + 0x13c, 16, 3, BIT(31), 0); + +static SUNXI_CCU_GATE(ac_dig_clk, "ac-dig", "pll-audio", + 0x140, BIT(31), 0); + +static SUNXI_CCU_GATE(ac_dig_4x_clk, "ac-dig-4x", "pll-audio-4x", + 0x140, BIT(30), 0); + +static SUNXI_CCU_GATE(avs_clk, "avs", "osc24M", + 0x144, BIT(31), 0); + +static const char * const hdmi_parents[] = { "pll-video0", "pll-video1" }; +static SUNXI_CCU_M_WITH_MUX_GATE(hdmi_clk, "hdmi", hdmi_parents, + 0x150, 0, 4, 24, 2, BIT(31), 0); + +static SUNXI_CCU_GATE(hdmi_ddc_clk, "hdmi-ddc", "osc24M", + 0x154, BIT(31), 0); + +static const char * const mbus_parents[] = { "osc24M", "pll-periph0-2x", + "pll-ddr0", "pll-ddr1" }; +static SUNXI_CCU_M_WITH_MUX_GATE(mbus_clk, "mbus", mbus_parents, + 0x15c, 0, 3, 24, 2, BIT(31), CLK_IS_CRITICAL); + +static const char * const dsi_dphy_parents[] = { "pll-video0", "pll-periph0" }; +static SUNXI_CCU_M_WITH_MUX_GATE(dsi_dphy_clk, "dsi-dphy", dsi_dphy_parents, + 0x168, 0, 3, 24, 2, BIT(31), 0); + +static SUNXI_CCU_M_WITH_GATE(gpu_clk, "gpu", "pll-gpu", + 0x1a0, 0, 3, BIT(31), 0); + +/* Fixed Factor clocks */ +static CLK_FIXED_FACTOR(osc12M_clk, "osc12M", "osc24M", 1, 2, 0); + +/* We hardcode the divider to 4 for now */ +static CLK_FIXED_FACTOR(pll_audio_clk, "pll-audio", + "pll-audio-base", 4, 1, CLK_SET_RATE_PARENT); +static CLK_FIXED_FACTOR(pll_audio_2x_clk, "pll-audio-2x", + "pll-audio-base", 2, 1, CLK_SET_RATE_PARENT); +static CLK_FIXED_FACTOR(pll_audio_4x_clk, "pll-audio-4x", + "pll-audio-base", 1, 1, CLK_SET_RATE_PARENT); +static CLK_FIXED_FACTOR(pll_audio_8x_clk, "pll-audio-8x", + "pll-audio-base", 1, 2, CLK_SET_RATE_PARENT); +static CLK_FIXED_FACTOR(pll_periph0_2x_clk, "pll-periph0-2x", + "pll-periph0", 1, 2, 0); +static CLK_FIXED_FACTOR(pll_periph1_2x_clk, "pll-periph1-2x", + "pll-periph1", 1, 2, 0); +static CLK_FIXED_FACTOR(pll_video0_2x_clk, "pll-video0-2x", + "pll-video0", 1, 2, 0); + +static struct ccu_common *sun50i_a64_ccu_clks[] = { + &pll_cpux_clk.common, + &pll_audio_base_clk.common, + &pll_video0_clk.common, + &pll_ve_clk.common, + &pll_ddr0_clk.common, + &pll_periph0_clk.common, + &pll_periph1_clk.common, + &pll_video1_clk.common, + &pll_gpu_clk.common, + &pll_mipi_clk.common, + &pll_hsic_clk.common, + &pll_de_clk.common, + &pll_ddr1_clk.common, + &cpux_clk.common, + &axi_clk.common, + &ahb1_clk.common, + &apb1_clk.common, + &apb2_clk.common, + &ahb2_clk.common, + &bus_mipi_dsi_clk.common, + &bus_ce_clk.common, + &bus_dma_clk.common, + &bus_mmc0_clk.common, + &bus_mmc1_clk.common, + &bus_mmc2_clk.common, + &bus_nand_clk.common, + &bus_dram_clk.common, + &bus_emac_clk.common, + &bus_ts_clk.common, + &bus_hstimer_clk.common, + &bus_spi0_clk.common, + &bus_spi1_clk.common, + &bus_otg_clk.common, + &bus_ehci0_clk.common, + &bus_ehci1_clk.common, + &bus_ohci0_clk.common, + &bus_ohci1_clk.common, + &bus_ve_clk.common, + &bus_tcon0_clk.common, + &bus_tcon1_clk.common, + &bus_deinterlace_clk.common, + &bus_csi_clk.common, + &bus_hdmi_clk.common, + &bus_de_clk.common, + &bus_gpu_clk.common, + &bus_msgbox_clk.common, + &bus_spinlock_clk.common, + &bus_codec_clk.common, + &bus_spdif_clk.common, + &bus_pio_clk.common, + &bus_ths_clk.common, + &bus_i2s0_clk.common, + &bus_i2s1_clk.common, + &bus_i2s2_clk.common, + &bus_i2c0_clk.common, + &bus_i2c1_clk.common, + &bus_i2c2_clk.common, + &bus_scr_clk.common, + &bus_uart0_clk.common, + &bus_uart1_clk.common, + &bus_uart2_clk.common, + &bus_uart3_clk.common, + &bus_uart4_clk.common, + &bus_dbg_clk.common, + &ths_clk.common, + &nand_clk.common, + &mmc0_clk.common, + &mmc1_clk.common, + &mmc2_clk.common, + &ts_clk.common, + &ce_clk.common, + &spi0_clk.common, + &spi1_clk.common, + &i2s0_clk.common, + &i2s1_clk.common, + &i2s2_clk.common, + &spdif_clk.common, + &usb_phy0_clk.common, + &usb_phy1_clk.common, + &usb_hsic_clk.common, + &usb_hsic_12m_clk.common, + &usb_ohci0_clk.common, + &usb_ohci1_clk.common, + &dram_clk.common, + &dram_ve_clk.common, + &dram_csi_clk.common, + &dram_deinterlace_clk.common, + &dram_ts_clk.common, + &de_clk.common, + &tcon0_clk.common, + &tcon1_clk.common, + &deinterlace_clk.common, + &csi_misc_clk.common, + &csi_sclk_clk.common, + &csi_mclk_clk.common, + &ve_clk.common, + &ac_dig_clk.common, + &ac_dig_4x_clk.common, + &avs_clk.common, + &hdmi_clk.common, + &hdmi_ddc_clk.common, + &mbus_clk.common, + &dsi_dphy_clk.common, + &gpu_clk.common, +}; + +static struct clk_hw_onecell_data sun50i_a64_hw_clks = { + .hws = { + [CLK_OSC_12M] = &osc12M_clk.hw, + [CLK_PLL_CPUX] = &pll_cpux_clk.common.hw, + [CLK_PLL_AUDIO_BASE] = &pll_audio_base_clk.common.hw, + [CLK_PLL_AUDIO] = &pll_audio_clk.hw, + [CLK_PLL_AUDIO_2X] = &pll_audio_2x_clk.hw, + [CLK_PLL_AUDIO_4X] = &pll_audio_4x_clk.hw, + [CLK_PLL_AUDIO_8X] = &pll_audio_8x_clk.hw, + [CLK_PLL_VIDEO0] = &pll_video0_clk.common.hw, + [CLK_PLL_VIDEO0_2X] = &pll_video0_2x_clk.hw, + [CLK_PLL_VE] = &pll_ve_clk.common.hw, + [CLK_PLL_DDR0] = &pll_ddr0_clk.common.hw, + [CLK_PLL_PERIPH0] = &pll_periph0_clk.common.hw, + [CLK_PLL_PERIPH0_2X] = &pll_periph0_2x_clk.hw, + [CLK_PLL_PERIPH1] = &pll_periph1_clk.common.hw, + [CLK_PLL_PERIPH1_2X] = &pll_periph1_2x_clk.hw, + [CLK_PLL_VIDEO1] = &pll_video1_clk.common.hw, + [CLK_PLL_GPU] = &pll_gpu_clk.common.hw, + [CLK_PLL_MIPI] = &pll_mipi_clk.common.hw, + [CLK_PLL_HSIC] = &pll_hsic_clk.common.hw, + [CLK_PLL_DE] = &pll_de_clk.common.hw, + [CLK_PLL_DDR1] = &pll_ddr1_clk.common.hw, + [CLK_CPUX] = &cpux_clk.common.hw, + [CLK_AXI] = &axi_clk.common.hw, + [CLK_AHB1] = &ahb1_clk.common.hw, + [CLK_APB1] = &apb1_clk.common.hw, + [CLK_APB2] = &apb2_clk.common.hw, + [CLK_AHB2] = &ahb2_clk.common.hw, + [CLK_BUS_MIPI_DSI] = &bus_mipi_dsi_clk.common.hw, + [CLK_BUS_CE] = &bus_ce_clk.common.hw, + [CLK_BUS_DMA] = &bus_dma_clk.common.hw, + [CLK_BUS_MMC0] = &bus_mmc0_clk.common.hw, + [CLK_BUS_MMC1] = &bus_mmc1_clk.common.hw, + [CLK_BUS_MMC2] = &bus_mmc2_clk.common.hw, + [CLK_BUS_NAND] = &bus_nand_clk.common.hw, + [CLK_BUS_DRAM] = &bus_dram_clk.common.hw, + [CLK_BUS_EMAC] = &bus_emac_clk.common.hw, + [CLK_BUS_TS] = &bus_ts_clk.common.hw, + [CLK_BUS_HSTIMER] = &bus_hstimer_clk.common.hw, + [CLK_BUS_SPI0] = &bus_spi0_clk.common.hw, + [CLK_BUS_SPI1] = &bus_spi1_clk.common.hw, + [CLK_BUS_OTG] = &bus_otg_clk.common.hw, + [CLK_BUS_EHCI0] = &bus_ehci0_clk.common.hw, + [CLK_BUS_EHCI1] = &bus_ehci1_clk.common.hw, + [CLK_BUS_OHCI0] = &bus_ohci0_clk.common.hw, + [CLK_BUS_OHCI1] = &bus_ohci1_clk.common.hw, + [CLK_BUS_VE] = &bus_ve_clk.common.hw, + [CLK_BUS_TCON0] = &bus_tcon0_clk.common.hw, + [CLK_BUS_TCON1] = &bus_tcon1_clk.common.hw, + [CLK_BUS_DEINTERLACE] = &bus_deinterlace_clk.common.hw, + [CLK_BUS_CSI] = &bus_csi_clk.common.hw, + [CLK_BUS_HDMI] = &bus_hdmi_clk.common.hw, + [CLK_BUS_DE] = &bus_de_clk.common.hw, + [CLK_BUS_GPU] = &bus_gpu_clk.common.hw, + [CLK_BUS_MSGBOX] = &bus_msgbox_clk.common.hw, + [CLK_BUS_SPINLOCK] = &bus_spinlock_clk.common.hw, + [CLK_BUS_CODEC] = &bus_codec_clk.common.hw, + [CLK_BUS_SPDIF] = &bus_spdif_clk.common.hw, + [CLK_BUS_PIO] = &bus_pio_clk.common.hw, + [CLK_BUS_THS] = &bus_ths_clk.common.hw, + [CLK_BUS_I2S0] = &bus_i2s0_clk.common.hw, + [CLK_BUS_I2S1] = &bus_i2s1_clk.common.hw, + [CLK_BUS_I2S2] = &bus_i2s2_clk.common.hw, + [CLK_BUS_I2C0] = &bus_i2c0_clk.common.hw, + [CLK_BUS_I2C1] = &bus_i2c1_clk.common.hw, + [CLK_BUS_I2C2] = &bus_i2c2_clk.common.hw, + [CLK_BUS_UART0] = &bus_uart0_clk.common.hw, + [CLK_BUS_UART1] = &bus_uart1_clk.common.hw, + [CLK_BUS_UART2] = &bus_uart2_clk.common.hw, + [CLK_BUS_UART3] = &bus_uart3_clk.common.hw, + [CLK_BUS_UART4] = &bus_uart4_clk.common.hw, + [CLK_BUS_SCR] = &bus_scr_clk.common.hw, + [CLK_BUS_DBG] = &bus_dbg_clk.common.hw, + [CLK_THS] = &ths_clk.common.hw, + [CLK_NAND] = &nand_clk.common.hw, + [CLK_MMC0] = &mmc0_clk.common.hw, + [CLK_MMC1] = &mmc1_clk.common.hw, + [CLK_MMC2] = &mmc2_clk.common.hw, + [CLK_TS] = &ts_clk.common.hw, + [CLK_CE] = &ce_clk.common.hw, + [CLK_SPI0] = &spi0_clk.common.hw, + [CLK_SPI1] = &spi1_clk.common.hw, + [CLK_I2S0] = &i2s0_clk.common.hw, + [CLK_I2S1] = &i2s1_clk.common.hw, + [CLK_I2S2] = &i2s2_clk.common.hw, + [CLK_SPDIF] = &spdif_clk.common.hw, + [CLK_USB_PHY0] = &usb_phy0_clk.common.hw, + [CLK_USB_PHY1] = &usb_phy1_clk.common.hw, + [CLK_USB_HSIC] = &usb_hsic_clk.common.hw, + [CLK_USB_HSIC_12M] = &usb_hsic_12m_clk.common.hw, + [CLK_USB_OHCI0] = &usb_ohci0_clk.common.hw, + [CLK_USB_OHCI1] = &usb_ohci1_clk.common.hw, + [CLK_DRAM] = &dram_clk.common.hw, + [CLK_DRAM_VE] = &dram_ve_clk.common.hw, + [CLK_DRAM_CSI] = &dram_csi_clk.common.hw, + [CLK_DRAM_DEINTERLACE] = &dram_deinterlace_clk.common.hw, + [CLK_DRAM_TS] = &dram_ts_clk.common.hw, + [CLK_DE] = &de_clk.common.hw, + [CLK_TCON0] = &tcon0_clk.common.hw, + [CLK_TCON1] = &tcon1_clk.common.hw, + [CLK_DEINTERLACE] = &deinterlace_clk.common.hw, + [CLK_CSI_MISC] = &csi_misc_clk.common.hw, + [CLK_CSI_SCLK] = &csi_sclk_clk.common.hw, + [CLK_CSI_MCLK] = &csi_mclk_clk.common.hw, + [CLK_VE] = &ve_clk.common.hw, + [CLK_AC_DIG] = &ac_dig_clk.common.hw, + [CLK_AC_DIG_4X] = &ac_dig_4x_clk.common.hw, + [CLK_AVS] = &avs_clk.common.hw, + [CLK_HDMI] = &hdmi_clk.common.hw, + [CLK_HDMI_DDC] = &hdmi_ddc_clk.common.hw, + [CLK_MBUS] = &mbus_clk.common.hw, + [CLK_DSI_DPHY] = &dsi_dphy_clk.common.hw, + [CLK_GPU] = &gpu_clk.common.hw, + }, + .num = CLK_NUMBER, +}; + +static struct ccu_reset_map sun50i_a64_ccu_resets[] = { + [RST_USB_PHY0] = { 0x0cc, BIT(0) }, + [RST_USB_PHY1] = { 0x0cc, BIT(1) }, + [RST_USB_HSIC] = { 0x0cc, BIT(2) }, + + + [RST_MBUS] = { 0x0fc, BIT(31) }, + + [RST_BUS_MIPI_DSI] = { 0x2c0, BIT(1) }, + [RST_BUS_CE] = { 0x2c0, BIT(5) }, + [RST_BUS_DMA] = { 0x2c0, BIT(6) }, + [RST_BUS_MMC0] = { 0x2c0, BIT(8) }, + [RST_BUS_MMC1] = { 0x2c0, BIT(9) }, + [RST_BUS_MMC2] = { 0x2c0, BIT(10) }, + [RST_BUS_NAND] = { 0x2c0, BIT(13) }, + [RST_BUS_DRAM] = { 0x2c0, BIT(14) }, + [RST_BUS_EMAC] = { 0x2c0, BIT(17) }, + [RST_BUS_TS] = { 0x2c0, BIT(18) }, + [RST_BUS_HSTIMER] = { 0x2c0, BIT(19) }, + [RST_BUS_SPI0] = { 0x2c0, BIT(20) }, + [RST_BUS_SPI1] = { 0x2c0, BIT(21) }, + [RST_BUS_OTG] = { 0x2c0, BIT(23) }, + [RST_BUS_EHCI0] = { 0x2c0, BIT(24) }, + [RST_BUS_EHCI1] = { 0x2c0, BIT(25) }, + [RST_BUS_OHCI0] = { 0x2c0, BIT(28) }, + [RST_BUS_OHCI1] = { 0x2c0, BIT(29) }, + + [RST_BUS_VE] = { 0x2c4, BIT(0) }, + [RST_BUS_TCON0] = { 0x2c4, BIT(3) }, + [RST_BUS_TCON1] = { 0x2c4, BIT(4) }, + [RST_BUS_DEINTERLACE] = { 0x2c4, BIT(5) }, + [RST_BUS_CSI] = { 0x2c4, BIT(8) }, + [RST_BUS_HDMI0] = { 0x2c4, BIT(10) }, + [RST_BUS_HDMI1] = { 0x2c4, BIT(11) }, + [RST_BUS_DE] = { 0x2c4, BIT(12) }, + [RST_BUS_GPU] = { 0x2c4, BIT(20) }, + [RST_BUS_MSGBOX] = { 0x2c4, BIT(21) }, + [RST_BUS_SPINLOCK] = { 0x2c4, BIT(22) }, + [RST_BUS_DBG] = { 0x2c4, BIT(31) }, + + [RST_BUS_LVDS] = { 0x2c8, BIT(0) }, + + [RST_BUS_CODEC] = { 0x2d0, BIT(0) }, + [RST_BUS_SPDIF] = { 0x2d0, BIT(1) }, + [RST_BUS_THS] = { 0x2d0, BIT(8) }, + [RST_BUS_I2S0] = { 0x2d0, BIT(12) }, + [RST_BUS_I2S1] = { 0x2d0, BIT(13) }, + [RST_BUS_I2S2] = { 0x2d0, BIT(14) }, + + [RST_BUS_I2C0] = { 0x2d8, BIT(0) }, + [RST_BUS_I2C1] = { 0x2d8, BIT(1) }, + [RST_BUS_I2C2] = { 0x2d8, BIT(2) }, + [RST_BUS_SCR] = { 0x2d8, BIT(5) }, + [RST_BUS_UART0] = { 0x2d8, BIT(16) }, + [RST_BUS_UART1] = { 0x2d8, BIT(17) }, + [RST_BUS_UART2] = { 0x2d8, BIT(18) }, + [RST_BUS_UART3] = { 0x2d8, BIT(19) }, + [RST_BUS_UART4] = { 0x2d8, BIT(20) }, +}; + +static const struct sunxi_ccu_desc sun50i_a64_ccu_desc = { + .ccu_clks = sun50i_a64_ccu_clks, + .num_ccu_clks = ARRAY_SIZE(sun50i_a64_ccu_clks), + + .hw_clks = &sun50i_a64_hw_clks, + + .resets = sun50i_a64_ccu_resets, + .num_resets = ARRAY_SIZE(sun50i_a64_ccu_resets), +}; + +static void __init sun50i_a64_ccu_setup(struct device_node *node) +{ + void __iomem *reg; + u32 val; + + reg = of_io_request_and_map(node, 0, of_node_full_name(node)); + if (IS_ERR(reg)) { + pr_err("%s: Could not map the clock registers\n", + of_node_full_name(node)); + return; + } + + /* Force the PLL-Audio-1x divider to 4 */ + val = readl(reg + SUN50I_A64_PLL_AUDIO_REG); + val &= ~GENMASK(19, 16); + writel(val | (3 << 16), reg + SUN50I_A64_PLL_AUDIO_REG); + + writel(0x515, reg + SUN50I_A64_PLL_MIPI_REG); + + sunxi_ccu_probe(node, reg, &sun50i_a64_ccu_desc); +} +CLK_OF_DECLARE(sun50i_a64_ccu, "allwinner,sun50i-a64-ccu", + sun50i_a64_ccu_setup); diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-a64.h b/drivers/clk/sunxi-ng/ccu-sun50i-a64.h new file mode 100644 index 000000000000..e3c77d92af1c --- /dev/null +++ b/drivers/clk/sunxi-ng/ccu-sun50i-a64.h @@ -0,0 +1,68 @@ +/* + * Copyright 2016 Maxime Ripard + * + * Maxime Ripard <maxime.ripard@free-electrons.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _CCU_SUN50I_A64_H_ +#define _CCU_SUN50I_A64_H_ + +#include <dt-bindings/clock/sun50i-a64-ccu.h> +#include <dt-bindings/reset/sun50i-a64-ccu.h> + +#define CLK_OSC_12M 0 +#define CLK_PLL_CPUX 1 +#define CLK_PLL_AUDIO_BASE 2 +#define CLK_PLL_AUDIO 3 +#define CLK_PLL_AUDIO_2X 4 +#define CLK_PLL_AUDIO_4X 5 +#define CLK_PLL_AUDIO_8X 6 +#define CLK_PLL_VIDEO0 7 +#define CLK_PLL_VIDEO0_2X 8 +#define CLK_PLL_VE 9 +#define CLK_PLL_DDR0 10 +#define CLK_PLL_PERIPH0 11 +#define CLK_PLL_PERIPH0_2X 12 +#define CLK_PLL_PERIPH1 13 +#define CLK_PLL_PERIPH1_2X 14 +#define CLK_PLL_VIDEO1 15 +#define CLK_PLL_GPU 16 +#define CLK_PLL_MIPI 17 +#define CLK_PLL_HSIC 18 +#define CLK_PLL_DE 19 +#define CLK_PLL_DDR1 20 +#define CLK_CPUX 21 +#define CLK_AXI 22 +#define CLK_APB 23 +#define CLK_AHB1 24 +#define CLK_APB1 25 +#define CLK_APB2 26 +#define CLK_AHB2 27 + +/* All the bus gates are exported */ + +/* The first bunch of module clocks are exported */ + +#define CLK_DRAM 92 + +/* All the DRAM gates are exported */ + +/* Some more module clocks are exported */ + +#define CLK_MBUS 110 + +/* And the DSI and GPU module clock is exported */ + +#define CLK_NUMBER (CLK_GPU + 1) + +#endif /* _CCU_SUN50I_A64_H_ */ diff --git a/include/dt-bindings/clock/sun50i-a64-ccu.h b/include/dt-bindings/clock/sun50i-a64-ccu.h new file mode 100644 index 000000000000..2abcd87c7a2d --- /dev/null +++ b/include/dt-bindings/clock/sun50i-a64-ccu.h @@ -0,0 +1,132 @@ +/* + * Copyright (C) 2016 Maxime Ripard <maxime.ripard@free-electrons.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef _DT_BINDINGS_CLK_SUN50I_A64_H_ +#define _DT_BINDINGS_CLK_SUN50I_A64_H_ + +#define CLK_BUS_MIPI_DSI 28 +#define CLK_BUS_CE 29 +#define CLK_BUS_DMA 30 +#define CLK_BUS_MMC0 31 +#define CLK_BUS_MMC1 32 +#define CLK_BUS_MMC2 33 +#define CLK_BUS_NAND 34 +#define CLK_BUS_DRAM 35 +#define CLK_BUS_EMAC 36 +#define CLK_BUS_TS 37 +#define CLK_BUS_HSTIMER 38 +#define CLK_BUS_SPI0 39 +#define CLK_BUS_SPI1 40 +#define CLK_BUS_OTG 41 +#define CLK_BUS_EHCI0 42 +#define CLK_BUS_EHCI1 43 +#define CLK_BUS_OHCI0 44 +#define CLK_BUS_OHCI1 45 +#define CLK_BUS_VE 46 +#define CLK_BUS_TCON0 47 +#define CLK_BUS_TCON1 48 +#define CLK_BUS_DEINTERLACE 49 +#define CLK_BUS_CSI 50 +#define CLK_BUS_HDMI 51 +#define CLK_BUS_DE 52 +#define CLK_BUS_GPU 53 +#define CLK_BUS_MSGBOX 54 +#define CLK_BUS_SPINLOCK 55 +#define CLK_BUS_CODEC 56 +#define CLK_BUS_SPDIF 57 +#define CLK_BUS_PIO 58 +#define CLK_BUS_THS 59 +#define CLK_BUS_I2S0 60 +#define CLK_BUS_I2S1 61 +#define CLK_BUS_I2S2 62 +#define CLK_BUS_I2C0 63 +#define CLK_BUS_I2C1 64 +#define CLK_BUS_I2C2 65 +#define CLK_BUS_SCR 66 +#define CLK_BUS_UART0 67 +#define CLK_BUS_UART1 68 +#define CLK_BUS_UART2 69 +#define CLK_BUS_UART3 70 +#define CLK_BUS_UART4 71 +#define CLK_BUS_DBG 72 +#define CLK_THS 73 +#define CLK_NAND 74 +#define CLK_MMC0 75 +#define CLK_MMC1 76 +#define CLK_MMC2 77 +#define CLK_TS 78 +#define CLK_CE 79 +#define CLK_SPI0 80 +#define CLK_SPI1 81 +#define CLK_I2S0 82 +#define CLK_I2S1 83 +#define CLK_I2S2 84 +#define CLK_SPDIF 85 +#define CLK_USB_PHY0 86 +#define CLK_USB_PHY1 87 +#define CLK_USB_HSIC 88 +#define CLK_USB_HSIC_12M 89 +#define CLK_USB_OHCI0 90 +#define CLK_USB_OHCI1 91 + +#define CLK_DRAM_VE 93 +#define CLK_DRAM_CSI 94 +#define CLK_DRAM_DEINTERLACE 95 +#define CLK_DRAM_TS 96 +#define CLK_DE 97 +#define CLK_TCON0 98 +#define CLK_TCON1 99 +#define CLK_DEINTERLACE 100 +#define CLK_CSI_MISC 101 +#define CLK_CSI_SCLK 102 +#define CLK_CSI_MCLK 103 +#define CLK_VE 104 +#define CLK_AC_DIG 105 +#define CLK_AC_DIG_4X 106 +#define CLK_AVS 107 +#define CLK_HDMI 108 +#define CLK_HDMI_DDC 109 + +#define CLK_DSI_DPHY 111 +#define CLK_GPU 112 + +#endif /* _DT_BINDINGS_CLK_SUN50I_H_ */ diff --git a/include/dt-bindings/reset/sun50i-a64-ccu.h b/include/dt-bindings/reset/sun50i-a64-ccu.h new file mode 100644 index 000000000000..e61fac294d73 --- /dev/null +++ b/include/dt-bindings/reset/sun50i-a64-ccu.h @@ -0,0 +1,97 @@ +/* + * Copyright (C) 2016 Maxime Ripard <maxime.ripard@free-electrons.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef _DT_BINDINGS_RST_SUN50I_A64_H_ +#define _DT_BINDINGS_RST_SUN50I_A64_H_ + +#define RST_USB_PHY0 0 +#define RST_USB_PHY1 1 +#define RST_USB_HSIC 2 +#define RST_MBUS 3 +#define RST_BUS_MIPI_DSI 4 +#define RST_BUS_CE 5 +#define RST_BUS_DMA 6 +#define RST_BUS_MMC0 7 +#define RST_BUS_MMC1 8 +#define RST_BUS_MMC2 9 +#define RST_BUS_NAND 10 +#define RST_BUS_DRAM 11 +#define RST_BUS_EMAC 12 +#define RST_BUS_TS 13 +#define RST_BUS_HSTIMER 14 +#define RST_BUS_SPI0 15 +#define RST_BUS_SPI1 16 +#define RST_BUS_OTG 17 +#define RST_BUS_EHCI0 18 +#define RST_BUS_EHCI1 19 +#define RST_BUS_OHCI0 20 +#define RST_BUS_OHCI1 21 +#define RST_BUS_VE 22 +#define RST_BUS_TCON0 23 +#define RST_BUS_TCON1 24 +#define RST_BUS_DEINTERLACE 25 +#define RST_BUS_CSI 26 +#define RST_BUS_HDMI0 27 +#define RST_BUS_HDMI1 28 +#define RST_BUS_DE 29 +#define RST_BUS_GPU 30 +#define RST_BUS_MSGBOX 31 +#define RST_BUS_SPINLOCK 32 +#define RST_BUS_DBG 33 +#define RST_BUS_LVDS 34 +#define RST_BUS_CODEC 35 +#define RST_BUS_SPDIF 36 +#define RST_BUS_THS 37 +#define RST_BUS_I2S0 38 +#define RST_BUS_I2S1 39 +#define RST_BUS_I2S2 40 +#define RST_BUS_I2C0 41 +#define RST_BUS_I2C1 42 +#define RST_BUS_I2C2 43 +#define RST_BUS_SCR 44 +#define RST_BUS_UART0 45 +#define RST_BUS_UART1 46 +#define RST_BUS_UART2 47 +#define RST_BUS_UART3 48 +#define RST_BUS_UART4 49 + +#endif /* _DT_BINDINGS_RST_SUN8I_H3_H_ */ -- 2.9.3 ^ permalink raw reply related [flat|nested] 35+ messages in thread
* Re: [PATCH v2 1/4] clk: sunxi-ng: Add A64 clocks 2016-09-09 20:10 ` Maxime Ripard @ 2016-09-10 3:24 ` Chen-Yu Tsai -1 siblings, 0 replies; 35+ messages in thread From: Chen-Yu Tsai @ 2016-09-10 3:24 UTC (permalink / raw) To: Maxime Ripard Cc: Mike Turquette, Stephen Boyd, Chen-Yu Tsai, linux-arm-kernel, Andre Przywara, linux-clk, linux-kernel, linux-sunxi On Sat, Sep 10, 2016 at 4:10 AM, Maxime Ripard <maxime.ripard@free-electrons.com> wrote: > Add the A64 CCU clocks set. > > Acked-by: Rob Herring <robh@kernel.org> > Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> > --- > .../devicetree/bindings/clock/sunxi-ccu.txt | 1 + > drivers/clk/sunxi-ng/Kconfig | 11 + > drivers/clk/sunxi-ng/Makefile | 1 + > drivers/clk/sunxi-ng/ccu-sun50i-a64.c | 870 +++++++++++++++++++++ > drivers/clk/sunxi-ng/ccu-sun50i-a64.h | 68 ++ > include/dt-bindings/clock/sun50i-a64-ccu.h | 132 ++++ > include/dt-bindings/reset/sun50i-a64-ccu.h | 97 +++ > 7 files changed, 1180 insertions(+) > create mode 100644 drivers/clk/sunxi-ng/ccu-sun50i-a64.c > create mode 100644 drivers/clk/sunxi-ng/ccu-sun50i-a64.h > create mode 100644 include/dt-bindings/clock/sun50i-a64-ccu.h > create mode 100644 include/dt-bindings/reset/sun50i-a64-ccu.h > > diff --git a/Documentation/devicetree/bindings/clock/sunxi-ccu.txt b/Documentation/devicetree/bindings/clock/sunxi-ccu.txt > index 3868458a5feb..74d44a4273f2 100644 > --- a/Documentation/devicetree/bindings/clock/sunxi-ccu.txt > +++ b/Documentation/devicetree/bindings/clock/sunxi-ccu.txt > @@ -7,6 +7,7 @@ Required properties : > - "allwinner,sun8i-a23-ccu" > - "allwinner,sun8i-a33-ccu" > - "allwinner,sun8i-h3-ccu" > + - "allwinner,sun50i-a64-ccu" > > - reg: Must contain the registers base address and length > - clocks: phandle to the oscillators feeding the CCU. Two are needed: > diff --git a/drivers/clk/sunxi-ng/Kconfig b/drivers/clk/sunxi-ng/Kconfig > index 254d9526c018..71e0c21c3545 100644 > --- a/drivers/clk/sunxi-ng/Kconfig > +++ b/drivers/clk/sunxi-ng/Kconfig > @@ -101,4 +101,15 @@ config SUN8I_H3_CCU > select SUNXI_CCU_PHASE > default MACH_SUN8I > > +config SUN50I_A64_CCU > + bool "Support for the Allwinner A64 CCU" > + select SUNXI_CCU_DIV > + select SUNXI_CCU_NK > + select SUNXI_CCU_NKM > + select SUNXI_CCU_NKMP > + select SUNXI_CCU_NM > + select SUNXI_CCU_MP > + select SUNXI_CCU_PHASE > + default ARM64 && ARCH_SUNXI > + > endif > diff --git a/drivers/clk/sunxi-ng/Makefile b/drivers/clk/sunxi-ng/Makefile > index 106cba27c331..964f22091a10 100644 > --- a/drivers/clk/sunxi-ng/Makefile > +++ b/drivers/clk/sunxi-ng/Makefile > @@ -22,3 +22,4 @@ obj-$(CONFIG_SUN6I_A31_CCU) += ccu-sun6i-a31.o > obj-$(CONFIG_SUN8I_A23_CCU) += ccu-sun8i-a23.o > obj-$(CONFIG_SUN8I_A33_CCU) += ccu-sun8i-a33.o > obj-$(CONFIG_SUN8I_H3_CCU) += ccu-sun8i-h3.o > +obj-$(CONFIG_SUN50I_A64_CCU) += ccu-sun50i-a64.o > diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c > new file mode 100644 > index 000000000000..d51ee416f515 > --- /dev/null > +++ b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c > @@ -0,0 +1,870 @@ > +/* > + * Copyright (c) 2016 Maxime Ripard. All rights reserved. > + * > + * This software is licensed under the terms of the GNU General Public > + * License version 2, as published by the Free Software Foundation, and > + * may be copied, distributed, and modified under those terms. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + */ > + > +#include <linux/clk-provider.h> > +#include <linux/of_address.h> > + > +#include "ccu_common.h" > +#include "ccu_reset.h" > + > +#include "ccu_div.h" > +#include "ccu_gate.h" > +#include "ccu_mp.h" > +#include "ccu_mult.h" > +#include "ccu_nk.h" > +#include "ccu_nkm.h" > +#include "ccu_nkmp.h" > +#include "ccu_nm.h" > +#include "ccu_phase.h" > + > +#include "ccu-sun50i-a64.h" > + > +static SUNXI_CCU_NKMP_WITH_GATE_LOCK(pll_cpux_clk, "pll-cpux", > + "osc24M", 0x000, > + 8, 5, /* N */ > + 4, 2, /* K */ > + 0, 2, /* M */ > + 16, 2, /* P */ You need a max = 4 for P. > + BIT(31), /* gate */ > + BIT(28), /* lock */ > + 0); > + > +/* > + * The Audio PLL is supposed to have 4 outputs: 3 fixed factors from > + * the base (2x, 4x and 8x), and one variable divider (the one true > + * pll audio). > + * > + * We don't have any need for the variable divider for now, so we just > + * hardcode it to match with the clock names > + */ > +#define SUN50I_A64_PLL_AUDIO_REG 0x008 > + > +static SUNXI_CCU_NM_WITH_GATE_LOCK(pll_audio_base_clk, "pll-audio-base", > + "osc24M", 0x008, > + 8, 7, /* N */ > + 0, 5, /* M */ > + BIT(31), /* gate */ > + BIT(28), /* lock */ > + 0); > + > +static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video0_clk, "pll-video0", > + "osc24M", 0x010, > + 8, 7, /* N */ > + 0, 4, /* M */ > + BIT(24), /* frac enable */ > + BIT(25), /* frac select */ > + 270000000, /* frac rate 0 */ > + 297000000, /* frac rate 1 */ > + BIT(31), /* gate */ > + BIT(28), /* lock */ > + 0); > + > +static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_ve_clk, "pll-ve", > + "osc24M", 0x018, > + 8, 7, /* N */ > + 0, 4, /* M */ > + BIT(24), /* frac enable */ > + BIT(25), /* frac select */ > + 270000000, /* frac rate 0 */ > + 297000000, /* frac rate 1 */ > + BIT(31), /* gate */ > + BIT(28), /* lock */ > + 0); > + > +static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_ddr0_clk, "pll-ddr0", > + "osc24M", 0x020, > + 8, 5, /* N */ > + 4, 2, /* K */ > + 0, 2, /* M */ > + BIT(31), /* gate */ > + BIT(28), /* lock */ > + 0); > + > +static SUNXI_CCU_NK_WITH_GATE_LOCK_POSTDIV(pll_periph0_clk, "pll-periph0", > + "osc24M", 0x028, > + 8, 5, /* N */ > + 4, 2, /* K */ The manual says to give preference to K >= 2. I suggest swapping N/K and leaving a note about it, so the actual K is in the inner loop (see ccu_nk.c) of the factor calculation. > + BIT(31), /* gate */ > + BIT(28), /* lock */ > + 2, /* post-div */ > + 0); > + > +static SUNXI_CCU_NK_WITH_GATE_LOCK_POSTDIV(pll_periph1_clk, "pll-periph1", > + "osc24M", 0x02c, > + 8, 5, /* N */ > + 4, 2, /* K */ > + BIT(31), /* gate */ > + BIT(28), /* lock */ > + 2, /* post-div */ > + 0); Same here. > + > +static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video1_clk, "pll-video1", > + "osc24M", 0x030, > + 8, 7, /* N */ > + 0, 4, /* M */ > + BIT(24), /* frac enable */ > + BIT(25), /* frac select */ > + 270000000, /* frac rate 0 */ > + 297000000, /* frac rate 1 */ > + BIT(31), /* gate */ > + BIT(28), /* lock */ > + 0); > + > +static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_gpu_clk, "pll-gpu", > + "osc24M", 0x038, > + 8, 7, /* N */ > + 0, 4, /* M */ > + BIT(24), /* frac enable */ > + BIT(25), /* frac select */ > + 270000000, /* frac rate 0 */ > + 297000000, /* frac rate 1 */ > + BIT(31), /* gate */ > + BIT(28), /* lock */ > + 0); > + > +/* > + * The output function can be changed to something more complex that > + * we do not handle yet. > + * > + * Hardcode the mode so that we don't fall in that case. > + */ > +#define SUN50I_A64_PLL_MIPI_REG 0x040 > + > +static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_mipi_clk, "pll-mipi", > + "pll-video0", 0x040, > + 8, 4, /* N */ > + 4, 2, /* K */ You need a table for K. (Manual says K >= 2). > + 0, 4, /* M */ > + BIT(31), /* gate */ > + BIT(28), /* lock */ > + 0); > + > +static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_hsic_clk, "pll-hsic", > + "osc24M", 0x044, > + 8, 7, /* N */ > + 0, 4, /* M */ > + BIT(24), /* frac enable */ > + BIT(25), /* frac select */ > + 270000000, /* frac rate 0 */ > + 297000000, /* frac rate 1 */ > + BIT(31), /* gate */ > + BIT(28), /* lock */ > + 0); > + > +static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_de_clk, "pll-de", > + "osc24M", 0x048, > + 8, 7, /* N */ > + 0, 4, /* M */ > + BIT(24), /* frac enable */ > + BIT(25), /* frac select */ > + 270000000, /* frac rate 0 */ > + 297000000, /* frac rate 1 */ > + BIT(31), /* gate */ > + BIT(28), /* lock */ > + 0); > + > +static SUNXI_CCU_NM_WITH_GATE_LOCK(pll_ddr1_clk, "pll-ddr1", > + "osc24M", 0x04c, > + 8, 7, /* N */ > + 0, 2, /* M */ > + BIT(31), /* gate */ > + BIT(28), /* lock */ > + 0); > + > +static const char * const cpux_parents[] = { "osc32k", "osc24M", > + "pll-cpux" , "pll-cpux" }; > +static SUNXI_CCU_MUX(cpux_clk, "cpux", cpux_parents, > + 0x050, 16, 2, CLK_IS_CRITICAL); > + > +static SUNXI_CCU_M(axi_clk, "axi", "cpux", 0x050, 0, 2, 0); > + > +static const char * const ahb1_parents[] = { "osc32k", "osc24M", > + "axi" , "pll-periph0" }; > +static struct ccu_div ahb1_clk = { > + .div = _SUNXI_CCU_DIV_FLAGS(4, 2, CLK_DIVIDER_POWER_OF_TWO), > + > + .mux = { > + .shift = 12, > + .width = 2, > + > + .variable_prediv = { > + .index = 3, > + .shift = 6, > + .width = 2, > + }, > + }, > + > + .common = { > + .reg = 0x054, > + .features = CCU_FEATURE_VARIABLE_PREDIV, > + .hw.init = CLK_HW_INIT_PARENTS("ahb1", > + ahb1_parents, > + &ccu_div_ops, > + 0), > + }, > +}; > + > +static struct clk_div_table apb1_div_table[] = { > + { .val = 0, .div = 2 }, > + { .val = 1, .div = 2 }, > + { .val = 2, .div = 4 }, > + { .val = 3, .div = 8 }, > + { /* Sentinel */ }, > +}; > +static SUNXI_CCU_DIV_TABLE(apb1_clk, "apb1", "ahb1", > + 0x054, 8, 2, apb1_div_table, 0); > + > +static const char * const apb2_parents[] = { "osc32k", "osc24M", > + "pll-periph0-2x" , > + "pll-periph0-2x" }; > +static SUNXI_CCU_MP_WITH_MUX(apb2_clk, "apb2", apb2_parents, 0x058, > + 0, 5, /* M */ > + 16, 2, /* P */ > + 24, 2, /* mux */ > + 0); > + > +static const char * const ahb2_parents[] = { "ahb1" , "pll-periph0" }; > +static const struct ccu_mux_fixed_prediv ahb2_fixed_predivs[] = { > + { .index = 1, .div = 2 }, > +}; > +static struct ccu_mux ahb2_clk = { > + .mux = { > + .shift = 0, > + .width = 1, > + .fixed_predivs = ahb2_fixed_predivs, > + .n_predivs = ARRAY_SIZE(ahb2_fixed_predivs), > + }, > + > + .common = { > + .reg = 0x05c, > + .features = CCU_FEATURE_FIXED_PREDIV, > + .hw.init = CLK_HW_INIT_PARENTS("ahb2", > + ahb2_parents, > + &ccu_mux_ops, > + 0), > + }, > +}; > + > +static SUNXI_CCU_GATE(bus_mipi_dsi_clk, "bus-mipi-dsi", "ahb1", > + 0x060, BIT(1), 0); > +static SUNXI_CCU_GATE(bus_ce_clk, "bus-ce", "ahb1", > + 0x060, BIT(5), 0); > +static SUNXI_CCU_GATE(bus_dma_clk, "bus-dma", "ahb1", > + 0x060, BIT(6), 0); > +static SUNXI_CCU_GATE(bus_mmc0_clk, "bus-mmc0", "ahb1", > + 0x060, BIT(8), 0); > +static SUNXI_CCU_GATE(bus_mmc1_clk, "bus-mmc1", "ahb1", > + 0x060, BIT(9), 0); > +static SUNXI_CCU_GATE(bus_mmc2_clk, "bus-mmc2", "ahb1", > + 0x060, BIT(10), 0); > +static SUNXI_CCU_GATE(bus_nand_clk, "bus-nand", "ahb1", > + 0x060, BIT(13), 0); > +static SUNXI_CCU_GATE(bus_dram_clk, "bus-dram", "ahb1", > + 0x060, BIT(14), 0); > +static SUNXI_CCU_GATE(bus_emac_clk, "bus-emac", "ahb2", > + 0x060, BIT(17), 0); > +static SUNXI_CCU_GATE(bus_ts_clk, "bus-ts", "ahb1", > + 0x060, BIT(18), 0); > +static SUNXI_CCU_GATE(bus_hstimer_clk, "bus-hstimer", "ahb1", > + 0x060, BIT(19), 0); > +static SUNXI_CCU_GATE(bus_spi0_clk, "bus-spi0", "ahb1", > + 0x060, BIT(20), 0); > +static SUNXI_CCU_GATE(bus_spi1_clk, "bus-spi1", "ahb1", > + 0x060, BIT(21), 0); > +static SUNXI_CCU_GATE(bus_otg_clk, "bus-otg", "ahb1", > + 0x060, BIT(23), 0); > +static SUNXI_CCU_GATE(bus_ehci0_clk, "bus-ehci0", "ahb1", > + 0x060, BIT(24), 0); > +static SUNXI_CCU_GATE(bus_ehci1_clk, "bus-ehci1", "ahb2", > + 0x060, BIT(25), 0); > +static SUNXI_CCU_GATE(bus_ohci0_clk, "bus-ohci0", "ahb1", > + 0x060, BIT(28), 0); > +static SUNXI_CCU_GATE(bus_ohci1_clk, "bus-ohci1", "ahb2", > + 0x060, BIT(29), 0); > + > +static SUNXI_CCU_GATE(bus_ve_clk, "bus-ve", "ahb1", > + 0x064, BIT(0), 0); > +static SUNXI_CCU_GATE(bus_tcon0_clk, "bus-tcon0", "ahb1", > + 0x064, BIT(3), 0); > +static SUNXI_CCU_GATE(bus_tcon1_clk, "bus-tcon1", "ahb1", > + 0x064, BIT(4), 0); > +static SUNXI_CCU_GATE(bus_deinterlace_clk, "bus-deinterlace", "ahb1", > + 0x064, BIT(5), 0); > +static SUNXI_CCU_GATE(bus_csi_clk, "bus-csi", "ahb1", > + 0x064, BIT(8), 0); > +static SUNXI_CCU_GATE(bus_hdmi_clk, "bus-hdmi", "ahb1", > + 0x064, BIT(11), 0); > +static SUNXI_CCU_GATE(bus_de_clk, "bus-de", "ahb1", > + 0x064, BIT(12), 0); > +static SUNXI_CCU_GATE(bus_gpu_clk, "bus-gpu", "ahb1", > + 0x064, BIT(20), 0); > +static SUNXI_CCU_GATE(bus_msgbox_clk, "bus-msgbox", "ahb1", > + 0x064, BIT(21), 0); > +static SUNXI_CCU_GATE(bus_spinlock_clk, "bus-spinlock", "ahb1", > + 0x064, BIT(22), 0); > + > +static SUNXI_CCU_GATE(bus_codec_clk, "bus-codec", "apb1", > + 0x068, BIT(0), 0); > +static SUNXI_CCU_GATE(bus_spdif_clk, "bus-spdif", "apb1", > + 0x068, BIT(1), 0); > +static SUNXI_CCU_GATE(bus_pio_clk, "bus-pio", "apb1", > + 0x068, BIT(5), 0); > +static SUNXI_CCU_GATE(bus_ths_clk, "bus-ths", "apb1", > + 0x068, BIT(8), 0); > +static SUNXI_CCU_GATE(bus_i2s0_clk, "bus-i2s0", "apb1", > + 0x068, BIT(12), 0); > +static SUNXI_CCU_GATE(bus_i2s1_clk, "bus-i2s1", "apb1", > + 0x068, BIT(13), 0); > +static SUNXI_CCU_GATE(bus_i2s2_clk, "bus-i2s2", "apb1", > + 0x068, BIT(14), 0); > + > +static SUNXI_CCU_GATE(bus_i2c0_clk, "bus-i2c0", "apb2", > + 0x06c, BIT(0), 0); > +static SUNXI_CCU_GATE(bus_i2c1_clk, "bus-i2c1", "apb2", > + 0x06c, BIT(1), 0); > +static SUNXI_CCU_GATE(bus_i2c2_clk, "bus-i2c2", "apb2", > + 0x06c, BIT(2), 0); > +static SUNXI_CCU_GATE(bus_scr_clk, "bus-scr", "apb2", > + 0x06c, BIT(5), 0); > +static SUNXI_CCU_GATE(bus_uart0_clk, "bus-uart0", "apb2", > + 0x06c, BIT(16), 0); > +static SUNXI_CCU_GATE(bus_uart1_clk, "bus-uart1", "apb2", > + 0x06c, BIT(17), 0); > +static SUNXI_CCU_GATE(bus_uart2_clk, "bus-uart2", "apb2", > + 0x06c, BIT(18), 0); > +static SUNXI_CCU_GATE(bus_uart3_clk, "bus-uart3", "apb2", > + 0x06c, BIT(19), 0); > +static SUNXI_CCU_GATE(bus_uart4_clk, "bus-uart4", "apb2", > + 0x06c, BIT(20), 0); > + > +static SUNXI_CCU_GATE(bus_dbg_clk, "bus-dbg", "ahb1", > + 0x070, BIT(7), 0); > + > +static struct clk_div_table ths_div_table[] = { > + { .val = 0, .div = 1 }, > + { .val = 1, .div = 2 }, > + { .val = 2, .div = 4 }, > + { .val = 3, .div = 6 }, > +}; > +static SUNXI_CCU_DIV_TABLE_WITH_GATE(ths_clk, "ths", "osc24M", > + 0x074, 0, 2, ths_div_table, BIT(31), 0); Even though the mux has only one valid parent, I suggest you still implement it, in case some bogus value gets put in before the kernel loads. > + > +static const char * const mod0_default_parents[] = { "osc24M", "pll-periph0", > + "pll-periph1" }; > +static SUNXI_CCU_MP_WITH_MUX_GATE(nand_clk, "nand", mod0_default_parents, 0x080, > + 0, 4, /* M */ > + 16, 2, /* P */ > + 24, 2, /* mux */ > + BIT(31), /* gate */ > + 0); > + > +static const char * const mmc_default_parents[] = { "osc24M", "pll-periph0-2x", > + "pll-periph1-2x" }; > +static SUNXI_CCU_MP_WITH_MUX_GATE(mmc0_clk, "mmc0", mmc_default_parents, 0x088, > + 0, 4, /* M */ > + 16, 2, /* P */ > + 24, 2, /* mux */ > + BIT(31), /* gate */ > + 0); > + > +static SUNXI_CCU_MP_WITH_MUX_GATE(mmc1_clk, "mmc1", mmc_default_parents, 0x08c, > + 0, 4, /* M */ > + 16, 2, /* P */ > + 24, 2, /* mux */ > + BIT(31), /* gate */ > + 0); > + > +static SUNXI_CCU_MP_WITH_MUX_GATE(mmc2_clk, "mmc2", mmc_default_parents, 0x090, > + 0, 4, /* M */ > + 16, 2, /* P */ > + 24, 2, /* mux */ > + BIT(31), /* gate */ > + 0); > + > +static const char * const ts_parents[] = { "osc24M", "pll-periph0", }; > +static SUNXI_CCU_MP_WITH_MUX_GATE(ts_clk, "ts", ts_parents, 0x098, > + 0, 4, /* M */ > + 16, 2, /* P */ > + 24, 2, /* mux */ Manual says the mux is 4 bits wide. > + BIT(31), /* gate */ > + 0); > + > +static SUNXI_CCU_MP_WITH_MUX_GATE(ce_clk, "ce", mmc_default_parents, 0x09c, > + 0, 4, /* M */ > + 16, 2, /* P */ > + 24, 2, /* mux */ > + BIT(31), /* gate */ > + 0); > + > + > +static SUNXI_CCU_MP_WITH_MUX_GATE(spi0_clk, "spi0", mod0_default_parents, 0x0a0, > + 0, 4, /* M */ > + 16, 2, /* P */ > + 24, 2, /* mux */ > + BIT(31), /* gate */ > + 0); > + > +static SUNXI_CCU_MP_WITH_MUX_GATE(spi1_clk, "spi1", mod0_default_parents, 0x0a4, > + 0, 4, /* M */ > + 16, 2, /* P */ > + 24, 2, /* mux */ > + BIT(31), /* gate */ > + 0); > + > +static const char * const i2s_parents[] = { "pll-audio-8x", "pll-audio-4x", > + "pll-audio-2x", "pll-audio" }; > +static SUNXI_CCU_MUX_WITH_GATE(i2s0_clk, "i2s0", i2s_parents, > + 0x0b0, 16, 2, BIT(31), 0); > + > +static SUNXI_CCU_MUX_WITH_GATE(i2s1_clk, "i2s1", i2s_parents, > + 0x0b4, 16, 2, BIT(31), 0); > + > +static SUNXI_CCU_MUX_WITH_GATE(i2s2_clk, "i2s2", i2s_parents, > + 0x0b8, 16, 2, BIT(31), 0); > + > +static SUNXI_CCU_M_WITH_GATE(spdif_clk, "spdif", "pll-audio", > + 0x0c0, 0, 4, BIT(31), 0); CLK_SET_PARENT_RATE for the above audio clocks? > + > +static SUNXI_CCU_GATE(usb_phy0_clk, "usb-phy0", "osc24M", > + 0x0cc, BIT(8), 0); > +static SUNXI_CCU_GATE(usb_phy1_clk, "usb-phy1", "osc24M", > + 0x0cc, BIT(9), 0); > +static SUNXI_CCU_GATE(usb_hsic_clk, "usb-hsic", "pll-hsic", > + 0x0cc, BIT(10), 0); > +static SUNXI_CCU_GATE(usb_hsic_12m_clk, "usb-hsic-12M", "osc12M", > + 0x0cc, BIT(11), 0); > +static SUNXI_CCU_GATE(usb_ohci0_clk, "usb-ohci0", "osc12M", > + 0x0cc, BIT(16), 0); > +static SUNXI_CCU_GATE(usb_ohci1_clk, "usb-ohci1", "usb-ohci0", > + 0x0cc, BIT(17), 0); I guess we aren't modeling the 2 OHCI 12M muxes? > + > +static const char * const dram_parents[] = { "pll-ddr0", "pll-ddr1" }; > +static SUNXI_CCU_M_WITH_MUX(dram_clk, "dram", dram_parents, > + 0x0f4, 0, 4, 20, 2, CLK_IS_CRITICAL); > + > +static SUNXI_CCU_GATE(dram_ve_clk, "dram-ve", "dram", > + 0x100, BIT(0), 0); > +static SUNXI_CCU_GATE(dram_csi_clk, "dram-csi", "dram", > + 0x100, BIT(1), 0); > +static SUNXI_CCU_GATE(dram_deinterlace_clk, "dram-deinterlace", "dram", > + 0x100, BIT(2), 0); > +static SUNXI_CCU_GATE(dram_ts_clk, "dram-ts", "dram", > + 0x100, BIT(3), 0); > + > +static const char * const de_parents[] = { "pll-periph0-2x", "pll-de" }; > +static SUNXI_CCU_M_WITH_MUX_GATE(de_clk, "de", de_parents, > + 0x104, 0, 4, 24, 3, BIT(31), 0); > + > +static const char * const tcon0_parents[] = { "pll-mipi", "pll-video0-2x" }; > +static const u8 tcon0_table[] = { 0, 2, }; > +static SUNXI_CCU_MUX_TABLE_WITH_GATE(tcon0_clk, "tcon0", tcon0_parents, > + tcon0_table, 0x118, 24, 3, BIT(31), 0); > + > +static const char * const tcon1_parents[] = { "pll-video0", "pll-video1" }; > +static const u8 tcon1_table[] = { 0, 2, }; > +struct ccu_div tcon1_clk = { > + .enable = BIT(31), > + .div = _SUNXI_CCU_DIV(0, 4), > + .mux = _SUNXI_CCU_MUX_TABLE(24, 3, tcon1_table), > + .common = { > + .reg = 0x11c, > + .hw.init = CLK_HW_INIT_PARENTS("tcon1", > + tcon1_parents, > + &ccu_div_ops, > + 0), > + }, > +}; CLK_SET_PARENT_RATE for the TCON clocks? > + > +static const char * const deinterlace_parents[] = { "pll-periph0", "pll-periph1" }; > +static SUNXI_CCU_M_WITH_MUX_GATE(deinterlace_clk, "deinterlace", deinterlace_parents, > + 0x124, 0, 4, 24, 3, BIT(31), 0); > + > +static SUNXI_CCU_GATE(csi_misc_clk, "csi-misc", "osc24M", > + 0x130, BIT(31), 0); > + > +static const char * const csi_sclk_parents[] = { "pll-periph0", "pll-periph1" }; > +static SUNXI_CCU_M_WITH_MUX_GATE(csi_sclk_clk, "csi-sclk", csi_sclk_parents, > + 0x134, 16, 4, 24, 3, BIT(31), 0); > + > +static const char * const csi_mclk_parents[] = { "osc24M", "pll-video1", "pll-periph1" }; > +static SUNXI_CCU_M_WITH_MUX_GATE(csi_mclk_clk, "csi-mclk", csi_mclk_parents, > + 0x134, 0, 5, 8, 3, BIT(15), 0); > + > +static SUNXI_CCU_M_WITH_GATE(ve_clk, "ve", "pll-ve", > + 0x13c, 16, 3, BIT(31), 0); > + > +static SUNXI_CCU_GATE(ac_dig_clk, "ac-dig", "pll-audio", > + 0x140, BIT(31), 0); > + > +static SUNXI_CCU_GATE(ac_dig_4x_clk, "ac-dig-4x", "pll-audio-4x", > + 0x140, BIT(30), 0); CLK_SET_PARENT_RATE for the above audio clocks? > + > +static SUNXI_CCU_GATE(avs_clk, "avs", "osc24M", > + 0x144, BIT(31), 0); > + > +static const char * const hdmi_parents[] = { "pll-video0", "pll-video1" }; > +static SUNXI_CCU_M_WITH_MUX_GATE(hdmi_clk, "hdmi", hdmi_parents, > + 0x150, 0, 4, 24, 2, BIT(31), 0); Might need CLK_SET_PARENT_RATE for hdmi? > + > +static SUNXI_CCU_GATE(hdmi_ddc_clk, "hdmi-ddc", "osc24M", > + 0x154, BIT(31), 0); > + > +static const char * const mbus_parents[] = { "osc24M", "pll-periph0-2x", > + "pll-ddr0", "pll-ddr1" }; > +static SUNXI_CCU_M_WITH_MUX_GATE(mbus_clk, "mbus", mbus_parents, > + 0x15c, 0, 3, 24, 2, BIT(31), CLK_IS_CRITICAL); > + > +static const char * const dsi_dphy_parents[] = { "pll-video0", "pll-periph0" }; You need a mux table = { 0, 2 } here. > +static SUNXI_CCU_M_WITH_MUX_GATE(dsi_dphy_clk, "dsi-dphy", dsi_dphy_parents, > + 0x168, 0, 3, 24, 2, BIT(31), 0); > + > +static SUNXI_CCU_M_WITH_GATE(gpu_clk, "gpu", "pll-gpu", > + 0x1a0, 0, 3, BIT(31), 0); CLK_SET_PARENT_RATE for the GPU clock? > + > +/* Fixed Factor clocks */ > +static CLK_FIXED_FACTOR(osc12M_clk, "osc12M", "osc24M", 1, 2, 0); > + > +/* We hardcode the divider to 4 for now */ > +static CLK_FIXED_FACTOR(pll_audio_clk, "pll-audio", > + "pll-audio-base", 4, 1, CLK_SET_RATE_PARENT); > +static CLK_FIXED_FACTOR(pll_audio_2x_clk, "pll-audio-2x", > + "pll-audio-base", 2, 1, CLK_SET_RATE_PARENT); > +static CLK_FIXED_FACTOR(pll_audio_4x_clk, "pll-audio-4x", > + "pll-audio-base", 1, 1, CLK_SET_RATE_PARENT); > +static CLK_FIXED_FACTOR(pll_audio_8x_clk, "pll-audio-8x", > + "pll-audio-base", 1, 2, CLK_SET_RATE_PARENT); > +static CLK_FIXED_FACTOR(pll_periph0_2x_clk, "pll-periph0-2x", > + "pll-periph0", 1, 2, 0); > +static CLK_FIXED_FACTOR(pll_periph1_2x_clk, "pll-periph1-2x", > + "pll-periph1", 1, 2, 0); > +static CLK_FIXED_FACTOR(pll_video0_2x_clk, "pll-video0-2x", > + "pll-video0", 1, 2, 0); CLK_SET_PARENT_RATE for pll-video0-2x. > + > +static struct ccu_common *sun50i_a64_ccu_clks[] = { > + &pll_cpux_clk.common, > + &pll_audio_base_clk.common, > + &pll_video0_clk.common, > + &pll_ve_clk.common, > + &pll_ddr0_clk.common, > + &pll_periph0_clk.common, > + &pll_periph1_clk.common, > + &pll_video1_clk.common, > + &pll_gpu_clk.common, > + &pll_mipi_clk.common, > + &pll_hsic_clk.common, > + &pll_de_clk.common, > + &pll_ddr1_clk.common, > + &cpux_clk.common, > + &axi_clk.common, > + &ahb1_clk.common, > + &apb1_clk.common, > + &apb2_clk.common, > + &ahb2_clk.common, > + &bus_mipi_dsi_clk.common, > + &bus_ce_clk.common, > + &bus_dma_clk.common, > + &bus_mmc0_clk.common, > + &bus_mmc1_clk.common, > + &bus_mmc2_clk.common, > + &bus_nand_clk.common, > + &bus_dram_clk.common, > + &bus_emac_clk.common, > + &bus_ts_clk.common, > + &bus_hstimer_clk.common, > + &bus_spi0_clk.common, > + &bus_spi1_clk.common, > + &bus_otg_clk.common, > + &bus_ehci0_clk.common, > + &bus_ehci1_clk.common, > + &bus_ohci0_clk.common, > + &bus_ohci1_clk.common, > + &bus_ve_clk.common, > + &bus_tcon0_clk.common, > + &bus_tcon1_clk.common, > + &bus_deinterlace_clk.common, > + &bus_csi_clk.common, > + &bus_hdmi_clk.common, > + &bus_de_clk.common, > + &bus_gpu_clk.common, > + &bus_msgbox_clk.common, > + &bus_spinlock_clk.common, > + &bus_codec_clk.common, > + &bus_spdif_clk.common, > + &bus_pio_clk.common, > + &bus_ths_clk.common, > + &bus_i2s0_clk.common, > + &bus_i2s1_clk.common, > + &bus_i2s2_clk.common, > + &bus_i2c0_clk.common, > + &bus_i2c1_clk.common, > + &bus_i2c2_clk.common, > + &bus_scr_clk.common, > + &bus_uart0_clk.common, > + &bus_uart1_clk.common, > + &bus_uart2_clk.common, > + &bus_uart3_clk.common, > + &bus_uart4_clk.common, > + &bus_dbg_clk.common, > + &ths_clk.common, > + &nand_clk.common, > + &mmc0_clk.common, > + &mmc1_clk.common, > + &mmc2_clk.common, > + &ts_clk.common, > + &ce_clk.common, > + &spi0_clk.common, > + &spi1_clk.common, > + &i2s0_clk.common, > + &i2s1_clk.common, > + &i2s2_clk.common, > + &spdif_clk.common, > + &usb_phy0_clk.common, > + &usb_phy1_clk.common, > + &usb_hsic_clk.common, > + &usb_hsic_12m_clk.common, > + &usb_ohci0_clk.common, > + &usb_ohci1_clk.common, > + &dram_clk.common, > + &dram_ve_clk.common, > + &dram_csi_clk.common, > + &dram_deinterlace_clk.common, > + &dram_ts_clk.common, > + &de_clk.common, > + &tcon0_clk.common, > + &tcon1_clk.common, > + &deinterlace_clk.common, > + &csi_misc_clk.common, > + &csi_sclk_clk.common, > + &csi_mclk_clk.common, > + &ve_clk.common, > + &ac_dig_clk.common, > + &ac_dig_4x_clk.common, > + &avs_clk.common, > + &hdmi_clk.common, > + &hdmi_ddc_clk.common, > + &mbus_clk.common, > + &dsi_dphy_clk.common, > + &gpu_clk.common, > +}; > + > +static struct clk_hw_onecell_data sun50i_a64_hw_clks = { > + .hws = { > + [CLK_OSC_12M] = &osc12M_clk.hw, > + [CLK_PLL_CPUX] = &pll_cpux_clk.common.hw, > + [CLK_PLL_AUDIO_BASE] = &pll_audio_base_clk.common.hw, > + [CLK_PLL_AUDIO] = &pll_audio_clk.hw, > + [CLK_PLL_AUDIO_2X] = &pll_audio_2x_clk.hw, > + [CLK_PLL_AUDIO_4X] = &pll_audio_4x_clk.hw, > + [CLK_PLL_AUDIO_8X] = &pll_audio_8x_clk.hw, > + [CLK_PLL_VIDEO0] = &pll_video0_clk.common.hw, > + [CLK_PLL_VIDEO0_2X] = &pll_video0_2x_clk.hw, > + [CLK_PLL_VE] = &pll_ve_clk.common.hw, > + [CLK_PLL_DDR0] = &pll_ddr0_clk.common.hw, > + [CLK_PLL_PERIPH0] = &pll_periph0_clk.common.hw, > + [CLK_PLL_PERIPH0_2X] = &pll_periph0_2x_clk.hw, > + [CLK_PLL_PERIPH1] = &pll_periph1_clk.common.hw, > + [CLK_PLL_PERIPH1_2X] = &pll_periph1_2x_clk.hw, > + [CLK_PLL_VIDEO1] = &pll_video1_clk.common.hw, > + [CLK_PLL_GPU] = &pll_gpu_clk.common.hw, > + [CLK_PLL_MIPI] = &pll_mipi_clk.common.hw, > + [CLK_PLL_HSIC] = &pll_hsic_clk.common.hw, > + [CLK_PLL_DE] = &pll_de_clk.common.hw, > + [CLK_PLL_DDR1] = &pll_ddr1_clk.common.hw, > + [CLK_CPUX] = &cpux_clk.common.hw, > + [CLK_AXI] = &axi_clk.common.hw, > + [CLK_AHB1] = &ahb1_clk.common.hw, > + [CLK_APB1] = &apb1_clk.common.hw, > + [CLK_APB2] = &apb2_clk.common.hw, > + [CLK_AHB2] = &ahb2_clk.common.hw, > + [CLK_BUS_MIPI_DSI] = &bus_mipi_dsi_clk.common.hw, > + [CLK_BUS_CE] = &bus_ce_clk.common.hw, > + [CLK_BUS_DMA] = &bus_dma_clk.common.hw, > + [CLK_BUS_MMC0] = &bus_mmc0_clk.common.hw, > + [CLK_BUS_MMC1] = &bus_mmc1_clk.common.hw, > + [CLK_BUS_MMC2] = &bus_mmc2_clk.common.hw, > + [CLK_BUS_NAND] = &bus_nand_clk.common.hw, > + [CLK_BUS_DRAM] = &bus_dram_clk.common.hw, > + [CLK_BUS_EMAC] = &bus_emac_clk.common.hw, > + [CLK_BUS_TS] = &bus_ts_clk.common.hw, > + [CLK_BUS_HSTIMER] = &bus_hstimer_clk.common.hw, > + [CLK_BUS_SPI0] = &bus_spi0_clk.common.hw, > + [CLK_BUS_SPI1] = &bus_spi1_clk.common.hw, > + [CLK_BUS_OTG] = &bus_otg_clk.common.hw, > + [CLK_BUS_EHCI0] = &bus_ehci0_clk.common.hw, > + [CLK_BUS_EHCI1] = &bus_ehci1_clk.common.hw, > + [CLK_BUS_OHCI0] = &bus_ohci0_clk.common.hw, > + [CLK_BUS_OHCI1] = &bus_ohci1_clk.common.hw, > + [CLK_BUS_VE] = &bus_ve_clk.common.hw, > + [CLK_BUS_TCON0] = &bus_tcon0_clk.common.hw, > + [CLK_BUS_TCON1] = &bus_tcon1_clk.common.hw, > + [CLK_BUS_DEINTERLACE] = &bus_deinterlace_clk.common.hw, > + [CLK_BUS_CSI] = &bus_csi_clk.common.hw, > + [CLK_BUS_HDMI] = &bus_hdmi_clk.common.hw, > + [CLK_BUS_DE] = &bus_de_clk.common.hw, > + [CLK_BUS_GPU] = &bus_gpu_clk.common.hw, > + [CLK_BUS_MSGBOX] = &bus_msgbox_clk.common.hw, > + [CLK_BUS_SPINLOCK] = &bus_spinlock_clk.common.hw, > + [CLK_BUS_CODEC] = &bus_codec_clk.common.hw, > + [CLK_BUS_SPDIF] = &bus_spdif_clk.common.hw, > + [CLK_BUS_PIO] = &bus_pio_clk.common.hw, > + [CLK_BUS_THS] = &bus_ths_clk.common.hw, > + [CLK_BUS_I2S0] = &bus_i2s0_clk.common.hw, > + [CLK_BUS_I2S1] = &bus_i2s1_clk.common.hw, > + [CLK_BUS_I2S2] = &bus_i2s2_clk.common.hw, > + [CLK_BUS_I2C0] = &bus_i2c0_clk.common.hw, > + [CLK_BUS_I2C1] = &bus_i2c1_clk.common.hw, > + [CLK_BUS_I2C2] = &bus_i2c2_clk.common.hw, > + [CLK_BUS_UART0] = &bus_uart0_clk.common.hw, > + [CLK_BUS_UART1] = &bus_uart1_clk.common.hw, > + [CLK_BUS_UART2] = &bus_uart2_clk.common.hw, > + [CLK_BUS_UART3] = &bus_uart3_clk.common.hw, > + [CLK_BUS_UART4] = &bus_uart4_clk.common.hw, > + [CLK_BUS_SCR] = &bus_scr_clk.common.hw, > + [CLK_BUS_DBG] = &bus_dbg_clk.common.hw, > + [CLK_THS] = &ths_clk.common.hw, > + [CLK_NAND] = &nand_clk.common.hw, > + [CLK_MMC0] = &mmc0_clk.common.hw, > + [CLK_MMC1] = &mmc1_clk.common.hw, > + [CLK_MMC2] = &mmc2_clk.common.hw, > + [CLK_TS] = &ts_clk.common.hw, > + [CLK_CE] = &ce_clk.common.hw, > + [CLK_SPI0] = &spi0_clk.common.hw, > + [CLK_SPI1] = &spi1_clk.common.hw, > + [CLK_I2S0] = &i2s0_clk.common.hw, > + [CLK_I2S1] = &i2s1_clk.common.hw, > + [CLK_I2S2] = &i2s2_clk.common.hw, > + [CLK_SPDIF] = &spdif_clk.common.hw, > + [CLK_USB_PHY0] = &usb_phy0_clk.common.hw, > + [CLK_USB_PHY1] = &usb_phy1_clk.common.hw, > + [CLK_USB_HSIC] = &usb_hsic_clk.common.hw, > + [CLK_USB_HSIC_12M] = &usb_hsic_12m_clk.common.hw, > + [CLK_USB_OHCI0] = &usb_ohci0_clk.common.hw, > + [CLK_USB_OHCI1] = &usb_ohci1_clk.common.hw, > + [CLK_DRAM] = &dram_clk.common.hw, > + [CLK_DRAM_VE] = &dram_ve_clk.common.hw, > + [CLK_DRAM_CSI] = &dram_csi_clk.common.hw, > + [CLK_DRAM_DEINTERLACE] = &dram_deinterlace_clk.common.hw, > + [CLK_DRAM_TS] = &dram_ts_clk.common.hw, > + [CLK_DE] = &de_clk.common.hw, > + [CLK_TCON0] = &tcon0_clk.common.hw, > + [CLK_TCON1] = &tcon1_clk.common.hw, > + [CLK_DEINTERLACE] = &deinterlace_clk.common.hw, > + [CLK_CSI_MISC] = &csi_misc_clk.common.hw, > + [CLK_CSI_SCLK] = &csi_sclk_clk.common.hw, > + [CLK_CSI_MCLK] = &csi_mclk_clk.common.hw, > + [CLK_VE] = &ve_clk.common.hw, > + [CLK_AC_DIG] = &ac_dig_clk.common.hw, > + [CLK_AC_DIG_4X] = &ac_dig_4x_clk.common.hw, > + [CLK_AVS] = &avs_clk.common.hw, > + [CLK_HDMI] = &hdmi_clk.common.hw, > + [CLK_HDMI_DDC] = &hdmi_ddc_clk.common.hw, > + [CLK_MBUS] = &mbus_clk.common.hw, > + [CLK_DSI_DPHY] = &dsi_dphy_clk.common.hw, > + [CLK_GPU] = &gpu_clk.common.hw, > + }, > + .num = CLK_NUMBER, > +}; > + > +static struct ccu_reset_map sun50i_a64_ccu_resets[] = { > + [RST_USB_PHY0] = { 0x0cc, BIT(0) }, > + [RST_USB_PHY1] = { 0x0cc, BIT(1) }, > + [RST_USB_HSIC] = { 0x0cc, BIT(2) }, > + > + > + [RST_MBUS] = { 0x0fc, BIT(31) }, > + > + [RST_BUS_MIPI_DSI] = { 0x2c0, BIT(1) }, > + [RST_BUS_CE] = { 0x2c0, BIT(5) }, > + [RST_BUS_DMA] = { 0x2c0, BIT(6) }, > + [RST_BUS_MMC0] = { 0x2c0, BIT(8) }, > + [RST_BUS_MMC1] = { 0x2c0, BIT(9) }, > + [RST_BUS_MMC2] = { 0x2c0, BIT(10) }, > + [RST_BUS_NAND] = { 0x2c0, BIT(13) }, > + [RST_BUS_DRAM] = { 0x2c0, BIT(14) }, > + [RST_BUS_EMAC] = { 0x2c0, BIT(17) }, > + [RST_BUS_TS] = { 0x2c0, BIT(18) }, > + [RST_BUS_HSTIMER] = { 0x2c0, BIT(19) }, > + [RST_BUS_SPI0] = { 0x2c0, BIT(20) }, > + [RST_BUS_SPI1] = { 0x2c0, BIT(21) }, > + [RST_BUS_OTG] = { 0x2c0, BIT(23) }, > + [RST_BUS_EHCI0] = { 0x2c0, BIT(24) }, > + [RST_BUS_EHCI1] = { 0x2c0, BIT(25) }, > + [RST_BUS_OHCI0] = { 0x2c0, BIT(28) }, > + [RST_BUS_OHCI1] = { 0x2c0, BIT(29) }, > + > + [RST_BUS_VE] = { 0x2c4, BIT(0) }, > + [RST_BUS_TCON0] = { 0x2c4, BIT(3) }, > + [RST_BUS_TCON1] = { 0x2c4, BIT(4) }, > + [RST_BUS_DEINTERLACE] = { 0x2c4, BIT(5) }, > + [RST_BUS_CSI] = { 0x2c4, BIT(8) }, > + [RST_BUS_HDMI0] = { 0x2c4, BIT(10) }, > + [RST_BUS_HDMI1] = { 0x2c4, BIT(11) }, > + [RST_BUS_DE] = { 0x2c4, BIT(12) }, > + [RST_BUS_GPU] = { 0x2c4, BIT(20) }, > + [RST_BUS_MSGBOX] = { 0x2c4, BIT(21) }, > + [RST_BUS_SPINLOCK] = { 0x2c4, BIT(22) }, > + [RST_BUS_DBG] = { 0x2c4, BIT(31) }, > + > + [RST_BUS_LVDS] = { 0x2c8, BIT(0) }, > + > + [RST_BUS_CODEC] = { 0x2d0, BIT(0) }, > + [RST_BUS_SPDIF] = { 0x2d0, BIT(1) }, > + [RST_BUS_THS] = { 0x2d0, BIT(8) }, > + [RST_BUS_I2S0] = { 0x2d0, BIT(12) }, > + [RST_BUS_I2S1] = { 0x2d0, BIT(13) }, > + [RST_BUS_I2S2] = { 0x2d0, BIT(14) }, > + > + [RST_BUS_I2C0] = { 0x2d8, BIT(0) }, > + [RST_BUS_I2C1] = { 0x2d8, BIT(1) }, > + [RST_BUS_I2C2] = { 0x2d8, BIT(2) }, > + [RST_BUS_SCR] = { 0x2d8, BIT(5) }, > + [RST_BUS_UART0] = { 0x2d8, BIT(16) }, > + [RST_BUS_UART1] = { 0x2d8, BIT(17) }, > + [RST_BUS_UART2] = { 0x2d8, BIT(18) }, > + [RST_BUS_UART3] = { 0x2d8, BIT(19) }, > + [RST_BUS_UART4] = { 0x2d8, BIT(20) }, > +}; > + > +static const struct sunxi_ccu_desc sun50i_a64_ccu_desc = { > + .ccu_clks = sun50i_a64_ccu_clks, > + .num_ccu_clks = ARRAY_SIZE(sun50i_a64_ccu_clks), > + > + .hw_clks = &sun50i_a64_hw_clks, > + > + .resets = sun50i_a64_ccu_resets, > + .num_resets = ARRAY_SIZE(sun50i_a64_ccu_resets), > +}; > + > +static void __init sun50i_a64_ccu_setup(struct device_node *node) > +{ > + void __iomem *reg; > + u32 val; > + > + reg = of_io_request_and_map(node, 0, of_node_full_name(node)); > + if (IS_ERR(reg)) { > + pr_err("%s: Could not map the clock registers\n", > + of_node_full_name(node)); > + return; > + } > + > + /* Force the PLL-Audio-1x divider to 4 */ > + val = readl(reg + SUN50I_A64_PLL_AUDIO_REG); > + val &= ~GENMASK(19, 16); > + writel(val | (3 << 16), reg + SUN50I_A64_PLL_AUDIO_REG); > + > + writel(0x515, reg + SUN50I_A64_PLL_MIPI_REG); > + > + sunxi_ccu_probe(node, reg, &sun50i_a64_ccu_desc); > +} > +CLK_OF_DECLARE(sun50i_a64_ccu, "allwinner,sun50i-a64-ccu", > + sun50i_a64_ccu_setup); > diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-a64.h b/drivers/clk/sunxi-ng/ccu-sun50i-a64.h > new file mode 100644 > index 000000000000..e3c77d92af1c > --- /dev/null > +++ b/drivers/clk/sunxi-ng/ccu-sun50i-a64.h > @@ -0,0 +1,68 @@ > +/* > + * Copyright 2016 Maxime Ripard > + * > + * Maxime Ripard <maxime.ripard@free-electrons.com> > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License as published by > + * the Free Software Foundation; either version 2 of the License, or > + * (at your option) any later version. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + */ > + > +#ifndef _CCU_SUN50I_A64_H_ > +#define _CCU_SUN50I_A64_H_ > + > +#include <dt-bindings/clock/sun50i-a64-ccu.h> > +#include <dt-bindings/reset/sun50i-a64-ccu.h> > + > +#define CLK_OSC_12M 0 > +#define CLK_PLL_CPUX 1 > +#define CLK_PLL_AUDIO_BASE 2 > +#define CLK_PLL_AUDIO 3 > +#define CLK_PLL_AUDIO_2X 4 > +#define CLK_PLL_AUDIO_4X 5 > +#define CLK_PLL_AUDIO_8X 6 > +#define CLK_PLL_VIDEO0 7 > +#define CLK_PLL_VIDEO0_2X 8 > +#define CLK_PLL_VE 9 > +#define CLK_PLL_DDR0 10 > +#define CLK_PLL_PERIPH0 11 > +#define CLK_PLL_PERIPH0_2X 12 > +#define CLK_PLL_PERIPH1 13 > +#define CLK_PLL_PERIPH1_2X 14 > +#define CLK_PLL_VIDEO1 15 > +#define CLK_PLL_GPU 16 > +#define CLK_PLL_MIPI 17 > +#define CLK_PLL_HSIC 18 > +#define CLK_PLL_DE 19 > +#define CLK_PLL_DDR1 20 > +#define CLK_CPUX 21 > +#define CLK_AXI 22 > +#define CLK_APB 23 This is listed but never implemented. > +#define CLK_AHB1 24 > +#define CLK_APB1 25 > +#define CLK_APB2 26 > +#define CLK_AHB2 27 > + > +/* All the bus gates are exported */ > + > +/* The first bunch of module clocks are exported */ > + > +#define CLK_DRAM 92 > + > +/* All the DRAM gates are exported */ > + > +/* Some more module clocks are exported */ > + > +#define CLK_MBUS 110 > + > +/* And the DSI and GPU module clock is exported */ > + > +#define CLK_NUMBER (CLK_GPU + 1) > + > +#endif /* _CCU_SUN50I_A64_H_ */ > diff --git a/include/dt-bindings/clock/sun50i-a64-ccu.h b/include/dt-bindings/clock/sun50i-a64-ccu.h > new file mode 100644 > index 000000000000..2abcd87c7a2d > --- /dev/null > +++ b/include/dt-bindings/clock/sun50i-a64-ccu.h > @@ -0,0 +1,132 @@ > +/* > + * Copyright (C) 2016 Maxime Ripard <maxime.ripard@free-electrons.com> > + * > + * This file is dual-licensed: you can use it either under the terms > + * of the GPL or the X11 license, at your option. Note that this dual > + * licensing only applies to this file, and not this project as a > + * whole. > + * > + * a) This file is free software; you can redistribute it and/or > + * modify it under the terms of the GNU General Public License as > + * published by the Free Software Foundation; either version 2 of the > + * License, or (at your option) any later version. > + * > + * This file is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * Or, alternatively, > + * > + * b) Permission is hereby granted, free of charge, to any person > + * obtaining a copy of this software and associated documentation > + * files (the "Software"), to deal in the Software without > + * restriction, including without limitation the rights to use, > + * copy, modify, merge, publish, distribute, sublicense, and/or > + * sell copies of the Software, and to permit persons to whom the > + * Software is furnished to do so, subject to the following > + * conditions: > + * > + * The above copyright notice and this permission notice shall be > + * included in all copies or substantial portions of the Software. > + * > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, > + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES > + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND > + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT > + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, > + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING > + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR > + * OTHER DEALINGS IN THE SOFTWARE. > + */ > + > +#ifndef _DT_BINDINGS_CLK_SUN50I_A64_H_ > +#define _DT_BINDINGS_CLK_SUN50I_A64_H_ > + > +#define CLK_BUS_MIPI_DSI 28 > +#define CLK_BUS_CE 29 > +#define CLK_BUS_DMA 30 > +#define CLK_BUS_MMC0 31 > +#define CLK_BUS_MMC1 32 > +#define CLK_BUS_MMC2 33 > +#define CLK_BUS_NAND 34 > +#define CLK_BUS_DRAM 35 > +#define CLK_BUS_EMAC 36 > +#define CLK_BUS_TS 37 > +#define CLK_BUS_HSTIMER 38 > +#define CLK_BUS_SPI0 39 > +#define CLK_BUS_SPI1 40 > +#define CLK_BUS_OTG 41 > +#define CLK_BUS_EHCI0 42 > +#define CLK_BUS_EHCI1 43 > +#define CLK_BUS_OHCI0 44 > +#define CLK_BUS_OHCI1 45 > +#define CLK_BUS_VE 46 > +#define CLK_BUS_TCON0 47 > +#define CLK_BUS_TCON1 48 > +#define CLK_BUS_DEINTERLACE 49 > +#define CLK_BUS_CSI 50 > +#define CLK_BUS_HDMI 51 > +#define CLK_BUS_DE 52 > +#define CLK_BUS_GPU 53 > +#define CLK_BUS_MSGBOX 54 > +#define CLK_BUS_SPINLOCK 55 > +#define CLK_BUS_CODEC 56 > +#define CLK_BUS_SPDIF 57 > +#define CLK_BUS_PIO 58 > +#define CLK_BUS_THS 59 > +#define CLK_BUS_I2S0 60 > +#define CLK_BUS_I2S1 61 > +#define CLK_BUS_I2S2 62 > +#define CLK_BUS_I2C0 63 > +#define CLK_BUS_I2C1 64 > +#define CLK_BUS_I2C2 65 > +#define CLK_BUS_SCR 66 > +#define CLK_BUS_UART0 67 > +#define CLK_BUS_UART1 68 > +#define CLK_BUS_UART2 69 > +#define CLK_BUS_UART3 70 > +#define CLK_BUS_UART4 71 > +#define CLK_BUS_DBG 72 > +#define CLK_THS 73 > +#define CLK_NAND 74 > +#define CLK_MMC0 75 > +#define CLK_MMC1 76 > +#define CLK_MMC2 77 > +#define CLK_TS 78 > +#define CLK_CE 79 > +#define CLK_SPI0 80 > +#define CLK_SPI1 81 > +#define CLK_I2S0 82 > +#define CLK_I2S1 83 > +#define CLK_I2S2 84 > +#define CLK_SPDIF 85 > +#define CLK_USB_PHY0 86 > +#define CLK_USB_PHY1 87 > +#define CLK_USB_HSIC 88 > +#define CLK_USB_HSIC_12M 89 > +#define CLK_USB_OHCI0 90 > +#define CLK_USB_OHCI1 91 > + > +#define CLK_DRAM_VE 93 > +#define CLK_DRAM_CSI 94 > +#define CLK_DRAM_DEINTERLACE 95 > +#define CLK_DRAM_TS 96 > +#define CLK_DE 97 > +#define CLK_TCON0 98 > +#define CLK_TCON1 99 > +#define CLK_DEINTERLACE 100 > +#define CLK_CSI_MISC 101 > +#define CLK_CSI_SCLK 102 > +#define CLK_CSI_MCLK 103 > +#define CLK_VE 104 > +#define CLK_AC_DIG 105 > +#define CLK_AC_DIG_4X 106 > +#define CLK_AVS 107 > +#define CLK_HDMI 108 > +#define CLK_HDMI_DDC 109 > + > +#define CLK_DSI_DPHY 111 > +#define CLK_GPU 112 > + > +#endif /* _DT_BINDINGS_CLK_SUN50I_H_ */ > diff --git a/include/dt-bindings/reset/sun50i-a64-ccu.h b/include/dt-bindings/reset/sun50i-a64-ccu.h > new file mode 100644 > index 000000000000..e61fac294d73 > --- /dev/null > +++ b/include/dt-bindings/reset/sun50i-a64-ccu.h > @@ -0,0 +1,97 @@ > +/* > + * Copyright (C) 2016 Maxime Ripard <maxime.ripard@free-electrons.com> > + * > + * This file is dual-licensed: you can use it either under the terms > + * of the GPL or the X11 license, at your option. Note that this dual > + * licensing only applies to this file, and not this project as a > + * whole. > + * > + * a) This file is free software; you can redistribute it and/or > + * modify it under the terms of the GNU General Public License as > + * published by the Free Software Foundation; either version 2 of the > + * License, or (at your option) any later version. > + * > + * This file is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * Or, alternatively, > + * > + * b) Permission is hereby granted, free of charge, to any person > + * obtaining a copy of this software and associated documentation > + * files (the "Software"), to deal in the Software without > + * restriction, including without limitation the rights to use, > + * copy, modify, merge, publish, distribute, sublicense, and/or > + * sell copies of the Software, and to permit persons to whom the > + * Software is furnished to do so, subject to the following > + * conditions: > + * > + * The above copyright notice and this permission notice shall be > + * included in all copies or substantial portions of the Software. > + * > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, > + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES > + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND > + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT > + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, > + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING > + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR > + * OTHER DEALINGS IN THE SOFTWARE. > + */ > + > +#ifndef _DT_BINDINGS_RST_SUN50I_A64_H_ > +#define _DT_BINDINGS_RST_SUN50I_A64_H_ > + > +#define RST_USB_PHY0 0 > +#define RST_USB_PHY1 1 > +#define RST_USB_HSIC 2 There's also a DRAM reset in 0xf4 (DRAM configuration) > +#define RST_MBUS 3 > +#define RST_BUS_MIPI_DSI 4 > +#define RST_BUS_CE 5 > +#define RST_BUS_DMA 6 > +#define RST_BUS_MMC0 7 > +#define RST_BUS_MMC1 8 > +#define RST_BUS_MMC2 9 > +#define RST_BUS_NAND 10 > +#define RST_BUS_DRAM 11 > +#define RST_BUS_EMAC 12 > +#define RST_BUS_TS 13 > +#define RST_BUS_HSTIMER 14 > +#define RST_BUS_SPI0 15 > +#define RST_BUS_SPI1 16 > +#define RST_BUS_OTG 17 > +#define RST_BUS_EHCI0 18 > +#define RST_BUS_EHCI1 19 > +#define RST_BUS_OHCI0 20 > +#define RST_BUS_OHCI1 21 > +#define RST_BUS_VE 22 > +#define RST_BUS_TCON0 23 > +#define RST_BUS_TCON1 24 > +#define RST_BUS_DEINTERLACE 25 > +#define RST_BUS_CSI 26 > +#define RST_BUS_HDMI0 27 > +#define RST_BUS_HDMI1 28 > +#define RST_BUS_DE 29 > +#define RST_BUS_GPU 30 > +#define RST_BUS_MSGBOX 31 > +#define RST_BUS_SPINLOCK 32 > +#define RST_BUS_DBG 33 > +#define RST_BUS_LVDS 34 > +#define RST_BUS_CODEC 35 > +#define RST_BUS_SPDIF 36 > +#define RST_BUS_THS 37 > +#define RST_BUS_I2S0 38 > +#define RST_BUS_I2S1 39 > +#define RST_BUS_I2S2 40 > +#define RST_BUS_I2C0 41 > +#define RST_BUS_I2C1 42 > +#define RST_BUS_I2C2 43 > +#define RST_BUS_SCR 44 > +#define RST_BUS_UART0 45 > +#define RST_BUS_UART1 46 > +#define RST_BUS_UART2 47 > +#define RST_BUS_UART3 48 > +#define RST_BUS_UART4 49 > + > +#endif /* _DT_BINDINGS_RST_SUN8I_H3_H_ */ > -- > 2.9.3 > I didn't look at the 2 large arrays of clks. Everything else checks out. Regards ChenYu ^ permalink raw reply [flat|nested] 35+ messages in thread
* [PATCH v2 1/4] clk: sunxi-ng: Add A64 clocks @ 2016-09-10 3:24 ` Chen-Yu Tsai 0 siblings, 0 replies; 35+ messages in thread From: Chen-Yu Tsai @ 2016-09-10 3:24 UTC (permalink / raw) To: linux-arm-kernel On Sat, Sep 10, 2016 at 4:10 AM, Maxime Ripard <maxime.ripard@free-electrons.com> wrote: > Add the A64 CCU clocks set. > > Acked-by: Rob Herring <robh@kernel.org> > Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> > --- > .../devicetree/bindings/clock/sunxi-ccu.txt | 1 + > drivers/clk/sunxi-ng/Kconfig | 11 + > drivers/clk/sunxi-ng/Makefile | 1 + > drivers/clk/sunxi-ng/ccu-sun50i-a64.c | 870 +++++++++++++++++++++ > drivers/clk/sunxi-ng/ccu-sun50i-a64.h | 68 ++ > include/dt-bindings/clock/sun50i-a64-ccu.h | 132 ++++ > include/dt-bindings/reset/sun50i-a64-ccu.h | 97 +++ > 7 files changed, 1180 insertions(+) > create mode 100644 drivers/clk/sunxi-ng/ccu-sun50i-a64.c > create mode 100644 drivers/clk/sunxi-ng/ccu-sun50i-a64.h > create mode 100644 include/dt-bindings/clock/sun50i-a64-ccu.h > create mode 100644 include/dt-bindings/reset/sun50i-a64-ccu.h > > diff --git a/Documentation/devicetree/bindings/clock/sunxi-ccu.txt b/Documentation/devicetree/bindings/clock/sunxi-ccu.txt > index 3868458a5feb..74d44a4273f2 100644 > --- a/Documentation/devicetree/bindings/clock/sunxi-ccu.txt > +++ b/Documentation/devicetree/bindings/clock/sunxi-ccu.txt > @@ -7,6 +7,7 @@ Required properties : > - "allwinner,sun8i-a23-ccu" > - "allwinner,sun8i-a33-ccu" > - "allwinner,sun8i-h3-ccu" > + - "allwinner,sun50i-a64-ccu" > > - reg: Must contain the registers base address and length > - clocks: phandle to the oscillators feeding the CCU. Two are needed: > diff --git a/drivers/clk/sunxi-ng/Kconfig b/drivers/clk/sunxi-ng/Kconfig > index 254d9526c018..71e0c21c3545 100644 > --- a/drivers/clk/sunxi-ng/Kconfig > +++ b/drivers/clk/sunxi-ng/Kconfig > @@ -101,4 +101,15 @@ config SUN8I_H3_CCU > select SUNXI_CCU_PHASE > default MACH_SUN8I > > +config SUN50I_A64_CCU > + bool "Support for the Allwinner A64 CCU" > + select SUNXI_CCU_DIV > + select SUNXI_CCU_NK > + select SUNXI_CCU_NKM > + select SUNXI_CCU_NKMP > + select SUNXI_CCU_NM > + select SUNXI_CCU_MP > + select SUNXI_CCU_PHASE > + default ARM64 && ARCH_SUNXI > + > endif > diff --git a/drivers/clk/sunxi-ng/Makefile b/drivers/clk/sunxi-ng/Makefile > index 106cba27c331..964f22091a10 100644 > --- a/drivers/clk/sunxi-ng/Makefile > +++ b/drivers/clk/sunxi-ng/Makefile > @@ -22,3 +22,4 @@ obj-$(CONFIG_SUN6I_A31_CCU) += ccu-sun6i-a31.o > obj-$(CONFIG_SUN8I_A23_CCU) += ccu-sun8i-a23.o > obj-$(CONFIG_SUN8I_A33_CCU) += ccu-sun8i-a33.o > obj-$(CONFIG_SUN8I_H3_CCU) += ccu-sun8i-h3.o > +obj-$(CONFIG_SUN50I_A64_CCU) += ccu-sun50i-a64.o > diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c > new file mode 100644 > index 000000000000..d51ee416f515 > --- /dev/null > +++ b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c > @@ -0,0 +1,870 @@ > +/* > + * Copyright (c) 2016 Maxime Ripard. All rights reserved. > + * > + * This software is licensed under the terms of the GNU General Public > + * License version 2, as published by the Free Software Foundation, and > + * may be copied, distributed, and modified under those terms. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + */ > + > +#include <linux/clk-provider.h> > +#include <linux/of_address.h> > + > +#include "ccu_common.h" > +#include "ccu_reset.h" > + > +#include "ccu_div.h" > +#include "ccu_gate.h" > +#include "ccu_mp.h" > +#include "ccu_mult.h" > +#include "ccu_nk.h" > +#include "ccu_nkm.h" > +#include "ccu_nkmp.h" > +#include "ccu_nm.h" > +#include "ccu_phase.h" > + > +#include "ccu-sun50i-a64.h" > + > +static SUNXI_CCU_NKMP_WITH_GATE_LOCK(pll_cpux_clk, "pll-cpux", > + "osc24M", 0x000, > + 8, 5, /* N */ > + 4, 2, /* K */ > + 0, 2, /* M */ > + 16, 2, /* P */ You need a max = 4 for P. > + BIT(31), /* gate */ > + BIT(28), /* lock */ > + 0); > + > +/* > + * The Audio PLL is supposed to have 4 outputs: 3 fixed factors from > + * the base (2x, 4x and 8x), and one variable divider (the one true > + * pll audio). > + * > + * We don't have any need for the variable divider for now, so we just > + * hardcode it to match with the clock names > + */ > +#define SUN50I_A64_PLL_AUDIO_REG 0x008 > + > +static SUNXI_CCU_NM_WITH_GATE_LOCK(pll_audio_base_clk, "pll-audio-base", > + "osc24M", 0x008, > + 8, 7, /* N */ > + 0, 5, /* M */ > + BIT(31), /* gate */ > + BIT(28), /* lock */ > + 0); > + > +static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video0_clk, "pll-video0", > + "osc24M", 0x010, > + 8, 7, /* N */ > + 0, 4, /* M */ > + BIT(24), /* frac enable */ > + BIT(25), /* frac select */ > + 270000000, /* frac rate 0 */ > + 297000000, /* frac rate 1 */ > + BIT(31), /* gate */ > + BIT(28), /* lock */ > + 0); > + > +static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_ve_clk, "pll-ve", > + "osc24M", 0x018, > + 8, 7, /* N */ > + 0, 4, /* M */ > + BIT(24), /* frac enable */ > + BIT(25), /* frac select */ > + 270000000, /* frac rate 0 */ > + 297000000, /* frac rate 1 */ > + BIT(31), /* gate */ > + BIT(28), /* lock */ > + 0); > + > +static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_ddr0_clk, "pll-ddr0", > + "osc24M", 0x020, > + 8, 5, /* N */ > + 4, 2, /* K */ > + 0, 2, /* M */ > + BIT(31), /* gate */ > + BIT(28), /* lock */ > + 0); > + > +static SUNXI_CCU_NK_WITH_GATE_LOCK_POSTDIV(pll_periph0_clk, "pll-periph0", > + "osc24M", 0x028, > + 8, 5, /* N */ > + 4, 2, /* K */ The manual says to give preference to K >= 2. I suggest swapping N/K and leaving a note about it, so the actual K is in the inner loop (see ccu_nk.c) of the factor calculation. > + BIT(31), /* gate */ > + BIT(28), /* lock */ > + 2, /* post-div */ > + 0); > + > +static SUNXI_CCU_NK_WITH_GATE_LOCK_POSTDIV(pll_periph1_clk, "pll-periph1", > + "osc24M", 0x02c, > + 8, 5, /* N */ > + 4, 2, /* K */ > + BIT(31), /* gate */ > + BIT(28), /* lock */ > + 2, /* post-div */ > + 0); Same here. > + > +static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video1_clk, "pll-video1", > + "osc24M", 0x030, > + 8, 7, /* N */ > + 0, 4, /* M */ > + BIT(24), /* frac enable */ > + BIT(25), /* frac select */ > + 270000000, /* frac rate 0 */ > + 297000000, /* frac rate 1 */ > + BIT(31), /* gate */ > + BIT(28), /* lock */ > + 0); > + > +static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_gpu_clk, "pll-gpu", > + "osc24M", 0x038, > + 8, 7, /* N */ > + 0, 4, /* M */ > + BIT(24), /* frac enable */ > + BIT(25), /* frac select */ > + 270000000, /* frac rate 0 */ > + 297000000, /* frac rate 1 */ > + BIT(31), /* gate */ > + BIT(28), /* lock */ > + 0); > + > +/* > + * The output function can be changed to something more complex that > + * we do not handle yet. > + * > + * Hardcode the mode so that we don't fall in that case. > + */ > +#define SUN50I_A64_PLL_MIPI_REG 0x040 > + > +static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_mipi_clk, "pll-mipi", > + "pll-video0", 0x040, > + 8, 4, /* N */ > + 4, 2, /* K */ You need a table for K. (Manual says K >= 2). > + 0, 4, /* M */ > + BIT(31), /* gate */ > + BIT(28), /* lock */ > + 0); > + > +static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_hsic_clk, "pll-hsic", > + "osc24M", 0x044, > + 8, 7, /* N */ > + 0, 4, /* M */ > + BIT(24), /* frac enable */ > + BIT(25), /* frac select */ > + 270000000, /* frac rate 0 */ > + 297000000, /* frac rate 1 */ > + BIT(31), /* gate */ > + BIT(28), /* lock */ > + 0); > + > +static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_de_clk, "pll-de", > + "osc24M", 0x048, > + 8, 7, /* N */ > + 0, 4, /* M */ > + BIT(24), /* frac enable */ > + BIT(25), /* frac select */ > + 270000000, /* frac rate 0 */ > + 297000000, /* frac rate 1 */ > + BIT(31), /* gate */ > + BIT(28), /* lock */ > + 0); > + > +static SUNXI_CCU_NM_WITH_GATE_LOCK(pll_ddr1_clk, "pll-ddr1", > + "osc24M", 0x04c, > + 8, 7, /* N */ > + 0, 2, /* M */ > + BIT(31), /* gate */ > + BIT(28), /* lock */ > + 0); > + > +static const char * const cpux_parents[] = { "osc32k", "osc24M", > + "pll-cpux" , "pll-cpux" }; > +static SUNXI_CCU_MUX(cpux_clk, "cpux", cpux_parents, > + 0x050, 16, 2, CLK_IS_CRITICAL); > + > +static SUNXI_CCU_M(axi_clk, "axi", "cpux", 0x050, 0, 2, 0); > + > +static const char * const ahb1_parents[] = { "osc32k", "osc24M", > + "axi" , "pll-periph0" }; > +static struct ccu_div ahb1_clk = { > + .div = _SUNXI_CCU_DIV_FLAGS(4, 2, CLK_DIVIDER_POWER_OF_TWO), > + > + .mux = { > + .shift = 12, > + .width = 2, > + > + .variable_prediv = { > + .index = 3, > + .shift = 6, > + .width = 2, > + }, > + }, > + > + .common = { > + .reg = 0x054, > + .features = CCU_FEATURE_VARIABLE_PREDIV, > + .hw.init = CLK_HW_INIT_PARENTS("ahb1", > + ahb1_parents, > + &ccu_div_ops, > + 0), > + }, > +}; > + > +static struct clk_div_table apb1_div_table[] = { > + { .val = 0, .div = 2 }, > + { .val = 1, .div = 2 }, > + { .val = 2, .div = 4 }, > + { .val = 3, .div = 8 }, > + { /* Sentinel */ }, > +}; > +static SUNXI_CCU_DIV_TABLE(apb1_clk, "apb1", "ahb1", > + 0x054, 8, 2, apb1_div_table, 0); > + > +static const char * const apb2_parents[] = { "osc32k", "osc24M", > + "pll-periph0-2x" , > + "pll-periph0-2x" }; > +static SUNXI_CCU_MP_WITH_MUX(apb2_clk, "apb2", apb2_parents, 0x058, > + 0, 5, /* M */ > + 16, 2, /* P */ > + 24, 2, /* mux */ > + 0); > + > +static const char * const ahb2_parents[] = { "ahb1" , "pll-periph0" }; > +static const struct ccu_mux_fixed_prediv ahb2_fixed_predivs[] = { > + { .index = 1, .div = 2 }, > +}; > +static struct ccu_mux ahb2_clk = { > + .mux = { > + .shift = 0, > + .width = 1, > + .fixed_predivs = ahb2_fixed_predivs, > + .n_predivs = ARRAY_SIZE(ahb2_fixed_predivs), > + }, > + > + .common = { > + .reg = 0x05c, > + .features = CCU_FEATURE_FIXED_PREDIV, > + .hw.init = CLK_HW_INIT_PARENTS("ahb2", > + ahb2_parents, > + &ccu_mux_ops, > + 0), > + }, > +}; > + > +static SUNXI_CCU_GATE(bus_mipi_dsi_clk, "bus-mipi-dsi", "ahb1", > + 0x060, BIT(1), 0); > +static SUNXI_CCU_GATE(bus_ce_clk, "bus-ce", "ahb1", > + 0x060, BIT(5), 0); > +static SUNXI_CCU_GATE(bus_dma_clk, "bus-dma", "ahb1", > + 0x060, BIT(6), 0); > +static SUNXI_CCU_GATE(bus_mmc0_clk, "bus-mmc0", "ahb1", > + 0x060, BIT(8), 0); > +static SUNXI_CCU_GATE(bus_mmc1_clk, "bus-mmc1", "ahb1", > + 0x060, BIT(9), 0); > +static SUNXI_CCU_GATE(bus_mmc2_clk, "bus-mmc2", "ahb1", > + 0x060, BIT(10), 0); > +static SUNXI_CCU_GATE(bus_nand_clk, "bus-nand", "ahb1", > + 0x060, BIT(13), 0); > +static SUNXI_CCU_GATE(bus_dram_clk, "bus-dram", "ahb1", > + 0x060, BIT(14), 0); > +static SUNXI_CCU_GATE(bus_emac_clk, "bus-emac", "ahb2", > + 0x060, BIT(17), 0); > +static SUNXI_CCU_GATE(bus_ts_clk, "bus-ts", "ahb1", > + 0x060, BIT(18), 0); > +static SUNXI_CCU_GATE(bus_hstimer_clk, "bus-hstimer", "ahb1", > + 0x060, BIT(19), 0); > +static SUNXI_CCU_GATE(bus_spi0_clk, "bus-spi0", "ahb1", > + 0x060, BIT(20), 0); > +static SUNXI_CCU_GATE(bus_spi1_clk, "bus-spi1", "ahb1", > + 0x060, BIT(21), 0); > +static SUNXI_CCU_GATE(bus_otg_clk, "bus-otg", "ahb1", > + 0x060, BIT(23), 0); > +static SUNXI_CCU_GATE(bus_ehci0_clk, "bus-ehci0", "ahb1", > + 0x060, BIT(24), 0); > +static SUNXI_CCU_GATE(bus_ehci1_clk, "bus-ehci1", "ahb2", > + 0x060, BIT(25), 0); > +static SUNXI_CCU_GATE(bus_ohci0_clk, "bus-ohci0", "ahb1", > + 0x060, BIT(28), 0); > +static SUNXI_CCU_GATE(bus_ohci1_clk, "bus-ohci1", "ahb2", > + 0x060, BIT(29), 0); > + > +static SUNXI_CCU_GATE(bus_ve_clk, "bus-ve", "ahb1", > + 0x064, BIT(0), 0); > +static SUNXI_CCU_GATE(bus_tcon0_clk, "bus-tcon0", "ahb1", > + 0x064, BIT(3), 0); > +static SUNXI_CCU_GATE(bus_tcon1_clk, "bus-tcon1", "ahb1", > + 0x064, BIT(4), 0); > +static SUNXI_CCU_GATE(bus_deinterlace_clk, "bus-deinterlace", "ahb1", > + 0x064, BIT(5), 0); > +static SUNXI_CCU_GATE(bus_csi_clk, "bus-csi", "ahb1", > + 0x064, BIT(8), 0); > +static SUNXI_CCU_GATE(bus_hdmi_clk, "bus-hdmi", "ahb1", > + 0x064, BIT(11), 0); > +static SUNXI_CCU_GATE(bus_de_clk, "bus-de", "ahb1", > + 0x064, BIT(12), 0); > +static SUNXI_CCU_GATE(bus_gpu_clk, "bus-gpu", "ahb1", > + 0x064, BIT(20), 0); > +static SUNXI_CCU_GATE(bus_msgbox_clk, "bus-msgbox", "ahb1", > + 0x064, BIT(21), 0); > +static SUNXI_CCU_GATE(bus_spinlock_clk, "bus-spinlock", "ahb1", > + 0x064, BIT(22), 0); > + > +static SUNXI_CCU_GATE(bus_codec_clk, "bus-codec", "apb1", > + 0x068, BIT(0), 0); > +static SUNXI_CCU_GATE(bus_spdif_clk, "bus-spdif", "apb1", > + 0x068, BIT(1), 0); > +static SUNXI_CCU_GATE(bus_pio_clk, "bus-pio", "apb1", > + 0x068, BIT(5), 0); > +static SUNXI_CCU_GATE(bus_ths_clk, "bus-ths", "apb1", > + 0x068, BIT(8), 0); > +static SUNXI_CCU_GATE(bus_i2s0_clk, "bus-i2s0", "apb1", > + 0x068, BIT(12), 0); > +static SUNXI_CCU_GATE(bus_i2s1_clk, "bus-i2s1", "apb1", > + 0x068, BIT(13), 0); > +static SUNXI_CCU_GATE(bus_i2s2_clk, "bus-i2s2", "apb1", > + 0x068, BIT(14), 0); > + > +static SUNXI_CCU_GATE(bus_i2c0_clk, "bus-i2c0", "apb2", > + 0x06c, BIT(0), 0); > +static SUNXI_CCU_GATE(bus_i2c1_clk, "bus-i2c1", "apb2", > + 0x06c, BIT(1), 0); > +static SUNXI_CCU_GATE(bus_i2c2_clk, "bus-i2c2", "apb2", > + 0x06c, BIT(2), 0); > +static SUNXI_CCU_GATE(bus_scr_clk, "bus-scr", "apb2", > + 0x06c, BIT(5), 0); > +static SUNXI_CCU_GATE(bus_uart0_clk, "bus-uart0", "apb2", > + 0x06c, BIT(16), 0); > +static SUNXI_CCU_GATE(bus_uart1_clk, "bus-uart1", "apb2", > + 0x06c, BIT(17), 0); > +static SUNXI_CCU_GATE(bus_uart2_clk, "bus-uart2", "apb2", > + 0x06c, BIT(18), 0); > +static SUNXI_CCU_GATE(bus_uart3_clk, "bus-uart3", "apb2", > + 0x06c, BIT(19), 0); > +static SUNXI_CCU_GATE(bus_uart4_clk, "bus-uart4", "apb2", > + 0x06c, BIT(20), 0); > + > +static SUNXI_CCU_GATE(bus_dbg_clk, "bus-dbg", "ahb1", > + 0x070, BIT(7), 0); > + > +static struct clk_div_table ths_div_table[] = { > + { .val = 0, .div = 1 }, > + { .val = 1, .div = 2 }, > + { .val = 2, .div = 4 }, > + { .val = 3, .div = 6 }, > +}; > +static SUNXI_CCU_DIV_TABLE_WITH_GATE(ths_clk, "ths", "osc24M", > + 0x074, 0, 2, ths_div_table, BIT(31), 0); Even though the mux has only one valid parent, I suggest you still implement it, in case some bogus value gets put in before the kernel loads. > + > +static const char * const mod0_default_parents[] = { "osc24M", "pll-periph0", > + "pll-periph1" }; > +static SUNXI_CCU_MP_WITH_MUX_GATE(nand_clk, "nand", mod0_default_parents, 0x080, > + 0, 4, /* M */ > + 16, 2, /* P */ > + 24, 2, /* mux */ > + BIT(31), /* gate */ > + 0); > + > +static const char * const mmc_default_parents[] = { "osc24M", "pll-periph0-2x", > + "pll-periph1-2x" }; > +static SUNXI_CCU_MP_WITH_MUX_GATE(mmc0_clk, "mmc0", mmc_default_parents, 0x088, > + 0, 4, /* M */ > + 16, 2, /* P */ > + 24, 2, /* mux */ > + BIT(31), /* gate */ > + 0); > + > +static SUNXI_CCU_MP_WITH_MUX_GATE(mmc1_clk, "mmc1", mmc_default_parents, 0x08c, > + 0, 4, /* M */ > + 16, 2, /* P */ > + 24, 2, /* mux */ > + BIT(31), /* gate */ > + 0); > + > +static SUNXI_CCU_MP_WITH_MUX_GATE(mmc2_clk, "mmc2", mmc_default_parents, 0x090, > + 0, 4, /* M */ > + 16, 2, /* P */ > + 24, 2, /* mux */ > + BIT(31), /* gate */ > + 0); > + > +static const char * const ts_parents[] = { "osc24M", "pll-periph0", }; > +static SUNXI_CCU_MP_WITH_MUX_GATE(ts_clk, "ts", ts_parents, 0x098, > + 0, 4, /* M */ > + 16, 2, /* P */ > + 24, 2, /* mux */ Manual says the mux is 4 bits wide. > + BIT(31), /* gate */ > + 0); > + > +static SUNXI_CCU_MP_WITH_MUX_GATE(ce_clk, "ce", mmc_default_parents, 0x09c, > + 0, 4, /* M */ > + 16, 2, /* P */ > + 24, 2, /* mux */ > + BIT(31), /* gate */ > + 0); > + > + > +static SUNXI_CCU_MP_WITH_MUX_GATE(spi0_clk, "spi0", mod0_default_parents, 0x0a0, > + 0, 4, /* M */ > + 16, 2, /* P */ > + 24, 2, /* mux */ > + BIT(31), /* gate */ > + 0); > + > +static SUNXI_CCU_MP_WITH_MUX_GATE(spi1_clk, "spi1", mod0_default_parents, 0x0a4, > + 0, 4, /* M */ > + 16, 2, /* P */ > + 24, 2, /* mux */ > + BIT(31), /* gate */ > + 0); > + > +static const char * const i2s_parents[] = { "pll-audio-8x", "pll-audio-4x", > + "pll-audio-2x", "pll-audio" }; > +static SUNXI_CCU_MUX_WITH_GATE(i2s0_clk, "i2s0", i2s_parents, > + 0x0b0, 16, 2, BIT(31), 0); > + > +static SUNXI_CCU_MUX_WITH_GATE(i2s1_clk, "i2s1", i2s_parents, > + 0x0b4, 16, 2, BIT(31), 0); > + > +static SUNXI_CCU_MUX_WITH_GATE(i2s2_clk, "i2s2", i2s_parents, > + 0x0b8, 16, 2, BIT(31), 0); > + > +static SUNXI_CCU_M_WITH_GATE(spdif_clk, "spdif", "pll-audio", > + 0x0c0, 0, 4, BIT(31), 0); CLK_SET_PARENT_RATE for the above audio clocks? > + > +static SUNXI_CCU_GATE(usb_phy0_clk, "usb-phy0", "osc24M", > + 0x0cc, BIT(8), 0); > +static SUNXI_CCU_GATE(usb_phy1_clk, "usb-phy1", "osc24M", > + 0x0cc, BIT(9), 0); > +static SUNXI_CCU_GATE(usb_hsic_clk, "usb-hsic", "pll-hsic", > + 0x0cc, BIT(10), 0); > +static SUNXI_CCU_GATE(usb_hsic_12m_clk, "usb-hsic-12M", "osc12M", > + 0x0cc, BIT(11), 0); > +static SUNXI_CCU_GATE(usb_ohci0_clk, "usb-ohci0", "osc12M", > + 0x0cc, BIT(16), 0); > +static SUNXI_CCU_GATE(usb_ohci1_clk, "usb-ohci1", "usb-ohci0", > + 0x0cc, BIT(17), 0); I guess we aren't modeling the 2 OHCI 12M muxes? > + > +static const char * const dram_parents[] = { "pll-ddr0", "pll-ddr1" }; > +static SUNXI_CCU_M_WITH_MUX(dram_clk, "dram", dram_parents, > + 0x0f4, 0, 4, 20, 2, CLK_IS_CRITICAL); > + > +static SUNXI_CCU_GATE(dram_ve_clk, "dram-ve", "dram", > + 0x100, BIT(0), 0); > +static SUNXI_CCU_GATE(dram_csi_clk, "dram-csi", "dram", > + 0x100, BIT(1), 0); > +static SUNXI_CCU_GATE(dram_deinterlace_clk, "dram-deinterlace", "dram", > + 0x100, BIT(2), 0); > +static SUNXI_CCU_GATE(dram_ts_clk, "dram-ts", "dram", > + 0x100, BIT(3), 0); > + > +static const char * const de_parents[] = { "pll-periph0-2x", "pll-de" }; > +static SUNXI_CCU_M_WITH_MUX_GATE(de_clk, "de", de_parents, > + 0x104, 0, 4, 24, 3, BIT(31), 0); > + > +static const char * const tcon0_parents[] = { "pll-mipi", "pll-video0-2x" }; > +static const u8 tcon0_table[] = { 0, 2, }; > +static SUNXI_CCU_MUX_TABLE_WITH_GATE(tcon0_clk, "tcon0", tcon0_parents, > + tcon0_table, 0x118, 24, 3, BIT(31), 0); > + > +static const char * const tcon1_parents[] = { "pll-video0", "pll-video1" }; > +static const u8 tcon1_table[] = { 0, 2, }; > +struct ccu_div tcon1_clk = { > + .enable = BIT(31), > + .div = _SUNXI_CCU_DIV(0, 4), > + .mux = _SUNXI_CCU_MUX_TABLE(24, 3, tcon1_table), > + .common = { > + .reg = 0x11c, > + .hw.init = CLK_HW_INIT_PARENTS("tcon1", > + tcon1_parents, > + &ccu_div_ops, > + 0), > + }, > +}; CLK_SET_PARENT_RATE for the TCON clocks? > + > +static const char * const deinterlace_parents[] = { "pll-periph0", "pll-periph1" }; > +static SUNXI_CCU_M_WITH_MUX_GATE(deinterlace_clk, "deinterlace", deinterlace_parents, > + 0x124, 0, 4, 24, 3, BIT(31), 0); > + > +static SUNXI_CCU_GATE(csi_misc_clk, "csi-misc", "osc24M", > + 0x130, BIT(31), 0); > + > +static const char * const csi_sclk_parents[] = { "pll-periph0", "pll-periph1" }; > +static SUNXI_CCU_M_WITH_MUX_GATE(csi_sclk_clk, "csi-sclk", csi_sclk_parents, > + 0x134, 16, 4, 24, 3, BIT(31), 0); > + > +static const char * const csi_mclk_parents[] = { "osc24M", "pll-video1", "pll-periph1" }; > +static SUNXI_CCU_M_WITH_MUX_GATE(csi_mclk_clk, "csi-mclk", csi_mclk_parents, > + 0x134, 0, 5, 8, 3, BIT(15), 0); > + > +static SUNXI_CCU_M_WITH_GATE(ve_clk, "ve", "pll-ve", > + 0x13c, 16, 3, BIT(31), 0); > + > +static SUNXI_CCU_GATE(ac_dig_clk, "ac-dig", "pll-audio", > + 0x140, BIT(31), 0); > + > +static SUNXI_CCU_GATE(ac_dig_4x_clk, "ac-dig-4x", "pll-audio-4x", > + 0x140, BIT(30), 0); CLK_SET_PARENT_RATE for the above audio clocks? > + > +static SUNXI_CCU_GATE(avs_clk, "avs", "osc24M", > + 0x144, BIT(31), 0); > + > +static const char * const hdmi_parents[] = { "pll-video0", "pll-video1" }; > +static SUNXI_CCU_M_WITH_MUX_GATE(hdmi_clk, "hdmi", hdmi_parents, > + 0x150, 0, 4, 24, 2, BIT(31), 0); Might need CLK_SET_PARENT_RATE for hdmi? > + > +static SUNXI_CCU_GATE(hdmi_ddc_clk, "hdmi-ddc", "osc24M", > + 0x154, BIT(31), 0); > + > +static const char * const mbus_parents[] = { "osc24M", "pll-periph0-2x", > + "pll-ddr0", "pll-ddr1" }; > +static SUNXI_CCU_M_WITH_MUX_GATE(mbus_clk, "mbus", mbus_parents, > + 0x15c, 0, 3, 24, 2, BIT(31), CLK_IS_CRITICAL); > + > +static const char * const dsi_dphy_parents[] = { "pll-video0", "pll-periph0" }; You need a mux table = { 0, 2 } here. > +static SUNXI_CCU_M_WITH_MUX_GATE(dsi_dphy_clk, "dsi-dphy", dsi_dphy_parents, > + 0x168, 0, 3, 24, 2, BIT(31), 0); > + > +static SUNXI_CCU_M_WITH_GATE(gpu_clk, "gpu", "pll-gpu", > + 0x1a0, 0, 3, BIT(31), 0); CLK_SET_PARENT_RATE for the GPU clock? > + > +/* Fixed Factor clocks */ > +static CLK_FIXED_FACTOR(osc12M_clk, "osc12M", "osc24M", 1, 2, 0); > + > +/* We hardcode the divider to 4 for now */ > +static CLK_FIXED_FACTOR(pll_audio_clk, "pll-audio", > + "pll-audio-base", 4, 1, CLK_SET_RATE_PARENT); > +static CLK_FIXED_FACTOR(pll_audio_2x_clk, "pll-audio-2x", > + "pll-audio-base", 2, 1, CLK_SET_RATE_PARENT); > +static CLK_FIXED_FACTOR(pll_audio_4x_clk, "pll-audio-4x", > + "pll-audio-base", 1, 1, CLK_SET_RATE_PARENT); > +static CLK_FIXED_FACTOR(pll_audio_8x_clk, "pll-audio-8x", > + "pll-audio-base", 1, 2, CLK_SET_RATE_PARENT); > +static CLK_FIXED_FACTOR(pll_periph0_2x_clk, "pll-periph0-2x", > + "pll-periph0", 1, 2, 0); > +static CLK_FIXED_FACTOR(pll_periph1_2x_clk, "pll-periph1-2x", > + "pll-periph1", 1, 2, 0); > +static CLK_FIXED_FACTOR(pll_video0_2x_clk, "pll-video0-2x", > + "pll-video0", 1, 2, 0); CLK_SET_PARENT_RATE for pll-video0-2x. > + > +static struct ccu_common *sun50i_a64_ccu_clks[] = { > + &pll_cpux_clk.common, > + &pll_audio_base_clk.common, > + &pll_video0_clk.common, > + &pll_ve_clk.common, > + &pll_ddr0_clk.common, > + &pll_periph0_clk.common, > + &pll_periph1_clk.common, > + &pll_video1_clk.common, > + &pll_gpu_clk.common, > + &pll_mipi_clk.common, > + &pll_hsic_clk.common, > + &pll_de_clk.common, > + &pll_ddr1_clk.common, > + &cpux_clk.common, > + &axi_clk.common, > + &ahb1_clk.common, > + &apb1_clk.common, > + &apb2_clk.common, > + &ahb2_clk.common, > + &bus_mipi_dsi_clk.common, > + &bus_ce_clk.common, > + &bus_dma_clk.common, > + &bus_mmc0_clk.common, > + &bus_mmc1_clk.common, > + &bus_mmc2_clk.common, > + &bus_nand_clk.common, > + &bus_dram_clk.common, > + &bus_emac_clk.common, > + &bus_ts_clk.common, > + &bus_hstimer_clk.common, > + &bus_spi0_clk.common, > + &bus_spi1_clk.common, > + &bus_otg_clk.common, > + &bus_ehci0_clk.common, > + &bus_ehci1_clk.common, > + &bus_ohci0_clk.common, > + &bus_ohci1_clk.common, > + &bus_ve_clk.common, > + &bus_tcon0_clk.common, > + &bus_tcon1_clk.common, > + &bus_deinterlace_clk.common, > + &bus_csi_clk.common, > + &bus_hdmi_clk.common, > + &bus_de_clk.common, > + &bus_gpu_clk.common, > + &bus_msgbox_clk.common, > + &bus_spinlock_clk.common, > + &bus_codec_clk.common, > + &bus_spdif_clk.common, > + &bus_pio_clk.common, > + &bus_ths_clk.common, > + &bus_i2s0_clk.common, > + &bus_i2s1_clk.common, > + &bus_i2s2_clk.common, > + &bus_i2c0_clk.common, > + &bus_i2c1_clk.common, > + &bus_i2c2_clk.common, > + &bus_scr_clk.common, > + &bus_uart0_clk.common, > + &bus_uart1_clk.common, > + &bus_uart2_clk.common, > + &bus_uart3_clk.common, > + &bus_uart4_clk.common, > + &bus_dbg_clk.common, > + &ths_clk.common, > + &nand_clk.common, > + &mmc0_clk.common, > + &mmc1_clk.common, > + &mmc2_clk.common, > + &ts_clk.common, > + &ce_clk.common, > + &spi0_clk.common, > + &spi1_clk.common, > + &i2s0_clk.common, > + &i2s1_clk.common, > + &i2s2_clk.common, > + &spdif_clk.common, > + &usb_phy0_clk.common, > + &usb_phy1_clk.common, > + &usb_hsic_clk.common, > + &usb_hsic_12m_clk.common, > + &usb_ohci0_clk.common, > + &usb_ohci1_clk.common, > + &dram_clk.common, > + &dram_ve_clk.common, > + &dram_csi_clk.common, > + &dram_deinterlace_clk.common, > + &dram_ts_clk.common, > + &de_clk.common, > + &tcon0_clk.common, > + &tcon1_clk.common, > + &deinterlace_clk.common, > + &csi_misc_clk.common, > + &csi_sclk_clk.common, > + &csi_mclk_clk.common, > + &ve_clk.common, > + &ac_dig_clk.common, > + &ac_dig_4x_clk.common, > + &avs_clk.common, > + &hdmi_clk.common, > + &hdmi_ddc_clk.common, > + &mbus_clk.common, > + &dsi_dphy_clk.common, > + &gpu_clk.common, > +}; > + > +static struct clk_hw_onecell_data sun50i_a64_hw_clks = { > + .hws = { > + [CLK_OSC_12M] = &osc12M_clk.hw, > + [CLK_PLL_CPUX] = &pll_cpux_clk.common.hw, > + [CLK_PLL_AUDIO_BASE] = &pll_audio_base_clk.common.hw, > + [CLK_PLL_AUDIO] = &pll_audio_clk.hw, > + [CLK_PLL_AUDIO_2X] = &pll_audio_2x_clk.hw, > + [CLK_PLL_AUDIO_4X] = &pll_audio_4x_clk.hw, > + [CLK_PLL_AUDIO_8X] = &pll_audio_8x_clk.hw, > + [CLK_PLL_VIDEO0] = &pll_video0_clk.common.hw, > + [CLK_PLL_VIDEO0_2X] = &pll_video0_2x_clk.hw, > + [CLK_PLL_VE] = &pll_ve_clk.common.hw, > + [CLK_PLL_DDR0] = &pll_ddr0_clk.common.hw, > + [CLK_PLL_PERIPH0] = &pll_periph0_clk.common.hw, > + [CLK_PLL_PERIPH0_2X] = &pll_periph0_2x_clk.hw, > + [CLK_PLL_PERIPH1] = &pll_periph1_clk.common.hw, > + [CLK_PLL_PERIPH1_2X] = &pll_periph1_2x_clk.hw, > + [CLK_PLL_VIDEO1] = &pll_video1_clk.common.hw, > + [CLK_PLL_GPU] = &pll_gpu_clk.common.hw, > + [CLK_PLL_MIPI] = &pll_mipi_clk.common.hw, > + [CLK_PLL_HSIC] = &pll_hsic_clk.common.hw, > + [CLK_PLL_DE] = &pll_de_clk.common.hw, > + [CLK_PLL_DDR1] = &pll_ddr1_clk.common.hw, > + [CLK_CPUX] = &cpux_clk.common.hw, > + [CLK_AXI] = &axi_clk.common.hw, > + [CLK_AHB1] = &ahb1_clk.common.hw, > + [CLK_APB1] = &apb1_clk.common.hw, > + [CLK_APB2] = &apb2_clk.common.hw, > + [CLK_AHB2] = &ahb2_clk.common.hw, > + [CLK_BUS_MIPI_DSI] = &bus_mipi_dsi_clk.common.hw, > + [CLK_BUS_CE] = &bus_ce_clk.common.hw, > + [CLK_BUS_DMA] = &bus_dma_clk.common.hw, > + [CLK_BUS_MMC0] = &bus_mmc0_clk.common.hw, > + [CLK_BUS_MMC1] = &bus_mmc1_clk.common.hw, > + [CLK_BUS_MMC2] = &bus_mmc2_clk.common.hw, > + [CLK_BUS_NAND] = &bus_nand_clk.common.hw, > + [CLK_BUS_DRAM] = &bus_dram_clk.common.hw, > + [CLK_BUS_EMAC] = &bus_emac_clk.common.hw, > + [CLK_BUS_TS] = &bus_ts_clk.common.hw, > + [CLK_BUS_HSTIMER] = &bus_hstimer_clk.common.hw, > + [CLK_BUS_SPI0] = &bus_spi0_clk.common.hw, > + [CLK_BUS_SPI1] = &bus_spi1_clk.common.hw, > + [CLK_BUS_OTG] = &bus_otg_clk.common.hw, > + [CLK_BUS_EHCI0] = &bus_ehci0_clk.common.hw, > + [CLK_BUS_EHCI1] = &bus_ehci1_clk.common.hw, > + [CLK_BUS_OHCI0] = &bus_ohci0_clk.common.hw, > + [CLK_BUS_OHCI1] = &bus_ohci1_clk.common.hw, > + [CLK_BUS_VE] = &bus_ve_clk.common.hw, > + [CLK_BUS_TCON0] = &bus_tcon0_clk.common.hw, > + [CLK_BUS_TCON1] = &bus_tcon1_clk.common.hw, > + [CLK_BUS_DEINTERLACE] = &bus_deinterlace_clk.common.hw, > + [CLK_BUS_CSI] = &bus_csi_clk.common.hw, > + [CLK_BUS_HDMI] = &bus_hdmi_clk.common.hw, > + [CLK_BUS_DE] = &bus_de_clk.common.hw, > + [CLK_BUS_GPU] = &bus_gpu_clk.common.hw, > + [CLK_BUS_MSGBOX] = &bus_msgbox_clk.common.hw, > + [CLK_BUS_SPINLOCK] = &bus_spinlock_clk.common.hw, > + [CLK_BUS_CODEC] = &bus_codec_clk.common.hw, > + [CLK_BUS_SPDIF] = &bus_spdif_clk.common.hw, > + [CLK_BUS_PIO] = &bus_pio_clk.common.hw, > + [CLK_BUS_THS] = &bus_ths_clk.common.hw, > + [CLK_BUS_I2S0] = &bus_i2s0_clk.common.hw, > + [CLK_BUS_I2S1] = &bus_i2s1_clk.common.hw, > + [CLK_BUS_I2S2] = &bus_i2s2_clk.common.hw, > + [CLK_BUS_I2C0] = &bus_i2c0_clk.common.hw, > + [CLK_BUS_I2C1] = &bus_i2c1_clk.common.hw, > + [CLK_BUS_I2C2] = &bus_i2c2_clk.common.hw, > + [CLK_BUS_UART0] = &bus_uart0_clk.common.hw, > + [CLK_BUS_UART1] = &bus_uart1_clk.common.hw, > + [CLK_BUS_UART2] = &bus_uart2_clk.common.hw, > + [CLK_BUS_UART3] = &bus_uart3_clk.common.hw, > + [CLK_BUS_UART4] = &bus_uart4_clk.common.hw, > + [CLK_BUS_SCR] = &bus_scr_clk.common.hw, > + [CLK_BUS_DBG] = &bus_dbg_clk.common.hw, > + [CLK_THS] = &ths_clk.common.hw, > + [CLK_NAND] = &nand_clk.common.hw, > + [CLK_MMC0] = &mmc0_clk.common.hw, > + [CLK_MMC1] = &mmc1_clk.common.hw, > + [CLK_MMC2] = &mmc2_clk.common.hw, > + [CLK_TS] = &ts_clk.common.hw, > + [CLK_CE] = &ce_clk.common.hw, > + [CLK_SPI0] = &spi0_clk.common.hw, > + [CLK_SPI1] = &spi1_clk.common.hw, > + [CLK_I2S0] = &i2s0_clk.common.hw, > + [CLK_I2S1] = &i2s1_clk.common.hw, > + [CLK_I2S2] = &i2s2_clk.common.hw, > + [CLK_SPDIF] = &spdif_clk.common.hw, > + [CLK_USB_PHY0] = &usb_phy0_clk.common.hw, > + [CLK_USB_PHY1] = &usb_phy1_clk.common.hw, > + [CLK_USB_HSIC] = &usb_hsic_clk.common.hw, > + [CLK_USB_HSIC_12M] = &usb_hsic_12m_clk.common.hw, > + [CLK_USB_OHCI0] = &usb_ohci0_clk.common.hw, > + [CLK_USB_OHCI1] = &usb_ohci1_clk.common.hw, > + [CLK_DRAM] = &dram_clk.common.hw, > + [CLK_DRAM_VE] = &dram_ve_clk.common.hw, > + [CLK_DRAM_CSI] = &dram_csi_clk.common.hw, > + [CLK_DRAM_DEINTERLACE] = &dram_deinterlace_clk.common.hw, > + [CLK_DRAM_TS] = &dram_ts_clk.common.hw, > + [CLK_DE] = &de_clk.common.hw, > + [CLK_TCON0] = &tcon0_clk.common.hw, > + [CLK_TCON1] = &tcon1_clk.common.hw, > + [CLK_DEINTERLACE] = &deinterlace_clk.common.hw, > + [CLK_CSI_MISC] = &csi_misc_clk.common.hw, > + [CLK_CSI_SCLK] = &csi_sclk_clk.common.hw, > + [CLK_CSI_MCLK] = &csi_mclk_clk.common.hw, > + [CLK_VE] = &ve_clk.common.hw, > + [CLK_AC_DIG] = &ac_dig_clk.common.hw, > + [CLK_AC_DIG_4X] = &ac_dig_4x_clk.common.hw, > + [CLK_AVS] = &avs_clk.common.hw, > + [CLK_HDMI] = &hdmi_clk.common.hw, > + [CLK_HDMI_DDC] = &hdmi_ddc_clk.common.hw, > + [CLK_MBUS] = &mbus_clk.common.hw, > + [CLK_DSI_DPHY] = &dsi_dphy_clk.common.hw, > + [CLK_GPU] = &gpu_clk.common.hw, > + }, > + .num = CLK_NUMBER, > +}; > + > +static struct ccu_reset_map sun50i_a64_ccu_resets[] = { > + [RST_USB_PHY0] = { 0x0cc, BIT(0) }, > + [RST_USB_PHY1] = { 0x0cc, BIT(1) }, > + [RST_USB_HSIC] = { 0x0cc, BIT(2) }, > + > + > + [RST_MBUS] = { 0x0fc, BIT(31) }, > + > + [RST_BUS_MIPI_DSI] = { 0x2c0, BIT(1) }, > + [RST_BUS_CE] = { 0x2c0, BIT(5) }, > + [RST_BUS_DMA] = { 0x2c0, BIT(6) }, > + [RST_BUS_MMC0] = { 0x2c0, BIT(8) }, > + [RST_BUS_MMC1] = { 0x2c0, BIT(9) }, > + [RST_BUS_MMC2] = { 0x2c0, BIT(10) }, > + [RST_BUS_NAND] = { 0x2c0, BIT(13) }, > + [RST_BUS_DRAM] = { 0x2c0, BIT(14) }, > + [RST_BUS_EMAC] = { 0x2c0, BIT(17) }, > + [RST_BUS_TS] = { 0x2c0, BIT(18) }, > + [RST_BUS_HSTIMER] = { 0x2c0, BIT(19) }, > + [RST_BUS_SPI0] = { 0x2c0, BIT(20) }, > + [RST_BUS_SPI1] = { 0x2c0, BIT(21) }, > + [RST_BUS_OTG] = { 0x2c0, BIT(23) }, > + [RST_BUS_EHCI0] = { 0x2c0, BIT(24) }, > + [RST_BUS_EHCI1] = { 0x2c0, BIT(25) }, > + [RST_BUS_OHCI0] = { 0x2c0, BIT(28) }, > + [RST_BUS_OHCI1] = { 0x2c0, BIT(29) }, > + > + [RST_BUS_VE] = { 0x2c4, BIT(0) }, > + [RST_BUS_TCON0] = { 0x2c4, BIT(3) }, > + [RST_BUS_TCON1] = { 0x2c4, BIT(4) }, > + [RST_BUS_DEINTERLACE] = { 0x2c4, BIT(5) }, > + [RST_BUS_CSI] = { 0x2c4, BIT(8) }, > + [RST_BUS_HDMI0] = { 0x2c4, BIT(10) }, > + [RST_BUS_HDMI1] = { 0x2c4, BIT(11) }, > + [RST_BUS_DE] = { 0x2c4, BIT(12) }, > + [RST_BUS_GPU] = { 0x2c4, BIT(20) }, > + [RST_BUS_MSGBOX] = { 0x2c4, BIT(21) }, > + [RST_BUS_SPINLOCK] = { 0x2c4, BIT(22) }, > + [RST_BUS_DBG] = { 0x2c4, BIT(31) }, > + > + [RST_BUS_LVDS] = { 0x2c8, BIT(0) }, > + > + [RST_BUS_CODEC] = { 0x2d0, BIT(0) }, > + [RST_BUS_SPDIF] = { 0x2d0, BIT(1) }, > + [RST_BUS_THS] = { 0x2d0, BIT(8) }, > + [RST_BUS_I2S0] = { 0x2d0, BIT(12) }, > + [RST_BUS_I2S1] = { 0x2d0, BIT(13) }, > + [RST_BUS_I2S2] = { 0x2d0, BIT(14) }, > + > + [RST_BUS_I2C0] = { 0x2d8, BIT(0) }, > + [RST_BUS_I2C1] = { 0x2d8, BIT(1) }, > + [RST_BUS_I2C2] = { 0x2d8, BIT(2) }, > + [RST_BUS_SCR] = { 0x2d8, BIT(5) }, > + [RST_BUS_UART0] = { 0x2d8, BIT(16) }, > + [RST_BUS_UART1] = { 0x2d8, BIT(17) }, > + [RST_BUS_UART2] = { 0x2d8, BIT(18) }, > + [RST_BUS_UART3] = { 0x2d8, BIT(19) }, > + [RST_BUS_UART4] = { 0x2d8, BIT(20) }, > +}; > + > +static const struct sunxi_ccu_desc sun50i_a64_ccu_desc = { > + .ccu_clks = sun50i_a64_ccu_clks, > + .num_ccu_clks = ARRAY_SIZE(sun50i_a64_ccu_clks), > + > + .hw_clks = &sun50i_a64_hw_clks, > + > + .resets = sun50i_a64_ccu_resets, > + .num_resets = ARRAY_SIZE(sun50i_a64_ccu_resets), > +}; > + > +static void __init sun50i_a64_ccu_setup(struct device_node *node) > +{ > + void __iomem *reg; > + u32 val; > + > + reg = of_io_request_and_map(node, 0, of_node_full_name(node)); > + if (IS_ERR(reg)) { > + pr_err("%s: Could not map the clock registers\n", > + of_node_full_name(node)); > + return; > + } > + > + /* Force the PLL-Audio-1x divider to 4 */ > + val = readl(reg + SUN50I_A64_PLL_AUDIO_REG); > + val &= ~GENMASK(19, 16); > + writel(val | (3 << 16), reg + SUN50I_A64_PLL_AUDIO_REG); > + > + writel(0x515, reg + SUN50I_A64_PLL_MIPI_REG); > + > + sunxi_ccu_probe(node, reg, &sun50i_a64_ccu_desc); > +} > +CLK_OF_DECLARE(sun50i_a64_ccu, "allwinner,sun50i-a64-ccu", > + sun50i_a64_ccu_setup); > diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-a64.h b/drivers/clk/sunxi-ng/ccu-sun50i-a64.h > new file mode 100644 > index 000000000000..e3c77d92af1c > --- /dev/null > +++ b/drivers/clk/sunxi-ng/ccu-sun50i-a64.h > @@ -0,0 +1,68 @@ > +/* > + * Copyright 2016 Maxime Ripard > + * > + * Maxime Ripard <maxime.ripard@free-electrons.com> > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License as published by > + * the Free Software Foundation; either version 2 of the License, or > + * (at your option) any later version. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + */ > + > +#ifndef _CCU_SUN50I_A64_H_ > +#define _CCU_SUN50I_A64_H_ > + > +#include <dt-bindings/clock/sun50i-a64-ccu.h> > +#include <dt-bindings/reset/sun50i-a64-ccu.h> > + > +#define CLK_OSC_12M 0 > +#define CLK_PLL_CPUX 1 > +#define CLK_PLL_AUDIO_BASE 2 > +#define CLK_PLL_AUDIO 3 > +#define CLK_PLL_AUDIO_2X 4 > +#define CLK_PLL_AUDIO_4X 5 > +#define CLK_PLL_AUDIO_8X 6 > +#define CLK_PLL_VIDEO0 7 > +#define CLK_PLL_VIDEO0_2X 8 > +#define CLK_PLL_VE 9 > +#define CLK_PLL_DDR0 10 > +#define CLK_PLL_PERIPH0 11 > +#define CLK_PLL_PERIPH0_2X 12 > +#define CLK_PLL_PERIPH1 13 > +#define CLK_PLL_PERIPH1_2X 14 > +#define CLK_PLL_VIDEO1 15 > +#define CLK_PLL_GPU 16 > +#define CLK_PLL_MIPI 17 > +#define CLK_PLL_HSIC 18 > +#define CLK_PLL_DE 19 > +#define CLK_PLL_DDR1 20 > +#define CLK_CPUX 21 > +#define CLK_AXI 22 > +#define CLK_APB 23 This is listed but never implemented. > +#define CLK_AHB1 24 > +#define CLK_APB1 25 > +#define CLK_APB2 26 > +#define CLK_AHB2 27 > + > +/* All the bus gates are exported */ > + > +/* The first bunch of module clocks are exported */ > + > +#define CLK_DRAM 92 > + > +/* All the DRAM gates are exported */ > + > +/* Some more module clocks are exported */ > + > +#define CLK_MBUS 110 > + > +/* And the DSI and GPU module clock is exported */ > + > +#define CLK_NUMBER (CLK_GPU + 1) > + > +#endif /* _CCU_SUN50I_A64_H_ */ > diff --git a/include/dt-bindings/clock/sun50i-a64-ccu.h b/include/dt-bindings/clock/sun50i-a64-ccu.h > new file mode 100644 > index 000000000000..2abcd87c7a2d > --- /dev/null > +++ b/include/dt-bindings/clock/sun50i-a64-ccu.h > @@ -0,0 +1,132 @@ > +/* > + * Copyright (C) 2016 Maxime Ripard <maxime.ripard@free-electrons.com> > + * > + * This file is dual-licensed: you can use it either under the terms > + * of the GPL or the X11 license, at your option. Note that this dual > + * licensing only applies to this file, and not this project as a > + * whole. > + * > + * a) This file is free software; you can redistribute it and/or > + * modify it under the terms of the GNU General Public License as > + * published by the Free Software Foundation; either version 2 of the > + * License, or (at your option) any later version. > + * > + * This file is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * Or, alternatively, > + * > + * b) Permission is hereby granted, free of charge, to any person > + * obtaining a copy of this software and associated documentation > + * files (the "Software"), to deal in the Software without > + * restriction, including without limitation the rights to use, > + * copy, modify, merge, publish, distribute, sublicense, and/or > + * sell copies of the Software, and to permit persons to whom the > + * Software is furnished to do so, subject to the following > + * conditions: > + * > + * The above copyright notice and this permission notice shall be > + * included in all copies or substantial portions of the Software. > + * > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, > + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES > + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND > + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT > + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, > + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING > + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR > + * OTHER DEALINGS IN THE SOFTWARE. > + */ > + > +#ifndef _DT_BINDINGS_CLK_SUN50I_A64_H_ > +#define _DT_BINDINGS_CLK_SUN50I_A64_H_ > + > +#define CLK_BUS_MIPI_DSI 28 > +#define CLK_BUS_CE 29 > +#define CLK_BUS_DMA 30 > +#define CLK_BUS_MMC0 31 > +#define CLK_BUS_MMC1 32 > +#define CLK_BUS_MMC2 33 > +#define CLK_BUS_NAND 34 > +#define CLK_BUS_DRAM 35 > +#define CLK_BUS_EMAC 36 > +#define CLK_BUS_TS 37 > +#define CLK_BUS_HSTIMER 38 > +#define CLK_BUS_SPI0 39 > +#define CLK_BUS_SPI1 40 > +#define CLK_BUS_OTG 41 > +#define CLK_BUS_EHCI0 42 > +#define CLK_BUS_EHCI1 43 > +#define CLK_BUS_OHCI0 44 > +#define CLK_BUS_OHCI1 45 > +#define CLK_BUS_VE 46 > +#define CLK_BUS_TCON0 47 > +#define CLK_BUS_TCON1 48 > +#define CLK_BUS_DEINTERLACE 49 > +#define CLK_BUS_CSI 50 > +#define CLK_BUS_HDMI 51 > +#define CLK_BUS_DE 52 > +#define CLK_BUS_GPU 53 > +#define CLK_BUS_MSGBOX 54 > +#define CLK_BUS_SPINLOCK 55 > +#define CLK_BUS_CODEC 56 > +#define CLK_BUS_SPDIF 57 > +#define CLK_BUS_PIO 58 > +#define CLK_BUS_THS 59 > +#define CLK_BUS_I2S0 60 > +#define CLK_BUS_I2S1 61 > +#define CLK_BUS_I2S2 62 > +#define CLK_BUS_I2C0 63 > +#define CLK_BUS_I2C1 64 > +#define CLK_BUS_I2C2 65 > +#define CLK_BUS_SCR 66 > +#define CLK_BUS_UART0 67 > +#define CLK_BUS_UART1 68 > +#define CLK_BUS_UART2 69 > +#define CLK_BUS_UART3 70 > +#define CLK_BUS_UART4 71 > +#define CLK_BUS_DBG 72 > +#define CLK_THS 73 > +#define CLK_NAND 74 > +#define CLK_MMC0 75 > +#define CLK_MMC1 76 > +#define CLK_MMC2 77 > +#define CLK_TS 78 > +#define CLK_CE 79 > +#define CLK_SPI0 80 > +#define CLK_SPI1 81 > +#define CLK_I2S0 82 > +#define CLK_I2S1 83 > +#define CLK_I2S2 84 > +#define CLK_SPDIF 85 > +#define CLK_USB_PHY0 86 > +#define CLK_USB_PHY1 87 > +#define CLK_USB_HSIC 88 > +#define CLK_USB_HSIC_12M 89 > +#define CLK_USB_OHCI0 90 > +#define CLK_USB_OHCI1 91 > + > +#define CLK_DRAM_VE 93 > +#define CLK_DRAM_CSI 94 > +#define CLK_DRAM_DEINTERLACE 95 > +#define CLK_DRAM_TS 96 > +#define CLK_DE 97 > +#define CLK_TCON0 98 > +#define CLK_TCON1 99 > +#define CLK_DEINTERLACE 100 > +#define CLK_CSI_MISC 101 > +#define CLK_CSI_SCLK 102 > +#define CLK_CSI_MCLK 103 > +#define CLK_VE 104 > +#define CLK_AC_DIG 105 > +#define CLK_AC_DIG_4X 106 > +#define CLK_AVS 107 > +#define CLK_HDMI 108 > +#define CLK_HDMI_DDC 109 > + > +#define CLK_DSI_DPHY 111 > +#define CLK_GPU 112 > + > +#endif /* _DT_BINDINGS_CLK_SUN50I_H_ */ > diff --git a/include/dt-bindings/reset/sun50i-a64-ccu.h b/include/dt-bindings/reset/sun50i-a64-ccu.h > new file mode 100644 > index 000000000000..e61fac294d73 > --- /dev/null > +++ b/include/dt-bindings/reset/sun50i-a64-ccu.h > @@ -0,0 +1,97 @@ > +/* > + * Copyright (C) 2016 Maxime Ripard <maxime.ripard@free-electrons.com> > + * > + * This file is dual-licensed: you can use it either under the terms > + * of the GPL or the X11 license, at your option. Note that this dual > + * licensing only applies to this file, and not this project as a > + * whole. > + * > + * a) This file is free software; you can redistribute it and/or > + * modify it under the terms of the GNU General Public License as > + * published by the Free Software Foundation; either version 2 of the > + * License, or (at your option) any later version. > + * > + * This file is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * Or, alternatively, > + * > + * b) Permission is hereby granted, free of charge, to any person > + * obtaining a copy of this software and associated documentation > + * files (the "Software"), to deal in the Software without > + * restriction, including without limitation the rights to use, > + * copy, modify, merge, publish, distribute, sublicense, and/or > + * sell copies of the Software, and to permit persons to whom the > + * Software is furnished to do so, subject to the following > + * conditions: > + * > + * The above copyright notice and this permission notice shall be > + * included in all copies or substantial portions of the Software. > + * > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, > + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES > + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND > + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT > + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, > + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING > + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR > + * OTHER DEALINGS IN THE SOFTWARE. > + */ > + > +#ifndef _DT_BINDINGS_RST_SUN50I_A64_H_ > +#define _DT_BINDINGS_RST_SUN50I_A64_H_ > + > +#define RST_USB_PHY0 0 > +#define RST_USB_PHY1 1 > +#define RST_USB_HSIC 2 There's also a DRAM reset in 0xf4 (DRAM configuration) > +#define RST_MBUS 3 > +#define RST_BUS_MIPI_DSI 4 > +#define RST_BUS_CE 5 > +#define RST_BUS_DMA 6 > +#define RST_BUS_MMC0 7 > +#define RST_BUS_MMC1 8 > +#define RST_BUS_MMC2 9 > +#define RST_BUS_NAND 10 > +#define RST_BUS_DRAM 11 > +#define RST_BUS_EMAC 12 > +#define RST_BUS_TS 13 > +#define RST_BUS_HSTIMER 14 > +#define RST_BUS_SPI0 15 > +#define RST_BUS_SPI1 16 > +#define RST_BUS_OTG 17 > +#define RST_BUS_EHCI0 18 > +#define RST_BUS_EHCI1 19 > +#define RST_BUS_OHCI0 20 > +#define RST_BUS_OHCI1 21 > +#define RST_BUS_VE 22 > +#define RST_BUS_TCON0 23 > +#define RST_BUS_TCON1 24 > +#define RST_BUS_DEINTERLACE 25 > +#define RST_BUS_CSI 26 > +#define RST_BUS_HDMI0 27 > +#define RST_BUS_HDMI1 28 > +#define RST_BUS_DE 29 > +#define RST_BUS_GPU 30 > +#define RST_BUS_MSGBOX 31 > +#define RST_BUS_SPINLOCK 32 > +#define RST_BUS_DBG 33 > +#define RST_BUS_LVDS 34 > +#define RST_BUS_CODEC 35 > +#define RST_BUS_SPDIF 36 > +#define RST_BUS_THS 37 > +#define RST_BUS_I2S0 38 > +#define RST_BUS_I2S1 39 > +#define RST_BUS_I2S2 40 > +#define RST_BUS_I2C0 41 > +#define RST_BUS_I2C1 42 > +#define RST_BUS_I2C2 43 > +#define RST_BUS_SCR 44 > +#define RST_BUS_UART0 45 > +#define RST_BUS_UART1 46 > +#define RST_BUS_UART2 47 > +#define RST_BUS_UART3 48 > +#define RST_BUS_UART4 49 > + > +#endif /* _DT_BINDINGS_RST_SUN8I_H3_H_ */ > -- > 2.9.3 > I didn't look at the 2 large arrays of clks. Everything else checks out. Regards ChenYu ^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [PATCH v2 1/4] clk: sunxi-ng: Add A64 clocks 2016-09-10 3:24 ` Chen-Yu Tsai @ 2016-09-17 14:08 ` Maxime Ripard -1 siblings, 0 replies; 35+ messages in thread From: Maxime Ripard @ 2016-09-17 14:08 UTC (permalink / raw) To: Chen-Yu Tsai Cc: Mike Turquette, Stephen Boyd, linux-arm-kernel, Andre Przywara, linux-clk, linux-kernel, linux-sunxi [-- Attachment #1: Type: text/plain, Size: 24923 bytes --] Hi, On Sat, Sep 10, 2016 at 11:24:48AM +0800, Chen-Yu Tsai wrote: > > +static SUNXI_CCU_NK_WITH_GATE_LOCK_POSTDIV(pll_periph0_clk, "pll-periph0", > > + "osc24M", 0x028, > > + 8, 5, /* N */ > > + 4, 2, /* K */ > > The manual says to give preference to K >= 2. I suggest swapping N/K and > leaving a note about it, so the actual K is in the inner loop (see ccu_nk.c) > of the factor calculation. It also says that we should fix that frequency (and we don't), so we don't really care. > > +static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_mipi_clk, "pll-mipi", > > + "pll-video0", 0x040, > > + 8, 4, /* N */ > > + 4, 2, /* K */ > > You need a table for K. (Manual says K >= 2). Not really a table, but a minimum, like we have a maximum already. > > +static SUNXI_CCU_DIV_TABLE_WITH_GATE(ths_clk, "ths", "osc24M", > > + 0x074, 0, 2, ths_div_table, BIT(31), 0); > > Even though the mux has only one valid parent, I suggest you still implement it, > in case some bogus value gets put in before the kernel loads. Ack. > > +static const char * const ts_parents[] = { "osc24M", "pll-periph0", }; > > +static SUNXI_CCU_MP_WITH_MUX_GATE(ts_clk, "ts", ts_parents, 0x098, > > + 0, 4, /* M */ > > + 16, 2, /* P */ > > + 24, 2, /* mux */ > > Manual says the mux is 4 bits wide. Ack. > > +static const char * const i2s_parents[] = { "pll-audio-8x", "pll-audio-4x", > > + "pll-audio-2x", "pll-audio" }; > > +static SUNXI_CCU_MUX_WITH_GATE(i2s0_clk, "i2s0", i2s_parents, > > + 0x0b0, 16, 2, BIT(31), 0); > > + > > +static SUNXI_CCU_MUX_WITH_GATE(i2s1_clk, "i2s1", i2s_parents, > > + 0x0b4, 16, 2, BIT(31), 0); > > + > > +static SUNXI_CCU_MUX_WITH_GATE(i2s2_clk, "i2s2", i2s_parents, > > + 0x0b8, 16, 2, BIT(31), 0); > > + > > +static SUNXI_CCU_M_WITH_GATE(spdif_clk, "spdif", "pll-audio", > > + 0x0c0, 0, 4, BIT(31), 0); > > CLK_SET_PARENT_RATE for the above audio clocks? Indeed. > > +static SUNXI_CCU_GATE(usb_phy0_clk, "usb-phy0", "osc24M", > > + 0x0cc, BIT(8), 0); > > +static SUNXI_CCU_GATE(usb_phy1_clk, "usb-phy1", "osc24M", > > + 0x0cc, BIT(9), 0); > > +static SUNXI_CCU_GATE(usb_hsic_clk, "usb-hsic", "pll-hsic", > > + 0x0cc, BIT(10), 0); > > +static SUNXI_CCU_GATE(usb_hsic_12m_clk, "usb-hsic-12M", "osc12M", > > + 0x0cc, BIT(11), 0); > > +static SUNXI_CCU_GATE(usb_ohci0_clk, "usb-ohci0", "osc12M", > > + 0x0cc, BIT(16), 0); > > +static SUNXI_CCU_GATE(usb_ohci1_clk, "usb-ohci1", "usb-ohci0", > > + 0x0cc, BIT(17), 0); > > I guess we aren't modeling the 2 OHCI 12M muxes? To be honest, I can't even make sense of it. Which clocks are using it is unclear to me, so yeah, I don't know. I can probably leave some ID for it though, just in case. > > +static const char * const tcon1_parents[] = { "pll-video0", "pll-video1" }; > > +static const u8 tcon1_table[] = { 0, 2, }; > > +struct ccu_div tcon1_clk = { > > + .enable = BIT(31), > > + .div = _SUNXI_CCU_DIV(0, 4), > > + .mux = _SUNXI_CCU_MUX_TABLE(24, 3, tcon1_table), > > + .common = { > > + .reg = 0x11c, > > + .hw.init = CLK_HW_INIT_PARENTS("tcon1", > > + tcon1_parents, > > + &ccu_div_ops, > > + 0), > > + }, > > +}; > > CLK_SET_PARENT_RATE for the TCON clocks? Yep > > +static SUNXI_CCU_GATE(ac_dig_clk, "ac-dig", "pll-audio", > > + 0x140, BIT(31), 0); > > + > > +static SUNXI_CCU_GATE(ac_dig_4x_clk, "ac-dig-4x", "pll-audio-4x", > > + 0x140, BIT(30), 0); > > CLK_SET_PARENT_RATE for the above audio clocks? Ack. > > +static SUNXI_CCU_GATE(avs_clk, "avs", "osc24M", > > + 0x144, BIT(31), 0); > > + > > +static const char * const hdmi_parents[] = { "pll-video0", "pll-video1" }; > > +static SUNXI_CCU_M_WITH_MUX_GATE(hdmi_clk, "hdmi", hdmi_parents, > > + 0x150, 0, 4, 24, 2, BIT(31), 0); > > Might need CLK_SET_PARENT_RATE for hdmi? Ack > > +static SUNXI_CCU_GATE(hdmi_ddc_clk, "hdmi-ddc", "osc24M", > > + 0x154, BIT(31), 0); > > + > > +static const char * const mbus_parents[] = { "osc24M", "pll-periph0-2x", > > + "pll-ddr0", "pll-ddr1" }; > > +static SUNXI_CCU_M_WITH_MUX_GATE(mbus_clk, "mbus", mbus_parents, > > + 0x15c, 0, 3, 24, 2, BIT(31), CLK_IS_CRITICAL); > > + > > +static const char * const dsi_dphy_parents[] = { "pll-video0", "pll-periph0" }; > > You need a mux table = { 0, 2 } here. Indeed > > +static SUNXI_CCU_M_WITH_MUX_GATE(dsi_dphy_clk, "dsi-dphy", dsi_dphy_parents, > > + 0x168, 0, 3, 24, 2, BIT(31), 0); > > + > > +static SUNXI_CCU_M_WITH_GATE(gpu_clk, "gpu", "pll-gpu", > > + 0x1a0, 0, 3, BIT(31), 0); > > CLK_SET_PARENT_RATE for the GPU clock? Ack > > +static CLK_FIXED_FACTOR(pll_video0_2x_clk, "pll-video0-2x", > > + "pll-video0", 1, 2, 0); > > CLK_SET_PARENT_RATE for pll-video0-2x. Ack > > > + > > +static struct ccu_common *sun50i_a64_ccu_clks[] = { > > + &pll_cpux_clk.common, > > + &pll_audio_base_clk.common, > > + &pll_video0_clk.common, > > + &pll_ve_clk.common, > > + &pll_ddr0_clk.common, > > + &pll_periph0_clk.common, > > + &pll_periph1_clk.common, > > + &pll_video1_clk.common, > > + &pll_gpu_clk.common, > > + &pll_mipi_clk.common, > > + &pll_hsic_clk.common, > > + &pll_de_clk.common, > > + &pll_ddr1_clk.common, > > + &cpux_clk.common, > > + &axi_clk.common, > > + &ahb1_clk.common, > > + &apb1_clk.common, > > + &apb2_clk.common, > > + &ahb2_clk.common, > > + &bus_mipi_dsi_clk.common, > > + &bus_ce_clk.common, > > + &bus_dma_clk.common, > > + &bus_mmc0_clk.common, > > + &bus_mmc1_clk.common, > > + &bus_mmc2_clk.common, > > + &bus_nand_clk.common, > > + &bus_dram_clk.common, > > + &bus_emac_clk.common, > > + &bus_ts_clk.common, > > + &bus_hstimer_clk.common, > > + &bus_spi0_clk.common, > > + &bus_spi1_clk.common, > > + &bus_otg_clk.common, > > + &bus_ehci0_clk.common, > > + &bus_ehci1_clk.common, > > + &bus_ohci0_clk.common, > > + &bus_ohci1_clk.common, > > + &bus_ve_clk.common, > > + &bus_tcon0_clk.common, > > + &bus_tcon1_clk.common, > > + &bus_deinterlace_clk.common, > > + &bus_csi_clk.common, > > + &bus_hdmi_clk.common, > > + &bus_de_clk.common, > > + &bus_gpu_clk.common, > > + &bus_msgbox_clk.common, > > + &bus_spinlock_clk.common, > > + &bus_codec_clk.common, > > + &bus_spdif_clk.common, > > + &bus_pio_clk.common, > > + &bus_ths_clk.common, > > + &bus_i2s0_clk.common, > > + &bus_i2s1_clk.common, > > + &bus_i2s2_clk.common, > > + &bus_i2c0_clk.common, > > + &bus_i2c1_clk.common, > > + &bus_i2c2_clk.common, > > + &bus_scr_clk.common, > > + &bus_uart0_clk.common, > > + &bus_uart1_clk.common, > > + &bus_uart2_clk.common, > > + &bus_uart3_clk.common, > > + &bus_uart4_clk.common, > > + &bus_dbg_clk.common, > > + &ths_clk.common, > > + &nand_clk.common, > > + &mmc0_clk.common, > > + &mmc1_clk.common, > > + &mmc2_clk.common, > > + &ts_clk.common, > > + &ce_clk.common, > > + &spi0_clk.common, > > + &spi1_clk.common, > > + &i2s0_clk.common, > > + &i2s1_clk.common, > > + &i2s2_clk.common, > > + &spdif_clk.common, > > + &usb_phy0_clk.common, > > + &usb_phy1_clk.common, > > + &usb_hsic_clk.common, > > + &usb_hsic_12m_clk.common, > > + &usb_ohci0_clk.common, > > + &usb_ohci1_clk.common, > > + &dram_clk.common, > > + &dram_ve_clk.common, > > + &dram_csi_clk.common, > > + &dram_deinterlace_clk.common, > > + &dram_ts_clk.common, > > + &de_clk.common, > > + &tcon0_clk.common, > > + &tcon1_clk.common, > > + &deinterlace_clk.common, > > + &csi_misc_clk.common, > > + &csi_sclk_clk.common, > > + &csi_mclk_clk.common, > > + &ve_clk.common, > > + &ac_dig_clk.common, > > + &ac_dig_4x_clk.common, > > + &avs_clk.common, > > + &hdmi_clk.common, > > + &hdmi_ddc_clk.common, > > + &mbus_clk.common, > > + &dsi_dphy_clk.common, > > + &gpu_clk.common, > > +}; > > + > > +static struct clk_hw_onecell_data sun50i_a64_hw_clks = { > > + .hws = { > > + [CLK_OSC_12M] = &osc12M_clk.hw, > > + [CLK_PLL_CPUX] = &pll_cpux_clk.common.hw, > > + [CLK_PLL_AUDIO_BASE] = &pll_audio_base_clk.common.hw, > > + [CLK_PLL_AUDIO] = &pll_audio_clk.hw, > > + [CLK_PLL_AUDIO_2X] = &pll_audio_2x_clk.hw, > > + [CLK_PLL_AUDIO_4X] = &pll_audio_4x_clk.hw, > > + [CLK_PLL_AUDIO_8X] = &pll_audio_8x_clk.hw, > > + [CLK_PLL_VIDEO0] = &pll_video0_clk.common.hw, > > + [CLK_PLL_VIDEO0_2X] = &pll_video0_2x_clk.hw, > > + [CLK_PLL_VE] = &pll_ve_clk.common.hw, > > + [CLK_PLL_DDR0] = &pll_ddr0_clk.common.hw, > > + [CLK_PLL_PERIPH0] = &pll_periph0_clk.common.hw, > > + [CLK_PLL_PERIPH0_2X] = &pll_periph0_2x_clk.hw, > > + [CLK_PLL_PERIPH1] = &pll_periph1_clk.common.hw, > > + [CLK_PLL_PERIPH1_2X] = &pll_periph1_2x_clk.hw, > > + [CLK_PLL_VIDEO1] = &pll_video1_clk.common.hw, > > + [CLK_PLL_GPU] = &pll_gpu_clk.common.hw, > > + [CLK_PLL_MIPI] = &pll_mipi_clk.common.hw, > > + [CLK_PLL_HSIC] = &pll_hsic_clk.common.hw, > > + [CLK_PLL_DE] = &pll_de_clk.common.hw, > > + [CLK_PLL_DDR1] = &pll_ddr1_clk.common.hw, > > + [CLK_CPUX] = &cpux_clk.common.hw, > > + [CLK_AXI] = &axi_clk.common.hw, > > + [CLK_AHB1] = &ahb1_clk.common.hw, > > + [CLK_APB1] = &apb1_clk.common.hw, > > + [CLK_APB2] = &apb2_clk.common.hw, > > + [CLK_AHB2] = &ahb2_clk.common.hw, > > + [CLK_BUS_MIPI_DSI] = &bus_mipi_dsi_clk.common.hw, > > + [CLK_BUS_CE] = &bus_ce_clk.common.hw, > > + [CLK_BUS_DMA] = &bus_dma_clk.common.hw, > > + [CLK_BUS_MMC0] = &bus_mmc0_clk.common.hw, > > + [CLK_BUS_MMC1] = &bus_mmc1_clk.common.hw, > > + [CLK_BUS_MMC2] = &bus_mmc2_clk.common.hw, > > + [CLK_BUS_NAND] = &bus_nand_clk.common.hw, > > + [CLK_BUS_DRAM] = &bus_dram_clk.common.hw, > > + [CLK_BUS_EMAC] = &bus_emac_clk.common.hw, > > + [CLK_BUS_TS] = &bus_ts_clk.common.hw, > > + [CLK_BUS_HSTIMER] = &bus_hstimer_clk.common.hw, > > + [CLK_BUS_SPI0] = &bus_spi0_clk.common.hw, > > + [CLK_BUS_SPI1] = &bus_spi1_clk.common.hw, > > + [CLK_BUS_OTG] = &bus_otg_clk.common.hw, > > + [CLK_BUS_EHCI0] = &bus_ehci0_clk.common.hw, > > + [CLK_BUS_EHCI1] = &bus_ehci1_clk.common.hw, > > + [CLK_BUS_OHCI0] = &bus_ohci0_clk.common.hw, > > + [CLK_BUS_OHCI1] = &bus_ohci1_clk.common.hw, > > + [CLK_BUS_VE] = &bus_ve_clk.common.hw, > > + [CLK_BUS_TCON0] = &bus_tcon0_clk.common.hw, > > + [CLK_BUS_TCON1] = &bus_tcon1_clk.common.hw, > > + [CLK_BUS_DEINTERLACE] = &bus_deinterlace_clk.common.hw, > > + [CLK_BUS_CSI] = &bus_csi_clk.common.hw, > > + [CLK_BUS_HDMI] = &bus_hdmi_clk.common.hw, > > + [CLK_BUS_DE] = &bus_de_clk.common.hw, > > + [CLK_BUS_GPU] = &bus_gpu_clk.common.hw, > > + [CLK_BUS_MSGBOX] = &bus_msgbox_clk.common.hw, > > + [CLK_BUS_SPINLOCK] = &bus_spinlock_clk.common.hw, > > + [CLK_BUS_CODEC] = &bus_codec_clk.common.hw, > > + [CLK_BUS_SPDIF] = &bus_spdif_clk.common.hw, > > + [CLK_BUS_PIO] = &bus_pio_clk.common.hw, > > + [CLK_BUS_THS] = &bus_ths_clk.common.hw, > > + [CLK_BUS_I2S0] = &bus_i2s0_clk.common.hw, > > + [CLK_BUS_I2S1] = &bus_i2s1_clk.common.hw, > > + [CLK_BUS_I2S2] = &bus_i2s2_clk.common.hw, > > + [CLK_BUS_I2C0] = &bus_i2c0_clk.common.hw, > > + [CLK_BUS_I2C1] = &bus_i2c1_clk.common.hw, > > + [CLK_BUS_I2C2] = &bus_i2c2_clk.common.hw, > > + [CLK_BUS_UART0] = &bus_uart0_clk.common.hw, > > + [CLK_BUS_UART1] = &bus_uart1_clk.common.hw, > > + [CLK_BUS_UART2] = &bus_uart2_clk.common.hw, > > + [CLK_BUS_UART3] = &bus_uart3_clk.common.hw, > > + [CLK_BUS_UART4] = &bus_uart4_clk.common.hw, > > + [CLK_BUS_SCR] = &bus_scr_clk.common.hw, > > + [CLK_BUS_DBG] = &bus_dbg_clk.common.hw, > > + [CLK_THS] = &ths_clk.common.hw, > > + [CLK_NAND] = &nand_clk.common.hw, > > + [CLK_MMC0] = &mmc0_clk.common.hw, > > + [CLK_MMC1] = &mmc1_clk.common.hw, > > + [CLK_MMC2] = &mmc2_clk.common.hw, > > + [CLK_TS] = &ts_clk.common.hw, > > + [CLK_CE] = &ce_clk.common.hw, > > + [CLK_SPI0] = &spi0_clk.common.hw, > > + [CLK_SPI1] = &spi1_clk.common.hw, > > + [CLK_I2S0] = &i2s0_clk.common.hw, > > + [CLK_I2S1] = &i2s1_clk.common.hw, > > + [CLK_I2S2] = &i2s2_clk.common.hw, > > + [CLK_SPDIF] = &spdif_clk.common.hw, > > + [CLK_USB_PHY0] = &usb_phy0_clk.common.hw, > > + [CLK_USB_PHY1] = &usb_phy1_clk.common.hw, > > + [CLK_USB_HSIC] = &usb_hsic_clk.common.hw, > > + [CLK_USB_HSIC_12M] = &usb_hsic_12m_clk.common.hw, > > + [CLK_USB_OHCI0] = &usb_ohci0_clk.common.hw, > > + [CLK_USB_OHCI1] = &usb_ohci1_clk.common.hw, > > + [CLK_DRAM] = &dram_clk.common.hw, > > + [CLK_DRAM_VE] = &dram_ve_clk.common.hw, > > + [CLK_DRAM_CSI] = &dram_csi_clk.common.hw, > > + [CLK_DRAM_DEINTERLACE] = &dram_deinterlace_clk.common.hw, > > + [CLK_DRAM_TS] = &dram_ts_clk.common.hw, > > + [CLK_DE] = &de_clk.common.hw, > > + [CLK_TCON0] = &tcon0_clk.common.hw, > > + [CLK_TCON1] = &tcon1_clk.common.hw, > > + [CLK_DEINTERLACE] = &deinterlace_clk.common.hw, > > + [CLK_CSI_MISC] = &csi_misc_clk.common.hw, > > + [CLK_CSI_SCLK] = &csi_sclk_clk.common.hw, > > + [CLK_CSI_MCLK] = &csi_mclk_clk.common.hw, > > + [CLK_VE] = &ve_clk.common.hw, > > + [CLK_AC_DIG] = &ac_dig_clk.common.hw, > > + [CLK_AC_DIG_4X] = &ac_dig_4x_clk.common.hw, > > + [CLK_AVS] = &avs_clk.common.hw, > > + [CLK_HDMI] = &hdmi_clk.common.hw, > > + [CLK_HDMI_DDC] = &hdmi_ddc_clk.common.hw, > > + [CLK_MBUS] = &mbus_clk.common.hw, > > + [CLK_DSI_DPHY] = &dsi_dphy_clk.common.hw, > > + [CLK_GPU] = &gpu_clk.common.hw, > > + }, > > + .num = CLK_NUMBER, > > +}; > > + > > +static struct ccu_reset_map sun50i_a64_ccu_resets[] = { > > + [RST_USB_PHY0] = { 0x0cc, BIT(0) }, > > + [RST_USB_PHY1] = { 0x0cc, BIT(1) }, > > + [RST_USB_HSIC] = { 0x0cc, BIT(2) }, > > + > > + > > + [RST_MBUS] = { 0x0fc, BIT(31) }, > > + > > + [RST_BUS_MIPI_DSI] = { 0x2c0, BIT(1) }, > > + [RST_BUS_CE] = { 0x2c0, BIT(5) }, > > + [RST_BUS_DMA] = { 0x2c0, BIT(6) }, > > + [RST_BUS_MMC0] = { 0x2c0, BIT(8) }, > > + [RST_BUS_MMC1] = { 0x2c0, BIT(9) }, > > + [RST_BUS_MMC2] = { 0x2c0, BIT(10) }, > > + [RST_BUS_NAND] = { 0x2c0, BIT(13) }, > > + [RST_BUS_DRAM] = { 0x2c0, BIT(14) }, > > + [RST_BUS_EMAC] = { 0x2c0, BIT(17) }, > > + [RST_BUS_TS] = { 0x2c0, BIT(18) }, > > + [RST_BUS_HSTIMER] = { 0x2c0, BIT(19) }, > > + [RST_BUS_SPI0] = { 0x2c0, BIT(20) }, > > + [RST_BUS_SPI1] = { 0x2c0, BIT(21) }, > > + [RST_BUS_OTG] = { 0x2c0, BIT(23) }, > > + [RST_BUS_EHCI0] = { 0x2c0, BIT(24) }, > > + [RST_BUS_EHCI1] = { 0x2c0, BIT(25) }, > > + [RST_BUS_OHCI0] = { 0x2c0, BIT(28) }, > > + [RST_BUS_OHCI1] = { 0x2c0, BIT(29) }, > > + > > + [RST_BUS_VE] = { 0x2c4, BIT(0) }, > > + [RST_BUS_TCON0] = { 0x2c4, BIT(3) }, > > + [RST_BUS_TCON1] = { 0x2c4, BIT(4) }, > > + [RST_BUS_DEINTERLACE] = { 0x2c4, BIT(5) }, > > + [RST_BUS_CSI] = { 0x2c4, BIT(8) }, > > + [RST_BUS_HDMI0] = { 0x2c4, BIT(10) }, > > + [RST_BUS_HDMI1] = { 0x2c4, BIT(11) }, > > + [RST_BUS_DE] = { 0x2c4, BIT(12) }, > > + [RST_BUS_GPU] = { 0x2c4, BIT(20) }, > > + [RST_BUS_MSGBOX] = { 0x2c4, BIT(21) }, > > + [RST_BUS_SPINLOCK] = { 0x2c4, BIT(22) }, > > + [RST_BUS_DBG] = { 0x2c4, BIT(31) }, > > + > > + [RST_BUS_LVDS] = { 0x2c8, BIT(0) }, > > + > > + [RST_BUS_CODEC] = { 0x2d0, BIT(0) }, > > + [RST_BUS_SPDIF] = { 0x2d0, BIT(1) }, > > + [RST_BUS_THS] = { 0x2d0, BIT(8) }, > > + [RST_BUS_I2S0] = { 0x2d0, BIT(12) }, > > + [RST_BUS_I2S1] = { 0x2d0, BIT(13) }, > > + [RST_BUS_I2S2] = { 0x2d0, BIT(14) }, > > + > > + [RST_BUS_I2C0] = { 0x2d8, BIT(0) }, > > + [RST_BUS_I2C1] = { 0x2d8, BIT(1) }, > > + [RST_BUS_I2C2] = { 0x2d8, BIT(2) }, > > + [RST_BUS_SCR] = { 0x2d8, BIT(5) }, > > + [RST_BUS_UART0] = { 0x2d8, BIT(16) }, > > + [RST_BUS_UART1] = { 0x2d8, BIT(17) }, > > + [RST_BUS_UART2] = { 0x2d8, BIT(18) }, > > + [RST_BUS_UART3] = { 0x2d8, BIT(19) }, > > + [RST_BUS_UART4] = { 0x2d8, BIT(20) }, > > +}; > > + > > +static const struct sunxi_ccu_desc sun50i_a64_ccu_desc = { > > + .ccu_clks = sun50i_a64_ccu_clks, > > + .num_ccu_clks = ARRAY_SIZE(sun50i_a64_ccu_clks), > > + > > + .hw_clks = &sun50i_a64_hw_clks, > > + > > + .resets = sun50i_a64_ccu_resets, > > + .num_resets = ARRAY_SIZE(sun50i_a64_ccu_resets), > > +}; > > + > > +static void __init sun50i_a64_ccu_setup(struct device_node *node) > > +{ > > + void __iomem *reg; > > + u32 val; > > + > > + reg = of_io_request_and_map(node, 0, of_node_full_name(node)); > > + if (IS_ERR(reg)) { > > + pr_err("%s: Could not map the clock registers\n", > > + of_node_full_name(node)); > > + return; > > + } > > + > > + /* Force the PLL-Audio-1x divider to 4 */ > > + val = readl(reg + SUN50I_A64_PLL_AUDIO_REG); > > + val &= ~GENMASK(19, 16); > > + writel(val | (3 << 16), reg + SUN50I_A64_PLL_AUDIO_REG); > > + > > + writel(0x515, reg + SUN50I_A64_PLL_MIPI_REG); > > + > > + sunxi_ccu_probe(node, reg, &sun50i_a64_ccu_desc); > > +} > > +CLK_OF_DECLARE(sun50i_a64_ccu, "allwinner,sun50i-a64-ccu", > > + sun50i_a64_ccu_setup); > > diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-a64.h b/drivers/clk/sunxi-ng/ccu-sun50i-a64.h > > new file mode 100644 > > index 000000000000..e3c77d92af1c > > --- /dev/null > > +++ b/drivers/clk/sunxi-ng/ccu-sun50i-a64.h > > @@ -0,0 +1,68 @@ > > +/* > > + * Copyright 2016 Maxime Ripard > > + * > > + * Maxime Ripard <maxime.ripard@free-electrons.com> > > + * > > + * This program is free software; you can redistribute it and/or modify > > + * it under the terms of the GNU General Public License as published by > > + * the Free Software Foundation; either version 2 of the License, or > > + * (at your option) any later version. > > + * > > + * This program is distributed in the hope that it will be useful, > > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > > + * GNU General Public License for more details. > > + */ > > + > > +#ifndef _CCU_SUN50I_A64_H_ > > +#define _CCU_SUN50I_A64_H_ > > + > > +#include <dt-bindings/clock/sun50i-a64-ccu.h> > > +#include <dt-bindings/reset/sun50i-a64-ccu.h> > > + > > +#define CLK_OSC_12M 0 > > +#define CLK_PLL_CPUX 1 > > +#define CLK_PLL_AUDIO_BASE 2 > > +#define CLK_PLL_AUDIO 3 > > +#define CLK_PLL_AUDIO_2X 4 > > +#define CLK_PLL_AUDIO_4X 5 > > +#define CLK_PLL_AUDIO_8X 6 > > +#define CLK_PLL_VIDEO0 7 > > +#define CLK_PLL_VIDEO0_2X 8 > > +#define CLK_PLL_VE 9 > > +#define CLK_PLL_DDR0 10 > > +#define CLK_PLL_PERIPH0 11 > > +#define CLK_PLL_PERIPH0_2X 12 > > +#define CLK_PLL_PERIPH1 13 > > +#define CLK_PLL_PERIPH1_2X 14 > > +#define CLK_PLL_VIDEO1 15 > > +#define CLK_PLL_GPU 16 > > +#define CLK_PLL_MIPI 17 > > +#define CLK_PLL_HSIC 18 > > +#define CLK_PLL_DE 19 > > +#define CLK_PLL_DDR1 20 > > +#define CLK_CPUX 21 > > +#define CLK_AXI 22 > > +#define CLK_APB 23 > > This is listed but never implemented. Yes, on purpose. If we ever need to implement it, we won't have an headache. > > +#define RST_USB_PHY0 0 > > +#define RST_USB_PHY1 1 > > +#define RST_USB_HSIC 2 > > There's also a DRAM reset in 0xf4 (DRAM configuration) Ack. Thanks! Maxime -- Maxime Ripard, Free Electrons Embedded Linux and Kernel engineering http://free-electrons.com [-- Attachment #2: signature.asc --] [-- Type: application/pgp-signature, Size: 819 bytes --] ^ permalink raw reply [flat|nested] 35+ messages in thread
* [PATCH v2 1/4] clk: sunxi-ng: Add A64 clocks @ 2016-09-17 14:08 ` Maxime Ripard 0 siblings, 0 replies; 35+ messages in thread From: Maxime Ripard @ 2016-09-17 14:08 UTC (permalink / raw) To: linux-arm-kernel Hi, On Sat, Sep 10, 2016 at 11:24:48AM +0800, Chen-Yu Tsai wrote: > > +static SUNXI_CCU_NK_WITH_GATE_LOCK_POSTDIV(pll_periph0_clk, "pll-periph0", > > + "osc24M", 0x028, > > + 8, 5, /* N */ > > + 4, 2, /* K */ > > The manual says to give preference to K >= 2. I suggest swapping N/K and > leaving a note about it, so the actual K is in the inner loop (see ccu_nk.c) > of the factor calculation. It also says that we should fix that frequency (and we don't), so we don't really care. > > +static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_mipi_clk, "pll-mipi", > > + "pll-video0", 0x040, > > + 8, 4, /* N */ > > + 4, 2, /* K */ > > You need a table for K. (Manual says K >= 2). Not really a table, but a minimum, like we have a maximum already. > > +static SUNXI_CCU_DIV_TABLE_WITH_GATE(ths_clk, "ths", "osc24M", > > + 0x074, 0, 2, ths_div_table, BIT(31), 0); > > Even though the mux has only one valid parent, I suggest you still implement it, > in case some bogus value gets put in before the kernel loads. Ack. > > +static const char * const ts_parents[] = { "osc24M", "pll-periph0", }; > > +static SUNXI_CCU_MP_WITH_MUX_GATE(ts_clk, "ts", ts_parents, 0x098, > > + 0, 4, /* M */ > > + 16, 2, /* P */ > > + 24, 2, /* mux */ > > Manual says the mux is 4 bits wide. Ack. > > +static const char * const i2s_parents[] = { "pll-audio-8x", "pll-audio-4x", > > + "pll-audio-2x", "pll-audio" }; > > +static SUNXI_CCU_MUX_WITH_GATE(i2s0_clk, "i2s0", i2s_parents, > > + 0x0b0, 16, 2, BIT(31), 0); > > + > > +static SUNXI_CCU_MUX_WITH_GATE(i2s1_clk, "i2s1", i2s_parents, > > + 0x0b4, 16, 2, BIT(31), 0); > > + > > +static SUNXI_CCU_MUX_WITH_GATE(i2s2_clk, "i2s2", i2s_parents, > > + 0x0b8, 16, 2, BIT(31), 0); > > + > > +static SUNXI_CCU_M_WITH_GATE(spdif_clk, "spdif", "pll-audio", > > + 0x0c0, 0, 4, BIT(31), 0); > > CLK_SET_PARENT_RATE for the above audio clocks? Indeed. > > +static SUNXI_CCU_GATE(usb_phy0_clk, "usb-phy0", "osc24M", > > + 0x0cc, BIT(8), 0); > > +static SUNXI_CCU_GATE(usb_phy1_clk, "usb-phy1", "osc24M", > > + 0x0cc, BIT(9), 0); > > +static SUNXI_CCU_GATE(usb_hsic_clk, "usb-hsic", "pll-hsic", > > + 0x0cc, BIT(10), 0); > > +static SUNXI_CCU_GATE(usb_hsic_12m_clk, "usb-hsic-12M", "osc12M", > > + 0x0cc, BIT(11), 0); > > +static SUNXI_CCU_GATE(usb_ohci0_clk, "usb-ohci0", "osc12M", > > + 0x0cc, BIT(16), 0); > > +static SUNXI_CCU_GATE(usb_ohci1_clk, "usb-ohci1", "usb-ohci0", > > + 0x0cc, BIT(17), 0); > > I guess we aren't modeling the 2 OHCI 12M muxes? To be honest, I can't even make sense of it. Which clocks are using it is unclear to me, so yeah, I don't know. I can probably leave some ID for it though, just in case. > > +static const char * const tcon1_parents[] = { "pll-video0", "pll-video1" }; > > +static const u8 tcon1_table[] = { 0, 2, }; > > +struct ccu_div tcon1_clk = { > > + .enable = BIT(31), > > + .div = _SUNXI_CCU_DIV(0, 4), > > + .mux = _SUNXI_CCU_MUX_TABLE(24, 3, tcon1_table), > > + .common = { > > + .reg = 0x11c, > > + .hw.init = CLK_HW_INIT_PARENTS("tcon1", > > + tcon1_parents, > > + &ccu_div_ops, > > + 0), > > + }, > > +}; > > CLK_SET_PARENT_RATE for the TCON clocks? Yep > > +static SUNXI_CCU_GATE(ac_dig_clk, "ac-dig", "pll-audio", > > + 0x140, BIT(31), 0); > > + > > +static SUNXI_CCU_GATE(ac_dig_4x_clk, "ac-dig-4x", "pll-audio-4x", > > + 0x140, BIT(30), 0); > > CLK_SET_PARENT_RATE for the above audio clocks? Ack. > > +static SUNXI_CCU_GATE(avs_clk, "avs", "osc24M", > > + 0x144, BIT(31), 0); > > + > > +static const char * const hdmi_parents[] = { "pll-video0", "pll-video1" }; > > +static SUNXI_CCU_M_WITH_MUX_GATE(hdmi_clk, "hdmi", hdmi_parents, > > + 0x150, 0, 4, 24, 2, BIT(31), 0); > > Might need CLK_SET_PARENT_RATE for hdmi? Ack > > +static SUNXI_CCU_GATE(hdmi_ddc_clk, "hdmi-ddc", "osc24M", > > + 0x154, BIT(31), 0); > > + > > +static const char * const mbus_parents[] = { "osc24M", "pll-periph0-2x", > > + "pll-ddr0", "pll-ddr1" }; > > +static SUNXI_CCU_M_WITH_MUX_GATE(mbus_clk, "mbus", mbus_parents, > > + 0x15c, 0, 3, 24, 2, BIT(31), CLK_IS_CRITICAL); > > + > > +static const char * const dsi_dphy_parents[] = { "pll-video0", "pll-periph0" }; > > You need a mux table = { 0, 2 } here. Indeed > > +static SUNXI_CCU_M_WITH_MUX_GATE(dsi_dphy_clk, "dsi-dphy", dsi_dphy_parents, > > + 0x168, 0, 3, 24, 2, BIT(31), 0); > > + > > +static SUNXI_CCU_M_WITH_GATE(gpu_clk, "gpu", "pll-gpu", > > + 0x1a0, 0, 3, BIT(31), 0); > > CLK_SET_PARENT_RATE for the GPU clock? Ack > > +static CLK_FIXED_FACTOR(pll_video0_2x_clk, "pll-video0-2x", > > + "pll-video0", 1, 2, 0); > > CLK_SET_PARENT_RATE for pll-video0-2x. Ack > > > + > > +static struct ccu_common *sun50i_a64_ccu_clks[] = { > > + &pll_cpux_clk.common, > > + &pll_audio_base_clk.common, > > + &pll_video0_clk.common, > > + &pll_ve_clk.common, > > + &pll_ddr0_clk.common, > > + &pll_periph0_clk.common, > > + &pll_periph1_clk.common, > > + &pll_video1_clk.common, > > + &pll_gpu_clk.common, > > + &pll_mipi_clk.common, > > + &pll_hsic_clk.common, > > + &pll_de_clk.common, > > + &pll_ddr1_clk.common, > > + &cpux_clk.common, > > + &axi_clk.common, > > + &ahb1_clk.common, > > + &apb1_clk.common, > > + &apb2_clk.common, > > + &ahb2_clk.common, > > + &bus_mipi_dsi_clk.common, > > + &bus_ce_clk.common, > > + &bus_dma_clk.common, > > + &bus_mmc0_clk.common, > > + &bus_mmc1_clk.common, > > + &bus_mmc2_clk.common, > > + &bus_nand_clk.common, > > + &bus_dram_clk.common, > > + &bus_emac_clk.common, > > + &bus_ts_clk.common, > > + &bus_hstimer_clk.common, > > + &bus_spi0_clk.common, > > + &bus_spi1_clk.common, > > + &bus_otg_clk.common, > > + &bus_ehci0_clk.common, > > + &bus_ehci1_clk.common, > > + &bus_ohci0_clk.common, > > + &bus_ohci1_clk.common, > > + &bus_ve_clk.common, > > + &bus_tcon0_clk.common, > > + &bus_tcon1_clk.common, > > + &bus_deinterlace_clk.common, > > + &bus_csi_clk.common, > > + &bus_hdmi_clk.common, > > + &bus_de_clk.common, > > + &bus_gpu_clk.common, > > + &bus_msgbox_clk.common, > > + &bus_spinlock_clk.common, > > + &bus_codec_clk.common, > > + &bus_spdif_clk.common, > > + &bus_pio_clk.common, > > + &bus_ths_clk.common, > > + &bus_i2s0_clk.common, > > + &bus_i2s1_clk.common, > > + &bus_i2s2_clk.common, > > + &bus_i2c0_clk.common, > > + &bus_i2c1_clk.common, > > + &bus_i2c2_clk.common, > > + &bus_scr_clk.common, > > + &bus_uart0_clk.common, > > + &bus_uart1_clk.common, > > + &bus_uart2_clk.common, > > + &bus_uart3_clk.common, > > + &bus_uart4_clk.common, > > + &bus_dbg_clk.common, > > + &ths_clk.common, > > + &nand_clk.common, > > + &mmc0_clk.common, > > + &mmc1_clk.common, > > + &mmc2_clk.common, > > + &ts_clk.common, > > + &ce_clk.common, > > + &spi0_clk.common, > > + &spi1_clk.common, > > + &i2s0_clk.common, > > + &i2s1_clk.common, > > + &i2s2_clk.common, > > + &spdif_clk.common, > > + &usb_phy0_clk.common, > > + &usb_phy1_clk.common, > > + &usb_hsic_clk.common, > > + &usb_hsic_12m_clk.common, > > + &usb_ohci0_clk.common, > > + &usb_ohci1_clk.common, > > + &dram_clk.common, > > + &dram_ve_clk.common, > > + &dram_csi_clk.common, > > + &dram_deinterlace_clk.common, > > + &dram_ts_clk.common, > > + &de_clk.common, > > + &tcon0_clk.common, > > + &tcon1_clk.common, > > + &deinterlace_clk.common, > > + &csi_misc_clk.common, > > + &csi_sclk_clk.common, > > + &csi_mclk_clk.common, > > + &ve_clk.common, > > + &ac_dig_clk.common, > > + &ac_dig_4x_clk.common, > > + &avs_clk.common, > > + &hdmi_clk.common, > > + &hdmi_ddc_clk.common, > > + &mbus_clk.common, > > + &dsi_dphy_clk.common, > > + &gpu_clk.common, > > +}; > > + > > +static struct clk_hw_onecell_data sun50i_a64_hw_clks = { > > + .hws = { > > + [CLK_OSC_12M] = &osc12M_clk.hw, > > + [CLK_PLL_CPUX] = &pll_cpux_clk.common.hw, > > + [CLK_PLL_AUDIO_BASE] = &pll_audio_base_clk.common.hw, > > + [CLK_PLL_AUDIO] = &pll_audio_clk.hw, > > + [CLK_PLL_AUDIO_2X] = &pll_audio_2x_clk.hw, > > + [CLK_PLL_AUDIO_4X] = &pll_audio_4x_clk.hw, > > + [CLK_PLL_AUDIO_8X] = &pll_audio_8x_clk.hw, > > + [CLK_PLL_VIDEO0] = &pll_video0_clk.common.hw, > > + [CLK_PLL_VIDEO0_2X] = &pll_video0_2x_clk.hw, > > + [CLK_PLL_VE] = &pll_ve_clk.common.hw, > > + [CLK_PLL_DDR0] = &pll_ddr0_clk.common.hw, > > + [CLK_PLL_PERIPH0] = &pll_periph0_clk.common.hw, > > + [CLK_PLL_PERIPH0_2X] = &pll_periph0_2x_clk.hw, > > + [CLK_PLL_PERIPH1] = &pll_periph1_clk.common.hw, > > + [CLK_PLL_PERIPH1_2X] = &pll_periph1_2x_clk.hw, > > + [CLK_PLL_VIDEO1] = &pll_video1_clk.common.hw, > > + [CLK_PLL_GPU] = &pll_gpu_clk.common.hw, > > + [CLK_PLL_MIPI] = &pll_mipi_clk.common.hw, > > + [CLK_PLL_HSIC] = &pll_hsic_clk.common.hw, > > + [CLK_PLL_DE] = &pll_de_clk.common.hw, > > + [CLK_PLL_DDR1] = &pll_ddr1_clk.common.hw, > > + [CLK_CPUX] = &cpux_clk.common.hw, > > + [CLK_AXI] = &axi_clk.common.hw, > > + [CLK_AHB1] = &ahb1_clk.common.hw, > > + [CLK_APB1] = &apb1_clk.common.hw, > > + [CLK_APB2] = &apb2_clk.common.hw, > > + [CLK_AHB2] = &ahb2_clk.common.hw, > > + [CLK_BUS_MIPI_DSI] = &bus_mipi_dsi_clk.common.hw, > > + [CLK_BUS_CE] = &bus_ce_clk.common.hw, > > + [CLK_BUS_DMA] = &bus_dma_clk.common.hw, > > + [CLK_BUS_MMC0] = &bus_mmc0_clk.common.hw, > > + [CLK_BUS_MMC1] = &bus_mmc1_clk.common.hw, > > + [CLK_BUS_MMC2] = &bus_mmc2_clk.common.hw, > > + [CLK_BUS_NAND] = &bus_nand_clk.common.hw, > > + [CLK_BUS_DRAM] = &bus_dram_clk.common.hw, > > + [CLK_BUS_EMAC] = &bus_emac_clk.common.hw, > > + [CLK_BUS_TS] = &bus_ts_clk.common.hw, > > + [CLK_BUS_HSTIMER] = &bus_hstimer_clk.common.hw, > > + [CLK_BUS_SPI0] = &bus_spi0_clk.common.hw, > > + [CLK_BUS_SPI1] = &bus_spi1_clk.common.hw, > > + [CLK_BUS_OTG] = &bus_otg_clk.common.hw, > > + [CLK_BUS_EHCI0] = &bus_ehci0_clk.common.hw, > > + [CLK_BUS_EHCI1] = &bus_ehci1_clk.common.hw, > > + [CLK_BUS_OHCI0] = &bus_ohci0_clk.common.hw, > > + [CLK_BUS_OHCI1] = &bus_ohci1_clk.common.hw, > > + [CLK_BUS_VE] = &bus_ve_clk.common.hw, > > + [CLK_BUS_TCON0] = &bus_tcon0_clk.common.hw, > > + [CLK_BUS_TCON1] = &bus_tcon1_clk.common.hw, > > + [CLK_BUS_DEINTERLACE] = &bus_deinterlace_clk.common.hw, > > + [CLK_BUS_CSI] = &bus_csi_clk.common.hw, > > + [CLK_BUS_HDMI] = &bus_hdmi_clk.common.hw, > > + [CLK_BUS_DE] = &bus_de_clk.common.hw, > > + [CLK_BUS_GPU] = &bus_gpu_clk.common.hw, > > + [CLK_BUS_MSGBOX] = &bus_msgbox_clk.common.hw, > > + [CLK_BUS_SPINLOCK] = &bus_spinlock_clk.common.hw, > > + [CLK_BUS_CODEC] = &bus_codec_clk.common.hw, > > + [CLK_BUS_SPDIF] = &bus_spdif_clk.common.hw, > > + [CLK_BUS_PIO] = &bus_pio_clk.common.hw, > > + [CLK_BUS_THS] = &bus_ths_clk.common.hw, > > + [CLK_BUS_I2S0] = &bus_i2s0_clk.common.hw, > > + [CLK_BUS_I2S1] = &bus_i2s1_clk.common.hw, > > + [CLK_BUS_I2S2] = &bus_i2s2_clk.common.hw, > > + [CLK_BUS_I2C0] = &bus_i2c0_clk.common.hw, > > + [CLK_BUS_I2C1] = &bus_i2c1_clk.common.hw, > > + [CLK_BUS_I2C2] = &bus_i2c2_clk.common.hw, > > + [CLK_BUS_UART0] = &bus_uart0_clk.common.hw, > > + [CLK_BUS_UART1] = &bus_uart1_clk.common.hw, > > + [CLK_BUS_UART2] = &bus_uart2_clk.common.hw, > > + [CLK_BUS_UART3] = &bus_uart3_clk.common.hw, > > + [CLK_BUS_UART4] = &bus_uart4_clk.common.hw, > > + [CLK_BUS_SCR] = &bus_scr_clk.common.hw, > > + [CLK_BUS_DBG] = &bus_dbg_clk.common.hw, > > + [CLK_THS] = &ths_clk.common.hw, > > + [CLK_NAND] = &nand_clk.common.hw, > > + [CLK_MMC0] = &mmc0_clk.common.hw, > > + [CLK_MMC1] = &mmc1_clk.common.hw, > > + [CLK_MMC2] = &mmc2_clk.common.hw, > > + [CLK_TS] = &ts_clk.common.hw, > > + [CLK_CE] = &ce_clk.common.hw, > > + [CLK_SPI0] = &spi0_clk.common.hw, > > + [CLK_SPI1] = &spi1_clk.common.hw, > > + [CLK_I2S0] = &i2s0_clk.common.hw, > > + [CLK_I2S1] = &i2s1_clk.common.hw, > > + [CLK_I2S2] = &i2s2_clk.common.hw, > > + [CLK_SPDIF] = &spdif_clk.common.hw, > > + [CLK_USB_PHY0] = &usb_phy0_clk.common.hw, > > + [CLK_USB_PHY1] = &usb_phy1_clk.common.hw, > > + [CLK_USB_HSIC] = &usb_hsic_clk.common.hw, > > + [CLK_USB_HSIC_12M] = &usb_hsic_12m_clk.common.hw, > > + [CLK_USB_OHCI0] = &usb_ohci0_clk.common.hw, > > + [CLK_USB_OHCI1] = &usb_ohci1_clk.common.hw, > > + [CLK_DRAM] = &dram_clk.common.hw, > > + [CLK_DRAM_VE] = &dram_ve_clk.common.hw, > > + [CLK_DRAM_CSI] = &dram_csi_clk.common.hw, > > + [CLK_DRAM_DEINTERLACE] = &dram_deinterlace_clk.common.hw, > > + [CLK_DRAM_TS] = &dram_ts_clk.common.hw, > > + [CLK_DE] = &de_clk.common.hw, > > + [CLK_TCON0] = &tcon0_clk.common.hw, > > + [CLK_TCON1] = &tcon1_clk.common.hw, > > + [CLK_DEINTERLACE] = &deinterlace_clk.common.hw, > > + [CLK_CSI_MISC] = &csi_misc_clk.common.hw, > > + [CLK_CSI_SCLK] = &csi_sclk_clk.common.hw, > > + [CLK_CSI_MCLK] = &csi_mclk_clk.common.hw, > > + [CLK_VE] = &ve_clk.common.hw, > > + [CLK_AC_DIG] = &ac_dig_clk.common.hw, > > + [CLK_AC_DIG_4X] = &ac_dig_4x_clk.common.hw, > > + [CLK_AVS] = &avs_clk.common.hw, > > + [CLK_HDMI] = &hdmi_clk.common.hw, > > + [CLK_HDMI_DDC] = &hdmi_ddc_clk.common.hw, > > + [CLK_MBUS] = &mbus_clk.common.hw, > > + [CLK_DSI_DPHY] = &dsi_dphy_clk.common.hw, > > + [CLK_GPU] = &gpu_clk.common.hw, > > + }, > > + .num = CLK_NUMBER, > > +}; > > + > > +static struct ccu_reset_map sun50i_a64_ccu_resets[] = { > > + [RST_USB_PHY0] = { 0x0cc, BIT(0) }, > > + [RST_USB_PHY1] = { 0x0cc, BIT(1) }, > > + [RST_USB_HSIC] = { 0x0cc, BIT(2) }, > > + > > + > > + [RST_MBUS] = { 0x0fc, BIT(31) }, > > + > > + [RST_BUS_MIPI_DSI] = { 0x2c0, BIT(1) }, > > + [RST_BUS_CE] = { 0x2c0, BIT(5) }, > > + [RST_BUS_DMA] = { 0x2c0, BIT(6) }, > > + [RST_BUS_MMC0] = { 0x2c0, BIT(8) }, > > + [RST_BUS_MMC1] = { 0x2c0, BIT(9) }, > > + [RST_BUS_MMC2] = { 0x2c0, BIT(10) }, > > + [RST_BUS_NAND] = { 0x2c0, BIT(13) }, > > + [RST_BUS_DRAM] = { 0x2c0, BIT(14) }, > > + [RST_BUS_EMAC] = { 0x2c0, BIT(17) }, > > + [RST_BUS_TS] = { 0x2c0, BIT(18) }, > > + [RST_BUS_HSTIMER] = { 0x2c0, BIT(19) }, > > + [RST_BUS_SPI0] = { 0x2c0, BIT(20) }, > > + [RST_BUS_SPI1] = { 0x2c0, BIT(21) }, > > + [RST_BUS_OTG] = { 0x2c0, BIT(23) }, > > + [RST_BUS_EHCI0] = { 0x2c0, BIT(24) }, > > + [RST_BUS_EHCI1] = { 0x2c0, BIT(25) }, > > + [RST_BUS_OHCI0] = { 0x2c0, BIT(28) }, > > + [RST_BUS_OHCI1] = { 0x2c0, BIT(29) }, > > + > > + [RST_BUS_VE] = { 0x2c4, BIT(0) }, > > + [RST_BUS_TCON0] = { 0x2c4, BIT(3) }, > > + [RST_BUS_TCON1] = { 0x2c4, BIT(4) }, > > + [RST_BUS_DEINTERLACE] = { 0x2c4, BIT(5) }, > > + [RST_BUS_CSI] = { 0x2c4, BIT(8) }, > > + [RST_BUS_HDMI0] = { 0x2c4, BIT(10) }, > > + [RST_BUS_HDMI1] = { 0x2c4, BIT(11) }, > > + [RST_BUS_DE] = { 0x2c4, BIT(12) }, > > + [RST_BUS_GPU] = { 0x2c4, BIT(20) }, > > + [RST_BUS_MSGBOX] = { 0x2c4, BIT(21) }, > > + [RST_BUS_SPINLOCK] = { 0x2c4, BIT(22) }, > > + [RST_BUS_DBG] = { 0x2c4, BIT(31) }, > > + > > + [RST_BUS_LVDS] = { 0x2c8, BIT(0) }, > > + > > + [RST_BUS_CODEC] = { 0x2d0, BIT(0) }, > > + [RST_BUS_SPDIF] = { 0x2d0, BIT(1) }, > > + [RST_BUS_THS] = { 0x2d0, BIT(8) }, > > + [RST_BUS_I2S0] = { 0x2d0, BIT(12) }, > > + [RST_BUS_I2S1] = { 0x2d0, BIT(13) }, > > + [RST_BUS_I2S2] = { 0x2d0, BIT(14) }, > > + > > + [RST_BUS_I2C0] = { 0x2d8, BIT(0) }, > > + [RST_BUS_I2C1] = { 0x2d8, BIT(1) }, > > + [RST_BUS_I2C2] = { 0x2d8, BIT(2) }, > > + [RST_BUS_SCR] = { 0x2d8, BIT(5) }, > > + [RST_BUS_UART0] = { 0x2d8, BIT(16) }, > > + [RST_BUS_UART1] = { 0x2d8, BIT(17) }, > > + [RST_BUS_UART2] = { 0x2d8, BIT(18) }, > > + [RST_BUS_UART3] = { 0x2d8, BIT(19) }, > > + [RST_BUS_UART4] = { 0x2d8, BIT(20) }, > > +}; > > + > > +static const struct sunxi_ccu_desc sun50i_a64_ccu_desc = { > > + .ccu_clks = sun50i_a64_ccu_clks, > > + .num_ccu_clks = ARRAY_SIZE(sun50i_a64_ccu_clks), > > + > > + .hw_clks = &sun50i_a64_hw_clks, > > + > > + .resets = sun50i_a64_ccu_resets, > > + .num_resets = ARRAY_SIZE(sun50i_a64_ccu_resets), > > +}; > > + > > +static void __init sun50i_a64_ccu_setup(struct device_node *node) > > +{ > > + void __iomem *reg; > > + u32 val; > > + > > + reg = of_io_request_and_map(node, 0, of_node_full_name(node)); > > + if (IS_ERR(reg)) { > > + pr_err("%s: Could not map the clock registers\n", > > + of_node_full_name(node)); > > + return; > > + } > > + > > + /* Force the PLL-Audio-1x divider to 4 */ > > + val = readl(reg + SUN50I_A64_PLL_AUDIO_REG); > > + val &= ~GENMASK(19, 16); > > + writel(val | (3 << 16), reg + SUN50I_A64_PLL_AUDIO_REG); > > + > > + writel(0x515, reg + SUN50I_A64_PLL_MIPI_REG); > > + > > + sunxi_ccu_probe(node, reg, &sun50i_a64_ccu_desc); > > +} > > +CLK_OF_DECLARE(sun50i_a64_ccu, "allwinner,sun50i-a64-ccu", > > + sun50i_a64_ccu_setup); > > diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-a64.h b/drivers/clk/sunxi-ng/ccu-sun50i-a64.h > > new file mode 100644 > > index 000000000000..e3c77d92af1c > > --- /dev/null > > +++ b/drivers/clk/sunxi-ng/ccu-sun50i-a64.h > > @@ -0,0 +1,68 @@ > > +/* > > + * Copyright 2016 Maxime Ripard > > + * > > + * Maxime Ripard <maxime.ripard@free-electrons.com> > > + * > > + * This program is free software; you can redistribute it and/or modify > > + * it under the terms of the GNU General Public License as published by > > + * the Free Software Foundation; either version 2 of the License, or > > + * (at your option) any later version. > > + * > > + * This program is distributed in the hope that it will be useful, > > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > > + * GNU General Public License for more details. > > + */ > > + > > +#ifndef _CCU_SUN50I_A64_H_ > > +#define _CCU_SUN50I_A64_H_ > > + > > +#include <dt-bindings/clock/sun50i-a64-ccu.h> > > +#include <dt-bindings/reset/sun50i-a64-ccu.h> > > + > > +#define CLK_OSC_12M 0 > > +#define CLK_PLL_CPUX 1 > > +#define CLK_PLL_AUDIO_BASE 2 > > +#define CLK_PLL_AUDIO 3 > > +#define CLK_PLL_AUDIO_2X 4 > > +#define CLK_PLL_AUDIO_4X 5 > > +#define CLK_PLL_AUDIO_8X 6 > > +#define CLK_PLL_VIDEO0 7 > > +#define CLK_PLL_VIDEO0_2X 8 > > +#define CLK_PLL_VE 9 > > +#define CLK_PLL_DDR0 10 > > +#define CLK_PLL_PERIPH0 11 > > +#define CLK_PLL_PERIPH0_2X 12 > > +#define CLK_PLL_PERIPH1 13 > > +#define CLK_PLL_PERIPH1_2X 14 > > +#define CLK_PLL_VIDEO1 15 > > +#define CLK_PLL_GPU 16 > > +#define CLK_PLL_MIPI 17 > > +#define CLK_PLL_HSIC 18 > > +#define CLK_PLL_DE 19 > > +#define CLK_PLL_DDR1 20 > > +#define CLK_CPUX 21 > > +#define CLK_AXI 22 > > +#define CLK_APB 23 > > This is listed but never implemented. Yes, on purpose. If we ever need to implement it, we won't have an headache. > > +#define RST_USB_PHY0 0 > > +#define RST_USB_PHY1 1 > > +#define RST_USB_HSIC 2 > > There's also a DRAM reset in 0xf4 (DRAM configuration) Ack. Thanks! Maxime -- Maxime Ripard, Free Electrons Embedded Linux and Kernel engineering http://free-electrons.com -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 819 bytes Desc: not available URL: <http://lists.infradead.org/pipermail/linux-arm-kernel/attachments/20160917/b43d379f/attachment-0001.sig> ^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [PATCH v2 1/4] clk: sunxi-ng: Add A64 clocks 2016-09-09 20:10 ` Maxime Ripard @ 2016-09-14 21:45 ` Stephen Boyd -1 siblings, 0 replies; 35+ messages in thread From: Stephen Boyd @ 2016-09-14 21:45 UTC (permalink / raw) To: Maxime Ripard Cc: Mike Turquette, Chen-Yu Tsai, linux-arm-kernel, Andre Przywara, linux-clk, linux-kernel, linux-sunxi On 09/09, Maxime Ripard wrote: > index 106cba27c331..964f22091a10 100644 > --- a/drivers/clk/sunxi-ng/Makefile > +++ b/drivers/clk/sunxi-ng/Makefile > @@ -22,3 +22,4 @@ obj-$(CONFIG_SUN6I_A31_CCU) += ccu-sun6i-a31.o > obj-$(CONFIG_SUN8I_A23_CCU) += ccu-sun8i-a23.o > obj-$(CONFIG_SUN8I_A33_CCU) += ccu-sun8i-a33.o > obj-$(CONFIG_SUN8I_H3_CCU) += ccu-sun8i-h3.o > +obj-$(CONFIG_SUN50I_A64_CCU) += ccu-sun50i-a64.o Maybe do alphanumeric ordering? > diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c > new file mode 100644 > index 000000000000..d51ee416f515 > --- /dev/null > +++ b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c > @@ -0,0 +1,870 @@ > + > +static void __init sun50i_a64_ccu_setup(struct device_node *node) > +{ > + void __iomem *reg; > + u32 val; > + > + reg = of_io_request_and_map(node, 0, of_node_full_name(node)); > + if (IS_ERR(reg)) { > + pr_err("%s: Could not map the clock registers\n", > + of_node_full_name(node)); > + return; > + } > + > + /* Force the PLL-Audio-1x divider to 4 */ > + val = readl(reg + SUN50I_A64_PLL_AUDIO_REG); > + val &= ~GENMASK(19, 16); > + writel(val | (3 << 16), reg + SUN50I_A64_PLL_AUDIO_REG); > + > + writel(0x515, reg + SUN50I_A64_PLL_MIPI_REG); > + > + sunxi_ccu_probe(node, reg, &sun50i_a64_ccu_desc); > +} > +CLK_OF_DECLARE(sun50i_a64_ccu, "allwinner,sun50i-a64-ccu", > + sun50i_a64_ccu_setup); Is there a reason it can't be a platform driver? -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project ^ permalink raw reply [flat|nested] 35+ messages in thread
* [PATCH v2 1/4] clk: sunxi-ng: Add A64 clocks @ 2016-09-14 21:45 ` Stephen Boyd 0 siblings, 0 replies; 35+ messages in thread From: Stephen Boyd @ 2016-09-14 21:45 UTC (permalink / raw) To: linux-arm-kernel On 09/09, Maxime Ripard wrote: > index 106cba27c331..964f22091a10 100644 > --- a/drivers/clk/sunxi-ng/Makefile > +++ b/drivers/clk/sunxi-ng/Makefile > @@ -22,3 +22,4 @@ obj-$(CONFIG_SUN6I_A31_CCU) += ccu-sun6i-a31.o > obj-$(CONFIG_SUN8I_A23_CCU) += ccu-sun8i-a23.o > obj-$(CONFIG_SUN8I_A33_CCU) += ccu-sun8i-a33.o > obj-$(CONFIG_SUN8I_H3_CCU) += ccu-sun8i-h3.o > +obj-$(CONFIG_SUN50I_A64_CCU) += ccu-sun50i-a64.o Maybe do alphanumeric ordering? > diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c > new file mode 100644 > index 000000000000..d51ee416f515 > --- /dev/null > +++ b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c > @@ -0,0 +1,870 @@ > + > +static void __init sun50i_a64_ccu_setup(struct device_node *node) > +{ > + void __iomem *reg; > + u32 val; > + > + reg = of_io_request_and_map(node, 0, of_node_full_name(node)); > + if (IS_ERR(reg)) { > + pr_err("%s: Could not map the clock registers\n", > + of_node_full_name(node)); > + return; > + } > + > + /* Force the PLL-Audio-1x divider to 4 */ > + val = readl(reg + SUN50I_A64_PLL_AUDIO_REG); > + val &= ~GENMASK(19, 16); > + writel(val | (3 << 16), reg + SUN50I_A64_PLL_AUDIO_REG); > + > + writel(0x515, reg + SUN50I_A64_PLL_MIPI_REG); > + > + sunxi_ccu_probe(node, reg, &sun50i_a64_ccu_desc); > +} > +CLK_OF_DECLARE(sun50i_a64_ccu, "allwinner,sun50i-a64-ccu", > + sun50i_a64_ccu_setup); Is there a reason it can't be a platform driver? -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project ^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [PATCH v2 1/4] clk: sunxi-ng: Add A64 clocks 2016-09-14 21:45 ` Stephen Boyd @ 2016-09-17 14:23 ` Maxime Ripard -1 siblings, 0 replies; 35+ messages in thread From: Maxime Ripard @ 2016-09-17 14:23 UTC (permalink / raw) To: Stephen Boyd Cc: Mike Turquette, Chen-Yu Tsai, linux-arm-kernel, Andre Przywara, linux-clk, linux-kernel, linux-sunxi [-- Attachment #1: Type: text/plain, Size: 1968 bytes --] Hi Stephen, On Wed, Sep 14, 2016 at 02:45:54PM -0700, Stephen Boyd wrote: > On 09/09, Maxime Ripard wrote: > > index 106cba27c331..964f22091a10 100644 > > --- a/drivers/clk/sunxi-ng/Makefile > > +++ b/drivers/clk/sunxi-ng/Makefile > > @@ -22,3 +22,4 @@ obj-$(CONFIG_SUN6I_A31_CCU) += ccu-sun6i-a31.o > > obj-$(CONFIG_SUN8I_A23_CCU) += ccu-sun8i-a23.o > > obj-$(CONFIG_SUN8I_A33_CCU) += ccu-sun8i-a33.o > > obj-$(CONFIG_SUN8I_H3_CCU) += ccu-sun8i-h3.o > > +obj-$(CONFIG_SUN50I_A64_CCU) += ccu-sun50i-a64.o > > Maybe do alphanumeric ordering? Yes, of course. > > diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c > > new file mode 100644 > > index 000000000000..d51ee416f515 > > --- /dev/null > > +++ b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c > > @@ -0,0 +1,870 @@ > > + > > +static void __init sun50i_a64_ccu_setup(struct device_node *node) > > +{ > > + void __iomem *reg; > > + u32 val; > > + > > + reg = of_io_request_and_map(node, 0, of_node_full_name(node)); > > + if (IS_ERR(reg)) { > > + pr_err("%s: Could not map the clock registers\n", > > + of_node_full_name(node)); > > + return; > > + } > > + > > + /* Force the PLL-Audio-1x divider to 4 */ > > + val = readl(reg + SUN50I_A64_PLL_AUDIO_REG); > > + val &= ~GENMASK(19, 16); > > + writel(val | (3 << 16), reg + SUN50I_A64_PLL_AUDIO_REG); > > + > > + writel(0x515, reg + SUN50I_A64_PLL_MIPI_REG); > > + > > + sunxi_ccu_probe(node, reg, &sun50i_a64_ccu_desc); > > +} > > +CLK_OF_DECLARE(sun50i_a64_ccu, "allwinner,sun50i-a64-ccu", > > + sun50i_a64_ccu_setup); > > Is there a reason it can't be a platform driver? We have timers connected to those clocks. I'm not sure we'll ever use them, since we also have the arch timers, and we can always change that later, I'll change that. Maxime -- Maxime Ripard, Free Electrons Embedded Linux and Kernel engineering http://free-electrons.com [-- Attachment #2: signature.asc --] [-- Type: application/pgp-signature, Size: 819 bytes --] ^ permalink raw reply [flat|nested] 35+ messages in thread
* [PATCH v2 1/4] clk: sunxi-ng: Add A64 clocks @ 2016-09-17 14:23 ` Maxime Ripard 0 siblings, 0 replies; 35+ messages in thread From: Maxime Ripard @ 2016-09-17 14:23 UTC (permalink / raw) To: linux-arm-kernel Hi Stephen, On Wed, Sep 14, 2016 at 02:45:54PM -0700, Stephen Boyd wrote: > On 09/09, Maxime Ripard wrote: > > index 106cba27c331..964f22091a10 100644 > > --- a/drivers/clk/sunxi-ng/Makefile > > +++ b/drivers/clk/sunxi-ng/Makefile > > @@ -22,3 +22,4 @@ obj-$(CONFIG_SUN6I_A31_CCU) += ccu-sun6i-a31.o > > obj-$(CONFIG_SUN8I_A23_CCU) += ccu-sun8i-a23.o > > obj-$(CONFIG_SUN8I_A33_CCU) += ccu-sun8i-a33.o > > obj-$(CONFIG_SUN8I_H3_CCU) += ccu-sun8i-h3.o > > +obj-$(CONFIG_SUN50I_A64_CCU) += ccu-sun50i-a64.o > > Maybe do alphanumeric ordering? Yes, of course. > > diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c > > new file mode 100644 > > index 000000000000..d51ee416f515 > > --- /dev/null > > +++ b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c > > @@ -0,0 +1,870 @@ > > + > > +static void __init sun50i_a64_ccu_setup(struct device_node *node) > > +{ > > + void __iomem *reg; > > + u32 val; > > + > > + reg = of_io_request_and_map(node, 0, of_node_full_name(node)); > > + if (IS_ERR(reg)) { > > + pr_err("%s: Could not map the clock registers\n", > > + of_node_full_name(node)); > > + return; > > + } > > + > > + /* Force the PLL-Audio-1x divider to 4 */ > > + val = readl(reg + SUN50I_A64_PLL_AUDIO_REG); > > + val &= ~GENMASK(19, 16); > > + writel(val | (3 << 16), reg + SUN50I_A64_PLL_AUDIO_REG); > > + > > + writel(0x515, reg + SUN50I_A64_PLL_MIPI_REG); > > + > > + sunxi_ccu_probe(node, reg, &sun50i_a64_ccu_desc); > > +} > > +CLK_OF_DECLARE(sun50i_a64_ccu, "allwinner,sun50i-a64-ccu", > > + sun50i_a64_ccu_setup); > > Is there a reason it can't be a platform driver? We have timers connected to those clocks. I'm not sure we'll ever use them, since we also have the arch timers, and we can always change that later, I'll change that. Maxime -- Maxime Ripard, Free Electrons Embedded Linux and Kernel engineering http://free-electrons.com -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 819 bytes Desc: not available URL: <http://lists.infradead.org/pipermail/linux-arm-kernel/attachments/20160917/cb0efd43/attachment.sig> ^ permalink raw reply [flat|nested] 35+ messages in thread
* [PATCH v2 2/4] Documentation: devicetree: add vendor prefix for Pine64 2016-09-09 20:10 ` Maxime Ripard @ 2016-09-09 20:10 ` Maxime Ripard -1 siblings, 0 replies; 35+ messages in thread From: Maxime Ripard @ 2016-09-09 20:10 UTC (permalink / raw) To: Mike Turquette, Stephen Boyd, Chen-Yu Tsai, Maxime Ripard Cc: linux-arm-kernel, Andre Przywara, linux-clk, linux-kernel, linux-sunxi From: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Rob Herring <robh@kernel.org> [Maxime: Change title prefix to match the usual style] Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> --- Documentation/devicetree/bindings/vendor-prefixes.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt index 1992aa97d45a..492f92c9a2b2 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.txt +++ b/Documentation/devicetree/bindings/vendor-prefixes.txt @@ -199,6 +199,7 @@ parade Parade Technologies Inc. pericom Pericom Technology Inc. phytec PHYTEC Messtechnik GmbH picochip Picochip Ltd +pine64 Pine64 plathome Plat'Home Co., Ltd. plda PLDA pixcir PIXCIR MICROELECTRONICS Co., Ltd -- 2.9.3 ^ permalink raw reply related [flat|nested] 35+ messages in thread
* [PATCH v2 2/4] Documentation: devicetree: add vendor prefix for Pine64 @ 2016-09-09 20:10 ` Maxime Ripard 0 siblings, 0 replies; 35+ messages in thread From: Maxime Ripard @ 2016-09-09 20:10 UTC (permalink / raw) To: linux-arm-kernel From: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Rob Herring <robh@kernel.org> [Maxime: Change title prefix to match the usual style] Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> --- Documentation/devicetree/bindings/vendor-prefixes.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt index 1992aa97d45a..492f92c9a2b2 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.txt +++ b/Documentation/devicetree/bindings/vendor-prefixes.txt @@ -199,6 +199,7 @@ parade Parade Technologies Inc. pericom Pericom Technology Inc. phytec PHYTEC Messtechnik GmbH picochip Picochip Ltd +pine64 Pine64 plathome Plat'Home Co., Ltd. plda PLDA pixcir PIXCIR MICROELECTRONICS Co., Ltd -- 2.9.3 ^ permalink raw reply related [flat|nested] 35+ messages in thread
* Re: [PATCH v2 2/4] Documentation: devicetree: add vendor prefix for Pine64 2016-09-09 20:10 ` Maxime Ripard @ 2016-09-10 1:54 ` Chen-Yu Tsai -1 siblings, 0 replies; 35+ messages in thread From: Chen-Yu Tsai @ 2016-09-10 1:54 UTC (permalink / raw) To: Maxime Ripard Cc: Mike Turquette, Stephen Boyd, Chen-Yu Tsai, linux-arm-kernel, Andre Przywara, linux-clk, linux-kernel, linux-sunxi On Sat, Sep 10, 2016 at 4:10 AM, Maxime Ripard <maxime.ripard@free-electrons.com> wrote: > From: Andre Przywara <andre.przywara@arm.com> > > Signed-off-by: Andre Przywara <andre.przywara@arm.com> > Acked-by: Rob Herring <robh@kernel.org> > [Maxime: Change title prefix to match the usual style] > Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Chen-Yu Tsai <wens@csie.org> ^ permalink raw reply [flat|nested] 35+ messages in thread
* [PATCH v2 2/4] Documentation: devicetree: add vendor prefix for Pine64 @ 2016-09-10 1:54 ` Chen-Yu Tsai 0 siblings, 0 replies; 35+ messages in thread From: Chen-Yu Tsai @ 2016-09-10 1:54 UTC (permalink / raw) To: linux-arm-kernel On Sat, Sep 10, 2016 at 4:10 AM, Maxime Ripard <maxime.ripard@free-electrons.com> wrote: > From: Andre Przywara <andre.przywara@arm.com> > > Signed-off-by: Andre Przywara <andre.przywara@arm.com> > Acked-by: Rob Herring <robh@kernel.org> > [Maxime: Change title prefix to match the usual style] > Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Chen-Yu Tsai <wens@csie.org> ^ permalink raw reply [flat|nested] 35+ messages in thread
* [PATCH v2 3/4] arm64: dts: add Allwinner A64 SoC .dtsi 2016-09-09 20:10 ` Maxime Ripard @ 2016-09-09 20:10 ` Maxime Ripard -1 siblings, 0 replies; 35+ messages in thread From: Maxime Ripard @ 2016-09-09 20:10 UTC (permalink / raw) To: Mike Turquette, Stephen Boyd, Chen-Yu Tsai, Maxime Ripard Cc: linux-arm-kernel, Andre Przywara, linux-clk, linux-kernel, linux-sunxi From: Andre Przywara <andre.przywara@arm.com> The Allwinner A64 SoC is a low-cost chip with 4 ARM Cortex-A53 cores and the typical tablet / TV box peripherals. The SoC is based on the (32-bit) Allwinner H3 chip, sharing most of the peripherals and the memory map. Although the cores are proper 64-bit ones, the whole SoC is actually limited to 4GB (including all the supported DRAM), so we use 32-bit address and size cells. This has the nice feature of us being able to reuse the DT for 32-bit kernels as well. This .dtsi lists the hardware that we support so far. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Rob Herring <robh@kernel.org> [Maxime: Convert to CCU binding, drop the MMC support for now] Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> --- Documentation/devicetree/bindings/arm/sunxi.txt | 1 + MAINTAINERS | 1 + arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 279 ++++++++++++++++++++++++ 3 files changed, 281 insertions(+) create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi diff --git a/Documentation/devicetree/bindings/arm/sunxi.txt b/Documentation/devicetree/bindings/arm/sunxi.txt index 7e79fcc36b0d..7e59d8ba86af 100644 --- a/Documentation/devicetree/bindings/arm/sunxi.txt +++ b/Documentation/devicetree/bindings/arm/sunxi.txt @@ -14,3 +14,4 @@ using one of the following compatible strings: allwinner,sun8i-a83t allwinner,sun8i-h3 allwinner,sun9i-a80 + allwinner,sun50i-a64 diff --git a/MAINTAINERS b/MAINTAINERS index 20bb1d00098c..c8c0c85c113f 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -982,6 +982,7 @@ M: Chen-Yu Tsai <wens@csie.org> L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Maintained N: sun[x456789]i +F: arch/arm64/boot/dts/allwinner/ ARM/Allwinner SoC Clock Support M: Emilio López <emilio@elopez.com.ar> diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi new file mode 100644 index 000000000000..028cdbee20aa --- /dev/null +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi @@ -0,0 +1,279 @@ +/* + * Copyright (C) 2016 ARM Ltd. + * based on the Allwinner H3 dtsi: + * Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include <dt-bindings/clock/sun50i-a64-ccu.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/pinctrl/sun4i-a10.h> +#include <dt-bindings/reset/sun50i-a64-ccu.h> + +/ { + interrupt-parent = <&gic>; + #address-cells = <1>; + #size-cells = <1>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "arm,cortex-a53", "arm,armv8"; + device_type = "cpu"; + reg = <0>; + enable-method = "psci"; + }; + + cpu@1 { + compatible = "arm,cortex-a53", "arm,armv8"; + device_type = "cpu"; + reg = <1>; + enable-method = "psci"; + }; + + cpu@2 { + compatible = "arm,cortex-a53", "arm,armv8"; + device_type = "cpu"; + reg = <2>; + enable-method = "psci"; + }; + + cpu@3 { + compatible = "arm,cortex-a53", "arm,armv8"; + device_type = "cpu"; + reg = <3>; + enable-method = "psci"; + }; + }; + + osc24M: osc24M_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <24000000>; + clock-output-names = "osc24M"; + }; + + osc32k: osc32k_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <32768>; + clock-output-names = "osc32k"; + }; + + pmu { + compatible = "arm,cortex-a53-pmu", "arm,armv8-pmuv3"; + interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&cpu0>, + <&cpu1>, + <&cpu2>, + <&cpu3>; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 13 + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, + <GIC_PPI 14 + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, + <GIC_PPI 11 + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, + <GIC_PPI 10 + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + ccu: clock@01c20000 { + compatible = "allwinner,sun50i-a64-ccu"; + reg = <0x01c20000 0x400>; + clocks = <&osc24M>, <&osc32k>; + clock-names = "hosc", "losc"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + pio: pinctrl@1c20800 { + compatible = "allwinner,sun50i-a64-pinctrl"; + reg = <0x01c20800 0x400>; + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_PIO>; + gpio-controller; + #gpio-cells = <3>; + interrupt-controller; + #interrupt-cells = <2>; + + i2c1_pins: i2c1_pins { + allwinner,pins = "PH2", "PH3"; + allwinner,function = "i2c1"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; + + uart0_pins_a: uart0@0 { + allwinner,pins = "PB8", "PB9"; + allwinner,function = "uart0"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; + }; + + uart0: serial@1c28000 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c28000 0x400>; + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&ccu CLK_BUS_UART0>; + resets = <&ccu RST_BUS_UART0>; + status = "disabled"; + }; + + uart1: serial@1c28400 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c28400 0x400>; + interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&ccu CLK_BUS_UART1>; + resets = <&ccu RST_BUS_UART1>; + status = "disabled"; + }; + + uart2: serial@1c28800 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c28800 0x400>; + interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&ccu CLK_BUS_UART2>; + resets = <&ccu RST_BUS_UART2>; + status = "disabled"; + }; + + uart3: serial@1c28c00 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c28c00 0x400>; + interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&ccu CLK_BUS_UART3>; + resets = <&ccu RST_BUS_UART3>; + status = "disabled"; + }; + + uart4: serial@1c29000 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c29000 0x400>; + interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&ccu CLK_BUS_UART4>; + resets = <&ccu RST_BUS_UART4>; + status = "disabled"; + }; + + rtc: rtc@1f00000 { + compatible = "allwinner,sun6i-a31-rtc"; + reg = <0x01f00000 0x54>; + interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; + }; + + i2c0: i2c@1c2ac00 { + compatible = "allwinner,sun6i-a31-i2c"; + reg = <0x01c2ac00 0x400>; + interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_I2C0>; + resets = <&ccu RST_BUS_I2C0>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c1: i2c@1c2b000 { + compatible = "allwinner,sun6i-a31-i2c"; + reg = <0x01c2b000 0x400>; + interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_I2C1>; + resets = <&ccu RST_BUS_I2C1>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c2: i2c@1c2b400 { + compatible = "allwinner,sun6i-a31-i2c"; + reg = <0x01c2b400 0x400>; + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_I2C2>; + resets = <&ccu RST_BUS_I2C2>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + gic: interrupt-controller@1c81000 { + compatible = "arm,gic-400"; + reg = <0x01c81000 0x1000>, + <0x01c82000 0x2000>, + <0x01c84000 0x2000>, + <0x01c86000 0x2000>; + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; + interrupt-controller; + #interrupt-cells = <3>; + }; + }; +}; -- 2.9.3 ^ permalink raw reply related [flat|nested] 35+ messages in thread
* [PATCH v2 3/4] arm64: dts: add Allwinner A64 SoC .dtsi @ 2016-09-09 20:10 ` Maxime Ripard 0 siblings, 0 replies; 35+ messages in thread From: Maxime Ripard @ 2016-09-09 20:10 UTC (permalink / raw) To: linux-arm-kernel From: Andre Przywara <andre.przywara@arm.com> The Allwinner A64 SoC is a low-cost chip with 4 ARM Cortex-A53 cores and the typical tablet / TV box peripherals. The SoC is based on the (32-bit) Allwinner H3 chip, sharing most of the peripherals and the memory map. Although the cores are proper 64-bit ones, the whole SoC is actually limited to 4GB (including all the supported DRAM), so we use 32-bit address and size cells. This has the nice feature of us being able to reuse the DT for 32-bit kernels as well. This .dtsi lists the hardware that we support so far. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Rob Herring <robh@kernel.org> [Maxime: Convert to CCU binding, drop the MMC support for now] Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> --- Documentation/devicetree/bindings/arm/sunxi.txt | 1 + MAINTAINERS | 1 + arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 279 ++++++++++++++++++++++++ 3 files changed, 281 insertions(+) create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi diff --git a/Documentation/devicetree/bindings/arm/sunxi.txt b/Documentation/devicetree/bindings/arm/sunxi.txt index 7e79fcc36b0d..7e59d8ba86af 100644 --- a/Documentation/devicetree/bindings/arm/sunxi.txt +++ b/Documentation/devicetree/bindings/arm/sunxi.txt @@ -14,3 +14,4 @@ using one of the following compatible strings: allwinner,sun8i-a83t allwinner,sun8i-h3 allwinner,sun9i-a80 + allwinner,sun50i-a64 diff --git a/MAINTAINERS b/MAINTAINERS index 20bb1d00098c..c8c0c85c113f 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -982,6 +982,7 @@ M: Chen-Yu Tsai <wens@csie.org> L: linux-arm-kernel at lists.infradead.org (moderated for non-subscribers) S: Maintained N: sun[x456789]i +F: arch/arm64/boot/dts/allwinner/ ARM/Allwinner SoC Clock Support M: Emilio L?pez <emilio@elopez.com.ar> diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi new file mode 100644 index 000000000000..028cdbee20aa --- /dev/null +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi @@ -0,0 +1,279 @@ +/* + * Copyright (C) 2016 ARM Ltd. + * based on the Allwinner H3 dtsi: + * Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include <dt-bindings/clock/sun50i-a64-ccu.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/pinctrl/sun4i-a10.h> +#include <dt-bindings/reset/sun50i-a64-ccu.h> + +/ { + interrupt-parent = <&gic>; + #address-cells = <1>; + #size-cells = <1>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu at 0 { + compatible = "arm,cortex-a53", "arm,armv8"; + device_type = "cpu"; + reg = <0>; + enable-method = "psci"; + }; + + cpu at 1 { + compatible = "arm,cortex-a53", "arm,armv8"; + device_type = "cpu"; + reg = <1>; + enable-method = "psci"; + }; + + cpu at 2 { + compatible = "arm,cortex-a53", "arm,armv8"; + device_type = "cpu"; + reg = <2>; + enable-method = "psci"; + }; + + cpu at 3 { + compatible = "arm,cortex-a53", "arm,armv8"; + device_type = "cpu"; + reg = <3>; + enable-method = "psci"; + }; + }; + + osc24M: osc24M_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <24000000>; + clock-output-names = "osc24M"; + }; + + osc32k: osc32k_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <32768>; + clock-output-names = "osc32k"; + }; + + pmu { + compatible = "arm,cortex-a53-pmu", "arm,armv8-pmuv3"; + interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&cpu0>, + <&cpu1>, + <&cpu2>, + <&cpu3>; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 13 + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, + <GIC_PPI 14 + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, + <GIC_PPI 11 + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, + <GIC_PPI 10 + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + ccu: clock at 01c20000 { + compatible = "allwinner,sun50i-a64-ccu"; + reg = <0x01c20000 0x400>; + clocks = <&osc24M>, <&osc32k>; + clock-names = "hosc", "losc"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + pio: pinctrl at 1c20800 { + compatible = "allwinner,sun50i-a64-pinctrl"; + reg = <0x01c20800 0x400>; + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_PIO>; + gpio-controller; + #gpio-cells = <3>; + interrupt-controller; + #interrupt-cells = <2>; + + i2c1_pins: i2c1_pins { + allwinner,pins = "PH2", "PH3"; + allwinner,function = "i2c1"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; + + uart0_pins_a: uart0 at 0 { + allwinner,pins = "PB8", "PB9"; + allwinner,function = "uart0"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; + }; + + uart0: serial at 1c28000 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c28000 0x400>; + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&ccu CLK_BUS_UART0>; + resets = <&ccu RST_BUS_UART0>; + status = "disabled"; + }; + + uart1: serial at 1c28400 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c28400 0x400>; + interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&ccu CLK_BUS_UART1>; + resets = <&ccu RST_BUS_UART1>; + status = "disabled"; + }; + + uart2: serial at 1c28800 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c28800 0x400>; + interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&ccu CLK_BUS_UART2>; + resets = <&ccu RST_BUS_UART2>; + status = "disabled"; + }; + + uart3: serial at 1c28c00 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c28c00 0x400>; + interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&ccu CLK_BUS_UART3>; + resets = <&ccu RST_BUS_UART3>; + status = "disabled"; + }; + + uart4: serial at 1c29000 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c29000 0x400>; + interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&ccu CLK_BUS_UART4>; + resets = <&ccu RST_BUS_UART4>; + status = "disabled"; + }; + + rtc: rtc at 1f00000 { + compatible = "allwinner,sun6i-a31-rtc"; + reg = <0x01f00000 0x54>; + interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; + }; + + i2c0: i2c at 1c2ac00 { + compatible = "allwinner,sun6i-a31-i2c"; + reg = <0x01c2ac00 0x400>; + interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_I2C0>; + resets = <&ccu RST_BUS_I2C0>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c1: i2c at 1c2b000 { + compatible = "allwinner,sun6i-a31-i2c"; + reg = <0x01c2b000 0x400>; + interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_I2C1>; + resets = <&ccu RST_BUS_I2C1>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c2: i2c at 1c2b400 { + compatible = "allwinner,sun6i-a31-i2c"; + reg = <0x01c2b400 0x400>; + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_I2C2>; + resets = <&ccu RST_BUS_I2C2>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + gic: interrupt-controller at 1c81000 { + compatible = "arm,gic-400"; + reg = <0x01c81000 0x1000>, + <0x01c82000 0x2000>, + <0x01c84000 0x2000>, + <0x01c86000 0x2000>; + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; + interrupt-controller; + #interrupt-cells = <3>; + }; + }; +}; -- 2.9.3 ^ permalink raw reply related [flat|nested] 35+ messages in thread
* Re: [PATCH v2 3/4] arm64: dts: add Allwinner A64 SoC .dtsi 2016-09-09 20:10 ` Maxime Ripard (?) @ 2016-09-10 2:21 ` Chen-Yu Tsai -1 siblings, 0 replies; 35+ messages in thread From: Chen-Yu Tsai @ 2016-09-10 2:21 UTC (permalink / raw) To: Maxime Ripard Cc: Mike Turquette, Stephen Boyd, Chen-Yu Tsai, linux-arm-kernel, Andre Przywara, linux-clk, linux-kernel, linux-sunxi On Sat, Sep 10, 2016 at 4:10 AM, Maxime Ripard <maxime.ripard@free-electrons.com> wrote: > From: Andre Przywara <andre.przywara@arm.com> > > The Allwinner A64 SoC is a low-cost chip with 4 ARM Cortex-A53 cores > and the typical tablet / TV box peripherals. > The SoC is based on the (32-bit) Allwinner H3 chip, sharing most of > the peripherals and the memory map. > Although the cores are proper 64-bit ones, the whole SoC is actually > limited to 4GB (including all the supported DRAM), so we use 32-bit > address and size cells. This has the nice feature of us being able to > reuse the DT for 32-bit kernels as well. > This .dtsi lists the hardware that we support so far. > > Signed-off-by: Andre Przywara <andre.przywara@arm.com> > Acked-by: Rob Herring <robh@kernel.org> > [Maxime: Convert to CCU binding, drop the MMC support for now] > Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> > --- > Documentation/devicetree/bindings/arm/sunxi.txt | 1 + > MAINTAINERS | 1 + > arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 279 ++++++++++++++++++++++++ > 3 files changed, 281 insertions(+) > create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi > > diff --git a/Documentation/devicetree/bindings/arm/sunxi.txt b/Documentation/devicetree/bindings/arm/sunxi.txt > index 7e79fcc36b0d..7e59d8ba86af 100644 > --- a/Documentation/devicetree/bindings/arm/sunxi.txt > +++ b/Documentation/devicetree/bindings/arm/sunxi.txt > @@ -14,3 +14,4 @@ using one of the following compatible strings: > allwinner,sun8i-a83t > allwinner,sun8i-h3 > allwinner,sun9i-a80 > + allwinner,sun50i-a64 > diff --git a/MAINTAINERS b/MAINTAINERS > index 20bb1d00098c..c8c0c85c113f 100644 > --- a/MAINTAINERS > +++ b/MAINTAINERS > @@ -982,6 +982,7 @@ M: Chen-Yu Tsai <wens@csie.org> > L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) > S: Maintained > N: sun[x456789]i > +F: arch/arm64/boot/dts/allwinner/ > > ARM/Allwinner SoC Clock Support > M: Emilio López <emilio@elopez.com.ar> > diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi > new file mode 100644 > index 000000000000..028cdbee20aa > --- /dev/null > +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi > @@ -0,0 +1,279 @@ > +/* > + * Copyright (C) 2016 ARM Ltd. > + * based on the Allwinner H3 dtsi: > + * Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com> > + * > + * This file is dual-licensed: you can use it either under the terms > + * of the GPL or the X11 license, at your option. Note that this dual > + * licensing only applies to this file, and not this project as a > + * whole. > + * > + * a) This file is free software; you can redistribute it and/or > + * modify it under the terms of the GNU General Public License as > + * published by the Free Software Foundation; either version 2 of the > + * License, or (at your option) any later version. > + * > + * This file is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * Or, alternatively, > + * > + * b) Permission is hereby granted, free of charge, to any person > + * obtaining a copy of this software and associated documentation > + * files (the "Software"), to deal in the Software without > + * restriction, including without limitation the rights to use, > + * copy, modify, merge, publish, distribute, sublicense, and/or > + * sell copies of the Software, and to permit persons to whom the > + * Software is furnished to do so, subject to the following > + * conditions: > + * > + * The above copyright notice and this permission notice shall be > + * included in all copies or substantial portions of the Software. > + * > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, > + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES > + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND > + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT > + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, > + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING > + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR > + * OTHER DEALINGS IN THE SOFTWARE. > + */ > + > +#include <dt-bindings/clock/sun50i-a64-ccu.h> > +#include <dt-bindings/interrupt-controller/arm-gic.h> > +#include <dt-bindings/pinctrl/sun4i-a10.h> > +#include <dt-bindings/reset/sun50i-a64-ccu.h> > + > +/ { > + interrupt-parent = <&gic>; > + #address-cells = <1>; > + #size-cells = <1>; > + > + cpus { > + #address-cells = <1>; > + #size-cells = <0>; > + > + cpu@0 { > + compatible = "arm,cortex-a53", "arm,armv8"; > + device_type = "cpu"; > + reg = <0>; > + enable-method = "psci"; > + }; > + > + cpu@1 { > + compatible = "arm,cortex-a53", "arm,armv8"; > + device_type = "cpu"; > + reg = <1>; > + enable-method = "psci"; > + }; > + > + cpu@2 { > + compatible = "arm,cortex-a53", "arm,armv8"; > + device_type = "cpu"; > + reg = <2>; > + enable-method = "psci"; > + }; > + > + cpu@3 { > + compatible = "arm,cortex-a53", "arm,armv8"; > + device_type = "cpu"; > + reg = <3>; > + enable-method = "psci"; > + }; > + }; > + > + osc24M: osc24M_clk { > + #clock-cells = <0>; > + compatible = "fixed-clock"; > + clock-frequency = <24000000>; > + clock-output-names = "osc24M"; > + }; > + > + osc32k: osc32k_clk { > + #clock-cells = <0>; > + compatible = "fixed-clock"; > + clock-frequency = <32768>; > + clock-output-names = "osc32k"; > + }; > + > + pmu { > + compatible = "arm,cortex-a53-pmu", "arm,armv8-pmuv3"; > + interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-affinity = <&cpu0>, > + <&cpu1>, > + <&cpu2>, > + <&cpu3>; > + }; > + > + psci { > + compatible = "arm,psci-0.2"; > + method = "smc"; > + }; > + > + timer { > + compatible = "arm,armv8-timer"; > + interrupts = <GIC_PPI 13 > + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, > + <GIC_PPI 14 > + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, > + <GIC_PPI 11 > + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, > + <GIC_PPI 10 > + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; > + }; > + > + soc { > + compatible = "simple-bus"; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges; > + > + ccu: clock@01c20000 { > + compatible = "allwinner,sun50i-a64-ccu"; > + reg = <0x01c20000 0x400>; > + clocks = <&osc24M>, <&osc32k>; > + clock-names = "hosc", "losc"; > + #clock-cells = <1>; > + #reset-cells = <1>; > + }; > + > + pio: pinctrl@1c20800 { > + compatible = "allwinner,sun50i-a64-pinctrl"; > + reg = <0x01c20800 0x400>; > + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&ccu CLK_BUS_PIO>; > + gpio-controller; > + #gpio-cells = <3>; > + interrupt-controller; > + #interrupt-cells = <2>; > + > + i2c1_pins: i2c1_pins { > + allwinner,pins = "PH2", "PH3"; > + allwinner,function = "i2c1"; > + allwinner,drive = <SUN4I_PINCTRL_10_MA>; > + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; Since we figured out these properties are optional, I suggest we just drop them. Otherwise Acked-by: Chen-Yu Tsai <wens@csie.org> > + }; > + > + uart0_pins_a: uart0@0 { > + allwinner,pins = "PB8", "PB9"; > + allwinner,function = "uart0"; > + allwinner,drive = <SUN4I_PINCTRL_10_MA>; > + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; > + }; > + }; > + > + uart0: serial@1c28000 { > + compatible = "snps,dw-apb-uart"; > + reg = <0x01c28000 0x400>; > + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; > + reg-shift = <2>; > + reg-io-width = <4>; > + clocks = <&ccu CLK_BUS_UART0>; > + resets = <&ccu RST_BUS_UART0>; > + status = "disabled"; > + }; > + > + uart1: serial@1c28400 { > + compatible = "snps,dw-apb-uart"; > + reg = <0x01c28400 0x400>; > + interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; > + reg-shift = <2>; > + reg-io-width = <4>; > + clocks = <&ccu CLK_BUS_UART1>; > + resets = <&ccu RST_BUS_UART1>; > + status = "disabled"; > + }; > + > + uart2: serial@1c28800 { > + compatible = "snps,dw-apb-uart"; > + reg = <0x01c28800 0x400>; > + interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; > + reg-shift = <2>; > + reg-io-width = <4>; > + clocks = <&ccu CLK_BUS_UART2>; > + resets = <&ccu RST_BUS_UART2>; > + status = "disabled"; > + }; > + > + uart3: serial@1c28c00 { > + compatible = "snps,dw-apb-uart"; > + reg = <0x01c28c00 0x400>; > + interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; > + reg-shift = <2>; > + reg-io-width = <4>; > + clocks = <&ccu CLK_BUS_UART3>; > + resets = <&ccu RST_BUS_UART3>; > + status = "disabled"; > + }; > + > + uart4: serial@1c29000 { > + compatible = "snps,dw-apb-uart"; > + reg = <0x01c29000 0x400>; > + interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; > + reg-shift = <2>; > + reg-io-width = <4>; > + clocks = <&ccu CLK_BUS_UART4>; > + resets = <&ccu RST_BUS_UART4>; > + status = "disabled"; > + }; > + > + rtc: rtc@1f00000 { > + compatible = "allwinner,sun6i-a31-rtc"; > + reg = <0x01f00000 0x54>; > + interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; > + }; > + > + i2c0: i2c@1c2ac00 { > + compatible = "allwinner,sun6i-a31-i2c"; > + reg = <0x01c2ac00 0x400>; > + interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&ccu CLK_BUS_I2C0>; > + resets = <&ccu RST_BUS_I2C0>; > + status = "disabled"; > + #address-cells = <1>; > + #size-cells = <0>; > + }; > + > + i2c1: i2c@1c2b000 { > + compatible = "allwinner,sun6i-a31-i2c"; > + reg = <0x01c2b000 0x400>; > + interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&ccu CLK_BUS_I2C1>; > + resets = <&ccu RST_BUS_I2C1>; > + status = "disabled"; > + #address-cells = <1>; > + #size-cells = <0>; > + }; > + > + i2c2: i2c@1c2b400 { > + compatible = "allwinner,sun6i-a31-i2c"; > + reg = <0x01c2b400 0x400>; > + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&ccu CLK_BUS_I2C2>; > + resets = <&ccu RST_BUS_I2C2>; > + status = "disabled"; > + #address-cells = <1>; > + #size-cells = <0>; > + }; > + > + gic: interrupt-controller@1c81000 { > + compatible = "arm,gic-400"; > + reg = <0x01c81000 0x1000>, > + <0x01c82000 0x2000>, > + <0x01c84000 0x2000>, > + <0x01c86000 0x2000>; > + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; > + interrupt-controller; > + #interrupt-cells = <3>; > + }; > + }; > +}; > -- > 2.9.3 > ^ permalink raw reply [flat|nested] 35+ messages in thread
* [PATCH v2 3/4] arm64: dts: add Allwinner A64 SoC .dtsi @ 2016-09-10 2:21 ` Chen-Yu Tsai 0 siblings, 0 replies; 35+ messages in thread From: Chen-Yu Tsai @ 2016-09-10 2:21 UTC (permalink / raw) To: linux-arm-kernel On Sat, Sep 10, 2016 at 4:10 AM, Maxime Ripard <maxime.ripard@free-electrons.com> wrote: > From: Andre Przywara <andre.przywara@arm.com> > > The Allwinner A64 SoC is a low-cost chip with 4 ARM Cortex-A53 cores > and the typical tablet / TV box peripherals. > The SoC is based on the (32-bit) Allwinner H3 chip, sharing most of > the peripherals and the memory map. > Although the cores are proper 64-bit ones, the whole SoC is actually > limited to 4GB (including all the supported DRAM), so we use 32-bit > address and size cells. This has the nice feature of us being able to > reuse the DT for 32-bit kernels as well. > This .dtsi lists the hardware that we support so far. > > Signed-off-by: Andre Przywara <andre.przywara@arm.com> > Acked-by: Rob Herring <robh@kernel.org> > [Maxime: Convert to CCU binding, drop the MMC support for now] > Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> > --- > Documentation/devicetree/bindings/arm/sunxi.txt | 1 + > MAINTAINERS | 1 + > arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 279 ++++++++++++++++++++++++ > 3 files changed, 281 insertions(+) > create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi > > diff --git a/Documentation/devicetree/bindings/arm/sunxi.txt b/Documentation/devicetree/bindings/arm/sunxi.txt > index 7e79fcc36b0d..7e59d8ba86af 100644 > --- a/Documentation/devicetree/bindings/arm/sunxi.txt > +++ b/Documentation/devicetree/bindings/arm/sunxi.txt > @@ -14,3 +14,4 @@ using one of the following compatible strings: > allwinner,sun8i-a83t > allwinner,sun8i-h3 > allwinner,sun9i-a80 > + allwinner,sun50i-a64 > diff --git a/MAINTAINERS b/MAINTAINERS > index 20bb1d00098c..c8c0c85c113f 100644 > --- a/MAINTAINERS > +++ b/MAINTAINERS > @@ -982,6 +982,7 @@ M: Chen-Yu Tsai <wens@csie.org> > L: linux-arm-kernel at lists.infradead.org (moderated for non-subscribers) > S: Maintained > N: sun[x456789]i > +F: arch/arm64/boot/dts/allwinner/ > > ARM/Allwinner SoC Clock Support > M: Emilio L?pez <emilio@elopez.com.ar> > diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi > new file mode 100644 > index 000000000000..028cdbee20aa > --- /dev/null > +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi > @@ -0,0 +1,279 @@ > +/* > + * Copyright (C) 2016 ARM Ltd. > + * based on the Allwinner H3 dtsi: > + * Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com> > + * > + * This file is dual-licensed: you can use it either under the terms > + * of the GPL or the X11 license, at your option. Note that this dual > + * licensing only applies to this file, and not this project as a > + * whole. > + * > + * a) This file is free software; you can redistribute it and/or > + * modify it under the terms of the GNU General Public License as > + * published by the Free Software Foundation; either version 2 of the > + * License, or (at your option) any later version. > + * > + * This file is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * Or, alternatively, > + * > + * b) Permission is hereby granted, free of charge, to any person > + * obtaining a copy of this software and associated documentation > + * files (the "Software"), to deal in the Software without > + * restriction, including without limitation the rights to use, > + * copy, modify, merge, publish, distribute, sublicense, and/or > + * sell copies of the Software, and to permit persons to whom the > + * Software is furnished to do so, subject to the following > + * conditions: > + * > + * The above copyright notice and this permission notice shall be > + * included in all copies or substantial portions of the Software. > + * > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, > + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES > + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND > + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT > + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, > + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING > + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR > + * OTHER DEALINGS IN THE SOFTWARE. > + */ > + > +#include <dt-bindings/clock/sun50i-a64-ccu.h> > +#include <dt-bindings/interrupt-controller/arm-gic.h> > +#include <dt-bindings/pinctrl/sun4i-a10.h> > +#include <dt-bindings/reset/sun50i-a64-ccu.h> > + > +/ { > + interrupt-parent = <&gic>; > + #address-cells = <1>; > + #size-cells = <1>; > + > + cpus { > + #address-cells = <1>; > + #size-cells = <0>; > + > + cpu at 0 { > + compatible = "arm,cortex-a53", "arm,armv8"; > + device_type = "cpu"; > + reg = <0>; > + enable-method = "psci"; > + }; > + > + cpu at 1 { > + compatible = "arm,cortex-a53", "arm,armv8"; > + device_type = "cpu"; > + reg = <1>; > + enable-method = "psci"; > + }; > + > + cpu at 2 { > + compatible = "arm,cortex-a53", "arm,armv8"; > + device_type = "cpu"; > + reg = <2>; > + enable-method = "psci"; > + }; > + > + cpu at 3 { > + compatible = "arm,cortex-a53", "arm,armv8"; > + device_type = "cpu"; > + reg = <3>; > + enable-method = "psci"; > + }; > + }; > + > + osc24M: osc24M_clk { > + #clock-cells = <0>; > + compatible = "fixed-clock"; > + clock-frequency = <24000000>; > + clock-output-names = "osc24M"; > + }; > + > + osc32k: osc32k_clk { > + #clock-cells = <0>; > + compatible = "fixed-clock"; > + clock-frequency = <32768>; > + clock-output-names = "osc32k"; > + }; > + > + pmu { > + compatible = "arm,cortex-a53-pmu", "arm,armv8-pmuv3"; > + interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-affinity = <&cpu0>, > + <&cpu1>, > + <&cpu2>, > + <&cpu3>; > + }; > + > + psci { > + compatible = "arm,psci-0.2"; > + method = "smc"; > + }; > + > + timer { > + compatible = "arm,armv8-timer"; > + interrupts = <GIC_PPI 13 > + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, > + <GIC_PPI 14 > + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, > + <GIC_PPI 11 > + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, > + <GIC_PPI 10 > + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; > + }; > + > + soc { > + compatible = "simple-bus"; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges; > + > + ccu: clock at 01c20000 { > + compatible = "allwinner,sun50i-a64-ccu"; > + reg = <0x01c20000 0x400>; > + clocks = <&osc24M>, <&osc32k>; > + clock-names = "hosc", "losc"; > + #clock-cells = <1>; > + #reset-cells = <1>; > + }; > + > + pio: pinctrl at 1c20800 { > + compatible = "allwinner,sun50i-a64-pinctrl"; > + reg = <0x01c20800 0x400>; > + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&ccu CLK_BUS_PIO>; > + gpio-controller; > + #gpio-cells = <3>; > + interrupt-controller; > + #interrupt-cells = <2>; > + > + i2c1_pins: i2c1_pins { > + allwinner,pins = "PH2", "PH3"; > + allwinner,function = "i2c1"; > + allwinner,drive = <SUN4I_PINCTRL_10_MA>; > + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; Since we figured out these properties are optional, I suggest we just drop them. Otherwise Acked-by: Chen-Yu Tsai <wens@csie.org> > + }; > + > + uart0_pins_a: uart0 at 0 { > + allwinner,pins = "PB8", "PB9"; > + allwinner,function = "uart0"; > + allwinner,drive = <SUN4I_PINCTRL_10_MA>; > + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; > + }; > + }; > + > + uart0: serial at 1c28000 { > + compatible = "snps,dw-apb-uart"; > + reg = <0x01c28000 0x400>; > + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; > + reg-shift = <2>; > + reg-io-width = <4>; > + clocks = <&ccu CLK_BUS_UART0>; > + resets = <&ccu RST_BUS_UART0>; > + status = "disabled"; > + }; > + > + uart1: serial at 1c28400 { > + compatible = "snps,dw-apb-uart"; > + reg = <0x01c28400 0x400>; > + interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; > + reg-shift = <2>; > + reg-io-width = <4>; > + clocks = <&ccu CLK_BUS_UART1>; > + resets = <&ccu RST_BUS_UART1>; > + status = "disabled"; > + }; > + > + uart2: serial at 1c28800 { > + compatible = "snps,dw-apb-uart"; > + reg = <0x01c28800 0x400>; > + interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; > + reg-shift = <2>; > + reg-io-width = <4>; > + clocks = <&ccu CLK_BUS_UART2>; > + resets = <&ccu RST_BUS_UART2>; > + status = "disabled"; > + }; > + > + uart3: serial at 1c28c00 { > + compatible = "snps,dw-apb-uart"; > + reg = <0x01c28c00 0x400>; > + interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; > + reg-shift = <2>; > + reg-io-width = <4>; > + clocks = <&ccu CLK_BUS_UART3>; > + resets = <&ccu RST_BUS_UART3>; > + status = "disabled"; > + }; > + > + uart4: serial at 1c29000 { > + compatible = "snps,dw-apb-uart"; > + reg = <0x01c29000 0x400>; > + interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; > + reg-shift = <2>; > + reg-io-width = <4>; > + clocks = <&ccu CLK_BUS_UART4>; > + resets = <&ccu RST_BUS_UART4>; > + status = "disabled"; > + }; > + > + rtc: rtc at 1f00000 { > + compatible = "allwinner,sun6i-a31-rtc"; > + reg = <0x01f00000 0x54>; > + interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; > + }; > + > + i2c0: i2c at 1c2ac00 { > + compatible = "allwinner,sun6i-a31-i2c"; > + reg = <0x01c2ac00 0x400>; > + interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&ccu CLK_BUS_I2C0>; > + resets = <&ccu RST_BUS_I2C0>; > + status = "disabled"; > + #address-cells = <1>; > + #size-cells = <0>; > + }; > + > + i2c1: i2c at 1c2b000 { > + compatible = "allwinner,sun6i-a31-i2c"; > + reg = <0x01c2b000 0x400>; > + interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&ccu CLK_BUS_I2C1>; > + resets = <&ccu RST_BUS_I2C1>; > + status = "disabled"; > + #address-cells = <1>; > + #size-cells = <0>; > + }; > + > + i2c2: i2c at 1c2b400 { > + compatible = "allwinner,sun6i-a31-i2c"; > + reg = <0x01c2b400 0x400>; > + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&ccu CLK_BUS_I2C2>; > + resets = <&ccu RST_BUS_I2C2>; > + status = "disabled"; > + #address-cells = <1>; > + #size-cells = <0>; > + }; > + > + gic: interrupt-controller at 1c81000 { > + compatible = "arm,gic-400"; > + reg = <0x01c81000 0x1000>, > + <0x01c82000 0x2000>, > + <0x01c84000 0x2000>, > + <0x01c86000 0x2000>; > + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; > + interrupt-controller; > + #interrupt-cells = <3>; > + }; > + }; > +}; > -- > 2.9.3 > ^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [PATCH v2 3/4] arm64: dts: add Allwinner A64 SoC .dtsi @ 2016-09-10 2:21 ` Chen-Yu Tsai 0 siblings, 0 replies; 35+ messages in thread From: Chen-Yu Tsai @ 2016-09-10 2:21 UTC (permalink / raw) To: Maxime Ripard Cc: Mike Turquette, Stephen Boyd, Chen-Yu Tsai, linux-arm-kernel, Andre Przywara, linux-clk, linux-kernel, linux-sunxi On Sat, Sep 10, 2016 at 4:10 AM, Maxime Ripard <maxime.ripard@free-electrons.com> wrote: > From: Andre Przywara <andre.przywara@arm.com> > > The Allwinner A64 SoC is a low-cost chip with 4 ARM Cortex-A53 cores > and the typical tablet / TV box peripherals. > The SoC is based on the (32-bit) Allwinner H3 chip, sharing most of > the peripherals and the memory map. > Although the cores are proper 64-bit ones, the whole SoC is actually > limited to 4GB (including all the supported DRAM), so we use 32-bit > address and size cells. This has the nice feature of us being able to > reuse the DT for 32-bit kernels as well. > This .dtsi lists the hardware that we support so far. > > Signed-off-by: Andre Przywara <andre.przywara@arm.com> > Acked-by: Rob Herring <robh@kernel.org> > [Maxime: Convert to CCU binding, drop the MMC support for now] > Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> > --- > Documentation/devicetree/bindings/arm/sunxi.txt | 1 + > MAINTAINERS | 1 + > arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 279 ++++++++++++++++++= ++++++ > 3 files changed, 281 insertions(+) > create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi > > diff --git a/Documentation/devicetree/bindings/arm/sunxi.txt b/Documentat= ion/devicetree/bindings/arm/sunxi.txt > index 7e79fcc36b0d..7e59d8ba86af 100644 > --- a/Documentation/devicetree/bindings/arm/sunxi.txt > +++ b/Documentation/devicetree/bindings/arm/sunxi.txt > @@ -14,3 +14,4 @@ using one of the following compatible strings: > allwinner,sun8i-a83t > allwinner,sun8i-h3 > allwinner,sun9i-a80 > + allwinner,sun50i-a64 > diff --git a/MAINTAINERS b/MAINTAINERS > index 20bb1d00098c..c8c0c85c113f 100644 > --- a/MAINTAINERS > +++ b/MAINTAINERS > @@ -982,6 +982,7 @@ M: Chen-Yu Tsai <wens@csie.org> > L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribe= rs) > S: Maintained > N: sun[x456789]i > +F: arch/arm64/boot/dts/allwinner/ > > ARM/Allwinner SoC Clock Support > M: Emilio L=C3=B3pez <emilio@elopez.com.ar> > diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/b= oot/dts/allwinner/sun50i-a64.dtsi > new file mode 100644 > index 000000000000..028cdbee20aa > --- /dev/null > +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi > @@ -0,0 +1,279 @@ > +/* > + * Copyright (C) 2016 ARM Ltd. > + * based on the Allwinner H3 dtsi: > + * Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com> > + * > + * This file is dual-licensed: you can use it either under the terms > + * of the GPL or the X11 license, at your option. Note that this dual > + * licensing only applies to this file, and not this project as a > + * whole. > + * > + * a) This file is free software; you can redistribute it and/or > + * modify it under the terms of the GNU General Public License as > + * published by the Free Software Foundation; either version 2 of th= e > + * License, or (at your option) any later version. > + * > + * This file is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * Or, alternatively, > + * > + * b) Permission is hereby granted, free of charge, to any person > + * obtaining a copy of this software and associated documentation > + * files (the "Software"), to deal in the Software without > + * restriction, including without limitation the rights to use, > + * copy, modify, merge, publish, distribute, sublicense, and/or > + * sell copies of the Software, and to permit persons to whom the > + * Software is furnished to do so, subject to the following > + * conditions: > + * > + * The above copyright notice and this permission notice shall be > + * included in all copies or substantial portions of the Software. > + * > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, > + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES > + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND > + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT > + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, > + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING > + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR > + * OTHER DEALINGS IN THE SOFTWARE. > + */ > + > +#include <dt-bindings/clock/sun50i-a64-ccu.h> > +#include <dt-bindings/interrupt-controller/arm-gic.h> > +#include <dt-bindings/pinctrl/sun4i-a10.h> > +#include <dt-bindings/reset/sun50i-a64-ccu.h> > + > +/ { > + interrupt-parent =3D <&gic>; > + #address-cells =3D <1>; > + #size-cells =3D <1>; > + > + cpus { > + #address-cells =3D <1>; > + #size-cells =3D <0>; > + > + cpu@0 { > + compatible =3D "arm,cortex-a53", "arm,armv8"; > + device_type =3D "cpu"; > + reg =3D <0>; > + enable-method =3D "psci"; > + }; > + > + cpu@1 { > + compatible =3D "arm,cortex-a53", "arm,armv8"; > + device_type =3D "cpu"; > + reg =3D <1>; > + enable-method =3D "psci"; > + }; > + > + cpu@2 { > + compatible =3D "arm,cortex-a53", "arm,armv8"; > + device_type =3D "cpu"; > + reg =3D <2>; > + enable-method =3D "psci"; > + }; > + > + cpu@3 { > + compatible =3D "arm,cortex-a53", "arm,armv8"; > + device_type =3D "cpu"; > + reg =3D <3>; > + enable-method =3D "psci"; > + }; > + }; > + > + osc24M: osc24M_clk { > + #clock-cells =3D <0>; > + compatible =3D "fixed-clock"; > + clock-frequency =3D <24000000>; > + clock-output-names =3D "osc24M"; > + }; > + > + osc32k: osc32k_clk { > + #clock-cells =3D <0>; > + compatible =3D "fixed-clock"; > + clock-frequency =3D <32768>; > + clock-output-names =3D "osc32k"; > + }; > + > + pmu { > + compatible =3D "arm,cortex-a53-pmu", "arm,armv8-pmuv3"; > + interrupts =3D <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-affinity =3D <&cpu0>, > + <&cpu1>, > + <&cpu2>, > + <&cpu3>; > + }; > + > + psci { > + compatible =3D "arm,psci-0.2"; > + method =3D "smc"; > + }; > + > + timer { > + compatible =3D "arm,armv8-timer"; > + interrupts =3D <GIC_PPI 13 > + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, > + <GIC_PPI 14 > + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, > + <GIC_PPI 11 > + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, > + <GIC_PPI 10 > + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; > + }; > + > + soc { > + compatible =3D "simple-bus"; > + #address-cells =3D <1>; > + #size-cells =3D <1>; > + ranges; > + > + ccu: clock@01c20000 { > + compatible =3D "allwinner,sun50i-a64-ccu"; > + reg =3D <0x01c20000 0x400>; > + clocks =3D <&osc24M>, <&osc32k>; > + clock-names =3D "hosc", "losc"; > + #clock-cells =3D <1>; > + #reset-cells =3D <1>; > + }; > + > + pio: pinctrl@1c20800 { > + compatible =3D "allwinner,sun50i-a64-pinctrl"; > + reg =3D <0x01c20800 0x400>; > + interrupts =3D <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; > + clocks =3D <&ccu CLK_BUS_PIO>; > + gpio-controller; > + #gpio-cells =3D <3>; > + interrupt-controller; > + #interrupt-cells =3D <2>; > + > + i2c1_pins: i2c1_pins { > + allwinner,pins =3D "PH2", "PH3"; > + allwinner,function =3D "i2c1"; > + allwinner,drive =3D <SUN4I_PINCTRL_10_MA>= ; > + allwinner,pull =3D <SUN4I_PINCTRL_NO_PULL= >; Since we figured out these properties are optional, I suggest we just drop = them. Otherwise Acked-by: Chen-Yu Tsai <wens@csie.org> > + }; > + > + uart0_pins_a: uart0@0 { > + allwinner,pins =3D "PB8", "PB9"; > + allwinner,function =3D "uart0"; > + allwinner,drive =3D <SUN4I_PINCTRL_10_MA>= ; > + allwinner,pull =3D <SUN4I_PINCTRL_NO_PULL= >; > + }; > + }; > + > + uart0: serial@1c28000 { > + compatible =3D "snps,dw-apb-uart"; > + reg =3D <0x01c28000 0x400>; > + interrupts =3D <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; > + reg-shift =3D <2>; > + reg-io-width =3D <4>; > + clocks =3D <&ccu CLK_BUS_UART0>; > + resets =3D <&ccu RST_BUS_UART0>; > + status =3D "disabled"; > + }; > + > + uart1: serial@1c28400 { > + compatible =3D "snps,dw-apb-uart"; > + reg =3D <0x01c28400 0x400>; > + interrupts =3D <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; > + reg-shift =3D <2>; > + reg-io-width =3D <4>; > + clocks =3D <&ccu CLK_BUS_UART1>; > + resets =3D <&ccu RST_BUS_UART1>; > + status =3D "disabled"; > + }; > + > + uart2: serial@1c28800 { > + compatible =3D "snps,dw-apb-uart"; > + reg =3D <0x01c28800 0x400>; > + interrupts =3D <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; > + reg-shift =3D <2>; > + reg-io-width =3D <4>; > + clocks =3D <&ccu CLK_BUS_UART2>; > + resets =3D <&ccu RST_BUS_UART2>; > + status =3D "disabled"; > + }; > + > + uart3: serial@1c28c00 { > + compatible =3D "snps,dw-apb-uart"; > + reg =3D <0x01c28c00 0x400>; > + interrupts =3D <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; > + reg-shift =3D <2>; > + reg-io-width =3D <4>; > + clocks =3D <&ccu CLK_BUS_UART3>; > + resets =3D <&ccu RST_BUS_UART3>; > + status =3D "disabled"; > + }; > + > + uart4: serial@1c29000 { > + compatible =3D "snps,dw-apb-uart"; > + reg =3D <0x01c29000 0x400>; > + interrupts =3D <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; > + reg-shift =3D <2>; > + reg-io-width =3D <4>; > + clocks =3D <&ccu CLK_BUS_UART4>; > + resets =3D <&ccu RST_BUS_UART4>; > + status =3D "disabled"; > + }; > + > + rtc: rtc@1f00000 { > + compatible =3D "allwinner,sun6i-a31-rtc"; > + reg =3D <0x01f00000 0x54>; > + interrupts =3D <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; > + }; > + > + i2c0: i2c@1c2ac00 { > + compatible =3D "allwinner,sun6i-a31-i2c"; > + reg =3D <0x01c2ac00 0x400>; > + interrupts =3D <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; > + clocks =3D <&ccu CLK_BUS_I2C0>; > + resets =3D <&ccu RST_BUS_I2C0>; > + status =3D "disabled"; > + #address-cells =3D <1>; > + #size-cells =3D <0>; > + }; > + > + i2c1: i2c@1c2b000 { > + compatible =3D "allwinner,sun6i-a31-i2c"; > + reg =3D <0x01c2b000 0x400>; > + interrupts =3D <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; > + clocks =3D <&ccu CLK_BUS_I2C1>; > + resets =3D <&ccu RST_BUS_I2C1>; > + status =3D "disabled"; > + #address-cells =3D <1>; > + #size-cells =3D <0>; > + }; > + > + i2c2: i2c@1c2b400 { > + compatible =3D "allwinner,sun6i-a31-i2c"; > + reg =3D <0x01c2b400 0x400>; > + interrupts =3D <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; > + clocks =3D <&ccu CLK_BUS_I2C2>; > + resets =3D <&ccu RST_BUS_I2C2>; > + status =3D "disabled"; > + #address-cells =3D <1>; > + #size-cells =3D <0>; > + }; > + > + gic: interrupt-controller@1c81000 { > + compatible =3D "arm,gic-400"; > + reg =3D <0x01c81000 0x1000>, > + <0x01c82000 0x2000>, > + <0x01c84000 0x2000>, > + <0x01c86000 0x2000>; > + interrupts =3D <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4)= | IRQ_TYPE_LEVEL_HIGH)>; > + interrupt-controller; > + #interrupt-cells =3D <3>; > + }; > + }; > +}; > -- > 2.9.3 > ^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [PATCH v2 3/4] arm64: dts: add Allwinner A64 SoC .dtsi 2016-09-09 20:10 ` Maxime Ripard @ 2016-09-15 0:08 ` André Przywara -1 siblings, 0 replies; 35+ messages in thread From: André Przywara @ 2016-09-15 0:08 UTC (permalink / raw) To: Maxime Ripard, Mike Turquette, Stephen Boyd, Chen-Yu Tsai Cc: linux-arm-kernel, linux-clk, linux-kernel, linux-sunxi On 09/09/16 21:10, Maxime Ripard wrote: Hi Maxime, > From: Andre Przywara <andre.przywara@arm.com> > > The Allwinner A64 SoC is a low-cost chip with 4 ARM Cortex-A53 cores > and the typical tablet / TV box peripherals. > The SoC is based on the (32-bit) Allwinner H3 chip, sharing most of > the peripherals and the memory map. > Although the cores are proper 64-bit ones, the whole SoC is actually > limited to 4GB (including all the supported DRAM), so we use 32-bit > address and size cells. This has the nice feature of us being able to > reuse the DT for 32-bit kernels as well. > This .dtsi lists the hardware that we support so far. > > Signed-off-by: Andre Przywara <andre.przywara@arm.com> > Acked-by: Rob Herring <robh@kernel.org> > [Maxime: Convert to CCU binding, drop the MMC support for now] > Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> > --- > Documentation/devicetree/bindings/arm/sunxi.txt | 1 + > MAINTAINERS | 1 + > arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 279 ++++++++++++++++++++++++ > 3 files changed, 281 insertions(+) > create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi > > diff --git a/Documentation/devicetree/bindings/arm/sunxi.txt b/Documentation/devicetree/bindings/arm/sunxi.txt > index 7e79fcc36b0d..7e59d8ba86af 100644 > --- a/Documentation/devicetree/bindings/arm/sunxi.txt > +++ b/Documentation/devicetree/bindings/arm/sunxi.txt > @@ -14,3 +14,4 @@ using one of the following compatible strings: > allwinner,sun8i-a83t > allwinner,sun8i-h3 > allwinner,sun9i-a80 > + allwinner,sun50i-a64 > diff --git a/MAINTAINERS b/MAINTAINERS > index 20bb1d00098c..c8c0c85c113f 100644 > --- a/MAINTAINERS > +++ b/MAINTAINERS > @@ -982,6 +982,7 @@ M: Chen-Yu Tsai <wens@csie.org> > L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) > S: Maintained > N: sun[x456789]i > +F: arch/arm64/boot/dts/allwinner/ If you promise to not break it needlessly ;-) > > ARM/Allwinner SoC Clock Support > M: Emilio López <emilio@elopez.com.ar> > diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi > new file mode 100644 > index 000000000000..028cdbee20aa > --- /dev/null > +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi > @@ -0,0 +1,279 @@ > +/* > + * Copyright (C) 2016 ARM Ltd. > + * based on the Allwinner H3 dtsi: > + * Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com> > + * > + * This file is dual-licensed: you can use it either under the terms > + * of the GPL or the X11 license, at your option. Note that this dual > + * licensing only applies to this file, and not this project as a > + * whole. > + * > + * a) This file is free software; you can redistribute it and/or > + * modify it under the terms of the GNU General Public License as > + * published by the Free Software Foundation; either version 2 of the > + * License, or (at your option) any later version. > + * > + * This file is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * Or, alternatively, > + * > + * b) Permission is hereby granted, free of charge, to any person > + * obtaining a copy of this software and associated documentation > + * files (the "Software"), to deal in the Software without > + * restriction, including without limitation the rights to use, > + * copy, modify, merge, publish, distribute, sublicense, and/or > + * sell copies of the Software, and to permit persons to whom the > + * Software is furnished to do so, subject to the following > + * conditions: > + * > + * The above copyright notice and this permission notice shall be > + * included in all copies or substantial portions of the Software. > + * > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, > + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES > + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND > + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT > + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, > + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING > + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR > + * OTHER DEALINGS IN THE SOFTWARE. > + */ > + > +#include <dt-bindings/clock/sun50i-a64-ccu.h> > +#include <dt-bindings/interrupt-controller/arm-gic.h> > +#include <dt-bindings/pinctrl/sun4i-a10.h> > +#include <dt-bindings/reset/sun50i-a64-ccu.h> > + > +/ { > + interrupt-parent = <&gic>; > + #address-cells = <1>; > + #size-cells = <1>; > + > + cpus { > + #address-cells = <1>; > + #size-cells = <0>; > + > + cpu@0 { This is probably me to blame here since I put you up to it, but you need "cpux" names (e.g. "cpu0: cpu@0 {") to match the ones that the PMU node references below. dtc will refuse to compile it otherwise. > + compatible = "arm,cortex-a53", "arm,armv8"; > + device_type = "cpu"; > + reg = <0>; > + enable-method = "psci"; > + }; > + > + cpu@1 { > + compatible = "arm,cortex-a53", "arm,armv8"; > + device_type = "cpu"; > + reg = <1>; > + enable-method = "psci"; > + }; > + > + cpu@2 { > + compatible = "arm,cortex-a53", "arm,armv8"; > + device_type = "cpu"; > + reg = <2>; > + enable-method = "psci"; > + }; > + > + cpu@3 { > + compatible = "arm,cortex-a53", "arm,armv8"; > + device_type = "cpu"; > + reg = <3>; > + enable-method = "psci"; > + }; > + }; > + > + osc24M: osc24M_clk { > + #clock-cells = <0>; > + compatible = "fixed-clock"; > + clock-frequency = <24000000>; > + clock-output-names = "osc24M"; > + }; > + > + osc32k: osc32k_clk { > + #clock-cells = <0>; > + compatible = "fixed-clock"; > + clock-frequency = <32768>; > + clock-output-names = "osc32k"; > + }; > + > + pmu { > + compatible = "arm,cortex-a53-pmu", "arm,armv8-pmuv3"; > + interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-affinity = <&cpu0>, > + <&cpu1>, > + <&cpu2>, > + <&cpu3>; > + }; > + > + psci { > + compatible = "arm,psci-0.2"; > + method = "smc"; > + }; > + > + timer { > + compatible = "arm,armv8-timer"; > + interrupts = <GIC_PPI 13 > + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, > + <GIC_PPI 14 > + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, > + <GIC_PPI 11 > + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, > + <GIC_PPI 10 > + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; > + }; > + > + soc { > + compatible = "simple-bus"; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges; > + > + ccu: clock@01c20000 { > + compatible = "allwinner,sun50i-a64-ccu"; > + reg = <0x01c20000 0x400>; > + clocks = <&osc24M>, <&osc32k>; > + clock-names = "hosc", "losc"; > + #clock-cells = <1>; > + #reset-cells = <1>; > + }; > + > + pio: pinctrl@1c20800 { > + compatible = "allwinner,sun50i-a64-pinctrl"; > + reg = <0x01c20800 0x400>; > + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&ccu CLK_BUS_PIO>; > + gpio-controller; > + #gpio-cells = <3>; > + interrupt-controller; > + #interrupt-cells = <2>; > + > + i2c1_pins: i2c1_pins { > + allwinner,pins = "PH2", "PH3"; > + allwinner,function = "i2c1"; > + allwinner,drive = <SUN4I_PINCTRL_10_MA>; > + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; > + }; > + > + uart0_pins_a: uart0@0 { > + allwinner,pins = "PB8", "PB9"; > + allwinner,function = "uart0"; > + allwinner,drive = <SUN4I_PINCTRL_10_MA>; > + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; > + }; So did I get this right that there is a strict "no user - no pins" policy here? I don't see a reason why we shouldn't have at least the other UART pins described here as well - since they are a pure SoC property. That would make it easier for people to enable them (with a simple, scripted fdt one-liner command in U-Boot, for instance). I guess there will never be an official DT with more than 2 UARTs enabled, although we have actually five UARTs on the headers on the Pine64, for instance (and personally I am looking into using one as a terminal server). Also UART1 is connected to that WiFi/Bluetooth slot, having it enabled should make BT work without further ado (but I haven't tested this). Thoughts? > + }; > + > + uart0: serial@1c28000 { > + compatible = "snps,dw-apb-uart"; > + reg = <0x01c28000 0x400>; > + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; > + reg-shift = <2>; > + reg-io-width = <4>; > + clocks = <&ccu CLK_BUS_UART0>; > + resets = <&ccu RST_BUS_UART0>; > + status = "disabled"; > + }; > + > + uart1: serial@1c28400 { > + compatible = "snps,dw-apb-uart"; > + reg = <0x01c28400 0x400>; > + interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; > + reg-shift = <2>; > + reg-io-width = <4>; > + clocks = <&ccu CLK_BUS_UART1>; > + resets = <&ccu RST_BUS_UART1>; > + status = "disabled"; > + }; > + > + uart2: serial@1c28800 { > + compatible = "snps,dw-apb-uart"; > + reg = <0x01c28800 0x400>; > + interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; > + reg-shift = <2>; > + reg-io-width = <4>; > + clocks = <&ccu CLK_BUS_UART2>; > + resets = <&ccu RST_BUS_UART2>; > + status = "disabled"; > + }; > + > + uart3: serial@1c28c00 { > + compatible = "snps,dw-apb-uart"; > + reg = <0x01c28c00 0x400>; > + interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; > + reg-shift = <2>; > + reg-io-width = <4>; > + clocks = <&ccu CLK_BUS_UART3>; > + resets = <&ccu RST_BUS_UART3>; > + status = "disabled"; > + }; > + > + uart4: serial@1c29000 { > + compatible = "snps,dw-apb-uart"; > + reg = <0x01c29000 0x400>; > + interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; > + reg-shift = <2>; > + reg-io-width = <4>; > + clocks = <&ccu CLK_BUS_UART4>; > + resets = <&ccu RST_BUS_UART4>; > + status = "disabled"; > + }; > + > + rtc: rtc@1f00000 { > + compatible = "allwinner,sun6i-a31-rtc"; > + reg = <0x01f00000 0x54>; > + interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; > + }; > + > + i2c0: i2c@1c2ac00 { > + compatible = "allwinner,sun6i-a31-i2c"; > + reg = <0x01c2ac00 0x400>; > + interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&ccu CLK_BUS_I2C0>; > + resets = <&ccu RST_BUS_I2C0>; > + status = "disabled"; > + #address-cells = <1>; > + #size-cells = <0>; > + }; > + > + i2c1: i2c@1c2b000 { > + compatible = "allwinner,sun6i-a31-i2c"; > + reg = <0x01c2b000 0x400>; > + interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&ccu CLK_BUS_I2C1>; > + resets = <&ccu RST_BUS_I2C1>; > + status = "disabled"; > + #address-cells = <1>; > + #size-cells = <0>; > + }; > + > + i2c2: i2c@1c2b400 { > + compatible = "allwinner,sun6i-a31-i2c"; > + reg = <0x01c2b400 0x400>; > + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&ccu CLK_BUS_I2C2>; > + resets = <&ccu RST_BUS_I2C2>; > + status = "disabled"; > + #address-cells = <1>; > + #size-cells = <0>; > + }; > + > + gic: interrupt-controller@1c81000 { > + compatible = "arm,gic-400"; > + reg = <0x01c81000 0x1000>, > + <0x01c82000 0x2000>, > + <0x01c84000 0x2000>, > + <0x01c86000 0x2000>; > + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; > + interrupt-controller; > + #interrupt-cells = <3>; > + }; This is clearly bike-shedding at this point ;-), but I think the GIC should belong up into the core peripherals, not under the "soc" node. > + }; > +}; > Cheers, Andre. ^ permalink raw reply [flat|nested] 35+ messages in thread
* [PATCH v2 3/4] arm64: dts: add Allwinner A64 SoC .dtsi @ 2016-09-15 0:08 ` André Przywara 0 siblings, 0 replies; 35+ messages in thread From: André Przywara @ 2016-09-15 0:08 UTC (permalink / raw) To: linux-arm-kernel On 09/09/16 21:10, Maxime Ripard wrote: Hi Maxime, > From: Andre Przywara <andre.przywara@arm.com> > > The Allwinner A64 SoC is a low-cost chip with 4 ARM Cortex-A53 cores > and the typical tablet / TV box peripherals. > The SoC is based on the (32-bit) Allwinner H3 chip, sharing most of > the peripherals and the memory map. > Although the cores are proper 64-bit ones, the whole SoC is actually > limited to 4GB (including all the supported DRAM), so we use 32-bit > address and size cells. This has the nice feature of us being able to > reuse the DT for 32-bit kernels as well. > This .dtsi lists the hardware that we support so far. > > Signed-off-by: Andre Przywara <andre.przywara@arm.com> > Acked-by: Rob Herring <robh@kernel.org> > [Maxime: Convert to CCU binding, drop the MMC support for now] > Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> > --- > Documentation/devicetree/bindings/arm/sunxi.txt | 1 + > MAINTAINERS | 1 + > arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 279 ++++++++++++++++++++++++ > 3 files changed, 281 insertions(+) > create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi > > diff --git a/Documentation/devicetree/bindings/arm/sunxi.txt b/Documentation/devicetree/bindings/arm/sunxi.txt > index 7e79fcc36b0d..7e59d8ba86af 100644 > --- a/Documentation/devicetree/bindings/arm/sunxi.txt > +++ b/Documentation/devicetree/bindings/arm/sunxi.txt > @@ -14,3 +14,4 @@ using one of the following compatible strings: > allwinner,sun8i-a83t > allwinner,sun8i-h3 > allwinner,sun9i-a80 > + allwinner,sun50i-a64 > diff --git a/MAINTAINERS b/MAINTAINERS > index 20bb1d00098c..c8c0c85c113f 100644 > --- a/MAINTAINERS > +++ b/MAINTAINERS > @@ -982,6 +982,7 @@ M: Chen-Yu Tsai <wens@csie.org> > L: linux-arm-kernel at lists.infradead.org (moderated for non-subscribers) > S: Maintained > N: sun[x456789]i > +F: arch/arm64/boot/dts/allwinner/ If you promise to not break it needlessly ;-) > > ARM/Allwinner SoC Clock Support > M: Emilio L?pez <emilio@elopez.com.ar> > diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi > new file mode 100644 > index 000000000000..028cdbee20aa > --- /dev/null > +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi > @@ -0,0 +1,279 @@ > +/* > + * Copyright (C) 2016 ARM Ltd. > + * based on the Allwinner H3 dtsi: > + * Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com> > + * > + * This file is dual-licensed: you can use it either under the terms > + * of the GPL or the X11 license, at your option. Note that this dual > + * licensing only applies to this file, and not this project as a > + * whole. > + * > + * a) This file is free software; you can redistribute it and/or > + * modify it under the terms of the GNU General Public License as > + * published by the Free Software Foundation; either version 2 of the > + * License, or (at your option) any later version. > + * > + * This file is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * Or, alternatively, > + * > + * b) Permission is hereby granted, free of charge, to any person > + * obtaining a copy of this software and associated documentation > + * files (the "Software"), to deal in the Software without > + * restriction, including without limitation the rights to use, > + * copy, modify, merge, publish, distribute, sublicense, and/or > + * sell copies of the Software, and to permit persons to whom the > + * Software is furnished to do so, subject to the following > + * conditions: > + * > + * The above copyright notice and this permission notice shall be > + * included in all copies or substantial portions of the Software. > + * > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, > + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES > + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND > + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT > + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, > + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING > + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR > + * OTHER DEALINGS IN THE SOFTWARE. > + */ > + > +#include <dt-bindings/clock/sun50i-a64-ccu.h> > +#include <dt-bindings/interrupt-controller/arm-gic.h> > +#include <dt-bindings/pinctrl/sun4i-a10.h> > +#include <dt-bindings/reset/sun50i-a64-ccu.h> > + > +/ { > + interrupt-parent = <&gic>; > + #address-cells = <1>; > + #size-cells = <1>; > + > + cpus { > + #address-cells = <1>; > + #size-cells = <0>; > + > + cpu at 0 { This is probably me to blame here since I put you up to it, but you need "cpux" names (e.g. "cpu0: cpu at 0 {") to match the ones that the PMU node references below. dtc will refuse to compile it otherwise. > + compatible = "arm,cortex-a53", "arm,armv8"; > + device_type = "cpu"; > + reg = <0>; > + enable-method = "psci"; > + }; > + > + cpu at 1 { > + compatible = "arm,cortex-a53", "arm,armv8"; > + device_type = "cpu"; > + reg = <1>; > + enable-method = "psci"; > + }; > + > + cpu at 2 { > + compatible = "arm,cortex-a53", "arm,armv8"; > + device_type = "cpu"; > + reg = <2>; > + enable-method = "psci"; > + }; > + > + cpu at 3 { > + compatible = "arm,cortex-a53", "arm,armv8"; > + device_type = "cpu"; > + reg = <3>; > + enable-method = "psci"; > + }; > + }; > + > + osc24M: osc24M_clk { > + #clock-cells = <0>; > + compatible = "fixed-clock"; > + clock-frequency = <24000000>; > + clock-output-names = "osc24M"; > + }; > + > + osc32k: osc32k_clk { > + #clock-cells = <0>; > + compatible = "fixed-clock"; > + clock-frequency = <32768>; > + clock-output-names = "osc32k"; > + }; > + > + pmu { > + compatible = "arm,cortex-a53-pmu", "arm,armv8-pmuv3"; > + interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-affinity = <&cpu0>, > + <&cpu1>, > + <&cpu2>, > + <&cpu3>; > + }; > + > + psci { > + compatible = "arm,psci-0.2"; > + method = "smc"; > + }; > + > + timer { > + compatible = "arm,armv8-timer"; > + interrupts = <GIC_PPI 13 > + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, > + <GIC_PPI 14 > + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, > + <GIC_PPI 11 > + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, > + <GIC_PPI 10 > + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; > + }; > + > + soc { > + compatible = "simple-bus"; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges; > + > + ccu: clock at 01c20000 { > + compatible = "allwinner,sun50i-a64-ccu"; > + reg = <0x01c20000 0x400>; > + clocks = <&osc24M>, <&osc32k>; > + clock-names = "hosc", "losc"; > + #clock-cells = <1>; > + #reset-cells = <1>; > + }; > + > + pio: pinctrl at 1c20800 { > + compatible = "allwinner,sun50i-a64-pinctrl"; > + reg = <0x01c20800 0x400>; > + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&ccu CLK_BUS_PIO>; > + gpio-controller; > + #gpio-cells = <3>; > + interrupt-controller; > + #interrupt-cells = <2>; > + > + i2c1_pins: i2c1_pins { > + allwinner,pins = "PH2", "PH3"; > + allwinner,function = "i2c1"; > + allwinner,drive = <SUN4I_PINCTRL_10_MA>; > + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; > + }; > + > + uart0_pins_a: uart0 at 0 { > + allwinner,pins = "PB8", "PB9"; > + allwinner,function = "uart0"; > + allwinner,drive = <SUN4I_PINCTRL_10_MA>; > + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; > + }; So did I get this right that there is a strict "no user - no pins" policy here? I don't see a reason why we shouldn't have at least the other UART pins described here as well - since they are a pure SoC property. That would make it easier for people to enable them (with a simple, scripted fdt one-liner command in U-Boot, for instance). I guess there will never be an official DT with more than 2 UARTs enabled, although we have actually five UARTs on the headers on the Pine64, for instance (and personally I am looking into using one as a terminal server). Also UART1 is connected to that WiFi/Bluetooth slot, having it enabled should make BT work without further ado (but I haven't tested this). Thoughts? > + }; > + > + uart0: serial at 1c28000 { > + compatible = "snps,dw-apb-uart"; > + reg = <0x01c28000 0x400>; > + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; > + reg-shift = <2>; > + reg-io-width = <4>; > + clocks = <&ccu CLK_BUS_UART0>; > + resets = <&ccu RST_BUS_UART0>; > + status = "disabled"; > + }; > + > + uart1: serial at 1c28400 { > + compatible = "snps,dw-apb-uart"; > + reg = <0x01c28400 0x400>; > + interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; > + reg-shift = <2>; > + reg-io-width = <4>; > + clocks = <&ccu CLK_BUS_UART1>; > + resets = <&ccu RST_BUS_UART1>; > + status = "disabled"; > + }; > + > + uart2: serial at 1c28800 { > + compatible = "snps,dw-apb-uart"; > + reg = <0x01c28800 0x400>; > + interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; > + reg-shift = <2>; > + reg-io-width = <4>; > + clocks = <&ccu CLK_BUS_UART2>; > + resets = <&ccu RST_BUS_UART2>; > + status = "disabled"; > + }; > + > + uart3: serial at 1c28c00 { > + compatible = "snps,dw-apb-uart"; > + reg = <0x01c28c00 0x400>; > + interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; > + reg-shift = <2>; > + reg-io-width = <4>; > + clocks = <&ccu CLK_BUS_UART3>; > + resets = <&ccu RST_BUS_UART3>; > + status = "disabled"; > + }; > + > + uart4: serial at 1c29000 { > + compatible = "snps,dw-apb-uart"; > + reg = <0x01c29000 0x400>; > + interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; > + reg-shift = <2>; > + reg-io-width = <4>; > + clocks = <&ccu CLK_BUS_UART4>; > + resets = <&ccu RST_BUS_UART4>; > + status = "disabled"; > + }; > + > + rtc: rtc at 1f00000 { > + compatible = "allwinner,sun6i-a31-rtc"; > + reg = <0x01f00000 0x54>; > + interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; > + }; > + > + i2c0: i2c at 1c2ac00 { > + compatible = "allwinner,sun6i-a31-i2c"; > + reg = <0x01c2ac00 0x400>; > + interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&ccu CLK_BUS_I2C0>; > + resets = <&ccu RST_BUS_I2C0>; > + status = "disabled"; > + #address-cells = <1>; > + #size-cells = <0>; > + }; > + > + i2c1: i2c at 1c2b000 { > + compatible = "allwinner,sun6i-a31-i2c"; > + reg = <0x01c2b000 0x400>; > + interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&ccu CLK_BUS_I2C1>; > + resets = <&ccu RST_BUS_I2C1>; > + status = "disabled"; > + #address-cells = <1>; > + #size-cells = <0>; > + }; > + > + i2c2: i2c at 1c2b400 { > + compatible = "allwinner,sun6i-a31-i2c"; > + reg = <0x01c2b400 0x400>; > + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&ccu CLK_BUS_I2C2>; > + resets = <&ccu RST_BUS_I2C2>; > + status = "disabled"; > + #address-cells = <1>; > + #size-cells = <0>; > + }; > + > + gic: interrupt-controller at 1c81000 { > + compatible = "arm,gic-400"; > + reg = <0x01c81000 0x1000>, > + <0x01c82000 0x2000>, > + <0x01c84000 0x2000>, > + <0x01c86000 0x2000>; > + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; > + interrupt-controller; > + #interrupt-cells = <3>; > + }; This is clearly bike-shedding at this point ;-), but I think the GIC should belong up into the core peripherals, not under the "soc" node. > + }; > +}; > Cheers, Andre. ^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [PATCH v2 3/4] arm64: dts: add Allwinner A64 SoC .dtsi 2016-09-15 0:08 ` André Przywara @ 2016-09-17 14:51 ` Maxime Ripard -1 siblings, 0 replies; 35+ messages in thread From: Maxime Ripard @ 2016-09-17 14:51 UTC (permalink / raw) To: André Przywara Cc: Mike Turquette, Stephen Boyd, Chen-Yu Tsai, linux-arm-kernel, linux-clk, linux-kernel, linux-sunxi [-- Attachment #1: Type: text/plain, Size: 2976 bytes --] On Thu, Sep 15, 2016 at 01:08:45AM +0100, André Przywara wrote: > > --- a/MAINTAINERS > > +++ b/MAINTAINERS > > @@ -982,6 +982,7 @@ M: Chen-Yu Tsai <wens@csie.org> > > L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) > > S: Maintained > > N: sun[x456789]i > > +F: arch/arm64/boot/dts/allwinner/ > > If you promise to not break it needlessly ;-) We started doing so since 4.7, and we're already fighting needlessly with maintainers because of that. > > + cpus { > > + #address-cells = <1>; > > + #size-cells = <0>; > > + > > + cpu@0 { > > This is probably me to blame here since I put you up to it, but you need > "cpux" names (e.g. "cpu0: cpu@0 {") to match the ones that the PMU node > references below. dtc will refuse to compile it otherwise. Gaah, yes, of course. > > + i2c1_pins: i2c1_pins { > > + allwinner,pins = "PH2", "PH3"; > > + allwinner,function = "i2c1"; > > + allwinner,drive = <SUN4I_PINCTRL_10_MA>; > > + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; > > + }; > > + > > + uart0_pins_a: uart0@0 { > > + allwinner,pins = "PB8", "PB9"; > > + allwinner,function = "uart0"; > > + allwinner,drive = <SUN4I_PINCTRL_10_MA>; > > + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; > > + }; > > So did I get this right that there is a strict "no user - no pins" > policy here? > I don't see a reason why we shouldn't have at least the other UART pins > described here as well - since they are a pure SoC property. That would > make it easier for people to enable them (with a simple, scripted fdt > one-liner command in U-Boot, for instance). To avoid having huge DT that are longer to load and parse, especially since every one wires it in the exact same way all the time. And the combination is just too high. On the A64, the UART0 can be exposed through PB9 and PF4 for TX, and PB8 and PF2 for RX. Even though the common usage would be to use PB8 and PB9, or PF4 and PF6. But absolutely nothing prevents from using PB8 and PF4. You can then add CTS and RTS into the mix, and multiply that by the number of devices in the SoC. > I guess there will never be an official DT with more than 2 UARTs > enabled, although we have actually five UARTs on the headers on the > Pine64, for instance (and personally I am looking into using one as a > terminal server). We relaxed the rule lately however. Boards that have access to those UARTs on their headers can put a node in their DT with the right muxing filled already. Which brings you the simple, script fdt one-liner in U-Boot. > Also UART1 is connected to that WiFi/Bluetooth slot, having it enabled > should make BT work without further ado (but I haven't tested this). That's probably not true. You'll most likely need to enable a few regulators to have it working. Maxime -- Maxime Ripard, Free Electrons Embedded Linux and Kernel engineering http://free-electrons.com [-- Attachment #2: signature.asc --] [-- Type: application/pgp-signature, Size: 819 bytes --] ^ permalink raw reply [flat|nested] 35+ messages in thread
* [PATCH v2 3/4] arm64: dts: add Allwinner A64 SoC .dtsi @ 2016-09-17 14:51 ` Maxime Ripard 0 siblings, 0 replies; 35+ messages in thread From: Maxime Ripard @ 2016-09-17 14:51 UTC (permalink / raw) To: linux-arm-kernel On Thu, Sep 15, 2016 at 01:08:45AM +0100, Andr? Przywara wrote: > > --- a/MAINTAINERS > > +++ b/MAINTAINERS > > @@ -982,6 +982,7 @@ M: Chen-Yu Tsai <wens@csie.org> > > L: linux-arm-kernel at lists.infradead.org (moderated for non-subscribers) > > S: Maintained > > N: sun[x456789]i > > +F: arch/arm64/boot/dts/allwinner/ > > If you promise to not break it needlessly ;-) We started doing so since 4.7, and we're already fighting needlessly with maintainers because of that. > > + cpus { > > + #address-cells = <1>; > > + #size-cells = <0>; > > + > > + cpu at 0 { > > This is probably me to blame here since I put you up to it, but you need > "cpux" names (e.g. "cpu0: cpu at 0 {") to match the ones that the PMU node > references below. dtc will refuse to compile it otherwise. Gaah, yes, of course. > > + i2c1_pins: i2c1_pins { > > + allwinner,pins = "PH2", "PH3"; > > + allwinner,function = "i2c1"; > > + allwinner,drive = <SUN4I_PINCTRL_10_MA>; > > + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; > > + }; > > + > > + uart0_pins_a: uart0 at 0 { > > + allwinner,pins = "PB8", "PB9"; > > + allwinner,function = "uart0"; > > + allwinner,drive = <SUN4I_PINCTRL_10_MA>; > > + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; > > + }; > > So did I get this right that there is a strict "no user - no pins" > policy here? > I don't see a reason why we shouldn't have at least the other UART pins > described here as well - since they are a pure SoC property. That would > make it easier for people to enable them (with a simple, scripted fdt > one-liner command in U-Boot, for instance). To avoid having huge DT that are longer to load and parse, especially since every one wires it in the exact same way all the time. And the combination is just too high. On the A64, the UART0 can be exposed through PB9 and PF4 for TX, and PB8 and PF2 for RX. Even though the common usage would be to use PB8 and PB9, or PF4 and PF6. But absolutely nothing prevents from using PB8 and PF4. You can then add CTS and RTS into the mix, and multiply that by the number of devices in the SoC. > I guess there will never be an official DT with more than 2 UARTs > enabled, although we have actually five UARTs on the headers on the > Pine64, for instance (and personally I am looking into using one as a > terminal server). We relaxed the rule lately however. Boards that have access to those UARTs on their headers can put a node in their DT with the right muxing filled already. Which brings you the simple, script fdt one-liner in U-Boot. > Also UART1 is connected to that WiFi/Bluetooth slot, having it enabled > should make BT work without further ado (but I haven't tested this). That's probably not true. You'll most likely need to enable a few regulators to have it working. Maxime -- Maxime Ripard, Free Electrons Embedded Linux and Kernel engineering http://free-electrons.com -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 819 bytes Desc: not available URL: <http://lists.infradead.org/pipermail/linux-arm-kernel/attachments/20160917/cca5bec3/attachment.sig> ^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [PATCH v2 3/4] arm64: dts: add Allwinner A64 SoC .dtsi 2016-09-17 14:51 ` Maxime Ripard @ 2016-09-18 1:21 ` Icenowy Zheng -1 siblings, 0 replies; 35+ messages in thread From: Icenowy Zheng @ 2016-09-18 1:21 UTC (permalink / raw) To: Maxime Ripard, André Przywara Cc: Mike Turquette, linux-sunxi, Stephen Boyd, linux-kernel, Chen-Yu Tsai, linux-clk, linux-arm-kernel 17.09.2016, 22:56, "Maxime Ripard" <maxime.ripard@free-electrons.com>: > On Thu, Sep 15, 2016 at 01:08:45AM +0100, André Przywara wrote: >> > --- a/MAINTAINERS >> > +++ b/MAINTAINERS >> > @@ -982,6 +982,7 @@ M: Chen-Yu Tsai <wens@csie.org> >> > L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) >> > S: Maintained >> > N: sun[x456789]i >> > +F: arch/arm64/boot/dts/allwinner/ >> >> If you promise to not break it needlessly ;-) > > We started doing so since 4.7, and we're already fighting needlessly > with maintainers because of that. > >> > + cpus { >> > + #address-cells = <1>; >> > + #size-cells = <0>; >> > + >> > + cpu@0 { >> >> This is probably me to blame here since I put you up to it, but you need >> "cpux" names (e.g. "cpu0: cpu@0 {") to match the ones that the PMU node >> references below. dtc will refuse to compile it otherwise. > > Gaah, yes, of course. > >> > + i2c1_pins: i2c1_pins { >> > + allwinner,pins = "PH2", "PH3"; >> > + allwinner,function = "i2c1"; >> > + allwinner,drive = <SUN4I_PINCTRL_10_MA>; >> > + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; >> > + }; >> > + >> > + uart0_pins_a: uart0@0 { >> > + allwinner,pins = "PB8", "PB9"; >> > + allwinner,function = "uart0"; >> > + allwinner,drive = <SUN4I_PINCTRL_10_MA>; >> > + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; >> > + }; >> >> So did I get this right that there is a strict "no user - no pins" >> policy here? >> I don't see a reason why we shouldn't have at least the other UART pins >> described here as well - since they are a pure SoC property. That would >> make it easier for people to enable them (with a simple, scripted fdt >> one-liner command in U-Boot, for instance). > > To avoid having huge DT that are longer to load and parse, especially > since every one wires it in the exact same way all the time. And the > combination is just too high. > > On the A64, the UART0 can be exposed through PB9 and PF4 for TX, and > PB8 and PF2 for RX. Even though the common usage would be to use PB8 > and PB9, or PF4 and PF6. But absolutely nothing prevents from using > PB8 and PF4. > > You can then add CTS and RTS into the mix, and multiply that by the > number of devices in the SoC. > >> I guess there will never be an official DT with more than 2 UARTs >> enabled, although we have actually five UARTs on the headers on the >> Pine64, for instance (and personally I am looking into using one as a >> terminal server). > > We relaxed the rule lately however. Boards that have access to those > UARTs on their headers can put a node in their DT with the right > muxing filled already. Which brings you the simple, script fdt > one-liner in U-Boot. > >> Also UART1 is connected to that WiFi/Bluetooth slot, having it enabled >> should make BT work without further ado (but I haven't tested this). > > That's probably not true. You'll most likely need to enable a few > regulators to have it working. It seems that Andre has enabled the necessary regulator in the newest version of his ARM Trusted Firmware... > > Maxime > > -- > Maxime Ripard, Free Electrons > Embedded Linux and Kernel engineering > http://free-electrons.com > , > > _______________________________________________ > linux-arm-kernel mailing list > linux-arm-kernel@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 35+ messages in thread
* [PATCH v2 3/4] arm64: dts: add Allwinner A64 SoC .dtsi @ 2016-09-18 1:21 ` Icenowy Zheng 0 siblings, 0 replies; 35+ messages in thread From: Icenowy Zheng @ 2016-09-18 1:21 UTC (permalink / raw) To: linux-arm-kernel 17.09.2016, 22:56, "Maxime Ripard" <maxime.ripard@free-electrons.com>: > On Thu, Sep 15, 2016 at 01:08:45AM +0100, Andr? Przywara wrote: >> ?> --- a/MAINTAINERS >> ?> +++ b/MAINTAINERS >> ?> @@ -982,6 +982,7 @@ M: Chen-Yu Tsai <wens@csie.org> >> ?> L: linux-arm-kernel at lists.infradead.org (moderated for non-subscribers) >> ?> S: Maintained >> ?> N: sun[x456789]i >> ?> +F: arch/arm64/boot/dts/allwinner/ >> >> ?If you promise to not break it needlessly ;-) > > We started doing so since 4.7, and we're already fighting needlessly > with maintainers because of that. > >> ?> + cpus { >> ?> + #address-cells = <1>; >> ?> + #size-cells = <0>; >> ?> + >> ?> + cpu at 0 { >> >> ?This is probably me to blame here since I put you up to it, but you need >> ?"cpux" names (e.g. "cpu0: cpu at 0 {") to match the ones that the PMU node >> ?references below. dtc will refuse to compile it otherwise. > > Gaah, yes, of course. > >> ?> + i2c1_pins: i2c1_pins { >> ?> + allwinner,pins = "PH2", "PH3"; >> ?> + allwinner,function = "i2c1"; >> ?> + allwinner,drive = <SUN4I_PINCTRL_10_MA>; >> ?> + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; >> ?> + }; >> ?> + >> ?> + uart0_pins_a: uart0 at 0 { >> ?> + allwinner,pins = "PB8", "PB9"; >> ?> + allwinner,function = "uart0"; >> ?> + allwinner,drive = <SUN4I_PINCTRL_10_MA>; >> ?> + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; >> ?> + }; >> >> ?So did I get this right that there is a strict "no user - no pins" >> ?policy here? >> ?I don't see a reason why we shouldn't have at least the other UART pins >> ?described here as well - since they are a pure SoC property. That would >> ?make it easier for people to enable them (with a simple, scripted fdt >> ?one-liner command in U-Boot, for instance). > > To avoid having huge DT that are longer to load and parse, especially > since every one wires it in the exact same way all the time. And the > combination is just too high. > > On the A64, the UART0 can be exposed through PB9 and PF4 for TX, and > PB8 and PF2 for RX. Even though the common usage would be to use PB8 > and PB9, or PF4 and PF6. But absolutely nothing prevents from using > PB8 and PF4. > > You can then add CTS and RTS into the mix, and multiply that by the > number of devices in the SoC. > >> ?I guess there will never be an official DT with more than 2 UARTs >> ?enabled, although we have actually five UARTs on the headers on the >> ?Pine64, for instance (and personally I am looking into using one as a >> ?terminal server). > > We relaxed the rule lately however. Boards that have access to those > UARTs on their headers can put a node in their DT with the right > muxing filled already. Which brings you the simple, script fdt > one-liner in U-Boot. > >> ?Also UART1 is connected to that WiFi/Bluetooth slot, having it enabled >> ?should make BT work without further ado (but I haven't tested this). > > That's probably not true. You'll most likely need to enable a few > regulators to have it working. It seems that Andre has enabled the necessary regulator in the newest version of his ARM Trusted Firmware... > > Maxime > > -- > Maxime Ripard, Free Electrons > Embedded Linux and Kernel engineering > http://free-electrons.com > , > > _______________________________________________ > linux-arm-kernel mailing list > linux-arm-kernel at lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 35+ messages in thread
* [PATCH v2 4/4] arm64: dts: add Pine64 support 2016-09-09 20:10 ` Maxime Ripard @ 2016-09-09 20:10 ` Maxime Ripard -1 siblings, 0 replies; 35+ messages in thread From: Maxime Ripard @ 2016-09-09 20:10 UTC (permalink / raw) To: Mike Turquette, Stephen Boyd, Chen-Yu Tsai, Maxime Ripard Cc: linux-arm-kernel, Andre Przywara, linux-clk, linux-kernel, linux-sunxi From: Andre Przywara <andre.przywara@arm.com> The Pine64 is a cost-efficient development board based on the Allwinner A64 SoC. There are three models: the basic version with Fast Ethernet and 512 MB of DRAM (Pine64) and two Pine64+ versions, which both feature Gigabit Ethernet and additional connectors for touchscreens and a camera. Or as my son put it: "Those are smaller and these are missing." ;-) The two Pine64+ models just differ in the amount of DRAM (1GB vs. 2GB). Since U-Boot will figure out the right size for us and patches the DT accordingly we just need to provide one DT for the Pine64+. Signed-off-by: Andre Przywara <andre.przywara@arm.com> [Maxime: Removed the common DTSI and include directly the pine64 DTS] Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> --- arch/arm64/boot/dts/Makefile | 1 + arch/arm64/boot/dts/allwinner/Makefile | 5 ++ .../boot/dts/allwinner/sun50i-a64-pine64-plus.dts | 50 ++++++++++++++++ .../arm64/boot/dts/allwinner/sun50i-a64-pine64.dts | 70 ++++++++++++++++++++++ 4 files changed, 126 insertions(+) create mode 100644 arch/arm64/boot/dts/allwinner/Makefile create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-plus.dts create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile index 6e199c903676..ddcbf5a2c17e 100644 --- a/arch/arm64/boot/dts/Makefile +++ b/arch/arm64/boot/dts/Makefile @@ -1,4 +1,5 @@ dts-dirs += al +dts-dirs += allwinner dts-dirs += altera dts-dirs += amd dts-dirs += amlogic diff --git a/arch/arm64/boot/dts/allwinner/Makefile b/arch/arm64/boot/dts/allwinner/Makefile new file mode 100644 index 000000000000..1e29a5ae8282 --- /dev/null +++ b/arch/arm64/boot/dts/allwinner/Makefile @@ -0,0 +1,5 @@ +dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-pine64-plus.dtb sun50i-a64-pine64.dtb + +always := $(dtb-y) +subdir-y := $(dts-dirs) +clean-files := *.dtb diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-plus.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-plus.dts new file mode 100644 index 000000000000..790d14daaa6a --- /dev/null +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-plus.dts @@ -0,0 +1,50 @@ +/* + * Copyright (c) 2016 ARM Ltd. + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include "sun50i-a64-pine64.dts" + +/ { + model = "Pine64+"; + compatible = "pine64,pine64-plus", "allwinner,sun50i-a64"; + + /* TODO: Camera, Ethernet PHY, touchscreen, etc. */ +}; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts new file mode 100644 index 000000000000..da9bca51f5a9 --- /dev/null +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts @@ -0,0 +1,70 @@ +/* + * Copyright (c) 2016 ARM Ltd. + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; + +#include "sun50i-a64.dtsi" + +/ { + model = "Pine64"; + compatible = "pine64,pine64", "allwinner,sun50i-a64"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins_a>; + status = "okay"; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; + status = "okay"; +}; -- 2.9.3 ^ permalink raw reply related [flat|nested] 35+ messages in thread
* [PATCH v2 4/4] arm64: dts: add Pine64 support @ 2016-09-09 20:10 ` Maxime Ripard 0 siblings, 0 replies; 35+ messages in thread From: Maxime Ripard @ 2016-09-09 20:10 UTC (permalink / raw) To: linux-arm-kernel From: Andre Przywara <andre.przywara@arm.com> The Pine64 is a cost-efficient development board based on the Allwinner A64 SoC. There are three models: the basic version with Fast Ethernet and 512 MB of DRAM (Pine64) and two Pine64+ versions, which both feature Gigabit Ethernet and additional connectors for touchscreens and a camera. Or as my son put it: "Those are smaller and these are missing." ;-) The two Pine64+ models just differ in the amount of DRAM (1GB vs. 2GB). Since U-Boot will figure out the right size for us and patches the DT accordingly we just need to provide one DT for the Pine64+. Signed-off-by: Andre Przywara <andre.przywara@arm.com> [Maxime: Removed the common DTSI and include directly the pine64 DTS] Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> --- arch/arm64/boot/dts/Makefile | 1 + arch/arm64/boot/dts/allwinner/Makefile | 5 ++ .../boot/dts/allwinner/sun50i-a64-pine64-plus.dts | 50 ++++++++++++++++ .../arm64/boot/dts/allwinner/sun50i-a64-pine64.dts | 70 ++++++++++++++++++++++ 4 files changed, 126 insertions(+) create mode 100644 arch/arm64/boot/dts/allwinner/Makefile create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-plus.dts create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile index 6e199c903676..ddcbf5a2c17e 100644 --- a/arch/arm64/boot/dts/Makefile +++ b/arch/arm64/boot/dts/Makefile @@ -1,4 +1,5 @@ dts-dirs += al +dts-dirs += allwinner dts-dirs += altera dts-dirs += amd dts-dirs += amlogic diff --git a/arch/arm64/boot/dts/allwinner/Makefile b/arch/arm64/boot/dts/allwinner/Makefile new file mode 100644 index 000000000000..1e29a5ae8282 --- /dev/null +++ b/arch/arm64/boot/dts/allwinner/Makefile @@ -0,0 +1,5 @@ +dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-pine64-plus.dtb sun50i-a64-pine64.dtb + +always := $(dtb-y) +subdir-y := $(dts-dirs) +clean-files := *.dtb diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-plus.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-plus.dts new file mode 100644 index 000000000000..790d14daaa6a --- /dev/null +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-plus.dts @@ -0,0 +1,50 @@ +/* + * Copyright (c) 2016 ARM Ltd. + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include "sun50i-a64-pine64.dts" + +/ { + model = "Pine64+"; + compatible = "pine64,pine64-plus", "allwinner,sun50i-a64"; + + /* TODO: Camera, Ethernet PHY, touchscreen, etc. */ +}; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts new file mode 100644 index 000000000000..da9bca51f5a9 --- /dev/null +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts @@ -0,0 +1,70 @@ +/* + * Copyright (c) 2016 ARM Ltd. + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; + +#include "sun50i-a64.dtsi" + +/ { + model = "Pine64"; + compatible = "pine64,pine64", "allwinner,sun50i-a64"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins_a>; + status = "okay"; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; + status = "okay"; +}; -- 2.9.3 ^ permalink raw reply related [flat|nested] 35+ messages in thread
* Re: [PATCH v2 4/4] arm64: dts: add Pine64 support 2016-09-09 20:10 ` Maxime Ripard @ 2016-09-10 2:33 ` Chen-Yu Tsai -1 siblings, 0 replies; 35+ messages in thread From: Chen-Yu Tsai @ 2016-09-10 2:33 UTC (permalink / raw) To: Maxime Ripard Cc: Mike Turquette, Stephen Boyd, Chen-Yu Tsai, linux-arm-kernel, Andre Przywara, linux-clk, linux-kernel, linux-sunxi Hi, On Sat, Sep 10, 2016 at 4:10 AM, Maxime Ripard <maxime.ripard@free-electrons.com> wrote: > From: Andre Przywara <andre.przywara@arm.com> > > The Pine64 is a cost-efficient development board based on the > Allwinner A64 SoC. > There are three models: the basic version with Fast Ethernet and > 512 MB of DRAM (Pine64) and two Pine64+ versions, which both > feature Gigabit Ethernet and additional connectors for touchscreens > and a camera. Or as my son put it: "Those are smaller and these are > missing." ;-) > The two Pine64+ models just differ in the amount of DRAM > (1GB vs. 2GB). Since U-Boot will figure out the right size for us and > patches the DT accordingly we just need to provide one DT for the > Pine64+. > > Signed-off-by: Andre Przywara <andre.przywara@arm.com> > [Maxime: Removed the common DTSI and include directly the pine64 DTS] > Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> > --- > arch/arm64/boot/dts/Makefile | 1 + > arch/arm64/boot/dts/allwinner/Makefile | 5 ++ > .../boot/dts/allwinner/sun50i-a64-pine64-plus.dts | 50 ++++++++++++++++ > .../arm64/boot/dts/allwinner/sun50i-a64-pine64.dts | 70 ++++++++++++++++++++++ > 4 files changed, 126 insertions(+) > create mode 100644 arch/arm64/boot/dts/allwinner/Makefile > create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-plus.dts > create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts > > diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile > index 6e199c903676..ddcbf5a2c17e 100644 > --- a/arch/arm64/boot/dts/Makefile > +++ b/arch/arm64/boot/dts/Makefile > @@ -1,4 +1,5 @@ > dts-dirs += al > +dts-dirs += allwinner > dts-dirs += altera > dts-dirs += amd > dts-dirs += amlogic > diff --git a/arch/arm64/boot/dts/allwinner/Makefile b/arch/arm64/boot/dts/allwinner/Makefile > new file mode 100644 > index 000000000000..1e29a5ae8282 > --- /dev/null > +++ b/arch/arm64/boot/dts/allwinner/Makefile > @@ -0,0 +1,5 @@ > +dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-pine64-plus.dtb sun50i-a64-pine64.dtb > + > +always := $(dtb-y) > +subdir-y := $(dts-dirs) > +clean-files := *.dtb > diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-plus.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-plus.dts > new file mode 100644 > index 000000000000..790d14daaa6a > --- /dev/null > +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-plus.dts > @@ -0,0 +1,50 @@ > +/* > + * Copyright (c) 2016 ARM Ltd. > + * > + * This file is dual-licensed: you can use it either under the terms > + * of the GPL or the X11 license, at your option. Note that this dual > + * licensing only applies to this file, and not this project as a > + * whole. > + * > + * a) This library is free software; you can redistribute it and/or > + * modify it under the terms of the GNU General Public License as > + * published by the Free Software Foundation; either version 2 of the > + * License, or (at your option) any later version. > + * > + * This library is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * Or, alternatively, > + * > + * b) Permission is hereby granted, free of charge, to any person > + * obtaining a copy of this software and associated documentation > + * files (the "Software"), to deal in the Software without > + * restriction, including without limitation the rights to use, > + * copy, modify, merge, publish, distribute, sublicense, and/or > + * sell copies of the Software, and to permit persons to whom the > + * Software is furnished to do so, subject to the following > + * conditions: > + * > + * The above copyright notice and this permission notice shall be > + * included in all copies or substantial portions of the Software. > + * > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, > + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES > + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND > + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT > + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, > + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING > + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR > + * OTHER DEALINGS IN THE SOFTWARE. > + */ > + > +#include "sun50i-a64-pine64.dts" > + > +/ { > + model = "Pine64+"; > + compatible = "pine64,pine64-plus", "allwinner,sun50i-a64"; > + > + /* TODO: Camera, Ethernet PHY, touchscreen, etc. */ > +}; > diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts > new file mode 100644 > index 000000000000..da9bca51f5a9 > --- /dev/null > +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts > @@ -0,0 +1,70 @@ > +/* > + * Copyright (c) 2016 ARM Ltd. > + * > + * This file is dual-licensed: you can use it either under the terms > + * of the GPL or the X11 license, at your option. Note that this dual > + * licensing only applies to this file, and not this project as a > + * whole. > + * > + * a) This library is free software; you can redistribute it and/or > + * modify it under the terms of the GNU General Public License as > + * published by the Free Software Foundation; either version 2 of the > + * License, or (at your option) any later version. > + * > + * This library is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * Or, alternatively, > + * > + * b) Permission is hereby granted, free of charge, to any person > + * obtaining a copy of this software and associated documentation > + * files (the "Software"), to deal in the Software without > + * restriction, including without limitation the rights to use, > + * copy, modify, merge, publish, distribute, sublicense, and/or > + * sell copies of the Software, and to permit persons to whom the > + * Software is furnished to do so, subject to the following > + * conditions: > + * > + * The above copyright notice and this permission notice shall be > + * included in all copies or substantial portions of the Software. > + * > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, > + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES > + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND > + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT > + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, > + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING > + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR > + * OTHER DEALINGS IN THE SOFTWARE. > + */ > + > +/dts-v1/; > + > +#include "sun50i-a64.dtsi" > + > +/ { > + model = "Pine64"; > + compatible = "pine64,pine64", "allwinner,sun50i-a64"; > + > + aliases { > + serial0 = &uart0; > + }; > + > + chosen { > + stdout-path = "serial0:115200n8"; > + }; > +}; > + > +&uart0 { > + pinctrl-names = "default"; > + pinctrl-0 = <&uart0_pins_a>; > + status = "okay"; > +}; > + > +&i2c1 { > + pinctrl-names = "default"; > + pinctrl-0 = <&i2c1_pins>; > + status = "okay"; Schematics say this is missing an external pull-up. Has anyone tried it? Without a pull-up any access on the i2c bus should just block. Also this is on the RPi-2 compatible header. There's also an UART and SPI that are standard for the RPi-2 header. We should consider enabling them as well. ChenYu > +}; > -- > 2.9.3 > ^ permalink raw reply [flat|nested] 35+ messages in thread
* [PATCH v2 4/4] arm64: dts: add Pine64 support @ 2016-09-10 2:33 ` Chen-Yu Tsai 0 siblings, 0 replies; 35+ messages in thread From: Chen-Yu Tsai @ 2016-09-10 2:33 UTC (permalink / raw) To: linux-arm-kernel Hi, On Sat, Sep 10, 2016 at 4:10 AM, Maxime Ripard <maxime.ripard@free-electrons.com> wrote: > From: Andre Przywara <andre.przywara@arm.com> > > The Pine64 is a cost-efficient development board based on the > Allwinner A64 SoC. > There are three models: the basic version with Fast Ethernet and > 512 MB of DRAM (Pine64) and two Pine64+ versions, which both > feature Gigabit Ethernet and additional connectors for touchscreens > and a camera. Or as my son put it: "Those are smaller and these are > missing." ;-) > The two Pine64+ models just differ in the amount of DRAM > (1GB vs. 2GB). Since U-Boot will figure out the right size for us and > patches the DT accordingly we just need to provide one DT for the > Pine64+. > > Signed-off-by: Andre Przywara <andre.przywara@arm.com> > [Maxime: Removed the common DTSI and include directly the pine64 DTS] > Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> > --- > arch/arm64/boot/dts/Makefile | 1 + > arch/arm64/boot/dts/allwinner/Makefile | 5 ++ > .../boot/dts/allwinner/sun50i-a64-pine64-plus.dts | 50 ++++++++++++++++ > .../arm64/boot/dts/allwinner/sun50i-a64-pine64.dts | 70 ++++++++++++++++++++++ > 4 files changed, 126 insertions(+) > create mode 100644 arch/arm64/boot/dts/allwinner/Makefile > create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-plus.dts > create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts > > diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile > index 6e199c903676..ddcbf5a2c17e 100644 > --- a/arch/arm64/boot/dts/Makefile > +++ b/arch/arm64/boot/dts/Makefile > @@ -1,4 +1,5 @@ > dts-dirs += al > +dts-dirs += allwinner > dts-dirs += altera > dts-dirs += amd > dts-dirs += amlogic > diff --git a/arch/arm64/boot/dts/allwinner/Makefile b/arch/arm64/boot/dts/allwinner/Makefile > new file mode 100644 > index 000000000000..1e29a5ae8282 > --- /dev/null > +++ b/arch/arm64/boot/dts/allwinner/Makefile > @@ -0,0 +1,5 @@ > +dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-pine64-plus.dtb sun50i-a64-pine64.dtb > + > +always := $(dtb-y) > +subdir-y := $(dts-dirs) > +clean-files := *.dtb > diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-plus.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-plus.dts > new file mode 100644 > index 000000000000..790d14daaa6a > --- /dev/null > +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-plus.dts > @@ -0,0 +1,50 @@ > +/* > + * Copyright (c) 2016 ARM Ltd. > + * > + * This file is dual-licensed: you can use it either under the terms > + * of the GPL or the X11 license, at your option. Note that this dual > + * licensing only applies to this file, and not this project as a > + * whole. > + * > + * a) This library is free software; you can redistribute it and/or > + * modify it under the terms of the GNU General Public License as > + * published by the Free Software Foundation; either version 2 of the > + * License, or (at your option) any later version. > + * > + * This library is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * Or, alternatively, > + * > + * b) Permission is hereby granted, free of charge, to any person > + * obtaining a copy of this software and associated documentation > + * files (the "Software"), to deal in the Software without > + * restriction, including without limitation the rights to use, > + * copy, modify, merge, publish, distribute, sublicense, and/or > + * sell copies of the Software, and to permit persons to whom the > + * Software is furnished to do so, subject to the following > + * conditions: > + * > + * The above copyright notice and this permission notice shall be > + * included in all copies or substantial portions of the Software. > + * > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, > + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES > + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND > + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT > + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, > + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING > + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR > + * OTHER DEALINGS IN THE SOFTWARE. > + */ > + > +#include "sun50i-a64-pine64.dts" > + > +/ { > + model = "Pine64+"; > + compatible = "pine64,pine64-plus", "allwinner,sun50i-a64"; > + > + /* TODO: Camera, Ethernet PHY, touchscreen, etc. */ > +}; > diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts > new file mode 100644 > index 000000000000..da9bca51f5a9 > --- /dev/null > +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts > @@ -0,0 +1,70 @@ > +/* > + * Copyright (c) 2016 ARM Ltd. > + * > + * This file is dual-licensed: you can use it either under the terms > + * of the GPL or the X11 license, at your option. Note that this dual > + * licensing only applies to this file, and not this project as a > + * whole. > + * > + * a) This library is free software; you can redistribute it and/or > + * modify it under the terms of the GNU General Public License as > + * published by the Free Software Foundation; either version 2 of the > + * License, or (at your option) any later version. > + * > + * This library is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * Or, alternatively, > + * > + * b) Permission is hereby granted, free of charge, to any person > + * obtaining a copy of this software and associated documentation > + * files (the "Software"), to deal in the Software without > + * restriction, including without limitation the rights to use, > + * copy, modify, merge, publish, distribute, sublicense, and/or > + * sell copies of the Software, and to permit persons to whom the > + * Software is furnished to do so, subject to the following > + * conditions: > + * > + * The above copyright notice and this permission notice shall be > + * included in all copies or substantial portions of the Software. > + * > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, > + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES > + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND > + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT > + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, > + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING > + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR > + * OTHER DEALINGS IN THE SOFTWARE. > + */ > + > +/dts-v1/; > + > +#include "sun50i-a64.dtsi" > + > +/ { > + model = "Pine64"; > + compatible = "pine64,pine64", "allwinner,sun50i-a64"; > + > + aliases { > + serial0 = &uart0; > + }; > + > + chosen { > + stdout-path = "serial0:115200n8"; > + }; > +}; > + > +&uart0 { > + pinctrl-names = "default"; > + pinctrl-0 = <&uart0_pins_a>; > + status = "okay"; > +}; > + > +&i2c1 { > + pinctrl-names = "default"; > + pinctrl-0 = <&i2c1_pins>; > + status = "okay"; Schematics say this is missing an external pull-up. Has anyone tried it? Without a pull-up any access on the i2c bus should just block. Also this is on the RPi-2 compatible header. There's also an UART and SPI that are standard for the RPi-2 header. We should consider enabling them as well. ChenYu > +}; > -- > 2.9.3 > ^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [PATCH v2 4/4] arm64: dts: add Pine64 support 2016-09-10 2:33 ` Chen-Yu Tsai @ 2016-09-12 10:11 ` Andre Przywara -1 siblings, 0 replies; 35+ messages in thread From: Andre Przywara @ 2016-09-12 10:11 UTC (permalink / raw) To: Chen-Yu Tsai, Maxime Ripard Cc: Mike Turquette, Stephen Boyd, linux-arm-kernel, linux-clk, linux-kernel, linux-sunxi Hi, On 10/09/16 03:33, Chen-Yu Tsai wrote: > Hi, > > On Sat, Sep 10, 2016 at 4:10 AM, Maxime Ripard > <maxime.ripard@free-electrons.com> wrote: >> From: Andre Przywara <andre.przywara@arm.com> >> >> The Pine64 is a cost-efficient development board based on the >> Allwinner A64 SoC. >> There are three models: the basic version with Fast Ethernet and >> 512 MB of DRAM (Pine64) and two Pine64+ versions, which both >> feature Gigabit Ethernet and additional connectors for touchscreens >> and a camera. Or as my son put it: "Those are smaller and these are >> missing." ;-) >> The two Pine64+ models just differ in the amount of DRAM >> (1GB vs. 2GB). Since U-Boot will figure out the right size for us and >> patches the DT accordingly we just need to provide one DT for the >> Pine64+. >> >> Signed-off-by: Andre Przywara <andre.przywara@arm.com> >> [Maxime: Removed the common DTSI and include directly the pine64 DTS] >> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> >> --- >> arch/arm64/boot/dts/Makefile | 1 + >> arch/arm64/boot/dts/allwinner/Makefile | 5 ++ >> .../boot/dts/allwinner/sun50i-a64-pine64-plus.dts | 50 ++++++++++++++++ >> .../arm64/boot/dts/allwinner/sun50i-a64-pine64.dts | 70 ++++++++++++++++++++++ >> 4 files changed, 126 insertions(+) >> create mode 100644 arch/arm64/boot/dts/allwinner/Makefile >> create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-plus.dts >> create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts >> >> diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile >> index 6e199c903676..ddcbf5a2c17e 100644 >> --- a/arch/arm64/boot/dts/Makefile >> +++ b/arch/arm64/boot/dts/Makefile >> @@ -1,4 +1,5 @@ >> dts-dirs += al >> +dts-dirs += allwinner >> dts-dirs += altera >> dts-dirs += amd >> dts-dirs += amlogic >> diff --git a/arch/arm64/boot/dts/allwinner/Makefile b/arch/arm64/boot/dts/allwinner/Makefile >> new file mode 100644 >> index 000000000000..1e29a5ae8282 >> --- /dev/null >> +++ b/arch/arm64/boot/dts/allwinner/Makefile >> @@ -0,0 +1,5 @@ >> +dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-pine64-plus.dtb sun50i-a64-pine64.dtb >> + >> +always := $(dtb-y) >> +subdir-y := $(dts-dirs) >> +clean-files := *.dtb >> diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-plus.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-plus.dts >> new file mode 100644 >> index 000000000000..790d14daaa6a >> --- /dev/null >> +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-plus.dts >> @@ -0,0 +1,50 @@ >> +/* >> + * Copyright (c) 2016 ARM Ltd. >> + * >> + * This file is dual-licensed: you can use it either under the terms >> + * of the GPL or the X11 license, at your option. Note that this dual >> + * licensing only applies to this file, and not this project as a >> + * whole. >> + * >> + * a) This library is free software; you can redistribute it and/or >> + * modify it under the terms of the GNU General Public License as >> + * published by the Free Software Foundation; either version 2 of the >> + * License, or (at your option) any later version. >> + * >> + * This library is distributed in the hope that it will be useful, >> + * but WITHOUT ANY WARRANTY; without even the implied warranty of >> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the >> + * GNU General Public License for more details. >> + * >> + * Or, alternatively, >> + * >> + * b) Permission is hereby granted, free of charge, to any person >> + * obtaining a copy of this software and associated documentation >> + * files (the "Software"), to deal in the Software without >> + * restriction, including without limitation the rights to use, >> + * copy, modify, merge, publish, distribute, sublicense, and/or >> + * sell copies of the Software, and to permit persons to whom the >> + * Software is furnished to do so, subject to the following >> + * conditions: >> + * >> + * The above copyright notice and this permission notice shall be >> + * included in all copies or substantial portions of the Software. >> + * >> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, >> + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES >> + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND >> + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT >> + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, >> + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING >> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR >> + * OTHER DEALINGS IN THE SOFTWARE. >> + */ >> + >> +#include "sun50i-a64-pine64.dts" >> + >> +/ { >> + model = "Pine64+"; >> + compatible = "pine64,pine64-plus", "allwinner,sun50i-a64"; >> + >> + /* TODO: Camera, Ethernet PHY, touchscreen, etc. */ >> +}; >> diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts >> new file mode 100644 >> index 000000000000..da9bca51f5a9 >> --- /dev/null >> +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts >> @@ -0,0 +1,70 @@ >> +/* >> + * Copyright (c) 2016 ARM Ltd. >> + * >> + * This file is dual-licensed: you can use it either under the terms >> + * of the GPL or the X11 license, at your option. Note that this dual >> + * licensing only applies to this file, and not this project as a >> + * whole. >> + * >> + * a) This library is free software; you can redistribute it and/or >> + * modify it under the terms of the GNU General Public License as >> + * published by the Free Software Foundation; either version 2 of the >> + * License, or (at your option) any later version. >> + * >> + * This library is distributed in the hope that it will be useful, >> + * but WITHOUT ANY WARRANTY; without even the implied warranty of >> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the >> + * GNU General Public License for more details. >> + * >> + * Or, alternatively, >> + * >> + * b) Permission is hereby granted, free of charge, to any person >> + * obtaining a copy of this software and associated documentation >> + * files (the "Software"), to deal in the Software without >> + * restriction, including without limitation the rights to use, >> + * copy, modify, merge, publish, distribute, sublicense, and/or >> + * sell copies of the Software, and to permit persons to whom the >> + * Software is furnished to do so, subject to the following >> + * conditions: >> + * >> + * The above copyright notice and this permission notice shall be >> + * included in all copies or substantial portions of the Software. >> + * >> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, >> + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES >> + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND >> + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT >> + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, >> + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING >> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR >> + * OTHER DEALINGS IN THE SOFTWARE. >> + */ >> + >> +/dts-v1/; >> + >> +#include "sun50i-a64.dtsi" >> + >> +/ { >> + model = "Pine64"; >> + compatible = "pine64,pine64", "allwinner,sun50i-a64"; >> + >> + aliases { >> + serial0 = &uart0; >> + }; >> + >> + chosen { >> + stdout-path = "serial0:115200n8"; >> + }; >> +}; >> + >> +&uart0 { >> + pinctrl-names = "default"; >> + pinctrl-0 = <&uart0_pins_a>; >> + status = "okay"; >> +}; >> + >> +&i2c1 { >> + pinctrl-names = "default"; >> + pinctrl-0 = <&i2c1_pins>; >> + status = "okay"; > > Schematics say this is missing an external pull-up. Has anyone tried it? > Without a pull-up any access on the i2c bus should just block. I tried it a while ago (with an older kernel), though I had an external pull-up on the device side, I think. I can give it a try again with Maxime's branch once I find this I2C test device in one of my moving boxes ;-) Do other boards providing a Raspi-compatible header have an on-board pull-up here? So will (some) hardware extensions for the Raspi fail on the Pine64? > Also this is on the RPi-2 compatible header. There's also an UART and SPI > that are standard for the RPi-2 header. We should consider enabling them > as well. Interesting topic ;-) As both interfaces can be configured for GPIO as well, I think Maxime voted to not declare them as special function in the upstream DT. UART0 is used for the console, so I guess some people may decide to use those UART2 header pins for GPIO. Similarly for SPI: if you don't need it, you get four (or five) additional GPIO. A kind of related issue arises for those BT/Wifi headers. 99.9% of the users will plug the Pine64 BT/WiFi module in there, at which point we could declare MMC1 as SDIO and UART1 as enabled to cover this. But then again nothing prevents people from building a custom module which uses those pins for something else. Port G at least does not multiplex any other IP to those pins - apart from GPIO, of course. So what is the exact policy here? In the end I think any pin (including UART0's PB8 and PB9) can be configured as GPIO, so do we make some assumptions about "sensible" or predominant usage? Does "# echo $DEVICE > /sys/devices/platform/$DEVICE/driver/unbind" work to get those pins free later in case one wants to configure them as GPIOs? In this case we may consider being more generous in declaring common use cases in the upstream DT for the sake of the majority of users. Cheers, Andre. ^ permalink raw reply [flat|nested] 35+ messages in thread
* [PATCH v2 4/4] arm64: dts: add Pine64 support @ 2016-09-12 10:11 ` Andre Przywara 0 siblings, 0 replies; 35+ messages in thread From: Andre Przywara @ 2016-09-12 10:11 UTC (permalink / raw) To: linux-arm-kernel Hi, On 10/09/16 03:33, Chen-Yu Tsai wrote: > Hi, > > On Sat, Sep 10, 2016 at 4:10 AM, Maxime Ripard > <maxime.ripard@free-electrons.com> wrote: >> From: Andre Przywara <andre.przywara@arm.com> >> >> The Pine64 is a cost-efficient development board based on the >> Allwinner A64 SoC. >> There are three models: the basic version with Fast Ethernet and >> 512 MB of DRAM (Pine64) and two Pine64+ versions, which both >> feature Gigabit Ethernet and additional connectors for touchscreens >> and a camera. Or as my son put it: "Those are smaller and these are >> missing." ;-) >> The two Pine64+ models just differ in the amount of DRAM >> (1GB vs. 2GB). Since U-Boot will figure out the right size for us and >> patches the DT accordingly we just need to provide one DT for the >> Pine64+. >> >> Signed-off-by: Andre Przywara <andre.przywara@arm.com> >> [Maxime: Removed the common DTSI and include directly the pine64 DTS] >> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> >> --- >> arch/arm64/boot/dts/Makefile | 1 + >> arch/arm64/boot/dts/allwinner/Makefile | 5 ++ >> .../boot/dts/allwinner/sun50i-a64-pine64-plus.dts | 50 ++++++++++++++++ >> .../arm64/boot/dts/allwinner/sun50i-a64-pine64.dts | 70 ++++++++++++++++++++++ >> 4 files changed, 126 insertions(+) >> create mode 100644 arch/arm64/boot/dts/allwinner/Makefile >> create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-plus.dts >> create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts >> >> diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile >> index 6e199c903676..ddcbf5a2c17e 100644 >> --- a/arch/arm64/boot/dts/Makefile >> +++ b/arch/arm64/boot/dts/Makefile >> @@ -1,4 +1,5 @@ >> dts-dirs += al >> +dts-dirs += allwinner >> dts-dirs += altera >> dts-dirs += amd >> dts-dirs += amlogic >> diff --git a/arch/arm64/boot/dts/allwinner/Makefile b/arch/arm64/boot/dts/allwinner/Makefile >> new file mode 100644 >> index 000000000000..1e29a5ae8282 >> --- /dev/null >> +++ b/arch/arm64/boot/dts/allwinner/Makefile >> @@ -0,0 +1,5 @@ >> +dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-pine64-plus.dtb sun50i-a64-pine64.dtb >> + >> +always := $(dtb-y) >> +subdir-y := $(dts-dirs) >> +clean-files := *.dtb >> diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-plus.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-plus.dts >> new file mode 100644 >> index 000000000000..790d14daaa6a >> --- /dev/null >> +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-plus.dts >> @@ -0,0 +1,50 @@ >> +/* >> + * Copyright (c) 2016 ARM Ltd. >> + * >> + * This file is dual-licensed: you can use it either under the terms >> + * of the GPL or the X11 license, at your option. Note that this dual >> + * licensing only applies to this file, and not this project as a >> + * whole. >> + * >> + * a) This library is free software; you can redistribute it and/or >> + * modify it under the terms of the GNU General Public License as >> + * published by the Free Software Foundation; either version 2 of the >> + * License, or (at your option) any later version. >> + * >> + * This library is distributed in the hope that it will be useful, >> + * but WITHOUT ANY WARRANTY; without even the implied warranty of >> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the >> + * GNU General Public License for more details. >> + * >> + * Or, alternatively, >> + * >> + * b) Permission is hereby granted, free of charge, to any person >> + * obtaining a copy of this software and associated documentation >> + * files (the "Software"), to deal in the Software without >> + * restriction, including without limitation the rights to use, >> + * copy, modify, merge, publish, distribute, sublicense, and/or >> + * sell copies of the Software, and to permit persons to whom the >> + * Software is furnished to do so, subject to the following >> + * conditions: >> + * >> + * The above copyright notice and this permission notice shall be >> + * included in all copies or substantial portions of the Software. >> + * >> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, >> + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES >> + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND >> + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT >> + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, >> + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING >> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR >> + * OTHER DEALINGS IN THE SOFTWARE. >> + */ >> + >> +#include "sun50i-a64-pine64.dts" >> + >> +/ { >> + model = "Pine64+"; >> + compatible = "pine64,pine64-plus", "allwinner,sun50i-a64"; >> + >> + /* TODO: Camera, Ethernet PHY, touchscreen, etc. */ >> +}; >> diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts >> new file mode 100644 >> index 000000000000..da9bca51f5a9 >> --- /dev/null >> +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts >> @@ -0,0 +1,70 @@ >> +/* >> + * Copyright (c) 2016 ARM Ltd. >> + * >> + * This file is dual-licensed: you can use it either under the terms >> + * of the GPL or the X11 license, at your option. Note that this dual >> + * licensing only applies to this file, and not this project as a >> + * whole. >> + * >> + * a) This library is free software; you can redistribute it and/or >> + * modify it under the terms of the GNU General Public License as >> + * published by the Free Software Foundation; either version 2 of the >> + * License, or (at your option) any later version. >> + * >> + * This library is distributed in the hope that it will be useful, >> + * but WITHOUT ANY WARRANTY; without even the implied warranty of >> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the >> + * GNU General Public License for more details. >> + * >> + * Or, alternatively, >> + * >> + * b) Permission is hereby granted, free of charge, to any person >> + * obtaining a copy of this software and associated documentation >> + * files (the "Software"), to deal in the Software without >> + * restriction, including without limitation the rights to use, >> + * copy, modify, merge, publish, distribute, sublicense, and/or >> + * sell copies of the Software, and to permit persons to whom the >> + * Software is furnished to do so, subject to the following >> + * conditions: >> + * >> + * The above copyright notice and this permission notice shall be >> + * included in all copies or substantial portions of the Software. >> + * >> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, >> + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES >> + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND >> + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT >> + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, >> + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING >> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR >> + * OTHER DEALINGS IN THE SOFTWARE. >> + */ >> + >> +/dts-v1/; >> + >> +#include "sun50i-a64.dtsi" >> + >> +/ { >> + model = "Pine64"; >> + compatible = "pine64,pine64", "allwinner,sun50i-a64"; >> + >> + aliases { >> + serial0 = &uart0; >> + }; >> + >> + chosen { >> + stdout-path = "serial0:115200n8"; >> + }; >> +}; >> + >> +&uart0 { >> + pinctrl-names = "default"; >> + pinctrl-0 = <&uart0_pins_a>; >> + status = "okay"; >> +}; >> + >> +&i2c1 { >> + pinctrl-names = "default"; >> + pinctrl-0 = <&i2c1_pins>; >> + status = "okay"; > > Schematics say this is missing an external pull-up. Has anyone tried it? > Without a pull-up any access on the i2c bus should just block. I tried it a while ago (with an older kernel), though I had an external pull-up on the device side, I think. I can give it a try again with Maxime's branch once I find this I2C test device in one of my moving boxes ;-) Do other boards providing a Raspi-compatible header have an on-board pull-up here? So will (some) hardware extensions for the Raspi fail on the Pine64? > Also this is on the RPi-2 compatible header. There's also an UART and SPI > that are standard for the RPi-2 header. We should consider enabling them > as well. Interesting topic ;-) As both interfaces can be configured for GPIO as well, I think Maxime voted to not declare them as special function in the upstream DT. UART0 is used for the console, so I guess some people may decide to use those UART2 header pins for GPIO. Similarly for SPI: if you don't need it, you get four (or five) additional GPIO. A kind of related issue arises for those BT/Wifi headers. 99.9% of the users will plug the Pine64 BT/WiFi module in there, at which point we could declare MMC1 as SDIO and UART1 as enabled to cover this. But then again nothing prevents people from building a custom module which uses those pins for something else. Port G at least does not multiplex any other IP to those pins - apart from GPIO, of course. So what is the exact policy here? In the end I think any pin (including UART0's PB8 and PB9) can be configured as GPIO, so do we make some assumptions about "sensible" or predominant usage? Does "# echo $DEVICE > /sys/devices/platform/$DEVICE/driver/unbind" work to get those pins free later in case one wants to configure them as GPIOs? In this case we may consider being more generous in declaring common use cases in the upstream DT for the sake of the majority of users. Cheers, Andre. ^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [PATCH v2 4/4] arm64: dts: add Pine64 support 2016-09-12 10:11 ` Andre Przywara @ 2016-09-19 15:14 ` Chen-Yu Tsai -1 siblings, 0 replies; 35+ messages in thread From: Chen-Yu Tsai @ 2016-09-19 15:14 UTC (permalink / raw) To: Andre Przywara Cc: Chen-Yu Tsai, Maxime Ripard, Mike Turquette, Stephen Boyd, linux-arm-kernel, linux-clk, linux-kernel, linux-sunxi On Mon, Sep 12, 2016 at 6:11 PM, Andre Przywara <andre.przywara@arm.com> wrote: > Hi, > > On 10/09/16 03:33, Chen-Yu Tsai wrote: >> Hi, >> >> On Sat, Sep 10, 2016 at 4:10 AM, Maxime Ripard >> <maxime.ripard@free-electrons.com> wrote: >>> From: Andre Przywara <andre.przywara@arm.com> >>> >>> The Pine64 is a cost-efficient development board based on the >>> Allwinner A64 SoC. >>> There are three models: the basic version with Fast Ethernet and >>> 512 MB of DRAM (Pine64) and two Pine64+ versions, which both >>> feature Gigabit Ethernet and additional connectors for touchscreens >>> and a camera. Or as my son put it: "Those are smaller and these are >>> missing." ;-) >>> The two Pine64+ models just differ in the amount of DRAM >>> (1GB vs. 2GB). Since U-Boot will figure out the right size for us and >>> patches the DT accordingly we just need to provide one DT for the >>> Pine64+. >>> >>> Signed-off-by: Andre Przywara <andre.przywara@arm.com> >>> [Maxime: Removed the common DTSI and include directly the pine64 DTS] >>> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> >>> --- >>> arch/arm64/boot/dts/Makefile | 1 + >>> arch/arm64/boot/dts/allwinner/Makefile | 5 ++ >>> .../boot/dts/allwinner/sun50i-a64-pine64-plus.dts | 50 ++++++++++++++++ >>> .../arm64/boot/dts/allwinner/sun50i-a64-pine64.dts | 70 ++++++++++++++++++++++ >>> 4 files changed, 126 insertions(+) >>> create mode 100644 arch/arm64/boot/dts/allwinner/Makefile >>> create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-plus.dts >>> create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts >>> >>> diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile >>> index 6e199c903676..ddcbf5a2c17e 100644 >>> --- a/arch/arm64/boot/dts/Makefile >>> +++ b/arch/arm64/boot/dts/Makefile >>> @@ -1,4 +1,5 @@ >>> dts-dirs += al >>> +dts-dirs += allwinner >>> dts-dirs += altera >>> dts-dirs += amd >>> dts-dirs += amlogic >>> diff --git a/arch/arm64/boot/dts/allwinner/Makefile b/arch/arm64/boot/dts/allwinner/Makefile >>> new file mode 100644 >>> index 000000000000..1e29a5ae8282 >>> --- /dev/null >>> +++ b/arch/arm64/boot/dts/allwinner/Makefile >>> @@ -0,0 +1,5 @@ >>> +dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-pine64-plus.dtb sun50i-a64-pine64.dtb >>> + >>> +always := $(dtb-y) >>> +subdir-y := $(dts-dirs) >>> +clean-files := *.dtb >>> diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-plus.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-plus.dts >>> new file mode 100644 >>> index 000000000000..790d14daaa6a >>> --- /dev/null >>> +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-plus.dts >>> @@ -0,0 +1,50 @@ >>> +/* >>> + * Copyright (c) 2016 ARM Ltd. >>> + * >>> + * This file is dual-licensed: you can use it either under the terms >>> + * of the GPL or the X11 license, at your option. Note that this dual >>> + * licensing only applies to this file, and not this project as a >>> + * whole. >>> + * >>> + * a) This library is free software; you can redistribute it and/or >>> + * modify it under the terms of the GNU General Public License as >>> + * published by the Free Software Foundation; either version 2 of the >>> + * License, or (at your option) any later version. >>> + * >>> + * This library is distributed in the hope that it will be useful, >>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of >>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the >>> + * GNU General Public License for more details. >>> + * >>> + * Or, alternatively, >>> + * >>> + * b) Permission is hereby granted, free of charge, to any person >>> + * obtaining a copy of this software and associated documentation >>> + * files (the "Software"), to deal in the Software without >>> + * restriction, including without limitation the rights to use, >>> + * copy, modify, merge, publish, distribute, sublicense, and/or >>> + * sell copies of the Software, and to permit persons to whom the >>> + * Software is furnished to do so, subject to the following >>> + * conditions: >>> + * >>> + * The above copyright notice and this permission notice shall be >>> + * included in all copies or substantial portions of the Software. >>> + * >>> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, >>> + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES >>> + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND >>> + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT >>> + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, >>> + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING >>> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR >>> + * OTHER DEALINGS IN THE SOFTWARE. >>> + */ >>> + >>> +#include "sun50i-a64-pine64.dts" >>> + >>> +/ { >>> + model = "Pine64+"; >>> + compatible = "pine64,pine64-plus", "allwinner,sun50i-a64"; >>> + >>> + /* TODO: Camera, Ethernet PHY, touchscreen, etc. */ >>> +}; >>> diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts >>> new file mode 100644 >>> index 000000000000..da9bca51f5a9 >>> --- /dev/null >>> +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts >>> @@ -0,0 +1,70 @@ >>> +/* >>> + * Copyright (c) 2016 ARM Ltd. >>> + * >>> + * This file is dual-licensed: you can use it either under the terms >>> + * of the GPL or the X11 license, at your option. Note that this dual >>> + * licensing only applies to this file, and not this project as a >>> + * whole. >>> + * >>> + * a) This library is free software; you can redistribute it and/or >>> + * modify it under the terms of the GNU General Public License as >>> + * published by the Free Software Foundation; either version 2 of the >>> + * License, or (at your option) any later version. >>> + * >>> + * This library is distributed in the hope that it will be useful, >>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of >>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the >>> + * GNU General Public License for more details. >>> + * >>> + * Or, alternatively, >>> + * >>> + * b) Permission is hereby granted, free of charge, to any person >>> + * obtaining a copy of this software and associated documentation >>> + * files (the "Software"), to deal in the Software without >>> + * restriction, including without limitation the rights to use, >>> + * copy, modify, merge, publish, distribute, sublicense, and/or >>> + * sell copies of the Software, and to permit persons to whom the >>> + * Software is furnished to do so, subject to the following >>> + * conditions: >>> + * >>> + * The above copyright notice and this permission notice shall be >>> + * included in all copies or substantial portions of the Software. >>> + * >>> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, >>> + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES >>> + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND >>> + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT >>> + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, >>> + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING >>> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR >>> + * OTHER DEALINGS IN THE SOFTWARE. >>> + */ >>> + >>> +/dts-v1/; >>> + >>> +#include "sun50i-a64.dtsi" >>> + >>> +/ { >>> + model = "Pine64"; >>> + compatible = "pine64,pine64", "allwinner,sun50i-a64"; >>> + >>> + aliases { >>> + serial0 = &uart0; >>> + }; >>> + >>> + chosen { >>> + stdout-path = "serial0:115200n8"; >>> + }; >>> +}; >>> + >>> +&uart0 { >>> + pinctrl-names = "default"; >>> + pinctrl-0 = <&uart0_pins_a>; >>> + status = "okay"; >>> +}; >>> + >>> +&i2c1 { >>> + pinctrl-names = "default"; >>> + pinctrl-0 = <&i2c1_pins>; >>> + status = "okay"; >> >> Schematics say this is missing an external pull-up. Has anyone tried it? >> Without a pull-up any access on the i2c bus should just block. > > I tried it a while ago (with an older kernel), though I had an external > pull-up on the device side, I think. I can give it a try again with > Maxime's branch once I find this I2C test device in one of my moving > boxes ;-) > > Do other boards providing a Raspi-compatible header have an on-board > pull-up here? So will (some) hardware extensions for the Raspi fail on > the Pine64? IIRC The Bananapi series have pull-ups on the default I2C pins. >> Also this is on the RPi-2 compatible header. There's also an UART and SPI >> that are standard for the RPi-2 header. We should consider enabling them >> as well. > > Interesting topic ;-) > As both interfaces can be configured for GPIO as well, I think Maxime > voted to not declare them as special function in the upstream DT. > UART0 is used for the console, so I guess some people may decide to use > those UART2 header pins for GPIO. Similarly for SPI: if you don't need > it, you get four (or five) additional GPIO. > > A kind of related issue arises for those BT/Wifi headers. 99.9% of the > users will plug the Pine64 BT/WiFi module in there, at which point we > could declare MMC1 as SDIO and UART1 as enabled to cover this. > But then again nothing prevents people from building a custom module > which uses those pins for something else. Port G at least does not > multiplex any other IP to those pins - apart from GPIO, of course. > > So what is the exact policy here? In the end I think any pin (including > UART0's PB8 and PB9) can be configured as GPIO, so do we make some > assumptions about "sensible" or predominant usage? My personal position is if the vendor explicitly labeled X pin as Y peripheral, then we should enable it by default, since that is possibly what many users would be expecting. We can list, but explicitly disable, other peripherals that the vendor mentioned as optional or changeable. Obviously most pins are changeable from the SoC PoV, so my focus here is what the vendor intended. Unfortunately I've not completely worked this out with Maxime yet, and I am somewhat busy on other fronts lately. I'll be at ELCE this year, so hopefully we'll get this sorted out soon. > Does "# echo $DEVICE > /sys/devices/platform/$DEVICE/driver/unbind" work > to get those pins free later in case one wants to configure them as > GPIOs? In this case we may consider being more generous in declaring > common use cases in the upstream DT for the sake of the majority of users. I believe it does, but I've never actually tried it. Regards ChenYu ^ permalink raw reply [flat|nested] 35+ messages in thread
* [PATCH v2 4/4] arm64: dts: add Pine64 support @ 2016-09-19 15:14 ` Chen-Yu Tsai 0 siblings, 0 replies; 35+ messages in thread From: Chen-Yu Tsai @ 2016-09-19 15:14 UTC (permalink / raw) To: linux-arm-kernel On Mon, Sep 12, 2016 at 6:11 PM, Andre Przywara <andre.przywara@arm.com> wrote: > Hi, > > On 10/09/16 03:33, Chen-Yu Tsai wrote: >> Hi, >> >> On Sat, Sep 10, 2016 at 4:10 AM, Maxime Ripard >> <maxime.ripard@free-electrons.com> wrote: >>> From: Andre Przywara <andre.przywara@arm.com> >>> >>> The Pine64 is a cost-efficient development board based on the >>> Allwinner A64 SoC. >>> There are three models: the basic version with Fast Ethernet and >>> 512 MB of DRAM (Pine64) and two Pine64+ versions, which both >>> feature Gigabit Ethernet and additional connectors for touchscreens >>> and a camera. Or as my son put it: "Those are smaller and these are >>> missing." ;-) >>> The two Pine64+ models just differ in the amount of DRAM >>> (1GB vs. 2GB). Since U-Boot will figure out the right size for us and >>> patches the DT accordingly we just need to provide one DT for the >>> Pine64+. >>> >>> Signed-off-by: Andre Przywara <andre.przywara@arm.com> >>> [Maxime: Removed the common DTSI and include directly the pine64 DTS] >>> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> >>> --- >>> arch/arm64/boot/dts/Makefile | 1 + >>> arch/arm64/boot/dts/allwinner/Makefile | 5 ++ >>> .../boot/dts/allwinner/sun50i-a64-pine64-plus.dts | 50 ++++++++++++++++ >>> .../arm64/boot/dts/allwinner/sun50i-a64-pine64.dts | 70 ++++++++++++++++++++++ >>> 4 files changed, 126 insertions(+) >>> create mode 100644 arch/arm64/boot/dts/allwinner/Makefile >>> create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-plus.dts >>> create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts >>> >>> diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile >>> index 6e199c903676..ddcbf5a2c17e 100644 >>> --- a/arch/arm64/boot/dts/Makefile >>> +++ b/arch/arm64/boot/dts/Makefile >>> @@ -1,4 +1,5 @@ >>> dts-dirs += al >>> +dts-dirs += allwinner >>> dts-dirs += altera >>> dts-dirs += amd >>> dts-dirs += amlogic >>> diff --git a/arch/arm64/boot/dts/allwinner/Makefile b/arch/arm64/boot/dts/allwinner/Makefile >>> new file mode 100644 >>> index 000000000000..1e29a5ae8282 >>> --- /dev/null >>> +++ b/arch/arm64/boot/dts/allwinner/Makefile >>> @@ -0,0 +1,5 @@ >>> +dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-pine64-plus.dtb sun50i-a64-pine64.dtb >>> + >>> +always := $(dtb-y) >>> +subdir-y := $(dts-dirs) >>> +clean-files := *.dtb >>> diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-plus.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-plus.dts >>> new file mode 100644 >>> index 000000000000..790d14daaa6a >>> --- /dev/null >>> +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-plus.dts >>> @@ -0,0 +1,50 @@ >>> +/* >>> + * Copyright (c) 2016 ARM Ltd. >>> + * >>> + * This file is dual-licensed: you can use it either under the terms >>> + * of the GPL or the X11 license, at your option. Note that this dual >>> + * licensing only applies to this file, and not this project as a >>> + * whole. >>> + * >>> + * a) This library is free software; you can redistribute it and/or >>> + * modify it under the terms of the GNU General Public License as >>> + * published by the Free Software Foundation; either version 2 of the >>> + * License, or (at your option) any later version. >>> + * >>> + * This library is distributed in the hope that it will be useful, >>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of >>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the >>> + * GNU General Public License for more details. >>> + * >>> + * Or, alternatively, >>> + * >>> + * b) Permission is hereby granted, free of charge, to any person >>> + * obtaining a copy of this software and associated documentation >>> + * files (the "Software"), to deal in the Software without >>> + * restriction, including without limitation the rights to use, >>> + * copy, modify, merge, publish, distribute, sublicense, and/or >>> + * sell copies of the Software, and to permit persons to whom the >>> + * Software is furnished to do so, subject to the following >>> + * conditions: >>> + * >>> + * The above copyright notice and this permission notice shall be >>> + * included in all copies or substantial portions of the Software. >>> + * >>> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, >>> + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES >>> + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND >>> + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT >>> + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, >>> + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING >>> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR >>> + * OTHER DEALINGS IN THE SOFTWARE. >>> + */ >>> + >>> +#include "sun50i-a64-pine64.dts" >>> + >>> +/ { >>> + model = "Pine64+"; >>> + compatible = "pine64,pine64-plus", "allwinner,sun50i-a64"; >>> + >>> + /* TODO: Camera, Ethernet PHY, touchscreen, etc. */ >>> +}; >>> diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts >>> new file mode 100644 >>> index 000000000000..da9bca51f5a9 >>> --- /dev/null >>> +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts >>> @@ -0,0 +1,70 @@ >>> +/* >>> + * Copyright (c) 2016 ARM Ltd. >>> + * >>> + * This file is dual-licensed: you can use it either under the terms >>> + * of the GPL or the X11 license, at your option. Note that this dual >>> + * licensing only applies to this file, and not this project as a >>> + * whole. >>> + * >>> + * a) This library is free software; you can redistribute it and/or >>> + * modify it under the terms of the GNU General Public License as >>> + * published by the Free Software Foundation; either version 2 of the >>> + * License, or (at your option) any later version. >>> + * >>> + * This library is distributed in the hope that it will be useful, >>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of >>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the >>> + * GNU General Public License for more details. >>> + * >>> + * Or, alternatively, >>> + * >>> + * b) Permission is hereby granted, free of charge, to any person >>> + * obtaining a copy of this software and associated documentation >>> + * files (the "Software"), to deal in the Software without >>> + * restriction, including without limitation the rights to use, >>> + * copy, modify, merge, publish, distribute, sublicense, and/or >>> + * sell copies of the Software, and to permit persons to whom the >>> + * Software is furnished to do so, subject to the following >>> + * conditions: >>> + * >>> + * The above copyright notice and this permission notice shall be >>> + * included in all copies or substantial portions of the Software. >>> + * >>> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, >>> + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES >>> + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND >>> + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT >>> + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, >>> + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING >>> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR >>> + * OTHER DEALINGS IN THE SOFTWARE. >>> + */ >>> + >>> +/dts-v1/; >>> + >>> +#include "sun50i-a64.dtsi" >>> + >>> +/ { >>> + model = "Pine64"; >>> + compatible = "pine64,pine64", "allwinner,sun50i-a64"; >>> + >>> + aliases { >>> + serial0 = &uart0; >>> + }; >>> + >>> + chosen { >>> + stdout-path = "serial0:115200n8"; >>> + }; >>> +}; >>> + >>> +&uart0 { >>> + pinctrl-names = "default"; >>> + pinctrl-0 = <&uart0_pins_a>; >>> + status = "okay"; >>> +}; >>> + >>> +&i2c1 { >>> + pinctrl-names = "default"; >>> + pinctrl-0 = <&i2c1_pins>; >>> + status = "okay"; >> >> Schematics say this is missing an external pull-up. Has anyone tried it? >> Without a pull-up any access on the i2c bus should just block. > > I tried it a while ago (with an older kernel), though I had an external > pull-up on the device side, I think. I can give it a try again with > Maxime's branch once I find this I2C test device in one of my moving > boxes ;-) > > Do other boards providing a Raspi-compatible header have an on-board > pull-up here? So will (some) hardware extensions for the Raspi fail on > the Pine64? IIRC The Bananapi series have pull-ups on the default I2C pins. >> Also this is on the RPi-2 compatible header. There's also an UART and SPI >> that are standard for the RPi-2 header. We should consider enabling them >> as well. > > Interesting topic ;-) > As both interfaces can be configured for GPIO as well, I think Maxime > voted to not declare them as special function in the upstream DT. > UART0 is used for the console, so I guess some people may decide to use > those UART2 header pins for GPIO. Similarly for SPI: if you don't need > it, you get four (or five) additional GPIO. > > A kind of related issue arises for those BT/Wifi headers. 99.9% of the > users will plug the Pine64 BT/WiFi module in there, at which point we > could declare MMC1 as SDIO and UART1 as enabled to cover this. > But then again nothing prevents people from building a custom module > which uses those pins for something else. Port G at least does not > multiplex any other IP to those pins - apart from GPIO, of course. > > So what is the exact policy here? In the end I think any pin (including > UART0's PB8 and PB9) can be configured as GPIO, so do we make some > assumptions about "sensible" or predominant usage? My personal position is if the vendor explicitly labeled X pin as Y peripheral, then we should enable it by default, since that is possibly what many users would be expecting. We can list, but explicitly disable, other peripherals that the vendor mentioned as optional or changeable. Obviously most pins are changeable from the SoC PoV, so my focus here is what the vendor intended. Unfortunately I've not completely worked this out with Maxime yet, and I am somewhat busy on other fronts lately. I'll be at ELCE this year, so hopefully we'll get this sorted out soon. > Does "# echo $DEVICE > /sys/devices/platform/$DEVICE/driver/unbind" work > to get those pins free later in case one wants to configure them as > GPIOs? In this case we may consider being more generous in declaring > common use cases in the upstream DT for the sake of the majority of users. I believe it does, but I've never actually tried it. Regards ChenYu ^ permalink raw reply [flat|nested] 35+ messages in thread
end of thread, other threads:[~2016-09-19 15:15 UTC | newest] Thread overview: 35+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2016-09-09 20:10 [PATCH v2 0/4] arm64: Allwinner A64 support based on sunxi-ng Maxime Ripard 2016-09-09 20:10 ` Maxime Ripard 2016-09-09 20:10 ` [PATCH v2 1/4] clk: sunxi-ng: Add A64 clocks Maxime Ripard 2016-09-09 20:10 ` Maxime Ripard 2016-09-10 3:24 ` Chen-Yu Tsai 2016-09-10 3:24 ` Chen-Yu Tsai 2016-09-17 14:08 ` Maxime Ripard 2016-09-17 14:08 ` Maxime Ripard 2016-09-14 21:45 ` Stephen Boyd 2016-09-14 21:45 ` Stephen Boyd 2016-09-17 14:23 ` Maxime Ripard 2016-09-17 14:23 ` Maxime Ripard 2016-09-09 20:10 ` [PATCH v2 2/4] Documentation: devicetree: add vendor prefix for Pine64 Maxime Ripard 2016-09-09 20:10 ` Maxime Ripard 2016-09-10 1:54 ` Chen-Yu Tsai 2016-09-10 1:54 ` Chen-Yu Tsai 2016-09-09 20:10 ` [PATCH v2 3/4] arm64: dts: add Allwinner A64 SoC .dtsi Maxime Ripard 2016-09-09 20:10 ` Maxime Ripard 2016-09-10 2:21 ` Chen-Yu Tsai 2016-09-10 2:21 ` Chen-Yu Tsai 2016-09-10 2:21 ` Chen-Yu Tsai 2016-09-15 0:08 ` André Przywara 2016-09-15 0:08 ` André Przywara 2016-09-17 14:51 ` Maxime Ripard 2016-09-17 14:51 ` Maxime Ripard 2016-09-18 1:21 ` Icenowy Zheng 2016-09-18 1:21 ` Icenowy Zheng 2016-09-09 20:10 ` [PATCH v2 4/4] arm64: dts: add Pine64 support Maxime Ripard 2016-09-09 20:10 ` Maxime Ripard 2016-09-10 2:33 ` Chen-Yu Tsai 2016-09-10 2:33 ` Chen-Yu Tsai 2016-09-12 10:11 ` Andre Przywara 2016-09-12 10:11 ` Andre Przywara 2016-09-19 15:14 ` Chen-Yu Tsai 2016-09-19 15:14 ` Chen-Yu Tsai
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