[PATCH 0/3] xilinx: Swith platforms to DM_ETH_PHY

[PATCH 0/3] xilinx: Swith platforms to DM_ETH_PHY

[Michal Simek]

This patch series adds support for shared MDIO by using generic phy
framework. Also enable DM_ETH_PHY config for all xilinx platforms.

Thanks,
Michal


T Karthik Reddy (3):
  net: xilinx: axi_emac: Use shared MDIO bus support for axi emac driver
  net: xilinx: axi_emaclite: Use shared MDIO bus support for axi
    emaclite driver
  xilinx: Add CONFIG_DM_ETH_PHY config

 configs/microblaze-generic_defconfig |  1 +
 configs/xilinx_versal_virt_defconfig |  1 +
 configs/xilinx_zynq_virt_defconfig   |  1 +
 configs/xilinx_zynqmp_virt_defconfig |  1 +
 drivers/net/xilinx_axi_emac.c        | 38 ++++++++++++++++--------
 drivers/net/xilinx_emaclite.c        | 43 ++++++++++++++++++----------
 6 files changed, 58 insertions(+), 27 deletions(-)

-- 
2.36.0

[PATCH 1/3] net: xilinx: axi_emac: Use shared MDIO bus support for axi emac driver

[Michal Simek]

From: T Karthik Reddy <t.karthik.reddy@xilinx.com>

CONFIG_DM_ETH_PHY enables support to utilize generic ethernet phy
framework. Though if ethernet PHY node is in other ethernet node, it
will use shared MDIO to access the PHY of other ethernet. Move ethernet
print info statement from plat function to probe function, as phyaddr is
not enumerated when CONFIG_DM_ETH_PHY is enabled.

Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
---

 drivers/net/xilinx_axi_emac.c | 38 ++++++++++++++++++++++++-----------
 1 file changed, 26 insertions(+), 12 deletions(-)

diff --git a/drivers/net/xilinx_axi_emac.c b/drivers/net/xilinx_axi_emac.c
index a4715735c3c4..04277b1269f3 100644
--- a/drivers/net/xilinx_axi_emac.c
+++ b/drivers/net/xilinx_axi_emac.c
@@ -19,6 +19,7 @@
 #include <miiphy.h>
 #include <wait_bit.h>
 #include <linux/delay.h>
+#include <eth_phy.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -295,6 +296,9 @@ static int axiemac_phy_init(struct udevice *dev)
 	/* Set default MDIO divisor */
 	writel(XAE_MDIO_DIV_DFT | XAE_MDIO_MC_MDIOEN_MASK, &regs->mdio_mc);
 
+	if (IS_ENABLED(CONFIG_DM_ETH_PHY))
+		priv->phyaddr = eth_phy_get_addr(dev);
+
 	if (priv->phyaddr == -1) {
 		/* Detect the PHY address */
 		for (i = 31; i >= 0; i--) {
@@ -778,18 +782,29 @@ static int axi_emac_probe(struct udevice *dev)
 		priv->phy_of_handle = plat->phy_of_handle;
 		priv->interface = pdata->phy_interface;
 
-		priv->bus = mdio_alloc();
-		priv->bus->read = axiemac_miiphy_read;
-		priv->bus->write = axiemac_miiphy_write;
-		priv->bus->priv = priv;
+		if (IS_ENABLED(CONFIG_DM_ETH_PHY))
+			priv->bus = eth_phy_get_mdio_bus(dev);
 
-		ret = mdio_register_seq(priv->bus, dev_seq(dev));
-		if (ret)
-			return ret;
+		if (!priv->bus) {
+			priv->bus = mdio_alloc();
+			priv->bus->read = axiemac_miiphy_read;
+			priv->bus->write = axiemac_miiphy_write;
+			priv->bus->priv = priv;
+
+			ret = mdio_register_seq(priv->bus, dev_seq(dev));
+			if (ret)
+				return ret;
+		}
+
+		if (IS_ENABLED(CONFIG_DM_ETH_PHY))
+			eth_phy_set_mdio_bus(dev, priv->bus);
 
 		axiemac_phy_init(dev);
 	}
 
+	printf("AXI EMAC: %lx, phyaddr %d, interface %s\n", (ulong)pdata->iobase,
+	       priv->phyaddr, phy_string_for_interface(pdata->phy_interface));
+
 	return 0;
 }
 
@@ -844,8 +859,10 @@ static int axi_emac_of_to_plat(struct udevice *dev)
 		offset = fdtdec_lookup_phandle(gd->fdt_blob, node,
 					       "phy-handle");
 		if (offset > 0) {
-			plat->phyaddr = fdtdec_get_int(gd->fdt_blob, offset,
-						       "reg", -1);
+			if (!(IS_ENABLED(CONFIG_DM_ETH_PHY)))
+				plat->phyaddr = fdtdec_get_int(gd->fdt_blob,
+							       offset,
+							       "reg", -1);
 			plat->phy_of_handle = offset;
 		}
 
@@ -857,9 +874,6 @@ static int axi_emac_of_to_plat(struct udevice *dev)
 						     "xlnx,eth-hasnobuf");
 	}
 
-	printf("AXI EMAC: %lx, phyaddr %d, interface %s\n", (ulong)pdata->iobase,
-	       plat->phyaddr, phy_string_for_interface(pdata->phy_interface));
-
 	return 0;
 }
 
-- 
2.36.0

[PATCH 2/3] net: xilinx: axi_emaclite: Use shared MDIO bus support for axi emaclite driver

[Michal Simek]

From: T Karthik Reddy <t.karthik.reddy@xilinx.com>

CONFIG_DM_ETH_PHY enables support to utilize generic ethernet phy
framework. Though if ethernet PHY node is in other ethernet node, it
will use shared MDIO to access the PHY of other ethernet. Move ethernet
print info statement from plat function to probe function, as phyaddr is
not enumerated when CONFIG_DM_ETH_PHY is enabled.

Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
---

 drivers/net/xilinx_emaclite.c | 43 +++++++++++++++++++++++------------
 1 file changed, 28 insertions(+), 15 deletions(-)

diff --git a/drivers/net/xilinx_emaclite.c b/drivers/net/xilinx_emaclite.c
index 43fc36dc6a82..6c9f1f7c2728 100644
--- a/drivers/net/xilinx_emaclite.c
+++ b/drivers/net/xilinx_emaclite.c
@@ -22,6 +22,7 @@
 #include <linux/errno.h>
 #include <linux/kernel.h>
 #include <asm/io.h>
+#include <eth_phy.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -564,14 +565,27 @@ static int emaclite_probe(struct udevice *dev)
 	struct xemaclite *emaclite = dev_get_priv(dev);
 	int ret;
 
-	emaclite->bus = mdio_alloc();
-	emaclite->bus->read = emaclite_miiphy_read;
-	emaclite->bus->write = emaclite_miiphy_write;
-	emaclite->bus->priv = emaclite;
+	if (IS_ENABLED(CONFIG_DM_ETH_PHY))
+		emaclite->bus = eth_phy_get_mdio_bus(dev);
 
-	ret = mdio_register_seq(emaclite->bus, dev_seq(dev));
-	if (ret)
-		return ret;
+	if (!emaclite->bus) {
+		emaclite->bus = mdio_alloc();
+		emaclite->bus->read = emaclite_miiphy_read;
+		emaclite->bus->write = emaclite_miiphy_write;
+		emaclite->bus->priv = emaclite;
+
+		ret = mdio_register_seq(emaclite->bus, dev_seq(dev));
+		if (ret)
+			return ret;
+	}
+
+	if (IS_ENABLED(CONFIG_DM_ETH_PHY)) {
+		eth_phy_set_mdio_bus(dev, emaclite->bus);
+		emaclite->phyaddr = eth_phy_get_addr(dev);
+	}
+
+	printf("EMACLITE: %lx, phyaddr %d, %d/%d\n", (ulong)emaclite->regs,
+	       emaclite->phyaddr, emaclite->txpp, emaclite->rxpp);
 
 	return 0;
 }
@@ -606,20 +620,19 @@ static int emaclite_of_to_plat(struct udevice *dev)
 
 	emaclite->phyaddr = -1;
 
-	offset = fdtdec_lookup_phandle(gd->fdt_blob, dev_of_offset(dev),
-				      "phy-handle");
-	if (offset > 0)
-		emaclite->phyaddr = fdtdec_get_int(gd->fdt_blob, offset,
-						   "reg", -1);
+	if (!(IS_ENABLED(CONFIG_DM_ETH_PHY))) {
+		offset = fdtdec_lookup_phandle(gd->fdt_blob, dev_of_offset(dev),
+					       "phy-handle");
+		if (offset > 0)
+			emaclite->phyaddr = fdtdec_get_int(gd->fdt_blob,
+							   offset, "reg", -1);
+	}
 
 	emaclite->txpp = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
 					"xlnx,tx-ping-pong", 0);
 	emaclite->rxpp = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
 					"xlnx,rx-ping-pong", 0);
 
-	printf("EMACLITE: %lx, phyaddr %d, %d/%d\n", (ulong)emaclite->regs,
-	       emaclite->phyaddr, emaclite->txpp, emaclite->rxpp);
-
 	return 0;
 }
 
-- 
2.36.0

[PATCH 3/3] xilinx: Add CONFIG_DM_ETH_PHY config

[Michal Simek]

From: T Karthik Reddy <t.karthik.reddy@xilinx.com>

Enable CONFIG_DM_ETH_PHY to utilize shared MDIO bus support on all xilinx
platforms.

Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
---

 configs/microblaze-generic_defconfig | 1 +
 configs/xilinx_versal_virt_defconfig | 1 +
 configs/xilinx_zynq_virt_defconfig   | 1 +
 configs/xilinx_zynqmp_virt_defconfig | 1 +
 4 files changed, 4 insertions(+)

diff --git a/configs/microblaze-generic_defconfig b/configs/microblaze-generic_defconfig
index 3142b469c26b..7994110b28a7 100644
--- a/configs/microblaze-generic_defconfig
+++ b/configs/microblaze-generic_defconfig
@@ -76,6 +76,7 @@ CONFIG_PHY_NATSEMI=y
 CONFIG_PHY_REALTEK=y
 CONFIG_PHY_VITESSE=y
 CONFIG_DM_ETH=y
+CONFIG_DM_ETH_PHY=y
 CONFIG_XILINX_AXIEMAC=y
 CONFIG_XILINX_EMACLITE=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/xilinx_versal_virt_defconfig b/configs/xilinx_versal_virt_defconfig
index 38747ffd02cb..c9ae0185f8ad 100644
--- a/configs/xilinx_versal_virt_defconfig
+++ b/configs/xilinx_versal_virt_defconfig
@@ -92,6 +92,7 @@ CONFIG_PHY_REALTEK=y
 CONFIG_PHY_TI_DP83867=y
 CONFIG_PHY_VITESSE=y
 CONFIG_PHY_FIXED=y
+CONFIG_DM_ETH_PHY=y
 CONFIG_PHY_GIGE=y
 CONFIG_XILINX_AXIEMAC=y
 CONFIG_XILINX_AXIMRMAC=y
diff --git a/configs/xilinx_zynq_virt_defconfig b/configs/xilinx_zynq_virt_defconfig
index 1f3e6a42a146..120bc29393d8 100644
--- a/configs/xilinx_zynq_virt_defconfig
+++ b/configs/xilinx_zynq_virt_defconfig
@@ -111,6 +111,7 @@ CONFIG_PHY_MICREL=y
 CONFIG_PHY_MICREL_KSZ90X1=y
 CONFIG_PHY_REALTEK=y
 CONFIG_PHY_XILINX=y
+CONFIG_DM_ETH_PHY=y
 CONFIG_MII=y
 CONFIG_ZYNQ_GEM=y
 CONFIG_ARM_DCC=y
diff --git a/configs/xilinx_zynqmp_virt_defconfig b/configs/xilinx_zynqmp_virt_defconfig
index 35894076c52f..abaebb8edaf2 100644
--- a/configs/xilinx_zynqmp_virt_defconfig
+++ b/configs/xilinx_zynqmp_virt_defconfig
@@ -160,6 +160,7 @@ CONFIG_PHY_TI_DP83867=y
 CONFIG_PHY_VITESSE=y
 CONFIG_PHY_XILINX_GMII2RGMII=y
 CONFIG_PHY_FIXED=y
+CONFIG_DM_ETH_PHY=y
 CONFIG_XILINX_AXIEMAC=y
 CONFIG_ZYNQ_GEM=y
 CONFIG_DM_REGULATOR=y
-- 
2.36.0

RE: [PATCH 0/3] xilinx: Swith platforms to DM_ETH_PHY

[Ashok Reddy Soma]

Acked-for-series: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>

Thanks,
Ashok

> -----Original Message-----
> From: U-Boot <u-boot-bounces@lists.denx.de> On Behalf Of Michal Simek
> Sent: Tuesday, May 10, 2022 4:56 PM
> To: u-boot@lists.denx.de; git <git@xilinx.com>
> Cc: Joe Hershberger <joe.hershberger@ni.com>; Ramon Fried
> <rfried.dev@gmail.com>
> Subject: [PATCH 0/3] xilinx: Swith platforms to DM_ETH_PHY
> 
> 
> This patch series adds support for shared MDIO by using generic phy
> framework. Also enable DM_ETH_PHY config for all xilinx platforms.
> 
> Thanks,
> Michal
> 
> 
> T Karthik Reddy (3):
>   net: xilinx: axi_emac: Use shared MDIO bus support for axi emac driver
>   net: xilinx: axi_emaclite: Use shared MDIO bus support for axi
>     emaclite driver
>   xilinx: Add CONFIG_DM_ETH_PHY config
> 
>  configs/microblaze-generic_defconfig |  1 +
> configs/xilinx_versal_virt_defconfig |  1 +
>  configs/xilinx_zynq_virt_defconfig   |  1 +
>  configs/xilinx_zynqmp_virt_defconfig |  1 +
>  drivers/net/xilinx_axi_emac.c        | 38 ++++++++++++++++--------
>  drivers/net/xilinx_emaclite.c        | 43 ++++++++++++++++++----------
>  6 files changed, 58 insertions(+), 27 deletions(-)
> 
> --
> 2.36.0

Re: [PATCH 1/3] net: xilinx: axi_emac: Use shared MDIO bus support for axi emac driver

[Ramon Fried]

On Tue, May 10, 2022 at 2:26 PM Michal Simek <monstr@monstr.eu> wrote:
>
> From: T Karthik Reddy <t.karthik.reddy@xilinx.com>
>
> CONFIG_DM_ETH_PHY enables support to utilize generic ethernet phy
> framework. Though if ethernet PHY node is in other ethernet node, it
> will use shared MDIO to access the PHY of other ethernet. Move ethernet
> print info statement from plat function to probe function, as phyaddr is
> not enumerated when CONFIG_DM_ETH_PHY is enabled.
>
> Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
> Signed-off-by: Michal Simek <michal.simek@amd.com>
> ---
>
>  drivers/net/xilinx_axi_emac.c | 38 ++++++++++++++++++++++++-----------
>  1 file changed, 26 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/net/xilinx_axi_emac.c b/drivers/net/xilinx_axi_emac.c
> index a4715735c3c4..04277b1269f3 100644
> --- a/drivers/net/xilinx_axi_emac.c
> +++ b/drivers/net/xilinx_axi_emac.c
> @@ -19,6 +19,7 @@
>  #include <miiphy.h>
>  #include <wait_bit.h>
>  #include <linux/delay.h>
> +#include <eth_phy.h>
>
>  DECLARE_GLOBAL_DATA_PTR;
>
> @@ -295,6 +296,9 @@ static int axiemac_phy_init(struct udevice *dev)
>         /* Set default MDIO divisor */
>         writel(XAE_MDIO_DIV_DFT | XAE_MDIO_MC_MDIOEN_MASK, &regs->mdio_mc);
>
> +       if (IS_ENABLED(CONFIG_DM_ETH_PHY))
> +               priv->phyaddr = eth_phy_get_addr(dev);
> +
>         if (priv->phyaddr == -1) {
>                 /* Detect the PHY address */
>                 for (i = 31; i >= 0; i--) {
> @@ -778,18 +782,29 @@ static int axi_emac_probe(struct udevice *dev)
>                 priv->phy_of_handle = plat->phy_of_handle;
>                 priv->interface = pdata->phy_interface;
>
> -               priv->bus = mdio_alloc();
> -               priv->bus->read = axiemac_miiphy_read;
> -               priv->bus->write = axiemac_miiphy_write;
> -               priv->bus->priv = priv;
> +               if (IS_ENABLED(CONFIG_DM_ETH_PHY))
> +                       priv->bus = eth_phy_get_mdio_bus(dev);
>
> -               ret = mdio_register_seq(priv->bus, dev_seq(dev));
> -               if (ret)
> -                       return ret;
> +               if (!priv->bus) {
> +                       priv->bus = mdio_alloc();
> +                       priv->bus->read = axiemac_miiphy_read;
> +                       priv->bus->write = axiemac_miiphy_write;
> +                       priv->bus->priv = priv;
> +
> +                       ret = mdio_register_seq(priv->bus, dev_seq(dev));
> +                       if (ret)
> +                               return ret;
> +               }
> +
> +               if (IS_ENABLED(CONFIG_DM_ETH_PHY))
> +                       eth_phy_set_mdio_bus(dev, priv->bus);
>
>                 axiemac_phy_init(dev);
>         }
>
> +       printf("AXI EMAC: %lx, phyaddr %d, interface %s\n", (ulong)pdata->iobase,
> +              priv->phyaddr, phy_string_for_interface(pdata->phy_interface));
> +
>         return 0;
>  }
>
> @@ -844,8 +859,10 @@ static int axi_emac_of_to_plat(struct udevice *dev)
>                 offset = fdtdec_lookup_phandle(gd->fdt_blob, node,
>                                                "phy-handle");
>                 if (offset > 0) {
> -                       plat->phyaddr = fdtdec_get_int(gd->fdt_blob, offset,
> -                                                      "reg", -1);
> +                       if (!(IS_ENABLED(CONFIG_DM_ETH_PHY)))
> +                               plat->phyaddr = fdtdec_get_int(gd->fdt_blob,
> +                                                              offset,
> +                                                              "reg", -1);
>                         plat->phy_of_handle = offset;
>                 }
>
> @@ -857,9 +874,6 @@ static int axi_emac_of_to_plat(struct udevice *dev)
>                                                      "xlnx,eth-hasnobuf");
>         }
>
> -       printf("AXI EMAC: %lx, phyaddr %d, interface %s\n", (ulong)pdata->iobase,
> -              plat->phyaddr, phy_string_for_interface(pdata->phy_interface));
> -
>         return 0;
>  }
>
> --
> 2.36.0
>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>

Re: [PATCH 2/3] net: xilinx: axi_emaclite: Use shared MDIO bus support for axi emaclite driver

[Ramon Fried]

On Tue, May 10, 2022 at 2:26 PM Michal Simek <monstr@monstr.eu> wrote:
>
> From: T Karthik Reddy <t.karthik.reddy@xilinx.com>
>
> CONFIG_DM_ETH_PHY enables support to utilize generic ethernet phy
> framework. Though if ethernet PHY node is in other ethernet node, it
> will use shared MDIO to access the PHY of other ethernet. Move ethernet
> print info statement from plat function to probe function, as phyaddr is
> not enumerated when CONFIG_DM_ETH_PHY is enabled.
>
> Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
> Signed-off-by: Michal Simek <michal.simek@amd.com>
> ---
>
>  drivers/net/xilinx_emaclite.c | 43 +++++++++++++++++++++++------------
>  1 file changed, 28 insertions(+), 15 deletions(-)
>
> diff --git a/drivers/net/xilinx_emaclite.c b/drivers/net/xilinx_emaclite.c
> index 43fc36dc6a82..6c9f1f7c2728 100644
> --- a/drivers/net/xilinx_emaclite.c
> +++ b/drivers/net/xilinx_emaclite.c
> @@ -22,6 +22,7 @@
>  #include <linux/errno.h>
>  #include <linux/kernel.h>
>  #include <asm/io.h>
> +#include <eth_phy.h>
>
>  DECLARE_GLOBAL_DATA_PTR;
>
> @@ -564,14 +565,27 @@ static int emaclite_probe(struct udevice *dev)
>         struct xemaclite *emaclite = dev_get_priv(dev);
>         int ret;
>
> -       emaclite->bus = mdio_alloc();
> -       emaclite->bus->read = emaclite_miiphy_read;
> -       emaclite->bus->write = emaclite_miiphy_write;
> -       emaclite->bus->priv = emaclite;
> +       if (IS_ENABLED(CONFIG_DM_ETH_PHY))
> +               emaclite->bus = eth_phy_get_mdio_bus(dev);
>
> -       ret = mdio_register_seq(emaclite->bus, dev_seq(dev));
> -       if (ret)
> -               return ret;
> +       if (!emaclite->bus) {
> +               emaclite->bus = mdio_alloc();
> +               emaclite->bus->read = emaclite_miiphy_read;
> +               emaclite->bus->write = emaclite_miiphy_write;
> +               emaclite->bus->priv = emaclite;
> +
> +               ret = mdio_register_seq(emaclite->bus, dev_seq(dev));
> +               if (ret)
> +                       return ret;
> +       }
> +
> +       if (IS_ENABLED(CONFIG_DM_ETH_PHY)) {
> +               eth_phy_set_mdio_bus(dev, emaclite->bus);
> +               emaclite->phyaddr = eth_phy_get_addr(dev);
> +       }
> +
> +       printf("EMACLITE: %lx, phyaddr %d, %d/%d\n", (ulong)emaclite->regs,
> +              emaclite->phyaddr, emaclite->txpp, emaclite->rxpp);
>
>         return 0;
>  }
> @@ -606,20 +620,19 @@ static int emaclite_of_to_plat(struct udevice *dev)
>
>         emaclite->phyaddr = -1;
>
> -       offset = fdtdec_lookup_phandle(gd->fdt_blob, dev_of_offset(dev),
> -                                     "phy-handle");
> -       if (offset > 0)
> -               emaclite->phyaddr = fdtdec_get_int(gd->fdt_blob, offset,
> -                                                  "reg", -1);
> +       if (!(IS_ENABLED(CONFIG_DM_ETH_PHY))) {
> +               offset = fdtdec_lookup_phandle(gd->fdt_blob, dev_of_offset(dev),
> +                                              "phy-handle");
> +               if (offset > 0)
> +                       emaclite->phyaddr = fdtdec_get_int(gd->fdt_blob,
> +                                                          offset, "reg", -1);
> +       }
>
>         emaclite->txpp = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
>                                         "xlnx,tx-ping-pong", 0);
>         emaclite->rxpp = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
>                                         "xlnx,rx-ping-pong", 0);
>
> -       printf("EMACLITE: %lx, phyaddr %d, %d/%d\n", (ulong)emaclite->regs,
> -              emaclite->phyaddr, emaclite->txpp, emaclite->rxpp);
> -
>         return 0;
>  }
>
> --
> 2.36.0
>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>

Re: [PATCH 0/3] xilinx: Swith platforms to DM_ETH_PHY

[Michal Simek]

út 10. 5. 2022 v 13:26 odesílatel Michal Simek <monstr@monstr.eu> napsal:
>
>
> This patch series adds support for shared MDIO by using generic phy
> framework. Also enable DM_ETH_PHY config for all xilinx platforms.
>
> Thanks,
> Michal
>
>
> T Karthik Reddy (3):
>   net: xilinx: axi_emac: Use shared MDIO bus support for axi emac driver
>   net: xilinx: axi_emaclite: Use shared MDIO bus support for axi
>     emaclite driver
>   xilinx: Add CONFIG_DM_ETH_PHY config
>
>  configs/microblaze-generic_defconfig |  1 +
>  configs/xilinx_versal_virt_defconfig |  1 +
>  configs/xilinx_zynq_virt_defconfig   |  1 +
>  configs/xilinx_zynqmp_virt_defconfig |  1 +
>  drivers/net/xilinx_axi_emac.c        | 38 ++++++++++++++++--------
>  drivers/net/xilinx_emaclite.c        | 43 ++++++++++++++++++----------
>  6 files changed, 58 insertions(+), 27 deletions(-)
>
> --
> 2.36.0
>

applied.
M

-- 
Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel - Xilinx Microblaze
Maintainer of Linux kernel - Xilinx Zynq ARM and ZynqMP ARM64 SoCs
U-Boot custodian - Xilinx Microblaze/Zynq/ZynqMP/Versal SoCs