[PATCH 0/5] Resync Devices trees with Linux 5.16-rc3 and fix breakages

[PATCH 0/5] Resync Devices trees with Linux 5.16-rc3 and fix breakages

[Adam Ford]

The device trees for the RZ/G2[MNH] boards at kernel.org have undergone some
changes over time.  Some of these changes are MMC aliases and others
are AVB refernece clocks.  This series attempts to re-sync the device trees
with Kernel.org then address some minor driver, defconfig,
and config.h breakages caused by the resync.  This series also consolidates
the rz/g2[mnh] -u-boot.dtsi files into one common file to eliminate some
duplicate code and make future maintenance easier.

Adam Ford (5):
  net: ravb: Support multiple clocks
  arm: dts: beacon-rzg2: Resync device trees with Linux 5.16-rc3
  arm: dts: Create common rz-g2-beacon-u-boot file
  ARM: rmobile: Fix rzg2_beacon_defconfig to address new aliases
  configs: beacon-rzg2m: Config to address new aliases

 arch/arm/dts/beacon-renesom-baseboard.dtsi    | 16 +++-
 arch/arm/dts/beacon-renesom-som.dtsi          | 45 +++--------
 .../dts/r8a774a1-beacon-rzg2m-kit-u-boot.dtsi | 32 +-------
 arch/arm/dts/r8a774a1-beacon-rzg2m-kit.dts    |  3 +
 .../dts/r8a774b1-beacon-rzg2n-kit-u-boot.dtsi | 32 +-------
 arch/arm/dts/r8a774b1-beacon-rzg2n-kit.dts    |  3 +
 .../dts/r8a774e1-beacon-rzg2h-kit-u-boot.dtsi | 42 +----------
 arch/arm/dts/r8a774e1-beacon-rzg2h-kit.dts    |  3 +
 arch/arm/dts/rz-g2-beacon-u-boot.dtsi         | 75 +++++++++++++++++++
 board/beacon/beacon-rzg2m/MAINTAINERS         | 10 +++
 configs/rzg2_beacon_defconfig                 |  1 -
 drivers/net/ravb.c                            | 10 +--
 include/configs/beacon-rzg2m.h                |  2 +-
 13 files changed, 129 insertions(+), 145 deletions(-)
 create mode 100644 arch/arm/dts/rz-g2-beacon-u-boot.dtsi

-- 
2.32.0

[PATCH 1/5] net: ravb: Support multiple clocks

[Adam Ford]

The RZ/G2 series uses an external clock as a reference to the AVB.
If this clock is controlled by an external programmable clock,
it must be requested by the consumer or it will not turn on.
In order to do this, update the driver to use bulk enable and
disable functions to enable clocks for boards with multiple clocks.

Signed-off-by: Adam Ford <aford173@gmail.com>
---
 drivers/net/ravb.c | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/net/ravb.c b/drivers/net/ravb.c
index 6953b7286a..d756dddb02 100644
--- a/drivers/net/ravb.c
+++ b/drivers/net/ravb.c
@@ -129,7 +129,7 @@ struct ravb_priv {
 	struct phy_device	*phydev;
 	struct mii_dev		*bus;
 	void __iomem		*iobase;
-	struct clk		clk;
+	struct clk_bulk		clks;
 	struct gpio_desc	reset_gpio;
 };
 
@@ -485,7 +485,7 @@ static int ravb_probe(struct udevice *dev)
 	iobase = map_physmem(pdata->iobase, 0x1000, MAP_NOCACHE);
 	eth->iobase = iobase;
 
-	ret = clk_get_by_index(dev, 0, &eth->clk);
+	ret =  clk_get_bulk(dev, &eth->clks);
 	if (ret < 0)
 		goto err_mdio_alloc;
 
@@ -518,7 +518,7 @@ static int ravb_probe(struct udevice *dev)
 	eth->bus = miiphy_get_dev_by_name(dev->name);
 
 	/* Bring up PHY */
-	ret = clk_enable(&eth->clk);
+	ret = clk_enable_bulk(&eth->clks);
 	if (ret)
 		goto err_mdio_register;
 
@@ -533,7 +533,7 @@ static int ravb_probe(struct udevice *dev)
 	return 0;
 
 err_mdio_reset:
-	clk_disable(&eth->clk);
+	clk_release_bulk(&eth->clks);
 err_mdio_register:
 	mdio_free(mdiodev);
 err_mdio_alloc:
@@ -545,7 +545,7 @@ static int ravb_remove(struct udevice *dev)
 {
 	struct ravb_priv *eth = dev_get_priv(dev);
 
-	clk_disable(&eth->clk);
+	clk_release_bulk(&eth->clks);
 
 	free(eth->phydev);
 	mdio_unregister(eth->bus);
-- 
2.32.0

[PATCH 2/5] arm: dts: beacon-rzg2: Resync device trees with Linux 5.16-rc3

[Adam Ford]

The device trees for the Beacon RZ/G2[MNH] boards have undergone
some changes over time, so resync them now.

Signed-off-by: Adam Ford <aford173@gmail.com>
---
 arch/arm/dts/beacon-renesom-baseboard.dtsi | 16 ++++++--
 arch/arm/dts/beacon-renesom-som.dtsi       | 45 ++++++----------------
 arch/arm/dts/r8a774a1-beacon-rzg2m-kit.dts |  3 ++
 arch/arm/dts/r8a774b1-beacon-rzg2n-kit.dts |  3 ++
 arch/arm/dts/r8a774e1-beacon-rzg2h-kit.dts |  3 ++
 5 files changed, 32 insertions(+), 38 deletions(-)

diff --git a/arch/arm/dts/beacon-renesom-baseboard.dtsi b/arch/arm/dts/beacon-renesom-baseboard.dtsi
index 5f998d4706..2692cc64bf 100644
--- a/arch/arm/dts/beacon-renesom-baseboard.dtsi
+++ b/arch/arm/dts/beacon-renesom-baseboard.dtsi
@@ -197,6 +197,14 @@
 		compatible = "audio-graph-card";
 		label = "rcar-sound";
 		dais = <&rsnd_port0>, <&rsnd_port1>;
+		widgets = "Microphone", "Mic Jack",
+			  "Line", "Line In Jack",
+			  "Headphone", "Headphone Jack";
+		mic-det-gpio = <&gpio0 2 GPIO_ACTIVE_LOW>;
+		routing = "Headphone Jack", "HPOUTL",
+			 "Headphone Jack", "HPOUTR",
+			 "IN3R", "MICBIAS",
+			 "Mic Jack", "IN3R";
 	};
 
 	vccq_sdhi0: regulator-vccq-sdhi0 {
@@ -271,12 +279,12 @@
 &ehci0 {
 	dr_mode = "otg";
 	status = "okay";
-	clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>, <&versaclock5 3>;
+	clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>, <&usb2_clksel>, <&versaclock5 3>;
 };
 
 &ehci1 {
 	status = "okay";
-	clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
+	clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>, <&usb2_clksel>, <&versaclock5 3>;
 };
 
 &hdmi0 {
@@ -615,7 +623,7 @@
 };
 
 &rcar_sound {
-	pinctrl-0 = <&sound_pins &sound_clk_pins>;
+	pinctrl-0 = <&sound_pins>, <&sound_clk_pins>;
 	pinctrl-names = "default";
 
 	/* Single DAI */
@@ -639,7 +647,7 @@
 				bitclock-master = <&rsnd_endpoint0>;
 				frame-master = <&rsnd_endpoint0>;
 
-				playback = <&ssi1 &dvc1 &src1>;
+				playback = <&ssi1>, <&dvc1>, <&src1>;
 				capture = <&ssi0>;
 			};
 		};
diff --git a/arch/arm/dts/beacon-renesom-som.dtsi b/arch/arm/dts/beacon-renesom-som.dtsi
index d30bab3c8b..0d136809eb 100644
--- a/arch/arm/dts/beacon-renesom-som.dtsi
+++ b/arch/arm/dts/beacon-renesom-som.dtsi
@@ -7,19 +7,10 @@
 #include <dt-bindings/clk/versaclock.h>
 
 / {
-	aliases {
-		spi0 = &rpc;
-	};
-
 	memory@48000000 {
 		device_type = "memory";
 		/* first 128MB is reserved for secure area. */
-		reg = <0x0 0x48000000 0x0 0xc000000>;
-	};
-
-	memory@57000000 {
-		device_type = "memory";
-		reg = <0x0 0x57000000 0x0 0x29000000>;
+		reg = <0x0 0x48000000 0x0 0x78000000>;
 	};
 
 	osc_32k: osc_32k {
@@ -59,12 +50,17 @@
 &avb {
 	pinctrl-0 = <&avb_pins>;
 	pinctrl-names = "default";
+	phy-mode = "rgmii-rxid";
 	phy-handle = <&phy0>;
 	rx-internal-delay-ps = <1800>;
 	tx-internal-delay-ps = <2000>;
+	clocks = <&cpg CPG_MOD 812>, <&versaclock5 4>;
+	clock-names = "fck", "refclk";
 	status = "okay";
 
 	phy0: ethernet-phy@0 {
+		compatible = "ethernet-phy-id004d.d074",
+			     "ethernet-phy-ieee802.3-c22";
 		reg = <0>;
 		interrupt-parent = <&gpio2>;
 		interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
@@ -153,7 +149,7 @@
 	};
 
 	eeprom@50 {
-		compatible = "microchip,at24c64", "atmel,24c64";
+		compatible = "microchip,24c64", "atmel,24c64";
 		pagesize = <32>;
 		read-only;	/* Manufacturing EEPROM programmed at factory */
 		reg = <0x50>;
@@ -279,25 +275,6 @@
 	};
 };
 
-&rpc {
-	compatible = "renesas,rcar-gen3-rpc";
-	num-cs = <1>;
-	spi-max-frequency = <40000000>;
-	#address-cells = <1>;
-	#size-cells = <0>;
-	status = "okay";
-
-	flash0: spi-flash@0 {
-		#address-cells = <1>;
-		#size-cells = <1>;
-		reg = <0>;
-		compatible = "spi-flash", "jedec,spi-nor";
-		spi-max-frequency = <40000000>;
-		spi-tx-bus-width = <1>;
-		spi-rx-bus-width = <1>;
-	};
-};
-
 &scif_clk {
 	clock-frequency = <14745600>;
 };
@@ -340,17 +317,17 @@
 	vqmmc-supply = <&reg_1p8v>;
 	bus-width = <8>;
 	mmc-hs200-1_8v;
+	no-sd;
+	no-sdio;
 	non-removable;
 	fixed-emmc-driver-type = <1>;
 	status = "okay";
 };
 
 &usb2_clksel {
-	status = "okay";
 	clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>,
-		 <&versaclock5 3>, <&usb3s0_clk>;
-	clock-names = "ehci_ohci", "hs-usb-if",
-		      "usb_extal", "usb_xtal";
+		  <&versaclock5 3>, <&usb3s0_clk>;
+	status = "okay";
 };
 
 &usb3s0_clk {
diff --git a/arch/arm/dts/r8a774a1-beacon-rzg2m-kit.dts b/arch/arm/dts/r8a774a1-beacon-rzg2m-kit.dts
index 501cb05da2..3cf2e07694 100644
--- a/arch/arm/dts/r8a774a1-beacon-rzg2m-kit.dts
+++ b/arch/arm/dts/r8a774a1-beacon-rzg2m-kit.dts
@@ -21,6 +21,9 @@
 		serial4 = &hscif2;
 		serial5 = &scif5;
 		ethernet0 = &avb;
+		mmc0 = &sdhi3;
+		mmc1 = &sdhi0;
+		mmc2 = &sdhi2;
 	};
 
 	chosen {
diff --git a/arch/arm/dts/r8a774b1-beacon-rzg2n-kit.dts b/arch/arm/dts/r8a774b1-beacon-rzg2n-kit.dts
index 71763f4402..3c0d59def8 100644
--- a/arch/arm/dts/r8a774b1-beacon-rzg2n-kit.dts
+++ b/arch/arm/dts/r8a774b1-beacon-rzg2n-kit.dts
@@ -22,6 +22,9 @@
 		serial5 = &scif5;
 		serial6 = &scif4;
 		ethernet0 = &avb;
+		mmc0 = &sdhi3;
+		mmc1 = &sdhi0;
+		mmc2 = &sdhi2;
 	};
 
 	chosen {
diff --git a/arch/arm/dts/r8a774e1-beacon-rzg2h-kit.dts b/arch/arm/dts/r8a774e1-beacon-rzg2h-kit.dts
index 273f062f29..7b6649a3de 100644
--- a/arch/arm/dts/r8a774e1-beacon-rzg2h-kit.dts
+++ b/arch/arm/dts/r8a774e1-beacon-rzg2h-kit.dts
@@ -22,6 +22,9 @@
 		serial5 = &scif5;
 		serial6 = &scif4;
 		ethernet0 = &avb;
+		mmc0 = &sdhi3;
+		mmc1 = &sdhi0;
+		mmc2 = &sdhi2;
 	};
 
 	chosen {
-- 
2.32.0

[PATCH 3/5] arm: dts: Create common rz-g2-beacon-u-boot file

[Adam Ford]

The rzg2_beacon_defconfig creates an image for RZ/G2[MNH] and
as such creates three different device trees and each of them
have a corresponding -u-boot.dtsi file which are basically
copies of each other.  Create a common include file to be
referenced by each of the respective board-u-boot.dtsi files
to reduce duplicate code and simplify support going forward.
This also restores some lost functionality from the device
tree re-sync and updates the MAINTAINER file to include all
beacon-renesom device tree files.

Signed-off-by: Adam Ford <aford173@gmail.com>
---
 .../dts/r8a774a1-beacon-rzg2m-kit-u-boot.dtsi | 32 +-------
 .../dts/r8a774b1-beacon-rzg2n-kit-u-boot.dtsi | 32 +-------
 .../dts/r8a774e1-beacon-rzg2h-kit-u-boot.dtsi | 42 +----------
 arch/arm/dts/rz-g2-beacon-u-boot.dtsi         | 75 +++++++++++++++++++
 board/beacon/beacon-rzg2m/MAINTAINERS         | 10 +++
 5 files changed, 91 insertions(+), 100 deletions(-)
 create mode 100644 arch/arm/dts/rz-g2-beacon-u-boot.dtsi

diff --git a/arch/arm/dts/r8a774a1-beacon-rzg2m-kit-u-boot.dtsi b/arch/arm/dts/r8a774a1-beacon-rzg2m-kit-u-boot.dtsi
index a0c0a7f35c..85336d5f3b 100644
--- a/arch/arm/dts/r8a774a1-beacon-rzg2m-kit-u-boot.dtsi
+++ b/arch/arm/dts/r8a774a1-beacon-rzg2m-kit-u-boot.dtsi
@@ -1,34 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0
 /*
- * Copyright 2020 Compass Electronics Group, LLC
+ * Copyright 2021 LogicPD dba Beacon EmbeddedWorks
  */
 
-/ {
-	soc {
-		u-boot,dm-pre-reloc;
-	};
-};
-
-&cpg {
-	u-boot,dm-pre-reloc;
-};
-
-&extal_clk {
-	u-boot,dm-pre-reloc;
-};
-
-&prr {
-	u-boot,dm-pre-reloc;
-};
-
-&extalr_clk {
-	u-boot,dm-pre-reloc;
-};
-
-&sdhi0 {
-	/delete-property/ cd-gpios;
-};
-
-&sdhi2 {
-	status = "disabled";
-};
+#include "rz-g2-beacon-u-boot.dtsi"
diff --git a/arch/arm/dts/r8a774b1-beacon-rzg2n-kit-u-boot.dtsi b/arch/arm/dts/r8a774b1-beacon-rzg2n-kit-u-boot.dtsi
index a0c0a7f35c..85336d5f3b 100644
--- a/arch/arm/dts/r8a774b1-beacon-rzg2n-kit-u-boot.dtsi
+++ b/arch/arm/dts/r8a774b1-beacon-rzg2n-kit-u-boot.dtsi
@@ -1,34 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0
 /*
- * Copyright 2020 Compass Electronics Group, LLC
+ * Copyright 2021 LogicPD dba Beacon EmbeddedWorks
  */
 
-/ {
-	soc {
-		u-boot,dm-pre-reloc;
-	};
-};
-
-&cpg {
-	u-boot,dm-pre-reloc;
-};
-
-&extal_clk {
-	u-boot,dm-pre-reloc;
-};
-
-&prr {
-	u-boot,dm-pre-reloc;
-};
-
-&extalr_clk {
-	u-boot,dm-pre-reloc;
-};
-
-&sdhi0 {
-	/delete-property/ cd-gpios;
-};
-
-&sdhi2 {
-	status = "disabled";
-};
+#include "rz-g2-beacon-u-boot.dtsi"
diff --git a/arch/arm/dts/r8a774e1-beacon-rzg2h-kit-u-boot.dtsi b/arch/arm/dts/r8a774e1-beacon-rzg2h-kit-u-boot.dtsi
index eef200af2d..85336d5f3b 100644
--- a/arch/arm/dts/r8a774e1-beacon-rzg2h-kit-u-boot.dtsi
+++ b/arch/arm/dts/r8a774e1-beacon-rzg2h-kit-u-boot.dtsi
@@ -1,44 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0
 /*
- * Copyright 2020 Compass Electronics Group, LLC
+ * Copyright 2021 LogicPD dba Beacon EmbeddedWorks
  */
 
-/ {
-	soc {
-		u-boot,dm-pre-reloc;
-	};
-};
-
-&cpg {
-	u-boot,dm-pre-reloc;
-};
-
-&extal_clk {
-	u-boot,dm-pre-reloc;
-};
-
-&prr {
-	u-boot,dm-pre-reloc;
-};
-
-&extalr_clk {
-	u-boot,dm-pre-reloc;
-};
-
-&sdhi0 {
-	/delete-property/ cd-gpios;
-	sd-uhs-sdr12;
-	sd-uhs-sdr25;
-	sd-uhs-sdr104;
-	max-frequency = <208000000>;
-};
-
-&sdhi2 {
-	status = "disabled";
-};
-
-&sdhi3 {
-	mmc-ddr-1_8v;
-	mmc-hs200-1_8v;
-	mmc-hs400-1_8v;
-};
+#include "rz-g2-beacon-u-boot.dtsi"
diff --git a/arch/arm/dts/rz-g2-beacon-u-boot.dtsi b/arch/arm/dts/rz-g2-beacon-u-boot.dtsi
new file mode 100644
index 0000000000..ef0b96a71e
--- /dev/null
+++ b/arch/arm/dts/rz-g2-beacon-u-boot.dtsi
@@ -0,0 +1,75 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2021 LogicPD dba Beacon EmbeddedWorks
+ */
+
+/ {
+	aliases {
+		spi0 = &rpc;
+	};
+
+	soc {
+		u-boot,dm-pre-reloc;
+	};
+};
+
+&cpg {
+	u-boot,dm-pre-reloc;
+};
+
+&ehci0 {
+	clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>, <&versaclock5 3>;
+};
+
+&ehci1 {
+	clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>, <&versaclock5 3>;
+};
+
+&extal_clk {
+	u-boot,dm-pre-reloc;
+};
+
+&extalr_clk {
+	u-boot,dm-pre-reloc;
+};
+
+&prr {
+	u-boot,dm-pre-reloc;
+};
+
+&rpc {
+	compatible = "renesas,rcar-gen3-rpc";
+	num-cs = <1>;
+	spi-max-frequency = <40000000>;
+	#address-cells = <1>;
+	#size-cells = <0>;
+	status = "okay";
+
+	flash0: spi-flash@0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		reg = <0>;
+		compatible = "spi-flash", "jedec,spi-nor";
+		spi-max-frequency = <40000000>;
+		spi-tx-bus-width = <1>;
+		spi-rx-bus-width = <1>;
+	};
+};
+
+&sdhi0 {
+	/delete-property/ cd-gpios;
+	sd-uhs-sdr12;
+	sd-uhs-sdr25;
+	sd-uhs-sdr104;
+	max-frequency = <208000000>;
+};
+
+&sdhi2 {
+	status = "disabled";
+};
+
+&sdhi3 {
+	mmc-ddr-1_8v;
+	mmc-hs200-1_8v;
+	mmc-hs400-1_8v;
+};
diff --git a/board/beacon/beacon-rzg2m/MAINTAINERS b/board/beacon/beacon-rzg2m/MAINTAINERS
index 77c4057ab0..f8042bb2c4 100644
--- a/board/beacon/beacon-rzg2m/MAINTAINERS
+++ b/board/beacon/beacon-rzg2m/MAINTAINERS
@@ -4,3 +4,13 @@ S:	Maintained
 F:	board/beacon/beacon-rzg2m/
 F:	include/configs/beacon-rzg2m.h
 F:	configs/rzg2_beacon_defconfig
+F:	arch/arm/dts/beacon-renesom-baseboard.dtsi
+F:	arch/arm/dts/beacon-renesom-som.dtsi
+F:	arch/arm/dts/r8a774a1-beacon-rzg2m-kit.dts
+F:	arch/arm/dts/r8a774b1-beacon-rzg2n-kit.dts
+F:	arch/arm/dts/r8a774e1-beacon-rzg2h-kit.dts
+F:	arch/arm/dts/r8a774a1-beacon-rzg2m-kit-u-boot.dtsi
+F:	arch/arm/dts/r8a774b1-beacon-rzg2n-kit-u-boot.dtsi
+F:	arch/arm/dts/r8a774e1-beacon-rzg2h-kit-u-boot.dtsi
+F:	arch/arm/dts/rz-g2-beacon-u-boot.dtsi
+
-- 
2.32.0

[PATCH 4/5] ARM: rmobile: Fix rzg2_beacon_defconfig to address new aliases

[Adam Ford]

The resync of the device trees from Linux 5.16-rc3 caused aliases
to appear on the MMC devices which changed the numbering.
This broke the reading/writing of the environmental variables,
so update the defconfig accordingly.

Signed-off-by: Adam Ford <aford173@gmail.com>
---
 configs/rzg2_beacon_defconfig | 1 -
 1 file changed, 1 deletion(-)

diff --git a/configs/rzg2_beacon_defconfig b/configs/rzg2_beacon_defconfig
index b9bbc200b6..6c48c3b8c9 100644
--- a/configs/rzg2_beacon_defconfig
+++ b/configs/rzg2_beacon_defconfig
@@ -39,7 +39,6 @@ CONFIG_MULTI_DTB_FIT_LZO=y
 CONFIG_MULTI_DTB_FIT_USER_DEFINED_AREA=y
 CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_IS_IN_MMC=y
-CONFIG_SYS_MMC_ENV_DEV=1
 CONFIG_SYS_MMC_ENV_PART=2
 CONFIG_VERSION_VARIABLE=y
 CONFIG_REGMAP=y
-- 
2.32.0

[PATCH 5/5] configs: beacon-rzg2m: Config to address new aliases

[Adam Ford]

The resync of the device trees from Linux 5.16-rc3 caused aliases
to appear on the MMC devices which changed the numbering.
This changed the default boot device and caused boot failure.
Update the mmcdev variable to reflect the new aliases.

Signed-off-by: Adam Ford <aford173@gmail.com>
---
 include/configs/beacon-rzg2m.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/include/configs/beacon-rzg2m.h b/include/configs/beacon-rzg2m.h
index 18d442e06a..14d6df328a 100644
--- a/include/configs/beacon-rzg2m.h
+++ b/include/configs/beacon-rzg2m.h
@@ -23,7 +23,7 @@
 	"boot_fdt=try\0" \
 	"fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
 	"initrd_addr=0x43800000\0"		\
-	"mmcdev=0\0" \
+	"mmcdev=1\0" \
 	"mmcpart=1\0" \
 	"mmcrootpart=2\0" \
 	"finduuid=part uuid mmc ${mmcdev}:${mmcrootpart} uuid\0" \
-- 
2.32.0

Re: [PATCH 1/5] net: ravb: Support multiple clocks

[Ramon Fried]

On Mon, Dec 6, 2021 at 6:29 PM Adam Ford <aford173@gmail.com> wrote:
>
> The RZ/G2 series uses an external clock as a reference to the AVB.
> If this clock is controlled by an external programmable clock,
> it must be requested by the consumer or it will not turn on.
> In order to do this, update the driver to use bulk enable and
> disable functions to enable clocks for boards with multiple clocks.
>
> Signed-off-by: Adam Ford <aford173@gmail.com>
> ---
>  drivers/net/ravb.c | 10 +++++-----
>  1 file changed, 5 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/net/ravb.c b/drivers/net/ravb.c
> index 6953b7286a..d756dddb02 100644
> --- a/drivers/net/ravb.c
> +++ b/drivers/net/ravb.c
> @@ -129,7 +129,7 @@ struct ravb_priv {
>         struct phy_device       *phydev;
>         struct mii_dev          *bus;
>         void __iomem            *iobase;
> -       struct clk              clk;
> +       struct clk_bulk         clks;
>         struct gpio_desc        reset_gpio;
>  };
>
> @@ -485,7 +485,7 @@ static int ravb_probe(struct udevice *dev)
>         iobase = map_physmem(pdata->iobase, 0x1000, MAP_NOCACHE);
>         eth->iobase = iobase;
>
> -       ret = clk_get_by_index(dev, 0, &eth->clk);
> +       ret =  clk_get_bulk(dev, &eth->clks);
>         if (ret < 0)
>                 goto err_mdio_alloc;
>
> @@ -518,7 +518,7 @@ static int ravb_probe(struct udevice *dev)
>         eth->bus = miiphy_get_dev_by_name(dev->name);
>
>         /* Bring up PHY */
> -       ret = clk_enable(&eth->clk);
> +       ret = clk_enable_bulk(&eth->clks);
>         if (ret)
>                 goto err_mdio_register;
>
> @@ -533,7 +533,7 @@ static int ravb_probe(struct udevice *dev)
>         return 0;
>
>  err_mdio_reset:
> -       clk_disable(&eth->clk);
> +       clk_release_bulk(&eth->clks);
>  err_mdio_register:
>         mdio_free(mdiodev);
>  err_mdio_alloc:
> @@ -545,7 +545,7 @@ static int ravb_remove(struct udevice *dev)
>  {
>         struct ravb_priv *eth = dev_get_priv(dev);
>
> -       clk_disable(&eth->clk);
> +       clk_release_bulk(&eth->clks);
>
>         free(eth->phydev);
>         mdio_unregister(eth->bus);
> --
> 2.32.0
>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>