* [amdkfd] where are AQL packets processed after writing the userspace doorbell
@ 2020-12-22 5:12 Smith John
2020-12-22 6:17 ` Bridgman, John
0 siblings, 1 reply; 2+ messages in thread
From: Smith John @ 2020-12-22 5:12 UTC (permalink / raw)
To: amd-gfx
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Hi! I noticed that the AQL packets are more concise compared with PM4
packets. It seemed that AQL packets need more post-processing than PM4
packets.
I was wondering where the AQL packets are processed, such like calculating
the code address using code_entry_offset, resetting packets' headers into
INVALID, and writing values to the completion signal when finished.
Are all these operations done by the firmware?
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* Re: [amdkfd] where are AQL packets processed after writing the userspace doorbell
2020-12-22 5:12 [amdkfd] where are AQL packets processed after writing the userspace doorbell Smith John
@ 2020-12-22 6:17 ` Bridgman, John
0 siblings, 0 replies; 2+ messages in thread
From: Bridgman, John @ 2020-12-22 6:17 UTC (permalink / raw)
To: amd-gfx
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[AMD Official Use Only - Internal Distribution Only]
>Hi! I noticed that the AQL packets are more concise compared with PM4 packets. It seemed that AQL packets need more post-processing than PM4 packets.
>I was wondering where the AQL packets are processed, such like calculating the code address using code_entry_offset, resetting packets' headers into INVALID, and writing values to the completion signal when finished.
>Are all these operations done by the firmware?
Yes, these operations are performed entirely by MEC firmware.
There were special cases (eg certain debug scenarios) where we used a "soft AQL" layer in the ROC runtime which interpreted AQL packets and translated them into a series of PM4 packets, but I don't believe that mechanism is used any more. It was never used during normal processing anyways.
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2020-12-22 5:12 [amdkfd] where are AQL packets processed after writing the userspace doorbell Smith John
2020-12-22 6:17 ` Bridgman, John
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