* [U-Boot] [PATCH 0/8] powerpc: drop more non-generic boards
@ 2015-01-22 15:24 Masahiro Yamada
2015-01-22 15:24 ` [U-Boot] [PATCH 1/8] powerpc: mpc83xx: remove MPC8360ERDK, EMPC8360EMDS support Masahiro Yamada
` (7 more replies)
0 siblings, 8 replies; 19+ messages in thread
From: Masahiro Yamada @ 2015-01-22 15:24 UTC (permalink / raw)
To: u-boot
Masahiro Yamada (8):
powerpc: mpc83xx: remove MPC8360ERDK, EMPC8360EMDS support
powerpc: mpc85xx: remove P1_P2_RDB boards
powerpc: mpc85xx: remove P2020COME board support
powerpc: mpc85xx: remove P2020DS board support
powerpc: ppc4xx: remove PPChameleonEVB, CATcenter boards
powerpc: mpc5xxx: remove Total5200 board support
powerpc: mpc5xxx: PM520 board support
powerpc: remove icecube_5200, Lite5200, cpci5200, mecp5200, pf5200
arch/powerpc/cpu/mpc5xxx/Kconfig | 24 -
arch/powerpc/cpu/mpc5xxx/pci_mpc5200.c | 14 -
arch/powerpc/cpu/mpc83xx/Kconfig | 8 -
arch/powerpc/cpu/mpc85xx/Kconfig | 14 -
arch/powerpc/cpu/ppc4xx/Kconfig | 7 -
board/dave/PPChameleonEVB/Kconfig | 25 -
board/dave/PPChameleonEVB/MAINTAINERS | 20 -
board/dave/PPChameleonEVB/Makefile | 8 -
board/dave/PPChameleonEVB/PPChameleonEVB.c | 231 --------
board/dave/PPChameleonEVB/flash.c | 99 ----
board/dave/PPChameleonEVB/nand.c | 99 ----
board/dave/PPChameleonEVB/u-boot.lds | 115 ----
board/esd/cpci5200/Kconfig | 12 -
board/esd/cpci5200/MAINTAINERS | 6 -
board/esd/cpci5200/Makefile | 14 -
board/esd/cpci5200/cpci5200.c | 284 ----------
board/esd/cpci5200/mt46v16m16-75.h | 16 -
board/esd/cpci5200/strataflash.c | 786 --------------------------
board/esd/mecp5200/Kconfig | 12 -
board/esd/mecp5200/MAINTAINERS | 6 -
board/esd/mecp5200/Makefile | 8 -
board/esd/mecp5200/mecp5200.c | 251 ---------
board/esd/mecp5200/mt46v16m16-75.h | 16 -
board/esd/pf5200/Kconfig | 12 -
board/esd/pf5200/MAINTAINERS | 6 -
board/esd/pf5200/Makefile | 14 -
board/esd/pf5200/flash.c | 445 ---------------
board/esd/pf5200/mt46v16m16-75.h | 16 -
board/esd/pf5200/pf5200.c | 357 ------------
board/freescale/common/pq-mds-pib.c | 2 +-
board/freescale/mpc8360emds/Kconfig | 12 -
board/freescale/mpc8360emds/MAINTAINERS | 15 -
board/freescale/mpc8360emds/Makefile | 9 -
board/freescale/mpc8360emds/README | 155 -----
board/freescale/mpc8360emds/mpc8360emds.c | 453 ---------------
board/freescale/mpc8360emds/pci.c | 147 -----
board/freescale/mpc8360erdk/Kconfig | 12 -
board/freescale/mpc8360erdk/MAINTAINERS | 7 -
board/freescale/mpc8360erdk/Makefile | 9 -
board/freescale/mpc8360erdk/mpc8360erdk.c | 350 ------------
board/freescale/mpc8360erdk/nand.c | 89 ---
board/freescale/p1_p2_rdb/Kconfig | 12 -
board/freescale/p1_p2_rdb/MAINTAINERS | 37 --
board/freescale/p1_p2_rdb/Makefile | 30 -
board/freescale/p1_p2_rdb/README | 145 -----
board/freescale/p1_p2_rdb/ddr.c | 221 --------
board/freescale/p1_p2_rdb/law.c | 17 -
board/freescale/p1_p2_rdb/p1_p2_rdb.c | 303 ----------
board/freescale/p1_p2_rdb/pci.c | 27 -
board/freescale/p1_p2_rdb/spl.c | 141 -----
board/freescale/p1_p2_rdb/spl_minimal.c | 84 ---
board/freescale/p1_p2_rdb/tlb.c | 91 ---
board/freescale/p2020come/Kconfig | 12 -
board/freescale/p2020come/MAINTAINERS | 7 -
board/freescale/p2020come/Makefile | 10 -
board/freescale/p2020come/ddr.c | 29 -
board/freescale/p2020come/law.c | 23 -
board/freescale/p2020come/p2020come.c | 275 ---------
board/freescale/p2020come/tlb.c | 83 ---
board/freescale/p2020ds/Kconfig | 12 -
board/freescale/p2020ds/MAINTAINERS | 10 -
board/freescale/p2020ds/Makefile | 12 -
board/freescale/p2020ds/ddr.c | 129 -----
board/freescale/p2020ds/law.c | 20 -
board/freescale/p2020ds/p2020ds.c | 263 ---------
board/freescale/p2020ds/tlb.c | 90 ---
board/icecube/Kconfig | 9 -
board/icecube/MAINTAINERS | 21 -
board/icecube/Makefile | 8 -
board/icecube/README | 13 -
board/icecube/README.Lite5200B_low_power | 22 -
board/icecube/flash.c | 477 ----------------
board/icecube/icecube.c | 326 -----------
board/icecube/mt46v16m16-75.h | 16 -
board/icecube/mt46v32m16.h | 16 -
board/icecube/mt48lc16m16a2-75.h | 14 -
board/pm520/Kconfig | 9 -
board/pm520/MAINTAINERS | 9 -
board/pm520/Makefile | 8 -
board/pm520/flash.c | 659 ----------------------
board/pm520/mt46v16m16-75.h | 16 -
board/pm520/mt48lc16m16a2-75.h | 14 -
board/pm520/pm520.c | 253 ---------
board/total5200/Kconfig | 9 -
board/total5200/MAINTAINERS | 9 -
board/total5200/Makefile | 8 -
board/total5200/mt48lc16m16a2-75.h | 14 -
board/total5200/mt48lc32m16a2-75.h | 19 -
board/total5200/sdram.c | 159 ------
board/total5200/sdram.h | 18 -
board/total5200/total5200.c | 276 ---------
configs/CATcenter_25_defconfig | 4 -
configs/CATcenter_33_defconfig | 4 -
configs/CATcenter_defconfig | 4 -
configs/Lite5200_LOWBOOT08_defconfig | 4 -
configs/Lite5200_LOWBOOT_defconfig | 4 -
configs/Lite5200_defconfig | 3 -
configs/MPC8360EMDS_33_ATM_defconfig | 4 -
configs/MPC8360EMDS_33_HOST_33_defconfig | 4 -
configs/MPC8360EMDS_33_HOST_66_defconfig | 4 -
configs/MPC8360EMDS_33_SLAVE_defconfig | 4 -
configs/MPC8360EMDS_33_defconfig | 4 -
configs/MPC8360EMDS_66_ATM_defconfig | 4 -
configs/MPC8360EMDS_66_HOST_33_defconfig | 4 -
configs/MPC8360EMDS_66_HOST_66_defconfig | 4 -
configs/MPC8360EMDS_66_SLAVE_defconfig | 4 -
configs/MPC8360EMDS_66_defconfig | 4 -
configs/MPC8360ERDK_33_defconfig | 4 -
configs/MPC8360ERDK_defconfig | 3 -
configs/P1011RDB_36BIT_SDCARD_defconfig | 5 -
configs/P1011RDB_36BIT_SPIFLASH_defconfig | 5 -
configs/P1011RDB_36BIT_defconfig | 4 -
configs/P1011RDB_NAND_defconfig | 6 -
configs/P1011RDB_SDCARD_defconfig | 5 -
configs/P1011RDB_SPIFLASH_defconfig | 5 -
configs/P1011RDB_defconfig | 4 -
configs/P1020RDB_36BIT_SDCARD_defconfig | 5 -
configs/P1020RDB_36BIT_SPIFLASH_defconfig | 5 -
configs/P1020RDB_36BIT_defconfig | 4 -
configs/P1020RDB_NAND_defconfig | 6 -
configs/P1020RDB_SDCARD_defconfig | 5 -
configs/P1020RDB_SPIFLASH_defconfig | 5 -
configs/P1020RDB_defconfig | 4 -
configs/P2010RDB_36BIT_SDCARD_defconfig | 5 -
configs/P2010RDB_36BIT_SPIFLASH_defconfig | 5 -
configs/P2010RDB_36BIT_defconfig | 4 -
configs/P2010RDB_NAND_defconfig | 6 -
configs/P2010RDB_SDCARD_defconfig | 5 -
configs/P2010RDB_SPIFLASH_defconfig | 5 -
configs/P2010RDB_defconfig | 4 -
configs/P2020COME_SDCARD_defconfig | 4 -
configs/P2020COME_SPIFLASH_defconfig | 4 -
configs/P2020DS_36BIT_defconfig | 4 -
configs/P2020DS_DDR2_defconfig | 4 -
configs/P2020DS_SDCARD_defconfig | 4 -
configs/P2020DS_SPIFLASH_defconfig | 4 -
configs/P2020DS_defconfig | 3 -
configs/P2020RDB_36BIT_SDCARD_defconfig | 5 -
configs/P2020RDB_36BIT_SPIFLASH_defconfig | 5 -
configs/P2020RDB_36BIT_defconfig | 4 -
configs/P2020RDB_NAND_defconfig | 6 -
configs/P2020RDB_SDCARD_defconfig | 5 -
configs/P2020RDB_SPIFLASH_defconfig | 5 -
configs/P2020RDB_defconfig | 4 -
configs/PM520_DDR_defconfig | 4 -
configs/PM520_ROMBOOT_DDR_defconfig | 4 -
configs/PM520_ROMBOOT_defconfig | 4 -
configs/PM520_defconfig | 3 -
configs/PPChameleonEVB_BA_25_defconfig | 4 -
configs/PPChameleonEVB_BA_33_defconfig | 4 -
configs/PPChameleonEVB_HI_25_defconfig | 4 -
configs/PPChameleonEVB_HI_33_defconfig | 4 -
configs/PPChameleonEVB_ME_25_defconfig | 4 -
configs/PPChameleonEVB_ME_33_defconfig | 4 -
configs/PPChameleonEVB_defconfig | 3 -
configs/Total5200_Rev2_defconfig | 4 -
configs/Total5200_Rev2_lowboot_defconfig | 4 -
configs/Total5200_defconfig | 4 -
configs/Total5200_lowboot_defconfig | 4 -
configs/cpci5200_defconfig | 3 -
configs/icecube_5200_DDR_LOWBOOT08_defconfig | 4 -
configs/icecube_5200_DDR_LOWBOOT_defconfig | 4 -
configs/icecube_5200_DDR_defconfig | 4 -
configs/icecube_5200_LOWBOOT08_defconfig | 4 -
configs/icecube_5200_LOWBOOT_defconfig | 4 -
configs/icecube_5200_defconfig | 3 -
configs/lite5200b_LOWBOOT_defconfig | 4 -
configs/lite5200b_PM_defconfig | 4 -
configs/lite5200b_defconfig | 4 -
configs/mecp5200_defconfig | 3 -
configs/pf5200_defconfig | 3 -
doc/README.scrapyard | 27 +-
drivers/mtd/nand/nand_base.c | 5 -
drivers/net/mpc5xxx_fec.c | 5 -
drivers/video/cfb_console.c | 3 -
drivers/video/sed13806.c | 5 -
include/configs/CATcenter.h | 750 -------------------------
include/configs/IceCube.h | 403 -------------
include/configs/MPC8360EMDS.h | 735 ------------------------
include/configs/MPC8360ERDK.h | 620 --------------------
include/configs/P1_P2_RDB.h | 808 ---------------------------
include/configs/P2020COME.h | 547 ------------------
include/configs/P2020DS.h | 751 -------------------------
include/configs/PM520.h | 342 ------------
include/configs/PPChameleonEVB.h | 777 --------------------------
include/configs/Total5200.h | 386 -------------
include/configs/cpci5200.h | 390 -------------
include/configs/mecp5200.h | 319 -----------
include/configs/pf5200.h | 372 ------------
189 files changed, 23 insertions(+), 16227 deletions(-)
delete mode 100644 board/dave/PPChameleonEVB/Kconfig
delete mode 100644 board/dave/PPChameleonEVB/MAINTAINERS
delete mode 100644 board/dave/PPChameleonEVB/Makefile
delete mode 100644 board/dave/PPChameleonEVB/PPChameleonEVB.c
delete mode 100644 board/dave/PPChameleonEVB/flash.c
delete mode 100644 board/dave/PPChameleonEVB/nand.c
delete mode 100644 board/dave/PPChameleonEVB/u-boot.lds
delete mode 100644 board/esd/cpci5200/Kconfig
delete mode 100644 board/esd/cpci5200/MAINTAINERS
delete mode 100644 board/esd/cpci5200/Makefile
delete mode 100644 board/esd/cpci5200/cpci5200.c
delete mode 100644 board/esd/cpci5200/mt46v16m16-75.h
delete mode 100644 board/esd/cpci5200/strataflash.c
delete mode 100644 board/esd/mecp5200/Kconfig
delete mode 100644 board/esd/mecp5200/MAINTAINERS
delete mode 100644 board/esd/mecp5200/Makefile
delete mode 100644 board/esd/mecp5200/mecp5200.c
delete mode 100644 board/esd/mecp5200/mt46v16m16-75.h
delete mode 100644 board/esd/pf5200/Kconfig
delete mode 100644 board/esd/pf5200/MAINTAINERS
delete mode 100644 board/esd/pf5200/Makefile
delete mode 100644 board/esd/pf5200/flash.c
delete mode 100644 board/esd/pf5200/mt46v16m16-75.h
delete mode 100644 board/esd/pf5200/pf5200.c
delete mode 100644 board/freescale/mpc8360emds/Kconfig
delete mode 100644 board/freescale/mpc8360emds/MAINTAINERS
delete mode 100644 board/freescale/mpc8360emds/Makefile
delete mode 100644 board/freescale/mpc8360emds/README
delete mode 100644 board/freescale/mpc8360emds/mpc8360emds.c
delete mode 100644 board/freescale/mpc8360emds/pci.c
delete mode 100644 board/freescale/mpc8360erdk/Kconfig
delete mode 100644 board/freescale/mpc8360erdk/MAINTAINERS
delete mode 100644 board/freescale/mpc8360erdk/Makefile
delete mode 100644 board/freescale/mpc8360erdk/mpc8360erdk.c
delete mode 100644 board/freescale/mpc8360erdk/nand.c
delete mode 100644 board/freescale/p1_p2_rdb/Kconfig
delete mode 100644 board/freescale/p1_p2_rdb/MAINTAINERS
delete mode 100644 board/freescale/p1_p2_rdb/Makefile
delete mode 100644 board/freescale/p1_p2_rdb/README
delete mode 100644 board/freescale/p1_p2_rdb/ddr.c
delete mode 100644 board/freescale/p1_p2_rdb/law.c
delete mode 100644 board/freescale/p1_p2_rdb/p1_p2_rdb.c
delete mode 100644 board/freescale/p1_p2_rdb/pci.c
delete mode 100644 board/freescale/p1_p2_rdb/spl.c
delete mode 100644 board/freescale/p1_p2_rdb/spl_minimal.c
delete mode 100644 board/freescale/p1_p2_rdb/tlb.c
delete mode 100644 board/freescale/p2020come/Kconfig
delete mode 100644 board/freescale/p2020come/MAINTAINERS
delete mode 100644 board/freescale/p2020come/Makefile
delete mode 100644 board/freescale/p2020come/ddr.c
delete mode 100644 board/freescale/p2020come/law.c
delete mode 100644 board/freescale/p2020come/p2020come.c
delete mode 100644 board/freescale/p2020come/tlb.c
delete mode 100644 board/freescale/p2020ds/Kconfig
delete mode 100644 board/freescale/p2020ds/MAINTAINERS
delete mode 100644 board/freescale/p2020ds/Makefile
delete mode 100644 board/freescale/p2020ds/ddr.c
delete mode 100644 board/freescale/p2020ds/law.c
delete mode 100644 board/freescale/p2020ds/p2020ds.c
delete mode 100644 board/freescale/p2020ds/tlb.c
delete mode 100644 board/icecube/Kconfig
delete mode 100644 board/icecube/MAINTAINERS
delete mode 100644 board/icecube/Makefile
delete mode 100644 board/icecube/README
delete mode 100644 board/icecube/README.Lite5200B_low_power
delete mode 100644 board/icecube/flash.c
delete mode 100644 board/icecube/icecube.c
delete mode 100644 board/icecube/mt46v16m16-75.h
delete mode 100644 board/icecube/mt46v32m16.h
delete mode 100644 board/icecube/mt48lc16m16a2-75.h
delete mode 100644 board/pm520/Kconfig
delete mode 100644 board/pm520/MAINTAINERS
delete mode 100644 board/pm520/Makefile
delete mode 100644 board/pm520/flash.c
delete mode 100644 board/pm520/mt46v16m16-75.h
delete mode 100644 board/pm520/mt48lc16m16a2-75.h
delete mode 100644 board/pm520/pm520.c
delete mode 100644 board/total5200/Kconfig
delete mode 100644 board/total5200/MAINTAINERS
delete mode 100644 board/total5200/Makefile
delete mode 100644 board/total5200/mt48lc16m16a2-75.h
delete mode 100644 board/total5200/mt48lc32m16a2-75.h
delete mode 100644 board/total5200/sdram.c
delete mode 100644 board/total5200/sdram.h
delete mode 100644 board/total5200/total5200.c
delete mode 100644 configs/CATcenter_25_defconfig
delete mode 100644 configs/CATcenter_33_defconfig
delete mode 100644 configs/CATcenter_defconfig
delete mode 100644 configs/Lite5200_LOWBOOT08_defconfig
delete mode 100644 configs/Lite5200_LOWBOOT_defconfig
delete mode 100644 configs/Lite5200_defconfig
delete mode 100644 configs/MPC8360EMDS_33_ATM_defconfig
delete mode 100644 configs/MPC8360EMDS_33_HOST_33_defconfig
delete mode 100644 configs/MPC8360EMDS_33_HOST_66_defconfig
delete mode 100644 configs/MPC8360EMDS_33_SLAVE_defconfig
delete mode 100644 configs/MPC8360EMDS_33_defconfig
delete mode 100644 configs/MPC8360EMDS_66_ATM_defconfig
delete mode 100644 configs/MPC8360EMDS_66_HOST_33_defconfig
delete mode 100644 configs/MPC8360EMDS_66_HOST_66_defconfig
delete mode 100644 configs/MPC8360EMDS_66_SLAVE_defconfig
delete mode 100644 configs/MPC8360EMDS_66_defconfig
delete mode 100644 configs/MPC8360ERDK_33_defconfig
delete mode 100644 configs/MPC8360ERDK_defconfig
delete mode 100644 configs/P1011RDB_36BIT_SDCARD_defconfig
delete mode 100644 configs/P1011RDB_36BIT_SPIFLASH_defconfig
delete mode 100644 configs/P1011RDB_36BIT_defconfig
delete mode 100644 configs/P1011RDB_NAND_defconfig
delete mode 100644 configs/P1011RDB_SDCARD_defconfig
delete mode 100644 configs/P1011RDB_SPIFLASH_defconfig
delete mode 100644 configs/P1011RDB_defconfig
delete mode 100644 configs/P1020RDB_36BIT_SDCARD_defconfig
delete mode 100644 configs/P1020RDB_36BIT_SPIFLASH_defconfig
delete mode 100644 configs/P1020RDB_36BIT_defconfig
delete mode 100644 configs/P1020RDB_NAND_defconfig
delete mode 100644 configs/P1020RDB_SDCARD_defconfig
delete mode 100644 configs/P1020RDB_SPIFLASH_defconfig
delete mode 100644 configs/P1020RDB_defconfig
delete mode 100644 configs/P2010RDB_36BIT_SDCARD_defconfig
delete mode 100644 configs/P2010RDB_36BIT_SPIFLASH_defconfig
delete mode 100644 configs/P2010RDB_36BIT_defconfig
delete mode 100644 configs/P2010RDB_NAND_defconfig
delete mode 100644 configs/P2010RDB_SDCARD_defconfig
delete mode 100644 configs/P2010RDB_SPIFLASH_defconfig
delete mode 100644 configs/P2010RDB_defconfig
delete mode 100644 configs/P2020COME_SDCARD_defconfig
delete mode 100644 configs/P2020COME_SPIFLASH_defconfig
delete mode 100644 configs/P2020DS_36BIT_defconfig
delete mode 100644 configs/P2020DS_DDR2_defconfig
delete mode 100644 configs/P2020DS_SDCARD_defconfig
delete mode 100644 configs/P2020DS_SPIFLASH_defconfig
delete mode 100644 configs/P2020DS_defconfig
delete mode 100644 configs/P2020RDB_36BIT_SDCARD_defconfig
delete mode 100644 configs/P2020RDB_36BIT_SPIFLASH_defconfig
delete mode 100644 configs/P2020RDB_36BIT_defconfig
delete mode 100644 configs/P2020RDB_NAND_defconfig
delete mode 100644 configs/P2020RDB_SDCARD_defconfig
delete mode 100644 configs/P2020RDB_SPIFLASH_defconfig
delete mode 100644 configs/P2020RDB_defconfig
delete mode 100644 configs/PM520_DDR_defconfig
delete mode 100644 configs/PM520_ROMBOOT_DDR_defconfig
delete mode 100644 configs/PM520_ROMBOOT_defconfig
delete mode 100644 configs/PM520_defconfig
delete mode 100644 configs/PPChameleonEVB_BA_25_defconfig
delete mode 100644 configs/PPChameleonEVB_BA_33_defconfig
delete mode 100644 configs/PPChameleonEVB_HI_25_defconfig
delete mode 100644 configs/PPChameleonEVB_HI_33_defconfig
delete mode 100644 configs/PPChameleonEVB_ME_25_defconfig
delete mode 100644 configs/PPChameleonEVB_ME_33_defconfig
delete mode 100644 configs/PPChameleonEVB_defconfig
delete mode 100644 configs/Total5200_Rev2_defconfig
delete mode 100644 configs/Total5200_Rev2_lowboot_defconfig
delete mode 100644 configs/Total5200_defconfig
delete mode 100644 configs/Total5200_lowboot_defconfig
delete mode 100644 configs/cpci5200_defconfig
delete mode 100644 configs/icecube_5200_DDR_LOWBOOT08_defconfig
delete mode 100644 configs/icecube_5200_DDR_LOWBOOT_defconfig
delete mode 100644 configs/icecube_5200_DDR_defconfig
delete mode 100644 configs/icecube_5200_LOWBOOT08_defconfig
delete mode 100644 configs/icecube_5200_LOWBOOT_defconfig
delete mode 100644 configs/icecube_5200_defconfig
delete mode 100644 configs/lite5200b_LOWBOOT_defconfig
delete mode 100644 configs/lite5200b_PM_defconfig
delete mode 100644 configs/lite5200b_defconfig
delete mode 100644 configs/mecp5200_defconfig
delete mode 100644 configs/pf5200_defconfig
delete mode 100644 include/configs/CATcenter.h
delete mode 100644 include/configs/IceCube.h
delete mode 100644 include/configs/MPC8360EMDS.h
delete mode 100644 include/configs/MPC8360ERDK.h
delete mode 100644 include/configs/P1_P2_RDB.h
delete mode 100644 include/configs/P2020COME.h
delete mode 100644 include/configs/P2020DS.h
delete mode 100644 include/configs/PM520.h
delete mode 100644 include/configs/PPChameleonEVB.h
delete mode 100644 include/configs/Total5200.h
delete mode 100644 include/configs/cpci5200.h
delete mode 100644 include/configs/mecp5200.h
delete mode 100644 include/configs/pf5200.h
--
1.9.1
^ permalink raw reply [flat|nested] 19+ messages in thread
* [U-Boot] [PATCH 1/8] powerpc: mpc83xx: remove MPC8360ERDK, EMPC8360EMDS support
2015-01-22 15:24 [U-Boot] [PATCH 0/8] powerpc: drop more non-generic boards Masahiro Yamada
@ 2015-01-22 15:24 ` Masahiro Yamada
2015-01-23 21:57 ` Tom Rini
2015-01-22 15:24 ` [U-Boot] [PATCH 2/8] powerpc: mpc85xx: remove P1_P2_RDB boards Masahiro Yamada
` (6 subsequent siblings)
7 siblings, 1 reply; 19+ messages in thread
From: Masahiro Yamada @ 2015-01-22 15:24 UTC (permalink / raw)
To: u-boot
These boards are still non-generic boards.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Dave Liu <daveliu@freescale.com>
Cc: Anton Vorontsov <avorontsov@ru.mvista.com>
---
arch/powerpc/cpu/mpc83xx/Kconfig | 8 -
board/freescale/common/pq-mds-pib.c | 2 +-
board/freescale/mpc8360emds/Kconfig | 12 -
board/freescale/mpc8360emds/MAINTAINERS | 15 -
board/freescale/mpc8360emds/Makefile | 9 -
board/freescale/mpc8360emds/README | 155 -------
board/freescale/mpc8360emds/mpc8360emds.c | 453 ------------------
board/freescale/mpc8360emds/pci.c | 147 ------
board/freescale/mpc8360erdk/Kconfig | 12 -
board/freescale/mpc8360erdk/MAINTAINERS | 7 -
board/freescale/mpc8360erdk/Makefile | 9 -
board/freescale/mpc8360erdk/mpc8360erdk.c | 350 --------------
board/freescale/mpc8360erdk/nand.c | 89 ----
configs/MPC8360EMDS_33_ATM_defconfig | 4 -
configs/MPC8360EMDS_33_HOST_33_defconfig | 4 -
configs/MPC8360EMDS_33_HOST_66_defconfig | 4 -
configs/MPC8360EMDS_33_SLAVE_defconfig | 4 -
configs/MPC8360EMDS_33_defconfig | 4 -
configs/MPC8360EMDS_66_ATM_defconfig | 4 -
configs/MPC8360EMDS_66_HOST_33_defconfig | 4 -
configs/MPC8360EMDS_66_HOST_66_defconfig | 4 -
configs/MPC8360EMDS_66_SLAVE_defconfig | 4 -
configs/MPC8360EMDS_66_defconfig | 4 -
configs/MPC8360ERDK_33_defconfig | 4 -
configs/MPC8360ERDK_defconfig | 3 -
doc/README.scrapyard | 12 +-
include/configs/MPC8360EMDS.h | 735 ------------------------------
include/configs/MPC8360ERDK.h | 620 -------------------------
28 files changed, 8 insertions(+), 2674 deletions(-)
delete mode 100644 board/freescale/mpc8360emds/Kconfig
delete mode 100644 board/freescale/mpc8360emds/MAINTAINERS
delete mode 100644 board/freescale/mpc8360emds/Makefile
delete mode 100644 board/freescale/mpc8360emds/README
delete mode 100644 board/freescale/mpc8360emds/mpc8360emds.c
delete mode 100644 board/freescale/mpc8360emds/pci.c
delete mode 100644 board/freescale/mpc8360erdk/Kconfig
delete mode 100644 board/freescale/mpc8360erdk/MAINTAINERS
delete mode 100644 board/freescale/mpc8360erdk/Makefile
delete mode 100644 board/freescale/mpc8360erdk/mpc8360erdk.c
delete mode 100644 board/freescale/mpc8360erdk/nand.c
delete mode 100644 configs/MPC8360EMDS_33_ATM_defconfig
delete mode 100644 configs/MPC8360EMDS_33_HOST_33_defconfig
delete mode 100644 configs/MPC8360EMDS_33_HOST_66_defconfig
delete mode 100644 configs/MPC8360EMDS_33_SLAVE_defconfig
delete mode 100644 configs/MPC8360EMDS_33_defconfig
delete mode 100644 configs/MPC8360EMDS_66_ATM_defconfig
delete mode 100644 configs/MPC8360EMDS_66_HOST_33_defconfig
delete mode 100644 configs/MPC8360EMDS_66_HOST_66_defconfig
delete mode 100644 configs/MPC8360EMDS_66_SLAVE_defconfig
delete mode 100644 configs/MPC8360EMDS_66_defconfig
delete mode 100644 configs/MPC8360ERDK_33_defconfig
delete mode 100644 configs/MPC8360ERDK_defconfig
delete mode 100644 include/configs/MPC8360EMDS.h
delete mode 100644 include/configs/MPC8360ERDK.h
diff --git a/arch/powerpc/cpu/mpc83xx/Kconfig b/arch/powerpc/cpu/mpc83xx/Kconfig
index 69a600c..4d6cb09 100644
--- a/arch/powerpc/cpu/mpc83xx/Kconfig
+++ b/arch/powerpc/cpu/mpc83xx/Kconfig
@@ -41,12 +41,6 @@ config TARGET_MPC8349EMDS
config TARGET_MPC8349ITX
bool "Support MPC8349ITX"
-config TARGET_MPC8360EMDS
- bool "Support MPC8360EMDS"
-
-config TARGET_MPC8360ERDK
- bool "Support MPC8360ERDK"
-
config TARGET_MPC837XEMDS
bool "Support MPC837XEMDS"
@@ -81,8 +75,6 @@ source "board/freescale/mpc8323erdb/Kconfig"
source "board/freescale/mpc832xemds/Kconfig"
source "board/freescale/mpc8349emds/Kconfig"
source "board/freescale/mpc8349itx/Kconfig"
-source "board/freescale/mpc8360emds/Kconfig"
-source "board/freescale/mpc8360erdk/Kconfig"
source "board/freescale/mpc837xemds/Kconfig"
source "board/freescale/mpc837xerdb/Kconfig"
source "board/ids/ids8313/Kconfig"
diff --git a/board/freescale/common/pq-mds-pib.c b/board/freescale/common/pq-mds-pib.c
index 5f7a67d..1eb3786 100644
--- a/board/freescale/common/pq-mds-pib.c
+++ b/board/freescale/common/pq-mds-pib.c
@@ -63,7 +63,7 @@ int pib_init(void)
#endif
#if defined(CONFIG_PQ_MDS_PIB_ATM)
-#if defined(CONFIG_MPC8360EMDS) || defined(CONFIG_MPC8569MDS)
+#if defined(CONFIG_MPC8569MDS)
val8 = 0;
i2c_write(0x20, 0x6, 1, &val8, 1);
i2c_write(0x20, 0x7, 1, &val8, 1);
diff --git a/board/freescale/mpc8360emds/Kconfig b/board/freescale/mpc8360emds/Kconfig
deleted file mode 100644
index 3f4f95c..0000000
--- a/board/freescale/mpc8360emds/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_MPC8360EMDS
-
-config SYS_BOARD
- default "mpc8360emds"
-
-config SYS_VENDOR
- default "freescale"
-
-config SYS_CONFIG_NAME
- default "MPC8360EMDS"
-
-endif
diff --git a/board/freescale/mpc8360emds/MAINTAINERS b/board/freescale/mpc8360emds/MAINTAINERS
deleted file mode 100644
index 91ff2ef..0000000
--- a/board/freescale/mpc8360emds/MAINTAINERS
+++ /dev/null
@@ -1,15 +0,0 @@
-MPC8360EMDS BOARD
-M: Dave Liu <daveliu@freescale.com>
-S: Maintained
-F: board/freescale/mpc8360emds/
-F: include/configs/MPC8360EMDS.h
-F: configs/MPC8360EMDS_33_defconfig
-F: configs/MPC8360EMDS_33_ATM_defconfig
-F: configs/MPC8360EMDS_33_HOST_33_defconfig
-F: configs/MPC8360EMDS_33_HOST_66_defconfig
-F: configs/MPC8360EMDS_33_SLAVE_defconfig
-F: configs/MPC8360EMDS_66_defconfig
-F: configs/MPC8360EMDS_66_ATM_defconfig
-F: configs/MPC8360EMDS_66_HOST_33_defconfig
-F: configs/MPC8360EMDS_66_HOST_66_defconfig
-F: configs/MPC8360EMDS_66_SLAVE_defconfig
diff --git a/board/freescale/mpc8360emds/Makefile b/board/freescale/mpc8360emds/Makefile
deleted file mode 100644
index e8332ce..0000000
--- a/board/freescale/mpc8360emds/Makefile
+++ /dev/null
@@ -1,9 +0,0 @@
-#
-# (C) Copyright 2006
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y += mpc8360emds.o
-obj-$(CONFIG_PCI) += pci.o
diff --git a/board/freescale/mpc8360emds/README b/board/freescale/mpc8360emds/README
deleted file mode 100644
index 6afa753..0000000
--- a/board/freescale/mpc8360emds/README
+++ /dev/null
@@ -1,155 +0,0 @@
-Freescale MPC8360EMDS Board
------------------------------------------
-1. Board Switches and Jumpers
-1.0 There are four Dual-In-Line Packages(DIP) Switches on MPC8360EMDS board
- For some reason, the HW designers describe the switch settings
- in terms of 0 and 1, and then map that to physical switches where
- the label "On" refers to logic 0 and "Off" is logic 1.
-
- Switch bits are numbered 1 through, like, 4 6 8 or 10, but the
- bits may contribute to signals that are numbered based at 0,
- and some of those signals may be high-bit-number-0 too. Heed
- well the names and labels and do not get confused.
-
- "Off" == 1
- "On" == 0
-
- SW18 is switch 18 as silk-screened onto the board.
- SW4[8] is the bit labeled 8 on Switch 4.
- SW2[1:6] refers to bits labeled 1 through 6 in order on switch 2.
- SW3[7:1] refers to bits labeled 7 through 1 in order on switch 3.
- SW3[1:8]= 0000_0001 refers to bits labeled 1 through 6 is set as "On"
- and bits labeled 8 is set as "Off".
-
-1.1 There are three type boards for MPC8360E silicon up to now, They are
-
- * MPC8360E-MDS-PB PROTO (a.k.a 8360SYS PROTOTYPE)
- * MPC8360E-MDS-PB PILOT (a.k.a 8360SYS PILOT)
- * MPC8360EA-MDS-PB PROTO (a.k.a 8360SYS2 PROTOTYPE)
-
-1.2 For all the MPC8360EMDS Board
-
- First, make sure the board default setting is consistent with the
- document shipped with your board. Then apply the following setting:
- SW3[1-8]= 0000_0100 (HRCW setting value is performed on local bus)
- SW4[1-8]= 0011_0000 (Flash boot on local bus)
- SW9[1-8]= 0110_0110 (PCI Mode enabled. HRCW is read from FLASH)
- SW10[1-8]= 0000_1000 (core PLL setting)
- SW11[1-8]= 0000_0100 (SW11 is on the another side of the board)
- JP6 1-2
- on board Oscillator: 66M
-
-1.3 Since different board/chip rev. combinations have AC timing issues,
- u-boot forces RGMII-ID (RGMII with Internal Delay) mode on by default
- by the patch (mpc83xx: Disable G1TXCLK, G2TXCLK h/w buffers).
-
- When the rev2.x silicon mount on these boards, and if you are using
- u-boot version after this patch, to make the ethernet interfaces usable,
- and to enable RGMII-ID on your board, you have to setup the jumpers
- correctly.
-
- * MPC8360E-MDS-PB PROTO
- nothing to do
- * MPC8360E-MDS-PB PILOT
- JP9 and JP8 should be ON
- * MPC8360EA-MDS-PB PROTO
- JP2 and JP3 should be ON
-
-2. Memory Map
-
-2.1. The memory map should look pretty much like this:
-
- 0x0000_0000 0x7fff_ffff DDR 2G
- 0x8000_0000 0x8fff_ffff PCI MEM prefetch 256M
- 0x9000_0000 0x9fff_ffff PCI MEM non-prefetch 256M
- 0xc000_0000 0xdfff_ffff Empty 512M
- 0xe000_0000 0xe01f_ffff Int Mem Reg Space 2M
- 0xe020_0000 0xe02f_ffff Empty 1M
- 0xe030_0000 0xe03f_ffff PCI IO 1M
- 0xe040_0000 0xefff_ffff Empty 252M
- 0xf000_0000 0xf3ff_ffff Local Bus SDRAM 64M
- 0xf400_0000 0xf7ff_ffff Empty 64M
- 0xf800_0000 0xf800_7fff BCSR on CS1 32K
- 0xf800_8000 0xf800_ffff PIB CS4 32K
- 0xf801_0000 0xf801_7fff PIB CS5 32K
- 0xfe00_0000 0xfeff_ffff FLASH on CS0 16M
-
-
-3. Definitions
-
-3.1 Explanation of NEW definitions in:
-
- include/configs/MPC8360EMDS.h
-
- CONFIG_MPC83xx MPC83xx family for both MPC8349 and MPC8360
- CONFIG_MPC8360 MPC8360 specific
- CONFIG_MPC8360EMDS MPC8360EMDS board specific
-
-4. Compilation
-
- MPC8360EMDS shipped with 33.33MHz or 66MHz oscillator(check U41 chip).
-
- Assuming you're using BASH shell:
-
- export CROSS_COMPILE=your-cross-compile-prefix
- cd u-boot
- make distclean
- make MPC8360EMDS_XX_config
- make
-
- MPC8360EMDS support ATM, PCI in host and slave mode.
-
- To make u-boot support ATM :
- 1) Make MPC8360EMDS_XX_ATM_config
-
- To make u-boot support PCI host 66M :
- 1) DIP SW support PCI mode as described in Section 1.1.
- 2) Make MPC8360EMDS_XX_HOST_66_config
-
- To make u-boot support PCI host 33M :
- 1) DIP SW setting is similar as Section 1.1, except for SW3[4] is 1
- 2) Make MPC8360EMDS_XX_HOST_33_config
-
- To make u-boot support PCI slave 66M :
- 1) DIP SW setting is similar as Section 1.1, except for SW9[3] is 1
- 2) Make MPC8360EMDS_XX_SLAVE_config
-
- (where XX is:
- 33 - 33.33MHz oscillator
- 66 - 66MHz oscillator)
-
-5. Downloading and Flashing Images
-
-5.0 Download over serial line using Kermit:
-
- loadb
- [Drop to kermit:
- ^\c
- send <u-boot-bin-image>
- c
- ]
-
-
- Or via tftp:
-
- tftp 10000 u-boot.bin
-
-5.1 Reflash U-boot Image using U-boot
-
- tftp 20000 u-boot.bin
- protect off fef00000 fef3ffff
- erase fef00000 fef3ffff
-
- cp.b 20000 fef00000 xxxx
-
- or
-
- cp.b 20000 fef00000 3ffff
-
-
-You have to supply the correct byte count with 'xxxx' from the TFTP result log.
-Maybe 3ffff will work too, that corresponds to the erased sectors.
-
-
-6. Notes
- 1) The console baudrate for MPC8360EMDS is 115200bps.
diff --git a/board/freescale/mpc8360emds/mpc8360emds.c b/board/freescale/mpc8360emds/mpc8360emds.c
deleted file mode 100644
index f0a55f8..0000000
--- a/board/freescale/mpc8360emds/mpc8360emds.c
+++ /dev/null
@@ -1,453 +0,0 @@
-/*
- * Copyright (C) 2006,2010-2011 Freescale Semiconductor, Inc.
- * Dave Liu <daveliu@freescale.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <ioports.h>
-#include <mpc83xx.h>
-#include <i2c.h>
-#include <miiphy.h>
-#include <phy.h>
-#include <fsl_mdio.h>
-#if defined(CONFIG_PCI)
-#include <pci.h>
-#endif
-#include <spd_sdram.h>
-#include <asm/mmu.h>
-#include <asm/io.h>
-#include <asm/mmu.h>
-#if defined(CONFIG_OF_LIBFDT)
-#include <libfdt.h>
-#endif
-#include <hwconfig.h>
-#include <fdt_support.h>
-#if defined(CONFIG_PQ_MDS_PIB)
-#include "../common/pq-mds-pib.h"
-#endif
-#include "../../../drivers/qe/uec.h"
-
-const qe_iop_conf_t qe_iop_conf_tab[] = {
- /* GETH1 */
- {0, 3, 1, 0, 1}, /* TxD0 */
- {0, 4, 1, 0, 1}, /* TxD1 */
- {0, 5, 1, 0, 1}, /* TxD2 */
- {0, 6, 1, 0, 1}, /* TxD3 */
- {1, 6, 1, 0, 3}, /* TxD4 */
- {1, 7, 1, 0, 1}, /* TxD5 */
- {1, 9, 1, 0, 2}, /* TxD6 */
- {1, 10, 1, 0, 2}, /* TxD7 */
- {0, 9, 2, 0, 1}, /* RxD0 */
- {0, 10, 2, 0, 1}, /* RxD1 */
- {0, 11, 2, 0, 1}, /* RxD2 */
- {0, 12, 2, 0, 1}, /* RxD3 */
- {0, 13, 2, 0, 1}, /* RxD4 */
- {1, 1, 2, 0, 2}, /* RxD5 */
- {1, 0, 2, 0, 2}, /* RxD6 */
- {1, 4, 2, 0, 2}, /* RxD7 */
- {0, 7, 1, 0, 1}, /* TX_EN */
- {0, 8, 1, 0, 1}, /* TX_ER */
- {0, 15, 2, 0, 1}, /* RX_DV */
- {0, 16, 2, 0, 1}, /* RX_ER */
- {0, 0, 2, 0, 1}, /* RX_CLK */
- {2, 9, 1, 0, 3}, /* GTX_CLK - CLK10 */
- {2, 8, 2, 0, 1}, /* GTX125 - CLK9 */
- /* GETH2 */
- {0, 17, 1, 0, 1}, /* TxD0 */
- {0, 18, 1, 0, 1}, /* TxD1 */
- {0, 19, 1, 0, 1}, /* TxD2 */
- {0, 20, 1, 0, 1}, /* TxD3 */
- {1, 2, 1, 0, 1}, /* TxD4 */
- {1, 3, 1, 0, 2}, /* TxD5 */
- {1, 5, 1, 0, 3}, /* TxD6 */
- {1, 8, 1, 0, 3}, /* TxD7 */
- {0, 23, 2, 0, 1}, /* RxD0 */
- {0, 24, 2, 0, 1}, /* RxD1 */
- {0, 25, 2, 0, 1}, /* RxD2 */
- {0, 26, 2, 0, 1}, /* RxD3 */
- {0, 27, 2, 0, 1}, /* RxD4 */
- {1, 12, 2, 0, 2}, /* RxD5 */
- {1, 13, 2, 0, 3}, /* RxD6 */
- {1, 11, 2, 0, 2}, /* RxD7 */
- {0, 21, 1, 0, 1}, /* TX_EN */
- {0, 22, 1, 0, 1}, /* TX_ER */
- {0, 29, 2, 0, 1}, /* RX_DV */
- {0, 30, 2, 0, 1}, /* RX_ER */
- {0, 31, 2, 0, 1}, /* RX_CLK */
- {2, 2, 1, 0, 2}, /* GTX_CLK = CLK10 */
- {2, 3, 2, 0, 1}, /* GTX125 - CLK4 */
-
- {0, 1, 3, 0, 2}, /* MDIO */
- {0, 2, 1, 0, 1}, /* MDC */
-
- {5, 0, 1, 0, 2}, /* UART2_SOUT */
- {5, 1, 2, 0, 3}, /* UART2_CTS */
- {5, 2, 1, 0, 1}, /* UART2_RTS */
- {5, 3, 2, 0, 2}, /* UART2_SIN */
-
- {0, 0, 0, 0, QE_IOP_TAB_END}, /* END of table */
-};
-
-/* Handle "mpc8360ea rev.2.1 erratum 2: RGMII Timing"? */
-static int board_handle_erratum2(void)
-{
- const immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
-
- return REVID_MAJOR(immr->sysconf.spridr) == 2 &&
- REVID_MINOR(immr->sysconf.spridr) == 1;
-}
-
-int board_early_init_f(void)
-{
- const immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
- u8 *bcsr = (u8 *)CONFIG_SYS_BCSR;
-
- /* Enable flash write */
- bcsr[0xa] &= ~0x04;
-
- /* Disable G1TXCLK, G2TXCLK h/w buffers (rev.2.x h/w bug workaround) */
- if (REVID_MAJOR(immr->sysconf.spridr) == 2)
- bcsr[0xe] = 0x30;
-
- /* Enable second UART */
- bcsr[0x9] &= ~0x01;
-
- if (board_handle_erratum2()) {
- void *immap = (immap_t *)(CONFIG_SYS_IMMR + 0x14a8);
-
- /*
- * IMMR + 0x14A8[4:5] = 11 (clk delay for UCC 2)
- * IMMR + 0x14A8[18:19] = 11 (clk delay for UCC 1)
- */
- setbits_be32(immap, 0x0c003000);
-
- /*
- * IMMR + 0x14AC[20:27] = 10101010
- * (data delay for both UCC's)
- */
- clrsetbits_be32(immap + 4, 0xff0, 0xaa0);
- }
- return 0;
-}
-
-int board_early_init_r(void)
-{
- gd_t *gd;
-#ifdef CONFIG_PQ_MDS_PIB
- pib_init();
-#endif
- /*
- * BAT6 is used for SDRAM when DDR size is 512MB or larger than 256MB
- * So re-setup PCI MEM space used BAT5 after relocated to DDR
- */
- gd = (gd_t *)(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
- if (gd->ram_size > CONFIG_MAX_MEM_MAPPED) {
- write_bat(DBAT5, CONFIG_SYS_DBAT6U, CONFIG_SYS_DBAT6L);
- write_bat(IBAT5, CONFIG_SYS_IBAT6U, CONFIG_SYS_IBAT6L);
- }
-
- return 0;
-}
-
-#ifdef CONFIG_UEC_ETH
-static uec_info_t uec_info[] = {
-#ifdef CONFIG_UEC_ETH1
- STD_UEC_INFO(1),
-#endif
-#ifdef CONFIG_UEC_ETH2
- STD_UEC_INFO(2),
-#endif
-};
-
-int board_eth_init(bd_t *bd)
-{
- if (board_handle_erratum2()) {
- int i;
-
- for (i = 0; i < ARRAY_SIZE(uec_info); i++) {
- uec_info[i].enet_interface_type =
- PHY_INTERFACE_MODE_RGMII_RXID;
- uec_info[i].speed = SPEED_1000;
- }
- }
- return uec_eth_init(bd, uec_info, ARRAY_SIZE(uec_info));
-}
-#endif /* CONFIG_UEC_ETH */
-
-#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
-extern void ddr_enable_ecc(unsigned int dram_size);
-#endif
-int fixed_sdram(void);
-static int sdram_init(unsigned int base);
-
-phys_size_t initdram(int board_type)
-{
- volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
- u32 msize = 0;
- u32 lbc_sdram_size;
-
- if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
- return -1;
-
- /* DDR SDRAM - Main SODIMM */
- im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR;
-#if defined(CONFIG_SPD_EEPROM)
- msize = spd_sdram();
-#else
- msize = fixed_sdram();
-#endif
-
-#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
- /*
- * Initialize DDR ECC byte
- */
- ddr_enable_ecc(msize * 1024 * 1024);
-#endif
- /*
- * Initialize SDRAM if it is on local bus.
- */
- lbc_sdram_size = sdram_init(msize * 1024 * 1024);
- if (!msize)
- msize = lbc_sdram_size;
-
- /* return total bus SDRAM size(bytes) -- DDR */
- return (msize * 1024 * 1024);
-}
-
-#if !defined(CONFIG_SPD_EEPROM)
-/*************************************************************************
- * fixed sdram init -- doesn't use serial presence detect.
- ************************************************************************/
-int fixed_sdram(void)
-{
- volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
- u32 msize = CONFIG_SYS_DDR_SIZE;
- u32 ddr_size = msize << 20;
- u32 ddr_size_log2 = __ilog2(ddr_size);
- u32 half_ddr_size = ddr_size >> 1;
-
- im->sysconf.ddrlaw[0].bar =
- CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
- im->sysconf.ddrlaw[0].ar =
- LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
-#if (CONFIG_SYS_DDR_SIZE != 256)
-#warning Currenly any ddr size other than 256 is not supported
-#endif
-#ifdef CONFIG_DDR_II
- im->ddr.csbnds[0].csbnds = CONFIG_SYS_DDR_CS0_BNDS;
- im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
- im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
- im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
- im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
- im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
- im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG;
- im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
- im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
- im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2;
- im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
- im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL;
-#else
-
-#if ((CONFIG_SYS_DDR_SDRAM_BASE & 0x00FFFFFF) != 0)
-#warning Chip select bounds is only configurable in 16MB increments
-#endif
- im->ddr.csbnds[0].csbnds =
- ((CONFIG_SYS_DDR_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
- (((CONFIG_SYS_DDR_SDRAM_BASE + half_ddr_size - 1) >>
- CSBNDS_EA_SHIFT) & CSBNDS_EA);
- im->ddr.csbnds[1].csbnds =
- (((CONFIG_SYS_DDR_SDRAM_BASE + half_ddr_size) >>
- CSBNDS_SA_SHIFT) & CSBNDS_SA) |
- (((CONFIG_SYS_DDR_SDRAM_BASE + ddr_size - 1) >>
- CSBNDS_EA_SHIFT) & CSBNDS_EA);
-
- im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
- im->ddr.cs_config[1] = CONFIG_SYS_DDR_CS1_CONFIG;
-
- im->ddr.cs_config[2] = 0;
- im->ddr.cs_config[3] = 0;
-
- im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
- im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
- im->ddr.sdram_cfg = CONFIG_SYS_DDR_CONTROL;
-
- im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
- im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
-#endif
- udelay(200);
- im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
-
- return msize;
-}
-#endif /*!CONFIG_SYS_SPD_EEPROM */
-
-int checkboard(void)
-{
- puts("Board: Freescale MPC8360EMDS\n");
- return 0;
-}
-
-/*
- * if MPC8360EMDS is soldered with SDRAM
- */
-#ifdef CONFIG_SYS_LB_SDRAM
-/*
- * Initialize SDRAM memory on the Local Bus.
- */
-
-static int sdram_init(unsigned int base)
-{
- volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
- fsl_lbc_t *lbc = LBC_BASE_ADDR;
- const int sdram_size = CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024;
- int rem = base % sdram_size;
- uint *sdram_addr;
-
- /* window base address should be aligned to the window size */
- if (rem)
- base = base - rem + sdram_size;
-
- /*
- * Setup BAT6 for SDRAM when DDR size is 512MB or larger than 256MB
- * After relocated to DDR, reuse BAT5 for PCI MEM space
- */
- if (base > CONFIG_MAX_MEM_MAPPED) {
- unsigned long batl = base | BATL_PP_10 | BATL_MEMCOHERENCE;
- unsigned long batu = base | BATU_BL_64M | BATU_VS | BATU_VP;
-
- /* Setup the BAT6 for SDRAM */
- write_bat(DBAT6, batu, batl);
- write_bat(IBAT6, batu, batl);
- }
-
- sdram_addr = (uint *)base;
- /*
- * Setup SDRAM Base and Option Registers
- */
- set_lbc_br(2, base | CONFIG_SYS_BR2);
- set_lbc_or(2, CONFIG_SYS_OR2);
- immap->sysconf.lblaw[2].bar = base;
- immap->sysconf.lblaw[2].ar = CONFIG_SYS_LBLAWAR2;
-
- /*setup mtrpt, lsrt and lbcr for LB bus */
- lbc->lbcr = CONFIG_SYS_LBC_LBCR;
- lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
- lbc->lsrt = CONFIG_SYS_LBC_LSRT;
- asm("sync");
-
- /*
- * Configure the SDRAM controller Machine Mode Register.
- */
- lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5; /* Normal Operation */
- lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_1; /* Precharge All Banks */
- asm("sync");
- *sdram_addr = 0xff;
- udelay(100);
-
- /*
- * We need do 8 times auto refresh operation.
- */
- lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_2;
- asm("sync");
- *sdram_addr = 0xff; /* 1 times */
- udelay(100);
- *sdram_addr = 0xff; /* 2 times */
- udelay(100);
- *sdram_addr = 0xff; /* 3 times */
- udelay(100);
- *sdram_addr = 0xff; /* 4 times */
- udelay(100);
- *sdram_addr = 0xff; /* 5 times */
- udelay(100);
- *sdram_addr = 0xff; /* 6 times */
- udelay(100);
- *sdram_addr = 0xff; /* 7 times */
- udelay(100);
- *sdram_addr = 0xff; /* 8 times */
- udelay(100);
-
- /* Mode register write operation */
- lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_4;
- asm("sync");
- *(sdram_addr + 0xcc) = 0xff;
- udelay(100);
-
- /* Normal operation */
- lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5 | 0x40000000;
- asm("sync");
- *sdram_addr = 0xff;
- udelay(100);
-
- /*
- * In non-aligned case we don't [normally] use that memory because
- * there is a hole.
- */
- if (rem)
- return 0;
- return CONFIG_SYS_LBC_SDRAM_SIZE;
-}
-#else
-static int sdram_init(unsigned int base) { return 0; }
-#endif
-
-#if defined(CONFIG_OF_BOARD_SETUP)
-static void ft_board_fixup_qe_usb(void *blob, bd_t *bd)
-{
- if (!hwconfig_subarg_cmp("qe_usb", "mode", "peripheral"))
- return;
-
- do_fixup_by_compat(blob, "fsl,mpc8323-qe-usb", "mode",
- "peripheral", sizeof("peripheral"), 1);
-}
-
-int ft_board_setup(void *blob, bd_t *bd)
-{
- ft_cpu_setup(blob, bd);
-#ifdef CONFIG_PCI
- ft_pci_setup(blob, bd);
-#endif
- ft_board_fixup_qe_usb(blob, bd);
- /*
- * mpc8360ea pb mds errata 2: RGMII timing
- * if on mpc8360ea rev. 2.1,
- * change both ucc phy-connection-types from rgmii-id to rgmii-rxid
- */
- if (board_handle_erratum2()) {
- int nodeoffset;
- const char *prop;
- int path;
-
- nodeoffset = fdt_path_offset(blob, "/aliases");
- if (nodeoffset >= 0) {
-#if defined(CONFIG_HAS_ETH0)
- /* fixup UCC 1 if using rgmii-id mode */
- prop = fdt_getprop(blob, nodeoffset, "ethernet0", NULL);
- if (prop) {
- path = fdt_path_offset(blob, prop);
- prop = fdt_getprop(blob, path,
- "phy-connection-type", 0);
- if (prop && (strcmp(prop, "rgmii-id") == 0))
- fdt_fixup_phy_connection(blob, path,
- PHY_INTERFACE_MODE_RGMII_RXID);
- }
-#endif
-#if defined(CONFIG_HAS_ETH1)
- /* fixup UCC 2 if using rgmii-id mode */
- prop = fdt_getprop(blob, nodeoffset, "ethernet1", NULL);
- if (prop) {
- path = fdt_path_offset(blob, prop);
- prop = fdt_getprop(blob, path,
- "phy-connection-type", 0);
- if (prop && (strcmp(prop, "rgmii-id") == 0))
- fdt_fixup_phy_connection(blob, path,
- PHY_INTERFACE_MODE_RGMII_RXID);
- }
-#endif
- }
- }
-
- return 0;
-}
-#endif
diff --git a/board/freescale/mpc8360emds/pci.c b/board/freescale/mpc8360emds/pci.c
deleted file mode 100644
index 71244df..0000000
--- a/board/freescale/mpc8360emds/pci.c
+++ /dev/null
@@ -1,147 +0,0 @@
-/*
- * Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * PCI Configuration space access support for MPC83xx PCI Bridge
- */
-
-#include <asm/mmu.h>
-#include <asm/io.h>
-#include <common.h>
-#include <mpc83xx.h>
-#include <pci.h>
-#include <i2c.h>
-#include <asm/fsl_i2c.h>
-#include "../common/pq-mds-pib.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static struct pci_region pci1_regions[] = {
- {
- bus_start: CONFIG_SYS_PCI1_MEM_BASE,
- phys_start: CONFIG_SYS_PCI1_MEM_PHYS,
- size: CONFIG_SYS_PCI1_MEM_SIZE,
- flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
- },
- {
- bus_start: CONFIG_SYS_PCI1_IO_BASE,
- phys_start: CONFIG_SYS_PCI1_IO_PHYS,
- size: CONFIG_SYS_PCI1_IO_SIZE,
- flags: PCI_REGION_IO
- },
- {
- bus_start: CONFIG_SYS_PCI1_MMIO_BASE,
- phys_start: CONFIG_SYS_PCI1_MMIO_PHYS,
- size: CONFIG_SYS_PCI1_MMIO_SIZE,
- flags: PCI_REGION_MEM
- },
-};
-
-#ifdef CONFIG_MPC83XX_PCI2
-static struct pci_region pci2_regions[] = {
- {
- bus_start: CONFIG_SYS_PCI2_MEM_BASE,
- phys_start: CONFIG_SYS_PCI2_MEM_PHYS,
- size: CONFIG_SYS_PCI2_MEM_SIZE,
- flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
- },
- {
- bus_start: CONFIG_SYS_PCI2_IO_BASE,
- phys_start: CONFIG_SYS_PCI2_IO_PHYS,
- size: CONFIG_SYS_PCI2_IO_SIZE,
- flags: PCI_REGION_IO
- },
- {
- bus_start: CONFIG_SYS_PCI2_MMIO_BASE,
- phys_start: CONFIG_SYS_PCI2_MMIO_PHYS,
- size: CONFIG_SYS_PCI2_MMIO_SIZE,
- flags: PCI_REGION_MEM
- },
-};
-#endif
-
-void pci_init_board(void)
-#ifdef CONFIG_PCISLAVE
-{
- volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
- volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
- volatile pcictrl83xx_t *pci_ctrl = &immr->pci_ctrl[0];
- struct pci_region *reg[] = { pci1_regions };
-
- /* Configure PCI Local Access Windows */
- pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
- pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_512M;
-
- pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
- pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_1M;
-
- mpc83xx_pci_init(1, reg);
-
- /*
- * Configure PCI Inbound Translation Windows
- */
- pci_ctrl[0].pitar0 = 0x0;
- pci_ctrl[0].pibar0 = 0x0;
- pci_ctrl[0].piwar0 = PIWAR_EN | PIWAR_RTT_SNOOP |
- PIWAR_WTT_SNOOP | PIWAR_IWS_4K;
-
- pci_ctrl[0].pitar1 = 0x0;
- pci_ctrl[0].pibar1 = 0x0;
- pci_ctrl[0].piebar1 = 0x0;
- pci_ctrl[0].piwar1 &= ~PIWAR_EN;
-
- pci_ctrl[0].pitar2 = 0x0;
- pci_ctrl[0].pibar2 = 0x0;
- pci_ctrl[0].piebar2 = 0x0;
- pci_ctrl[0].piwar2 &= ~PIWAR_EN;
-
- /* Unlock the configuration bit */
- mpc83xx_pcislave_unlock(0);
- printf("PCI: Agent mode enabled\n");
-}
-#else
-{
- volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
- volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
- volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
-#ifndef CONFIG_MPC83XX_PCI2
- struct pci_region *reg[] = { pci1_regions };
-#else
- struct pci_region *reg[] = { pci1_regions, pci2_regions };
-#endif
-
- /* initialize the PCA9555PW IO expander on the PIB board */
- pib_init();
-
-#if defined(CONFIG_PCI_66M)
- clk->occr = OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2;
- printf("PCI clock is 66MHz\n");
-#elif defined(CONFIG_PCI_33M)
- clk->occr = OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2 |
- OCCR_PCICD0 | OCCR_PCICD1 | OCCR_PCICD2 | OCCR_PCICR;
- printf("PCI clock is 33MHz\n");
-#else
- clk->occr = OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2;
- printf("PCI clock is 66MHz\n");
-#endif
- udelay(2000);
-
- /* Configure PCI Local Access Windows */
- pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
- pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_512M;
-
- pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
- pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_1M;
-
- udelay(2000);
-
-#ifndef CONFIG_MPC83XX_PCI2
- mpc83xx_pci_init(1, reg);
-#else
- mpc83xx_pci_init(2, reg);
-#endif
-}
-#endif /* CONFIG_PCISLAVE */
diff --git a/board/freescale/mpc8360erdk/Kconfig b/board/freescale/mpc8360erdk/Kconfig
deleted file mode 100644
index 5c9be7c..0000000
--- a/board/freescale/mpc8360erdk/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_MPC8360ERDK
-
-config SYS_BOARD
- default "mpc8360erdk"
-
-config SYS_VENDOR
- default "freescale"
-
-config SYS_CONFIG_NAME
- default "MPC8360ERDK"
-
-endif
diff --git a/board/freescale/mpc8360erdk/MAINTAINERS b/board/freescale/mpc8360erdk/MAINTAINERS
deleted file mode 100644
index e5b5995..0000000
--- a/board/freescale/mpc8360erdk/MAINTAINERS
+++ /dev/null
@@ -1,7 +0,0 @@
-MPC8360ERDK BOARD
-#M: Anton Vorontsov <avorontsov@ru.mvista.com>
-S: Orphan (since 2014-03)
-F: board/freescale/mpc8360erdk/
-F: include/configs/MPC8360ERDK.h
-F: configs/MPC8360ERDK_defconfig
-F: configs/MPC8360ERDK_33_defconfig
diff --git a/board/freescale/mpc8360erdk/Makefile b/board/freescale/mpc8360erdk/Makefile
deleted file mode 100644
index e2235c2..0000000
--- a/board/freescale/mpc8360erdk/Makefile
+++ /dev/null
@@ -1,9 +0,0 @@
-#
-# (C) Copyright 2006
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y += mpc8360erdk.o
-obj-$(CONFIG_CMD_NAND) += nand.o
diff --git a/board/freescale/mpc8360erdk/mpc8360erdk.c b/board/freescale/mpc8360erdk/mpc8360erdk.c
deleted file mode 100644
index 478f820..0000000
--- a/board/freescale/mpc8360erdk/mpc8360erdk.c
+++ /dev/null
@@ -1,350 +0,0 @@
-/*
- * Copyright (C) 2006 Freescale Semiconductor, Inc.
- * Dave Liu <daveliu@freescale.com>
- *
- * Copyright (C) 2007 Logic Product Development, Inc.
- * Peter Barada <peterb@logicpd.com>
- *
- * Copyright (C) 2007 MontaVista Software, Inc.
- * Anton Vorontsov <avorontsov@ru.mvista.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <ioports.h>
-#include <mpc83xx.h>
-#include <i2c.h>
-#include <miiphy.h>
-#include <asm/io.h>
-#include <asm/mmu.h>
-#include <pci.h>
-#include <libfdt.h>
-
-const qe_iop_conf_t qe_iop_conf_tab[] = {
- /* MDIO */
- {0, 1, 3, 0, 2}, /* MDIO */
- {0, 2, 1, 0, 1}, /* MDC */
-
- /* UCC1 - UEC (Gigabit) */
- {0, 3, 1, 0, 1}, /* TxD0 */
- {0, 4, 1, 0, 1}, /* TxD1 */
- {0, 5, 1, 0, 1}, /* TxD2 */
- {0, 6, 1, 0, 1}, /* TxD3 */
- {0, 9, 2, 0, 1}, /* RxD0 */
- {0, 10, 2, 0, 1}, /* RxD1 */
- {0, 11, 2, 0, 1}, /* RxD2 */
- {0, 12, 2, 0, 1}, /* RxD3 */
- {0, 7, 1, 0, 1}, /* TX_EN */
- {0, 8, 1, 0, 1}, /* TX_ER */
- {0, 15, 2, 0, 1}, /* RX_DV */
- {0, 0, 2, 0, 1}, /* RX_CLK */
- {2, 9, 1, 0, 3}, /* GTX_CLK - CLK10 */
- {2, 8, 2, 0, 1}, /* GTX125 - CLK9 */
-
- /* UCC2 - UEC (Gigabit) */
- {0, 17, 1, 0, 1}, /* TxD0 */
- {0, 18, 1, 0, 1}, /* TxD1 */
- {0, 19, 1, 0, 1}, /* TxD2 */
- {0, 20, 1, 0, 1}, /* TxD3 */
- {0, 23, 2, 0, 1}, /* RxD0 */
- {0, 24, 2, 0, 1}, /* RxD1 */
- {0, 25, 2, 0, 1}, /* RxD2 */
- {0, 26, 2, 0, 1}, /* RxD3 */
- {0, 21, 1, 0, 1}, /* TX_EN */
- {0, 22, 1, 0, 1}, /* TX_ER */
- {0, 29, 2, 0, 1}, /* RX_DV */
- {0, 31, 2, 0, 1}, /* RX_CLK */
- {2, 2, 1, 0, 2}, /* GTX_CLK - CLK10 */
- {2, 3, 2, 0, 1}, /* GTX125 - CLK4 */
-
- /* UCC7 - UEC */
- {4, 0, 1, 0, 1}, /* TxD0 */
- {4, 1, 1, 0, 1}, /* TxD1 */
- {4, 2, 1, 0, 1}, /* TxD2 */
- {4, 3, 1, 0, 1}, /* TxD3 */
- {4, 6, 2, 0, 1}, /* RxD0 */
- {4, 7, 2, 0, 1}, /* RxD1 */
- {4, 8, 2, 0, 1}, /* RxD2 */
- {4, 9, 2, 0, 1}, /* RxD3 */
- {4, 4, 1, 0, 1}, /* TX_EN */
- {4, 5, 1, 0, 1}, /* TX_ER */
- {4, 12, 2, 0, 1}, /* RX_DV */
- {4, 13, 2, 0, 1}, /* RX_ER */
- {4, 10, 2, 0, 1}, /* COL */
- {4, 11, 2, 0, 1}, /* CRS */
- {2, 18, 2, 0, 1}, /* TX_CLK - CLK19 */
- {2, 19, 2, 0, 1}, /* RX_CLK - CLK20 */
-
- /* UCC4 - UEC */
- {1, 14, 1, 0, 1}, /* TxD0 */
- {1, 15, 1, 0, 1}, /* TxD1 */
- {1, 16, 1, 0, 1}, /* TxD2 */
- {1, 17, 1, 0, 1}, /* TxD3 */
- {1, 20, 2, 0, 1}, /* RxD0 */
- {1, 21, 2, 0, 1}, /* RxD1 */
- {1, 22, 2, 0, 1}, /* RxD2 */
- {1, 23, 2, 0, 1}, /* RxD3 */
- {1, 18, 1, 0, 1}, /* TX_EN */
- {1, 19, 1, 0, 2}, /* TX_ER */
- {1, 26, 2, 0, 1}, /* RX_DV */
- {1, 27, 2, 0, 1}, /* RX_ER */
- {1, 24, 2, 0, 1}, /* COL */
- {1, 25, 2, 0, 1}, /* CRS */
- {2, 6, 2, 0, 1}, /* TX_CLK - CLK7 */
- {2, 7, 2, 0, 1}, /* RX_CLK - CLK8 */
-
- /* PCI1 */
- {5, 4, 2, 0, 3}, /* PCI_M66EN */
- {5, 5, 1, 0, 3}, /* PCI_INTA */
- {5, 6, 1, 0, 3}, /* PCI_RSTO */
- {5, 7, 3, 0, 3}, /* PCI_C_BE0 */
- {5, 8, 3, 0, 3}, /* PCI_C_BE1 */
- {5, 9, 3, 0, 3}, /* PCI_C_BE2 */
- {5, 10, 3, 0, 3}, /* PCI_C_BE3 */
- {5, 11, 3, 0, 3}, /* PCI_PAR */
- {5, 12, 3, 0, 3}, /* PCI_FRAME */
- {5, 13, 3, 0, 3}, /* PCI_TRDY */
- {5, 14, 3, 0, 3}, /* PCI_IRDY */
- {5, 15, 3, 0, 3}, /* PCI_STOP */
- {5, 16, 3, 0, 3}, /* PCI_DEVSEL */
- {5, 17, 0, 0, 0}, /* PCI_IDSEL */
- {5, 18, 3, 0, 3}, /* PCI_SERR */
- {5, 19, 3, 0, 3}, /* PCI_PERR */
- {5, 20, 3, 0, 3}, /* PCI_REQ0 */
- {5, 21, 2, 0, 3}, /* PCI_REQ1 */
- {5, 22, 2, 0, 3}, /* PCI_GNT2 */
- {5, 23, 3, 0, 3}, /* PCI_GNT0 */
- {5, 24, 1, 0, 3}, /* PCI_GNT1 */
- {5, 25, 1, 0, 3}, /* PCI_GNT2 */
- {5, 26, 0, 0, 0}, /* PCI_CLK0 */
- {5, 27, 0, 0, 0}, /* PCI_CLK1 */
- {5, 28, 0, 0, 0}, /* PCI_CLK2 */
- {5, 29, 0, 0, 3}, /* PCI_SYNC_OUT */
- {6, 0, 3, 0, 3}, /* PCI_AD0 */
- {6, 1, 3, 0, 3}, /* PCI_AD1 */
- {6, 2, 3, 0, 3}, /* PCI_AD2 */
- {6, 3, 3, 0, 3}, /* PCI_AD3 */
- {6, 4, 3, 0, 3}, /* PCI_AD4 */
- {6, 5, 3, 0, 3}, /* PCI_AD5 */
- {6, 6, 3, 0, 3}, /* PCI_AD6 */
- {6, 7, 3, 0, 3}, /* PCI_AD7 */
- {6, 8, 3, 0, 3}, /* PCI_AD8 */
- {6, 9, 3, 0, 3}, /* PCI_AD9 */
- {6, 10, 3, 0, 3}, /* PCI_AD10 */
- {6, 11, 3, 0, 3}, /* PCI_AD11 */
- {6, 12, 3, 0, 3}, /* PCI_AD12 */
- {6, 13, 3, 0, 3}, /* PCI_AD13 */
- {6, 14, 3, 0, 3}, /* PCI_AD14 */
- {6, 15, 3, 0, 3}, /* PCI_AD15 */
- {6, 16, 3, 0, 3}, /* PCI_AD16 */
- {6, 17, 3, 0, 3}, /* PCI_AD17 */
- {6, 18, 3, 0, 3}, /* PCI_AD18 */
- {6, 19, 3, 0, 3}, /* PCI_AD19 */
- {6, 20, 3, 0, 3}, /* PCI_AD20 */
- {6, 21, 3, 0, 3}, /* PCI_AD21 */
- {6, 22, 3, 0, 3}, /* PCI_AD22 */
- {6, 23, 3, 0, 3}, /* PCI_AD23 */
- {6, 24, 3, 0, 3}, /* PCI_AD24 */
- {6, 25, 3, 0, 3}, /* PCI_AD25 */
- {6, 26, 3, 0, 3}, /* PCI_AD26 */
- {6, 27, 3, 0, 3}, /* PCI_AD27 */
- {6, 28, 3, 0, 3}, /* PCI_AD28 */
- {6, 29, 3, 0, 3}, /* PCI_AD29 */
- {6, 30, 3, 0, 3}, /* PCI_AD30 */
- {6, 31, 3, 0, 3}, /* PCI_AD31 */
-
- /* NAND */
- {4, 18, 2, 0, 0}, /* NAND_RYnBY */
-
- /* DUART - UART2 */
- {5, 0, 1, 0, 2}, /* UART2_SOUT */
- {5, 2, 1, 0, 1}, /* UART2_RTS */
- {5, 3, 2, 0, 2}, /* UART2_SIN */
- {5, 1, 2, 0, 3}, /* UART2_CTS */
-
- /* UCC5 - UART3 */
- {3, 0, 1, 0, 1}, /* UART3_TX */
- {3, 4, 1, 0, 1}, /* UART3_RTS */
- {3, 6, 2, 0, 1}, /* UART3_RX */
- {3, 12, 2, 0, 0}, /* UART3_CTS */
- {3, 13, 2, 0, 0}, /* UCC5_CD */
-
- /* UCC6 - UART4 */
- {3, 14, 1, 0, 1}, /* UART4_TX */
- {3, 18, 1, 0, 1}, /* UART4_RTS */
- {3, 20, 2, 0, 1}, /* UART4_RX */
- {3, 26, 2, 0, 0}, /* UART4_CTS */
- {3, 27, 2, 0, 0}, /* UCC6_CD */
-
- /* Fujitsu MB86277 (MINT) graphics controller */
- {0, 30, 1, 0, 0}, /* nSRESET_GRAPHICS */
- {1, 5, 1, 0, 0}, /* nXRST_GRAPHICS */
- {1, 7, 1, 0, 0}, /* LVDS_BKLT_CTR */
- {2, 16, 1, 0, 0}, /* LVDS_BKLT_EN */
-
- /* AD7843 ADC/Touchscreen controller */
- {4, 14, 1, 0, 0}, /* SPI_nCS0 */
- {4, 28, 3, 0, 3}, /* SPI_MOSI */
- {4, 29, 3, 0, 3}, /* SPI_MISO */
- {4, 30, 3, 0, 3}, /* SPI_CLK */
-
- /* Freescale QUICC Engine USB Host Controller (FHCI) */
- {1, 2, 1, 0, 3}, /* USBOE */
- {1, 3, 1, 0, 3}, /* USBTP */
- {1, 8, 1, 0, 1}, /* USBTN */
- {1, 9, 2, 1, 3}, /* USBRP */
- {1, 10, 2, 0, 3}, /* USBRXD */
- {1, 11, 2, 1, 3}, /* USBRN */
- {2, 20, 2, 0, 1}, /* CLK21 */
- {4, 20, 1, 0, 0}, /* SPEED */
- {4, 21, 1, 0, 0}, /* SUSPND */
-
- /* END of table */
- {0, 0, 0, 0, QE_IOP_TAB_END},
-};
-
-int board_early_init_r(void)
-{
- void *reg = (void *)(CONFIG_SYS_IMMR + 0x14a8);
- u32 val;
-
- /*
- * Because of errata in the UCCs, we have to write to the reserved
- * registers to slow the clocks down.
- */
- val = in_be32(reg);
- /* UCC1 */
- val |= 0x00003000;
- /* UCC2 */
- val |= 0x0c000000;
- out_be32(reg, val);
-
- return 0;
-}
-
-int fixed_sdram(void)
-{
- volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
- u32 msize = 0;
- u32 ddr_size;
- u32 ddr_size_log2;
-
- msize = CONFIG_SYS_DDR_SIZE;
- for (ddr_size = msize << 20, ddr_size_log2 = 0;
- (ddr_size > 1); ddr_size = ddr_size >> 1, ddr_size_log2++) {
- if (ddr_size & 1)
- return -1;
- }
-
- im->sysconf.ddrlaw[0].ar =
- LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
-
- im->ddr.csbnds[0].csbnds = CONFIG_SYS_DDR_CS0_BNDS;
- im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
- im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
- im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
- im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
- im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
- im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG;
- im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
- im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
- im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2;
- im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
- im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL;
- udelay(200);
- im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
-
- return msize;
-}
-
-phys_size_t initdram(int board_type)
-{
-#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
- extern void ddr_enable_ecc(unsigned int dram_size);
-#endif
- volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
- u32 msize = 0;
-
- if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
- return -1;
-
- /* DDR SDRAM - Main SODIMM */
- im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR;
- msize = fixed_sdram();
-
-#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
- /*
- * Initialize DDR ECC byte
- */
- ddr_enable_ecc(msize * 1024 * 1024);
-#endif
-
- /* return total bus SDRAM size(bytes) -- DDR */
- return (msize * 1024 * 1024);
-}
-
-int checkboard(void)
-{
- puts("Board: Freescale/Logic MPC8360ERDK\n");
- return 0;
-}
-
-static struct pci_region pci_regions[] = {
- {
- .bus_start = CONFIG_SYS_PCI1_MEM_BASE,
- .phys_start = CONFIG_SYS_PCI1_MEM_PHYS,
- .size = CONFIG_SYS_PCI1_MEM_SIZE,
- .flags = PCI_REGION_MEM | PCI_REGION_PREFETCH,
- },
- {
- .bus_start = CONFIG_SYS_PCI1_MMIO_BASE,
- .phys_start = CONFIG_SYS_PCI1_MMIO_PHYS,
- .size = CONFIG_SYS_PCI1_MMIO_SIZE,
- .flags = PCI_REGION_MEM,
- },
- {
- .bus_start = CONFIG_SYS_PCI1_IO_BASE,
- .phys_start = CONFIG_SYS_PCI1_IO_PHYS,
- .size = CONFIG_SYS_PCI1_IO_SIZE,
- .flags = PCI_REGION_IO,
- },
-};
-
-void pci_init_board(void)
-{
- volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
- volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
- volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
- struct pci_region *reg[] = { pci_regions, };
-
-#if defined(CONFIG_PCI_33M)
- clk->occr = OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2 |
- OCCR_PCICD0 | OCCR_PCICD1 | OCCR_PCICD2 | OCCR_PCICR;
- printf("PCI clock is 33MHz\n");
-#else
- clk->occr = OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2;
- printf("PCI clock is 66MHz\n");
-#endif
-
- udelay(2000);
-
- /* Configure PCI Local Access Windows */
- pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
- pci_law[0].ar = LBLAWAR_EN | LBLAWAR_512MB;
-
- pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
- pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB;
-
- mpc83xx_pci_init(1, reg);
-}
-
-#if defined(CONFIG_OF_BOARD_SETUP)
-int ft_board_setup(void *blob, bd_t *bd)
-{
- ft_cpu_setup(blob, bd);
- ft_pci_setup(blob, bd);
-
- return 0;
-}
-#endif
diff --git a/board/freescale/mpc8360erdk/nand.c b/board/freescale/mpc8360erdk/nand.c
deleted file mode 100644
index 237c0c4..0000000
--- a/board/freescale/mpc8360erdk/nand.c
+++ /dev/null
@@ -1,89 +0,0 @@
-/*
- * MPC8360E-RDK support for the NAND on FSL UPM
- *
- * Copyright (C) 2007 MontaVista Software, Inc.
- * Anton Vorontsov <avorontsov@ru.mvista.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <config.h>
-#include <common.h>
-#include <asm/io.h>
-#include <asm/immap_83xx.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/fsl_upm.h>
-#include <nand.h>
-
-static struct immap *im = (struct immap *)CONFIG_SYS_IMMR;
-
-static const u32 upm_array[] = {
- 0x0ff03c30, 0x0ff03c30, 0x0ff03c34, 0x0ff33c30, /* Words 0 to 3 */
- 0xfff33c31, 0xfffffc30, 0xfffffc30, 0xfffffc30, /* Words 4 to 7 */
- 0x0faf3c30, 0x0faf3c30, 0x0faf3c30, 0x0fff3c34, /* Words 8 to 11 */
- 0xffff3c31, 0xfffffc30, 0xfffffc30, 0xfffffc30, /* Words 12 to 15 */
- 0x0fa3fc30, 0x0fa3fc30, 0x0fa3fc30, 0x0ff3fc34, /* Words 16 to 19 */
- 0xfff3fc31, 0xfffffc30, 0xfffffc30, 0xfffffc30, /* Words 20 to 23 */
- 0x0ff33c30, 0x0fa33c30, 0x0fa33c34, 0x0ff33c30, /* Words 24 to 27 */
- 0xfff33c31, 0xfff0fc30, 0xfff0fc30, 0xfff0fc30, /* Words 28 to 31 */
- 0xfff3fc30, 0xfff3fc30, 0xfff6fc30, 0xfffcfc30, /* Words 32 to 35 */
- 0xfffcfc30, 0xfffcfc30, 0xfffcfc30, 0xfffcfc30, /* Words 36 to 39 */
- 0xfffcfc30, 0xfffcfc30, 0xfffcfc30, 0xfffcfc30, /* Words 40 to 43 */
- 0xfffdfc30, 0xfffffc30, 0xfffffc30, 0xfffffc31, /* Words 44 to 47 */
- 0xfffffc30, 0xfffffc00, 0xfffffc00, 0xfffffc00, /* Words 48 to 51 */
- 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, /* Words 52 to 55 */
- 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, /* Words 56 to 59 */
- 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, /* Words 60 to 63 */
-};
-
-static void upm_setup(struct fsl_upm *upm)
-{
- int i;
-
- /* write upm array */
- out_be32(upm->mxmr, MxMR_OP_WARR);
-
- for (i = 0; i < 64; i++) {
- out_be32(upm->mdr, upm_array[i]);
- out_8(upm->io_addr, 0x0);
- }
-
- /* normal operation */
- out_be32(upm->mxmr, MxMR_OP_NORM);
- while (in_be32(upm->mxmr) != MxMR_OP_NORM)
- eieio();
-}
-
-static int dev_ready(int chip_nr)
-{
- if (in_be32(&im->qepio.ioport[4].pdat) & 0x00002000) {
- debug("nand ready\n");
- return 1;
- }
-
- debug("nand busy\n");
- return 0;
-}
-
-static struct fsl_upm_nand fun = {
- .upm = {
- .io_addr = (void *)CONFIG_SYS_NAND_BASE,
- },
- .width = 8,
- .upm_cmd_offset = 8,
- .upm_addr_offset = 16,
- .dev_ready = dev_ready,
- .wait_flags = FSL_UPM_WAIT_RUN_PATTERN,
- .chip_delay = 50,
-};
-
-int board_nand_init(struct nand_chip *nand)
-{
- fun.upm.mxmr = &im->im_lbc.mamr;
- fun.upm.mdr = &im->im_lbc.mdr;
- fun.upm.mar = &im->im_lbc.mar;
-
- upm_setup(&fun.upm);
-
- return fsl_upm_nand_init(nand, &fun);
-}
diff --git a/configs/MPC8360EMDS_33_ATM_defconfig b/configs/MPC8360EMDS_33_ATM_defconfig
deleted file mode 100644
index dc325b1..0000000
--- a/configs/MPC8360EMDS_33_ATM_defconfig
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_SYS_EXTRA_OPTIONS="CLKIN_33MHZ,PQ_MDS_PIB=1,PQ_MDS_PIB_ATM=1"
-CONFIG_PPC=y
-CONFIG_MPC83xx=y
-CONFIG_TARGET_MPC8360EMDS=y
diff --git a/configs/MPC8360EMDS_33_HOST_33_defconfig b/configs/MPC8360EMDS_33_HOST_33_defconfig
deleted file mode 100644
index fba273d..0000000
--- a/configs/MPC8360EMDS_33_HOST_33_defconfig
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_SYS_EXTRA_OPTIONS="CLKIN_33MHZ,PCI,PCI_33M,PQ_MDS_PIB=1"
-CONFIG_PPC=y
-CONFIG_MPC83xx=y
-CONFIG_TARGET_MPC8360EMDS=y
diff --git a/configs/MPC8360EMDS_33_HOST_66_defconfig b/configs/MPC8360EMDS_33_HOST_66_defconfig
deleted file mode 100644
index e0cf6da..0000000
--- a/configs/MPC8360EMDS_33_HOST_66_defconfig
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_SYS_EXTRA_OPTIONS="CLKIN_33MHZ,PCI,PCI_66M,PQ_MDS_PIB=1"
-CONFIG_PPC=y
-CONFIG_MPC83xx=y
-CONFIG_TARGET_MPC8360EMDS=y
diff --git a/configs/MPC8360EMDS_33_SLAVE_defconfig b/configs/MPC8360EMDS_33_SLAVE_defconfig
deleted file mode 100644
index c3f74fc..0000000
--- a/configs/MPC8360EMDS_33_SLAVE_defconfig
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_SYS_EXTRA_OPTIONS="CLKIN_33MHZ,PCI,PCISLAVE"
-CONFIG_PPC=y
-CONFIG_MPC83xx=y
-CONFIG_TARGET_MPC8360EMDS=y
diff --git a/configs/MPC8360EMDS_33_defconfig b/configs/MPC8360EMDS_33_defconfig
deleted file mode 100644
index 60c6ddb..0000000
--- a/configs/MPC8360EMDS_33_defconfig
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_SYS_EXTRA_OPTIONS="CLKIN_33MHZ"
-CONFIG_PPC=y
-CONFIG_MPC83xx=y
-CONFIG_TARGET_MPC8360EMDS=y
diff --git a/configs/MPC8360EMDS_66_ATM_defconfig b/configs/MPC8360EMDS_66_ATM_defconfig
deleted file mode 100644
index 16f12fb..0000000
--- a/configs/MPC8360EMDS_66_ATM_defconfig
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_SYS_EXTRA_OPTIONS="CLKIN_66MHZ,PQ_MDS_PIB=1,PQ_MDS_PIB_ATM=1"
-CONFIG_PPC=y
-CONFIG_MPC83xx=y
-CONFIG_TARGET_MPC8360EMDS=y
diff --git a/configs/MPC8360EMDS_66_HOST_33_defconfig b/configs/MPC8360EMDS_66_HOST_33_defconfig
deleted file mode 100644
index 797a584..0000000
--- a/configs/MPC8360EMDS_66_HOST_33_defconfig
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_SYS_EXTRA_OPTIONS="CLKIN_66MHZ,PCI,PCI_33M,PQ_MDS_PIB=1"
-CONFIG_PPC=y
-CONFIG_MPC83xx=y
-CONFIG_TARGET_MPC8360EMDS=y
diff --git a/configs/MPC8360EMDS_66_HOST_66_defconfig b/configs/MPC8360EMDS_66_HOST_66_defconfig
deleted file mode 100644
index a887c29..0000000
--- a/configs/MPC8360EMDS_66_HOST_66_defconfig
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_SYS_EXTRA_OPTIONS="CLKIN_66MHZ,PCI,PCI_66M,PQ_MDS_PIB=1"
-CONFIG_PPC=y
-CONFIG_MPC83xx=y
-CONFIG_TARGET_MPC8360EMDS=y
diff --git a/configs/MPC8360EMDS_66_SLAVE_defconfig b/configs/MPC8360EMDS_66_SLAVE_defconfig
deleted file mode 100644
index 4442c61..0000000
--- a/configs/MPC8360EMDS_66_SLAVE_defconfig
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_SYS_EXTRA_OPTIONS="CLKIN_66MHZ,PCI,PCISLAVE"
-CONFIG_PPC=y
-CONFIG_MPC83xx=y
-CONFIG_TARGET_MPC8360EMDS=y
diff --git a/configs/MPC8360EMDS_66_defconfig b/configs/MPC8360EMDS_66_defconfig
deleted file mode 100644
index fce95dd..0000000
--- a/configs/MPC8360EMDS_66_defconfig
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_SYS_EXTRA_OPTIONS="CLKIN_66MHZ"
-CONFIG_PPC=y
-CONFIG_MPC83xx=y
-CONFIG_TARGET_MPC8360EMDS=y
diff --git a/configs/MPC8360ERDK_33_defconfig b/configs/MPC8360ERDK_33_defconfig
deleted file mode 100644
index 91c47b7..0000000
--- a/configs/MPC8360ERDK_33_defconfig
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_SYS_EXTRA_OPTIONS="CLKIN_33MHZ"
-CONFIG_PPC=y
-CONFIG_MPC83xx=y
-CONFIG_TARGET_MPC8360ERDK=y
diff --git a/configs/MPC8360ERDK_defconfig b/configs/MPC8360ERDK_defconfig
deleted file mode 100644
index 7e9fa59..0000000
--- a/configs/MPC8360ERDK_defconfig
+++ /dev/null
@@ -1,3 +0,0 @@
-CONFIG_PPC=y
-CONFIG_MPC83xx=y
-CONFIG_TARGET_MPC8360ERDK=y
diff --git a/doc/README.scrapyard b/doc/README.scrapyard
index b79c5a4..3b201b7 100644
--- a/doc/README.scrapyard
+++ b/doc/README.scrapyard
@@ -12,11 +12,13 @@ The list should be sorted in reverse chronological order.
Board Arch CPU Commit Removed Last known maintainer/contact
=================================================================================================
-P3G4 powerpc 74xx_7xx - - Wolfgang Denk <wd@denx.de>
-ZUMA powerpc 74xx_7xx - - Nye Liu <nyet@zumanetworks.com>
-ppmc7xx powerpc 74xx_7xx - -
-ELPPC powerpc 74xx_7xx - -
-mpc7448hpc2 powerpc 74xx_7xx - - Roy Zang <tie-fei.zang@freescale.com>
+MPC8360EMDS powerpc mpc83xx - - Dave Liu <daveliu@freescale.com>
+MPC8360ERDK powerpc mpc83xx - - Anton Vorontsov <avorontsov@ru.mvista.com>
+P3G4 powerpc 74xx_7xx d928664f 2015-01-16 Wolfgang Denk <wd@denx.de>
+ZUMA powerpc 74xx_7xx d928664f 2015-01-16 Nye Liu <nyet@zumanetworks.com>
+ppmc7xx powerpc 74xx_7xx d928664f 2015-01-16
+ELPPC powerpc 74xx_7xx d928664f 2015-01-16
+mpc7448hpc2 powerpc 74xx_7xx d928664f 2015-01-16 Roy Zang <tie-fei.zang@freescale.com>
CPCI405 ppc4xx 405gp 5f1459dc 2015-01-13 Matthias Fuchs <matthias.fuchs@esd.eu>
CPCI405DT ppc4xx 405gpr 5f1459dc 2015-01-13 Matthias Fuchs <matthias.fuchs@esd.eu>
CPCI405AB ppc4xx 405gpr 5f1459dc 2015-01-13 Matthias Fuchs <matthias.fuchs@esd.eu>
diff --git a/include/configs/MPC8360EMDS.h b/include/configs/MPC8360EMDS.h
deleted file mode 100644
index aefde74..0000000
--- a/include/configs/MPC8360EMDS.h
+++ /dev/null
@@ -1,735 +0,0 @@
-/*
- * Copyright (C) 2006,2011 Freescale Semiconductor, Inc.
- *
- * Dave Liu <daveliu@freescale.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- */
-#define CONFIG_E300 1 /* E300 family */
-#define CONFIG_QE 1 /* Has QE */
-#define CONFIG_MPC8360 1 /* MPC8360 CPU specific */
-#define CONFIG_MPC8360EMDS 1 /* MPC8360EMDS board specific */
-
-#define CONFIG_SYS_TEXT_BASE 0xFE000000
-
-#undef CONFIG_PQ_MDS_PIB /* POWERQUICC MDS Platform IO Board */
-#undef CONFIG_PQ_MDS_PIB_ATM /* QOC3 ATM card */
-
-/*
- * System Clock Setup
- */
-#ifdef CONFIG_CLKIN_33MHZ
-#ifdef CONFIG_PCISLAVE
-#define CONFIG_83XX_PCICLK 33330000 /* in HZ */
-#else
-#define CONFIG_83XX_CLKIN 33330000 /* in Hz */
-#endif
-
-#ifndef CONFIG_SYS_CLK_FREQ
-#define CONFIG_SYS_CLK_FREQ 33330000
-#endif
-
-#elif defined(CONFIG_CLKIN_66MHZ)
-#ifdef CONFIG_PCISLAVE
-#define CONFIG_83XX_PCICLK 66000000 /* in HZ */
-#else
-#define CONFIG_83XX_CLKIN 66000000 /* in Hz */
-#endif
-
-#ifndef CONFIG_SYS_CLK_FREQ
-#define CONFIG_SYS_CLK_FREQ 66000000
-#endif
-#else
-#error Unknown oscillator frequency.
-#endif
-
-/*
- * Hardware Reset Configuration Word
- */
-#ifdef CONFIG_CLKIN_33MHZ
-#define CONFIG_SYS_HRCW_LOW (\
- HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
- HRCWL_DDR_TO_SCB_CLK_1X1 |\
- HRCWL_CSB_TO_CLKIN_8X1 |\
- HRCWL_VCO_1X2 |\
- HRCWL_CE_PLL_VCO_DIV_4 |\
- HRCWL_CE_PLL_DIV_1X1 |\
- HRCWL_CE_TO_PLL_1X15 |\
- HRCWL_CORE_TO_CSB_2X1)
-#elif defined(CONFIG_CLKIN_66MHZ)
-#define CONFIG_SYS_HRCW_LOW (\
- HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
- HRCWL_DDR_TO_SCB_CLK_1X1 |\
- HRCWL_CSB_TO_CLKIN_4X1 |\
- HRCWL_VCO_1X2 |\
- HRCWL_CE_PLL_VCO_DIV_4 |\
- HRCWL_CE_PLL_DIV_1X1 |\
- HRCWL_CE_TO_PLL_1X6 |\
- HRCWL_CORE_TO_CSB_2X1)
-#endif
-
-#ifdef CONFIG_PCISLAVE
-#define CONFIG_SYS_HRCW_HIGH (\
- HRCWH_PCI_AGENT |\
- HRCWH_PCI1_ARBITER_DISABLE |\
- HRCWH_PCICKDRV_DISABLE |\
- HRCWH_CORE_ENABLE |\
- HRCWH_FROM_0XFFF00100 |\
- HRCWH_BOOTSEQ_DISABLE |\
- HRCWH_SW_WATCHDOG_DISABLE |\
- HRCWH_ROM_LOC_LOCAL_16BIT)
-#else
-#define CONFIG_SYS_HRCW_HIGH (\
- HRCWH_PCI_HOST |\
- HRCWH_PCI1_ARBITER_ENABLE |\
- HRCWH_PCICKDRV_ENABLE |\
- HRCWH_CORE_ENABLE |\
- HRCWH_FROM_0X00000100 |\
- HRCWH_BOOTSEQ_DISABLE |\
- HRCWH_SW_WATCHDOG_DISABLE |\
- HRCWH_ROM_LOC_LOCAL_16BIT)
-#endif
-
-/*
- * System IO Config
- */
-#define CONFIG_SYS_SICRH 0x00000000
-#define CONFIG_SYS_SICRL 0x40000000
-
-#define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */
-#define CONFIG_BOARD_EARLY_INIT_R
-
-/*
- * IMMR new address
- */
-#define CONFIG_SYS_IMMR 0xE0000000
-
-/*
- * DDR Setup
- */
-#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */
-#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
- /* + 256M */
-#define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000)
-#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
-#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \
- | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
-
-#define CONFIG_SYS_83XX_DDR_USES_CS0
-
-#define CONFIG_DDR_ECC /* support DDR ECC function */
-#define CONFIG_DDR_ECC_CMD /* Use DDR ECC user commands */
-
-/*
- * DDRCDR - DDR Control Driver Register
- */
-#define CONFIG_SYS_DDRCDR_VALUE 0x80080001
-
-#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
-#if defined(CONFIG_SPD_EEPROM)
-/*
- * Determine DDR configuration from I2C interface.
- */
-#define SPD_EEPROM_ADDRESS 0x52 /* DDR SODIMM */
-#else
-/*
- * Manually set up DDR parameters
- */
-#define CONFIG_SYS_DDR_SIZE 256 /* MB */
-#if defined(CONFIG_DDR_II)
-#define CONFIG_SYS_DDRCDR 0x80080001
-#define CONFIG_SYS_DDR_CS0_BNDS 0x0000000f
-#define CONFIG_SYS_DDR_CS0_CONFIG 0x80330102
-#define CONFIG_SYS_DDR_TIMING_0 0x00220802
-#define CONFIG_SYS_DDR_TIMING_1 0x38357322
-#define CONFIG_SYS_DDR_TIMING_2 0x2f9048c8
-#define CONFIG_SYS_DDR_TIMING_3 0x00000000
-#define CONFIG_SYS_DDR_CLK_CNTL 0x02000000
-#define CONFIG_SYS_DDR_MODE 0x47d00432
-#define CONFIG_SYS_DDR_MODE2 0x8000c000
-#define CONFIG_SYS_DDR_INTERVAL 0x03cf0080
-#define CONFIG_SYS_DDR_SDRAM_CFG 0x43000000
-#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000
-#else
-#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
- | CSCONFIG_ROW_BIT_13 \
- | CSCONFIG_COL_BIT_9)
-#define CONFIG_SYS_DDR_CS1_CONFIG CONFIG_SYS_DDR_CS0_CONFIG
-#define CONFIG_SYS_DDR_TIMING_1 0x37344321 /* tCL-tRCD-tRP-tRAS=2.5-3-3-7 */
-#define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* may need tuning */
-#define CONFIG_SYS_DDR_CONTROL 0x42008000 /* Self refresh,2T timing */
-#define CONFIG_SYS_DDR_MODE 0x20000162 /* DLL,normal,seq,4/2.5 */
-#define CONFIG_SYS_DDR_INTERVAL 0x045b0100 /* page mode */
-#endif
-#endif
-
-/*
- * Memory test
- */
-#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
-#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */
-#define CONFIG_SYS_MEMTEST_END 0x00100000
-
-/*
- * The reserved memory
- */
-
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
-
-#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
-#define CONFIG_SYS_RAMBOOT
-#else
-#undef CONFIG_SYS_RAMBOOT
-#endif
-
-/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
-#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */
-#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */
-
-/*
- * Initial RAM Base Address Setup
- */
-#define CONFIG_SYS_INIT_RAM_LOCK 1
-#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
-#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
-#define CONFIG_SYS_GBL_DATA_OFFSET \
- (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-
-/*
- * Local Bus Configuration & Clock Setup
- */
-#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
-#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4
-#define CONFIG_SYS_LBC_LBCR 0x00000000
-
-/*
- * FLASH on the Local Bus
- */
-#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
-#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
-#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */
-#define CONFIG_SYS_FLASH_SIZE 32 /* max FLASH size is 32M */
-#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */
-#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
-
- /* Window base at flash base */
-#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_32MB)
-
-#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
- | BR_PS_16 /* 16 bit port */ \
- | BR_MS_GPCM /* MSEL = GPCM */ \
- | BR_V) /* valid */
-#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
- | OR_GPCM_XAM \
- | OR_GPCM_CSNT \
- | OR_GPCM_ACS_DIV2 \
- | OR_GPCM_XACS \
- | OR_GPCM_SCY_15 \
- | OR_GPCM_TRLX_SET \
- | OR_GPCM_EHTR_SET \
- | OR_GPCM_EAD)
-
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */
-
-#undef CONFIG_SYS_FLASH_CHECKSUM
-
-/*
- * BCSR on the Local Bus
- */
-#define CONFIG_SYS_BCSR 0xF8000000
- /* Access window base at BCSR base */
-#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_BCSR
-#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_64KB)
-
-#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_BCSR \
- | BR_PS_8 \
- | BR_MS_GPCM \
- | BR_V)
-#define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB \
- | OR_GPCM_XAM \
- | OR_GPCM_CSNT \
- | OR_GPCM_XACS \
- | OR_GPCM_SCY_15 \
- | OR_GPCM_TRLX_SET \
- | OR_GPCM_EHTR_SET \
- | OR_GPCM_EAD)
- /* 0xFFFFE9F7 */
-
-/*
- * SDRAM on the Local Bus
- */
-#define CONFIG_SYS_LBC_SDRAM_BASE 0xF0000000 /* SDRAM base address */
-#define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
-
-#define CONFIG_SYS_LB_SDRAM /* if board has SRDAM on local bus */
-
-#ifdef CONFIG_SYS_LB_SDRAM
-#define CONFIG_SYS_LBLAWBAR2 0
-#define CONFIG_SYS_LBLAWAR2 (LBLAWAR_EN | LBLAWAR_64MB)
-
-/*local bus BR2, OR2 definition for SDRAM if soldered on the EPB board */
-/*
- * Base Register 2 and Option Register 2 configure SDRAM.
- *
- * For BR2, need:
- * Base address = BR[0:16] = dynamic
- * port size = 32-bits = BR2[19:20] = 11
- * no parity checking = BR2[21:22] = 00
- * SDRAM for MSEL = BR2[24:26] = 011
- * Valid = BR[31] = 1
- *
- * 0 4 8 12 16 20 24 28
- * xxxx xxxx xxxx xxxx x001 1000 0110 0001 = 00001861
- */
-
-/* Port size=32bit, MSEL=DRAM */
-#define CONFIG_SYS_BR2 (BR_PS_32 | BR_MS_SDRAM | BR_V) /* 0xF0001861 */
-
-/*
- * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
- *
- * For OR2, need:
- * 64MB mask for AM, OR2[0:7] = 1111 1100
- * XAM, OR2[17:18] = 11
- * 9 columns OR2[19-21] = 010
- * 13 rows OR2[23-25] = 100
- * EAD set for extra time OR[31] = 1
- *
- * 0 4 8 12 16 20 24 28
- * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
- */
-
-#define CONFIG_SYS_OR2 (MEG_TO_AM(CONFIG_SYS_LBC_SDRAM_SIZE) \
- | OR_SDRAM_XAM \
- | ((9 - OR_SDRAM_MIN_COLS) << OR_SDRAM_COLS_SHIFT) \
- | ((13 - OR_SDRAM_MIN_ROWS) << OR_SDRAM_ROWS_SHIFT) \
- | OR_SDRAM_EAD)
- /* 0xFC006901 */
-
- /* LB sdram refresh timer, about 6us */
-#define CONFIG_SYS_LBC_LSRT 0x32000000
- /* LB refresh timer prescal, 266MHz/32 */
-#define CONFIG_SYS_LBC_MRTPR 0x20000000
-
-#define CONFIG_SYS_LBC_LSDMR_COMMON 0x0063b723
-
-/*
- * SDRAM Controller configuration sequence.
- */
-#define CONFIG_SYS_LBC_LSDMR_1 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL)
-#define CONFIG_SYS_LBC_LSDMR_2 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
-#define CONFIG_SYS_LBC_LSDMR_3 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
-#define CONFIG_SYS_LBC_LSDMR_4 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW)
-#define CONFIG_SYS_LBC_LSDMR_5 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL)
-
-#endif
-
-/*
- * Windows to access Platform I/O Boards (PIB) via local bus
- */
-#define CONFIG_SYS_PIB_BASE 0xF8008000
-#define CONFIG_SYS_PIB_WINDOW_SIZE (32 * 1024)
-
-/* [RFC] This LBLAW only covers the 2nd window (CS5) */
-#define CONFIG_SYS_LBLAWBAR3_PRELIM \
- CONFIG_SYS_PIB_BASE + CONFIG_SYS_PIB_WINDOW_SIZE
-#define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_32KB)
-
-/*
- * CS4 on Local Bus, to PIB
- */
- /* CS4 base address at 0xf8008000 */
-#define CONFIG_SYS_BR4_PRELIM (CONFIG_SYS_PIB_BASE \
- | BR_PS_8 \
- | BR_MS_GPCM \
- | BR_V)
- /* 0xF8008801 */
-#define CONFIG_SYS_OR4_PRELIM (OR_AM_32KB \
- | OR_GPCM_XAM \
- | OR_GPCM_CSNT \
- | OR_GPCM_XACS \
- | OR_GPCM_SCY_15 \
- | OR_GPCM_TRLX_SET \
- | OR_GPCM_EHTR_SET \
- | OR_GPCM_EAD)
- /* 0xffffe9f7 */
-
-/*
- * CS5 on Local Bus, to PIB
- */
- /* CS5 base address at 0xf8010000 */
-#define CONFIG_SYS_BR5_PRELIM ((CONFIG_SYS_PIB_BASE + \
- CONFIG_SYS_PIB_WINDOW_SIZE) \
- | BR_PS_8 \
- | BR_MS_GPCM \
- | BR_V)
- /* 0xF8010801 */
-#define CONFIG_SYS_OR5_PRELIM (CONFIG_SYS_PIB_BASE \
- | OR_GPCM_XAM \
- | OR_GPCM_CSNT \
- | OR_GPCM_XACS \
- | OR_GPCM_SCY_15 \
- | OR_GPCM_TRLX_SET \
- | OR_GPCM_EHTR_SET \
- | OR_GPCM_EAD)
- /* 0xffffe9f7 */
-
-/*
- * Serial Port
- */
-#define CONFIG_CONS_INDEX 1
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
-
-#define CONFIG_SYS_BAUDRATE_TABLE \
- {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
-
-#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
-#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
-
-#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
-#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
-/* Use the HUSH parser */
-#define CONFIG_SYS_HUSH_PARSER
-
-/* pass open firmware flat tree */
-#define CONFIG_OF_LIBFDT 1
-#define CONFIG_OF_BOARD_SETUP 1
-#define CONFIG_OF_STDOUT_VIA_ALIAS 1
-
-/* I2C */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_FSL
-#define CONFIG_SYS_FSL_I2C_SPEED 400000
-#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
-#define CONFIG_SYS_I2C_NOPROBES { {0, 0x52} }
-
-/*
- * Config on-board RTC
- */
-#define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */
-#define CONFIG_SYS_I2C_RTC_ADDR 0x68 /*@address 0x68 */
-
-/*
- * General PCI
- * Addresses are mapped 1-1.
- */
-#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
-#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
-#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
-#define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
-#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
-#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
-#define CONFIG_SYS_PCI1_IO_BASE 0x00000000
-#define CONFIG_SYS_PCI1_IO_PHYS 0xE0300000
-#define CONFIG_SYS_PCI1_IO_SIZE 0x100000 /* 1M */
-
-#define CONFIG_SYS_PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE
-#define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000
-#define CONFIG_SYS_PCI_SLV_MEM_SIZE 0x80000000
-
-
-#ifdef CONFIG_PCI
-#define CONFIG_PCI_INDIRECT_BRIDGE
-
-#define CONFIG_PCI_PNP /* do pci plug-and-play */
-#define CONFIG_83XX_PCI_STREAMING
-
-#undef CONFIG_EEPRO100
-#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
-#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
-
-#endif /* CONFIG_PCI */
-
-
-#define CONFIG_HWCONFIG 1
-
-/*
- * QE UEC ethernet configuration
- */
-#define CONFIG_UEC_ETH
-#define CONFIG_ETHPRIME "UEC0"
-#define CONFIG_PHY_MODE_NEED_CHANGE
-
-#define CONFIG_UEC_ETH1 /* GETH1 */
-
-#ifdef CONFIG_UEC_ETH1
-#define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */
-#define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE
-#define CONFIG_SYS_UEC1_TX_CLK QE_CLK9
-#define CONFIG_SYS_UEC1_ETH_TYPE GIGA_ETH
-#define CONFIG_SYS_UEC1_PHY_ADDR 0
-#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID
-#define CONFIG_SYS_UEC1_INTERFACE_SPEED 1000
-#endif
-
-#define CONFIG_UEC_ETH2 /* GETH2 */
-
-#ifdef CONFIG_UEC_ETH2
-#define CONFIG_SYS_UEC2_UCC_NUM 1 /* UCC2 */
-#define CONFIG_SYS_UEC2_RX_CLK QE_CLK_NONE
-#define CONFIG_SYS_UEC2_TX_CLK QE_CLK4
-#define CONFIG_SYS_UEC2_ETH_TYPE GIGA_ETH
-#define CONFIG_SYS_UEC2_PHY_ADDR 1
-#define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID
-#define CONFIG_SYS_UEC2_INTERFACE_SPEED 1000
-#endif
-
-/*
- * Environment
- */
-
-#ifndef CONFIG_SYS_RAMBOOT
- #define CONFIG_ENV_IS_IN_FLASH 1
- #define CONFIG_ENV_ADDR \
- (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
- #define CONFIG_ENV_SECT_SIZE 0x20000
- #define CONFIG_ENV_SIZE 0x2000
-#else
- #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */
- #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
- #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
- #define CONFIG_ENV_SIZE 0x2000
-#endif
-
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_SDRAM
-
-#if defined(CONFIG_PCI)
- #define CONFIG_CMD_PCI
-#endif
-
-#if defined(CONFIG_SYS_RAMBOOT)
- #undef CONFIG_CMD_SAVEENV
- #undef CONFIG_CMD_LOADS
-#endif
-
-
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
-
-#if defined(CONFIG_CMD_KGDB)
- #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
- #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-
- /* Print Buffer Size */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
- /* Boot Argument Buffer Size */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 256 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */
-
-/*
- * Core HID Setup
- */
-#define CONFIG_SYS_HID0_INIT 0x000000000
-#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
- HID0_ENABLE_INSTRUCTION_CACHE)
-#define CONFIG_SYS_HID2 HID2_HBE
-
-/*
- * MMU Setup
- */
-
-#define CONFIG_HIGH_BATS 1 /* High BATs supported */
-#define CONFIG_BAT_RW
-
-/* DDR/LBC SDRAM: cacheable */
-#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \
- | BATL_PP_RW \
- | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \
- | BATU_BL_256M \
- | BATU_VS \
- | BATU_VP)
-#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
-#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
-
-/* IMMRBAR & PCI IO: cache-inhibit and guarded */
-#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR \
- | BATL_PP_RW \
- | BATL_CACHEINHIBIT \
- | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR \
- | BATU_BL_4M \
- | BATU_VS \
- | BATU_VP)
-#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
-#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
-
-/* BCSR: cache-inhibit and guarded */
-#define CONFIG_SYS_IBAT2L (CONFIG_SYS_BCSR \
- | BATL_PP_RW \
- | BATL_CACHEINHIBIT \
- | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT2U (CONFIG_SYS_BCSR \
- | BATU_BL_128K \
- | BATU_VS \
- | BATU_VP)
-#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
-#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
-
-/* FLASH: icache cacheable, but dcache-inhibit and guarded */
-#define CONFIG_SYS_IBAT3L (CONFIG_SYS_FLASH_BASE \
- | BATL_PP_RW \
- | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT3U (CONFIG_SYS_FLASH_BASE \
- | BATU_BL_32M \
- | BATU_VS \
- | BATU_VP)
-#define CONFIG_SYS_DBAT3L (CONFIG_SYS_FLASH_BASE \
- | BATL_PP_RW \
- | BATL_CACHEINHIBIT \
- | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
-
-/* DDR/LBC SDRAM next 256M: cacheable */
-#define CONFIG_SYS_IBAT4L (CONFIG_SYS_SDRAM_BASE2 \
- | BATL_PP_RW \
- | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT4U (CONFIG_SYS_SDRAM_BASE2 \
- | BATU_BL_256M \
- | BATU_VS \
- | BATU_VP)
-#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
-#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
-
-/* Stack in dcache: cacheable, no memory coherence */
-#define CONFIG_SYS_IBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
-#define CONFIG_SYS_IBAT5U (CONFIG_SYS_INIT_RAM_ADDR \
- | BATU_BL_128K \
- | BATU_VS \
- | BATU_VP)
-#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
-#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
-
-#ifdef CONFIG_PCI
-/* PCI MEM space: cacheable */
-#define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI1_MEM_PHYS \
- | BATL_PP_RW \
- | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI1_MEM_PHYS \
- | BATU_BL_256M \
- | BATU_VS \
- | BATU_VP)
-#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
-#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
-/* PCI MMIO space: cache-inhibit and guarded */
-#define CONFIG_SYS_IBAT7L (CONFIG_SYS_PCI1_MMIO_PHYS \
- | BATL_PP_RW \
- | BATL_CACHEINHIBIT \
- | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT7U (CONFIG_SYS_PCI1_MMIO_PHYS \
- | BATU_BL_256M \
- | BATU_VS \
- | BATU_VP)
-#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
-#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
-#else
-#define CONFIG_SYS_IBAT6L (0)
-#define CONFIG_SYS_IBAT6U (0)
-#define CONFIG_SYS_IBAT7L (0)
-#define CONFIG_SYS_IBAT7U (0)
-#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
-#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
-#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
-#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
-#endif
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
-#endif
-
-/*
- * Environment Configuration
- */
-
-#define CONFIG_ENV_OVERWRITE
-
-#if defined(CONFIG_UEC_ETH)
-#define CONFIG_HAS_ETH0
-#define CONFIG_HAS_ETH1
-#endif
-
-#define CONFIG_BAUDRATE 115200
-
-#define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */
-
-#define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */
-#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "netdev=eth0\0" \
- "consoledev=ttyS0\0" \
- "ramdiskaddr=1000000\0" \
- "ramdiskfile=ramfs.83xx\0" \
- "fdtaddr=780000\0" \
- "fdtfile=mpc836x_mds.dtb\0" \
- ""
-
-#define CONFIG_NFSBOOTCOMMAND \
- "setenv bootargs root=/dev/nfs rw " \
- "nfsroot=$serverip:$rootpath " \
- "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \
- "$netdev:off " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr - $fdtaddr"
-
-#define CONFIG_RAMBOOTCOMMAND \
- "setenv bootargs root=/dev/ram rw " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "tftp $ramdiskaddr $ramdiskfile;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr $ramdiskaddr $fdtaddr"
-
-
-#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/MPC8360ERDK.h b/include/configs/MPC8360ERDK.h
deleted file mode 100644
index 1b8bad1..0000000
--- a/include/configs/MPC8360ERDK.h
+++ /dev/null
@@ -1,620 +0,0 @@
-/*
- * Copyright (C) 2006 Freescale Semiconductor, Inc.
- * Dave Liu <daveliu@freescale.com>
- *
- * Copyright (C) 2007 Logic Product Development, Inc.
- * Peter Barada <peterb@logicpd.com>
- *
- * Copyright (C) 2007 MontaVista Software, Inc.
- * Anton Vorontsov <avorontsov@ru.mvista.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- */
-#define CONFIG_E300 1 /* E300 family */
-#define CONFIG_QE 1 /* Has QE */
-#define CONFIG_MPC8360 1 /* MPC8360 CPU specific */
-#define CONFIG_MPC8360ERDK 1 /* MPC8360ERDK board specific */
-
-#define CONFIG_SYS_TEXT_BASE 0xFF800000
-
-/*
- * System Clock Setup
- */
-#ifdef CONFIG_CLKIN_33MHZ
-#define CONFIG_83XX_CLKIN 33333333
-#define CONFIG_SYS_CLK_FREQ 33333333
-#define CONFIG_PCI_33M 1
-#define HRCWL_CSB_TO_CLKIN_MPC8360ERDK HRCWL_CSB_TO_CLKIN_10X1
-#else
-#define CONFIG_83XX_CLKIN 66000000
-#define CONFIG_SYS_CLK_FREQ 66000000
-#define CONFIG_PCI_66M 1
-#define HRCWL_CSB_TO_CLKIN_MPC8360ERDK HRCWL_CSB_TO_CLKIN_5X1
-#endif /* CONFIG_CLKIN_33MHZ */
-
-/*
- * Hardware Reset Configuration Word
- */
-#define CONFIG_SYS_HRCW_LOW (\
- HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
- HRCWL_DDR_TO_SCB_CLK_1X1 |\
- HRCWL_CSB_TO_CLKIN_MPC8360ERDK |\
- HRCWL_CORE_TO_CSB_2X1 |\
- HRCWL_CE_TO_PLL_1X15)
-
-#define CONFIG_SYS_HRCW_HIGH (\
- HRCWH_PCI_HOST |\
- HRCWH_PCI1_ARBITER_ENABLE |\
- HRCWH_PCICKDRV_ENABLE |\
- HRCWH_CORE_ENABLE |\
- HRCWH_FROM_0X00000100 |\
- HRCWH_BOOTSEQ_DISABLE |\
- HRCWH_SW_WATCHDOG_DISABLE |\
- HRCWH_ROM_LOC_LOCAL_16BIT |\
- HRCWH_SECONDARY_DDR_DISABLE |\
- HRCWH_BIG_ENDIAN |\
- HRCWH_LALE_EARLY)
-
-/*
- * System IO Config
- */
-#define CONFIG_SYS_SICRH 0x00000000
-#define CONFIG_SYS_SICRL 0x40000000
-
-#define CONFIG_BOARD_EARLY_INIT_R
-
-/*
- * IMMR new address
- */
-#define CONFIG_SYS_IMMR 0xE0000000
-
-/*
- * DDR Setup
- */
-#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */
-#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
-#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
-#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \
- | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
-
-#define CONFIG_SYS_83XX_DDR_USES_CS0
-
-#define CONFIG_DDR_ECC /* support DDR ECC function */
-#define CONFIG_DDR_ECC_CMD /* Use DDR ECC user commands */
-
-/*
- * DDRCDR - DDR Control Driver Register
- */
-#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_DHC_EN \
- | DDRCDR_ODT \
- | DDRCDR_Q_DRN)
- /* 0x80080001 */
-
-#undef CONFIG_SPD_EEPROM /* Do not use SPD EEPROM for DDR setup */
-
-/*
- * Manually set up DDR parameters
- */
-#define CONFIG_DDR_II
-#define CONFIG_SYS_DDR_SIZE 256 /* MB */
-#define CONFIG_SYS_DDR_CS0_BNDS 0x0000000f
-#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
- | CSCONFIG_ROW_BIT_13 \
- | CSCONFIG_COL_BIT_10 \
- | CSCONFIG_ODT_WR_ONLY_CURRENT)
-#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SDRAM_TYPE_DDR2 \
- | SDRAM_CFG_ECC_EN)
-#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00001000
-#define CONFIG_SYS_DDR_CLK_CNTL (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
-#define CONFIG_SYS_DDR_INTERVAL ((256 << SDRAM_INTERVAL_BSTOPRE_SHIFT) \
- | (1115 << SDRAM_INTERVAL_REFINT_SHIFT))
-#define CONFIG_SYS_DDR_MODE 0x47800432
-#define CONFIG_SYS_DDR_MODE2 0x8000c000
-
-#define CONFIG_SYS_DDR_TIMING_0 ((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \
- (9 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \
- (3 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \
- (3 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \
- (0 << TIMING_CFG0_WWT_SHIFT) | \
- (0 << TIMING_CFG0_RRT_SHIFT) | \
- (0 << TIMING_CFG0_WRT_SHIFT) | \
- (0 << TIMING_CFG0_RWT_SHIFT))
-
-#define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_30) | \
- (2 << TIMING_CFG1_WRTORD_SHIFT) | \
- (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \
- (3 << TIMING_CFG1_WRREC_SHIFT) | \
- (10 << TIMING_CFG1_REFREC_SHIFT) | \
- (3 << TIMING_CFG1_ACTTORW_SHIFT) | \
- (8 << TIMING_CFG1_ACTTOPRE_SHIFT) | \
- (3 << TIMING_CFG1_PRETOACT_SHIFT))
-
-#define CONFIG_SYS_DDR_TIMING_2 ((9 << TIMING_CFG2_FOUR_ACT_SHIFT) | \
- (4 << TIMING_CFG2_CKE_PLS_SHIFT) | \
- (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \
- (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \
- (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \
- (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \
- (0 << TIMING_CFG2_CPO_SHIFT))
-
-#define CONFIG_SYS_DDR_TIMING_3 0x00000000
-
-/*
- * Memory test
- */
-#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
-#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */
-#define CONFIG_SYS_MEMTEST_END 0x00100000
-
-/*
- * The reserved memory
- */
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
-#define CONFIG_SYS_FLASH_BASE 0xFF800000 /* FLASH base address */
-
-#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
-#define CONFIG_SYS_RAMBOOT
-#else
-#undef CONFIG_SYS_RAMBOOT
-#endif
-
-#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */
-#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */
-
-/*
- * Initial RAM Base Address Setup
- */
-#define CONFIG_SYS_INIT_RAM_LOCK 1
-#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
-#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
-#define CONFIG_SYS_GBL_DATA_OFFSET \
- (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-
-/*
- * Local Bus Configuration & Clock Setup
- */
-#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
-#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4
-#define CONFIG_SYS_LBC_LBCR 0x00000000
-
-/*
- * FLASH on the Local Bus
- */
-#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
-#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
-#define CONFIG_SYS_FLASH_SIZE 8 /* max FLASH size is 32M */
-#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use intel Flash protection. */
-
- /* Window base@flash base */
-#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_32MB)
-
-#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
- | BR_PS_16 /* 16 bit port */ \
- | BR_MS_GPCM /* MSEL = GPCM */ \
- | BR_V) /* valid */
-#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
- | OR_UPM_XAM \
- | OR_GPCM_CSNT \
- | OR_GPCM_ACS_DIV2 \
- | OR_GPCM_XACS \
- | OR_GPCM_SCY_15 \
- | OR_GPCM_TRLX_SET \
- | OR_GPCM_EHTR_SET \
- | OR_GPCM_EAD)
-
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */
-
-#undef CONFIG_SYS_FLASH_CHECKSUM
-
-/*
- * NAND flash on the local bus
- */
-#define CONFIG_SYS_NAND_BASE 0x60000000
-#define CONFIG_CMD_NAND 1
-#define CONFIG_NAND_FSL_UPM 1
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_MTD_NAND_VERIFY_WRITE
-
-#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE
-/*
- * [RFC] Comment said 4KB window; code said 256MB window; OR1 says 64MB
- * ... What's correct?
- */
-#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_256MB)
-
-/* Port size 8 bit, UPMA */
-#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_NAND_BASE \
- | BR_PS_8 \
- | BR_MS_UPMA \
- | BR_V)
- /* 0x60000881 */
-#define CONFIG_SYS_OR1_PRELIM (OR_AM_64MB | OR_UPM_EAD)
- /* 0xFC000001 */
-
-/*
- * Fujitsu MB86277 (MINT) graphics controller
- */
-#define CONFIG_SYS_VIDEO_BASE 0x70000000
-
-#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_VIDEO_BASE
-#define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_64MB)
-
-/* Port size 32 bit, UPMB */
-#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_VIDEO_BASE \
- | BR_PS_32 \
- | BR_MS_UPMB \
- | BR_V)
- /* 0x000018a1 */
-#define CONFIG_SYS_OR2_PRELIM (OR_AM_64MB | OR_UPM_EAD)
- /* 0xFC000001 */
-
-/*
- * Serial Port
- */
-#define CONFIG_CONS_INDEX 1
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
-
-#define CONFIG_SYS_BAUDRATE_TABLE \
- {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
-
-#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
-#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
-
-#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
-#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
-/* Use the HUSH parser */
-#define CONFIG_SYS_HUSH_PARSER
-
-/* Pass open firmware flat tree */
-#define CONFIG_OF_LIBFDT 1
-#define CONFIG_OF_BOARD_SETUP 1
-#define CONFIG_OF_STDOUT_VIA_ALIAS
-
-/* I2C */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_FSL
-#define CONFIG_SYS_FSL_I2C_SPEED 400000
-#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
-#define CONFIG_SYS_FSL_I2C2_SPEED 400000
-#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
-#define CONFIG_SYS_I2C_NOPROBES { {0, 0x52} }
-
-/*
- * General PCI
- * Addresses are mapped 1-1.
- */
-#define CONFIG_PCI
-
-#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
-#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
-#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
-#define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
-#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
-#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
-#define CONFIG_SYS_PCI1_IO_BASE 0xE0300000
-#define CONFIG_SYS_PCI1_IO_PHYS 0xE0300000
-#define CONFIG_SYS_PCI1_IO_SIZE 0x100000 /* 1M */
-
-#ifdef CONFIG_PCI
-#define CONFIG_PCI_INDIRECT_BRIDGE
-
-#define CONFIG_PCI_PNP /* do pci plug-and-play */
-
-#undef CONFIG_EEPRO100
-#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
-#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
-
-#endif /* CONFIG_PCI */
-
-/*
- * QE UEC ethernet configuration
- */
-#define CONFIG_UEC_ETH
-#define CONFIG_ETHPRIME "UEC0"
-
-#define CONFIG_UEC_ETH1 /* GETH1 */
-
-#ifdef CONFIG_UEC_ETH1
-#define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */
-#define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE
-#define CONFIG_SYS_UEC1_TX_CLK QE_CLK9
-#define CONFIG_SYS_UEC1_ETH_TYPE GIGA_ETH
-#define CONFIG_SYS_UEC1_PHY_ADDR 2
-#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_RXID
-#define CONFIG_SYS_UEC1_INTERFACE_SPEED 1000
-#endif
-
-#define CONFIG_UEC_ETH2 /* GETH2 */
-
-#ifdef CONFIG_UEC_ETH2
-#define CONFIG_SYS_UEC2_UCC_NUM 1 /* UCC2 */
-#define CONFIG_SYS_UEC2_RX_CLK QE_CLK_NONE
-#define CONFIG_SYS_UEC2_TX_CLK QE_CLK4
-#define CONFIG_SYS_UEC2_ETH_TYPE GIGA_ETH
-#define CONFIG_SYS_UEC2_PHY_ADDR 4
-#define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_RXID
-#define CONFIG_SYS_UEC2_INTERFACE_SPEED 1000
-#endif
-
-/*
- * Environment
- */
-
-#ifndef CONFIG_SYS_RAMBOOT
-#define CONFIG_ENV_IS_IN_FLASH 1
-#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
-#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
-#define CONFIG_ENV_SIZE 0x20000
-#else /* CONFIG_SYS_RAMBOOT */
-#define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */
-#define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
-#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
-#define CONFIG_ENV_SIZE 0x2000
-#endif /* CONFIG_SYS_RAMBOOT */
-
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_DHCP
-
-#if defined(CONFIG_PCI)
-#define CONFIG_CMD_PCI
-#endif
-
-#if defined(CONFIG_SYS_RAMBOOT)
-#undef CONFIG_CMD_SAVEENV
-#undef CONFIG_CMD_LOADS
-#endif
-
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
-
-#if defined(CONFIG_CMD_KGDB)
- #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
- #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-
- /* Print Buffer Size */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
- /* Boot Argument Buffer Size */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 256 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */
-
-/*
- * Core HID Setup
- */
-#define CONFIG_SYS_HID0_INIT 0x000000000
-#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
- HID0_ENABLE_INSTRUCTION_CACHE)
-#define CONFIG_SYS_HID2 HID2_HBE
-
-/*
- * MMU Setup
- */
-
-#define CONFIG_HIGH_BATS 1 /* High BATs supported */
-
-/* DDR: cache cacheable */
-#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \
- | BATL_PP_RW \
- | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \
- | BATU_BL_256M \
- | BATU_VS \
- | BATU_VP)
-#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
-#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
-
-/* IMMRBAR & PCI IO: cache-inhibit and guarded */
-#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR \
- | BATL_PP_RW \
- | BATL_CACHEINHIBIT \
- | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR \
- | BATU_BL_4M \
- | BATU_VS \
- | BATU_VP)
-#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
-#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
-
-/* NAND: cache-inhibit and guarded */
-#define CONFIG_SYS_IBAT2L (CONFIG_SYS_NAND_BASE \
- | BATL_PP_RW \
- | BATL_CACHEINHIBIT \
- | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT2U (CONFIG_SYS_NAND_BASE \
- | BATU_BL_64M \
- | BATU_VS \
- | BATU_VP)
-#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
-#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
-
-/* FLASH: icache cacheable, but dcache-inhibit and guarded */
-#define CONFIG_SYS_IBAT3L (CONFIG_SYS_FLASH_BASE \
- | BATL_PP_RW \
- | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT3U (CONFIG_SYS_FLASH_BASE \
- | BATU_BL_32M \
- | BATU_VS \
- | BATU_VP)
-#define CONFIG_SYS_DBAT3L (CONFIG_SYS_FLASH_BASE \
- | BATL_PP_RW \
- | BATL_CACHEINHIBIT \
- | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
-
-/* Stack in dcache: cacheable, no memory coherence */
-#define CONFIG_SYS_IBAT4L (CONFIG_SYS_INIT_RAM_ADDR \
- | BATL_PP_RW)
-#define CONFIG_SYS_IBAT4U (CONFIG_SYS_INIT_RAM_ADDR \
- | BATU_BL_128K \
- | BATU_VS \
- | BATU_VP)
-#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
-#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
-
-#define CONFIG_SYS_IBAT5L (CONFIG_SYS_VIDEO_BASE \
- | BATL_PP_RW \
- | BATL_CACHEINHIBIT \
- | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT5U (CONFIG_SYS_VIDEO_BASE \
- | BATU_BL_64M \
- | BATU_VS \
- | BATU_VP)
-#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
-#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
-
-#ifdef CONFIG_PCI
-/* PCI MEM space: cacheable */
-#define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI1_MEM_PHYS \
- | BATL_PP_RW \
- | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI1_MEM_PHYS \
- | BATU_BL_256M \
- | BATU_VS \
- | BATU_VP)
-#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
-#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
-/* PCI MMIO space: cache-inhibit and guarded */
-#define CONFIG_SYS_IBAT7L (CONFIG_SYS_PCI1_MMIO_PHYS \
- | BATL_PP_RW \
- | BATL_CACHEINHIBIT \
- | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT7U (CONFIG_SYS_PCI1_MMIO_PHYS \
- | BATU_BL_256M \
- | BATU_VS \
- | BATU_VP)
-#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
-#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
-#else /* CONFIG_PCI */
-#define CONFIG_SYS_IBAT6L (0)
-#define CONFIG_SYS_IBAT6U (0)
-#define CONFIG_SYS_IBAT7L (0)
-#define CONFIG_SYS_IBAT7U (0)
-#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
-#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
-#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
-#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
-#endif /* CONFIG_PCI */
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
-#endif
-
-/*
- * Environment Configuration
- */
-#define CONFIG_ENV_OVERWRITE
-
-#if defined(CONFIG_UEC_ETH)
-#define CONFIG_HAS_ETH0
-#define CONFIG_HAS_ETH1
-#define CONFIG_HAS_ETH2
-#define CONFIG_HAS_ETH3
-#endif
-
-#define CONFIG_BAUDRATE 115200
-
-#define CONFIG_LOADADDR a00000
-#define CONFIG_HOSTNAME mpc8360erdk
-#define CONFIG_BOOTFILE "uImage"
-
-#define CONFIG_ROOTPATH "/nfsroot/"
-
-#define CONFIG_BOOTDELAY 2 /* -1 disables auto-boot */
-#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "netdev=eth0\0" \
- "consoledev=ttyS0\0" \
- "loadaddr=a00000\0" \
- "fdtaddr=900000\0" \
- "fdtfile=mpc836x_rdk.dtb\0" \
- "fsfile=fs\0" \
- "ubootfile=u-boot.bin\0" \
- "mtdparts=mtdparts=60000000.nand-flash:4096k(kernel),128k(dtb),"\
- "-(rootfs)\0" \
- "setbootargs=setenv bootargs console=$consoledev,$baudrate " \
- "$mtdparts panic=1\0" \
- "adddhcpargs=setenv bootargs $bootargs ip=on\0" \
- "addnfsargs=setenv bootargs $bootargs ip=$ipaddr:$serverip:" \
- "$gatewayip:$netmask:$hostname:$netdev:off " \
- "root=/dev/nfs rw nfsroot=$serverip:$rootpath\0" \
- "addnandargs=setenv bootargs $bootargs root=/dev/mtdblock3 " \
- "rootfstype=jffs2 rw\0" \
- "tftp_get_uboot=tftp 100000 $ubootfile\0" \
- "tftp_get_kernel=tftp $loadaddr $bootfile\0" \
- "tftp_get_dtb=tftp $fdtaddr $fdtfile\0" \
- "tftp_get_fs=tftp c00000 $fsfile\0" \
- "nand_erase_kernel=nand erase 0 400000\0" \
- "nand_erase_dtb=nand erase 400000 20000\0" \
- "nand_erase_fs=nand erase 420000 3be0000\0" \
- "nand_write_kernel=nand write.jffs2 $loadaddr 0 400000\0" \
- "nand_write_dtb=nand write.jffs2 $fdtaddr 400000 20000\0" \
- "nand_write_fs=nand write.jffs2 c00000 420000 $filesize\0" \
- "nand_read_kernel=nand read.jffs2 $loadaddr 0 400000\0" \
- "nand_read_dtb=nand read.jffs2 $fdtaddr 400000 20000\0" \
- "nor_reflash=protect off ff800000 ff87ffff ; " \
- "erase ff800000 ff87ffff ; " \
- "cp.b 100000 ff800000 $filesize\0" \
- "nand_reflash_kernel=run tftp_get_kernel nand_erase_kernel " \
- "nand_write_kernel\0" \
- "nand_reflash_dtb=run tftp_get_dtb nand_erase_dtb nand_write_dtb\0"\
- "nand_reflash_fs=run tftp_get_fs nand_erase_fs nand_write_fs\0" \
- "nand_reflash=run nand_reflash_kernel nand_reflash_dtb " \
- "nand_reflash_fs\0" \
- "boot_m=bootm $loadaddr - $fdtaddr\0" \
- "dhcpboot=dhcp ; run setbootargs adddhcpargs tftp_get_dtb boot_m\0"\
- "nfsboot=run setbootargs addnfsargs tftp_get_kernel tftp_get_dtb "\
- "boot_m\0" \
- "nandboot=run setbootargs addnandargs nand_read_kernel nand_read_dtb "\
- "boot_m\0" \
- ""
-
-#define CONFIG_BOOTCOMMAND "run dhcpboot"
-
-#endif /* __CONFIG_H */
--
1.9.1
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [U-Boot] [PATCH 2/8] powerpc: mpc85xx: remove P1_P2_RDB boards
2015-01-22 15:24 [U-Boot] [PATCH 0/8] powerpc: drop more non-generic boards Masahiro Yamada
2015-01-22 15:24 ` [U-Boot] [PATCH 1/8] powerpc: mpc83xx: remove MPC8360ERDK, EMPC8360EMDS support Masahiro Yamada
@ 2015-01-22 15:24 ` Masahiro Yamada
2015-01-23 21:57 ` Tom Rini
2015-01-22 15:24 ` [U-Boot] [PATCH 3/8] powerpc: mpc85xx: remove P2020COME board support Masahiro Yamada
` (5 subsequent siblings)
7 siblings, 1 reply; 19+ messages in thread
From: Masahiro Yamada @ 2015-01-22 15:24 UTC (permalink / raw)
To: u-boot
These boards are still non-generic boards:
P1011RDB, P1022RDB, P2010RDB, P2020RDB
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Poonam Aggrwal <poonam.aggrwal@freescale.com>
---
arch/powerpc/cpu/mpc85xx/Kconfig | 6 -
board/freescale/p1_p2_rdb/Kconfig | 12 -
board/freescale/p1_p2_rdb/MAINTAINERS | 37 --
board/freescale/p1_p2_rdb/Makefile | 30 --
board/freescale/p1_p2_rdb/README | 145 ------
board/freescale/p1_p2_rdb/ddr.c | 221 --------
board/freescale/p1_p2_rdb/law.c | 17 -
board/freescale/p1_p2_rdb/p1_p2_rdb.c | 303 -----------
board/freescale/p1_p2_rdb/pci.c | 27 -
board/freescale/p1_p2_rdb/spl.c | 141 ------
board/freescale/p1_p2_rdb/spl_minimal.c | 84 ----
board/freescale/p1_p2_rdb/tlb.c | 91 ----
configs/P1011RDB_36BIT_SDCARD_defconfig | 5 -
configs/P1011RDB_36BIT_SPIFLASH_defconfig | 5 -
configs/P1011RDB_36BIT_defconfig | 4 -
configs/P1011RDB_NAND_defconfig | 6 -
configs/P1011RDB_SDCARD_defconfig | 5 -
configs/P1011RDB_SPIFLASH_defconfig | 5 -
configs/P1011RDB_defconfig | 4 -
configs/P1020RDB_36BIT_SDCARD_defconfig | 5 -
configs/P1020RDB_36BIT_SPIFLASH_defconfig | 5 -
configs/P1020RDB_36BIT_defconfig | 4 -
configs/P1020RDB_NAND_defconfig | 6 -
configs/P1020RDB_SDCARD_defconfig | 5 -
configs/P1020RDB_SPIFLASH_defconfig | 5 -
configs/P1020RDB_defconfig | 4 -
configs/P2010RDB_36BIT_SDCARD_defconfig | 5 -
configs/P2010RDB_36BIT_SPIFLASH_defconfig | 5 -
configs/P2010RDB_36BIT_defconfig | 4 -
configs/P2010RDB_NAND_defconfig | 6 -
configs/P2010RDB_SDCARD_defconfig | 5 -
configs/P2010RDB_SPIFLASH_defconfig | 5 -
configs/P2010RDB_defconfig | 4 -
configs/P2020RDB_36BIT_SDCARD_defconfig | 5 -
configs/P2020RDB_36BIT_SPIFLASH_defconfig | 5 -
configs/P2020RDB_36BIT_defconfig | 4 -
configs/P2020RDB_NAND_defconfig | 6 -
configs/P2020RDB_SDCARD_defconfig | 5 -
configs/P2020RDB_SPIFLASH_defconfig | 5 -
configs/P2020RDB_defconfig | 4 -
doc/README.scrapyard | 4 +
include/configs/P1_P2_RDB.h | 808 ------------------------------
42 files changed, 4 insertions(+), 2058 deletions(-)
delete mode 100644 board/freescale/p1_p2_rdb/Kconfig
delete mode 100644 board/freescale/p1_p2_rdb/MAINTAINERS
delete mode 100644 board/freescale/p1_p2_rdb/Makefile
delete mode 100644 board/freescale/p1_p2_rdb/README
delete mode 100644 board/freescale/p1_p2_rdb/ddr.c
delete mode 100644 board/freescale/p1_p2_rdb/law.c
delete mode 100644 board/freescale/p1_p2_rdb/p1_p2_rdb.c
delete mode 100644 board/freescale/p1_p2_rdb/pci.c
delete mode 100644 board/freescale/p1_p2_rdb/spl.c
delete mode 100644 board/freescale/p1_p2_rdb/spl_minimal.c
delete mode 100644 board/freescale/p1_p2_rdb/tlb.c
delete mode 100644 configs/P1011RDB_36BIT_SDCARD_defconfig
delete mode 100644 configs/P1011RDB_36BIT_SPIFLASH_defconfig
delete mode 100644 configs/P1011RDB_36BIT_defconfig
delete mode 100644 configs/P1011RDB_NAND_defconfig
delete mode 100644 configs/P1011RDB_SDCARD_defconfig
delete mode 100644 configs/P1011RDB_SPIFLASH_defconfig
delete mode 100644 configs/P1011RDB_defconfig
delete mode 100644 configs/P1020RDB_36BIT_SDCARD_defconfig
delete mode 100644 configs/P1020RDB_36BIT_SPIFLASH_defconfig
delete mode 100644 configs/P1020RDB_36BIT_defconfig
delete mode 100644 configs/P1020RDB_NAND_defconfig
delete mode 100644 configs/P1020RDB_SDCARD_defconfig
delete mode 100644 configs/P1020RDB_SPIFLASH_defconfig
delete mode 100644 configs/P1020RDB_defconfig
delete mode 100644 configs/P2010RDB_36BIT_SDCARD_defconfig
delete mode 100644 configs/P2010RDB_36BIT_SPIFLASH_defconfig
delete mode 100644 configs/P2010RDB_36BIT_defconfig
delete mode 100644 configs/P2010RDB_NAND_defconfig
delete mode 100644 configs/P2010RDB_SDCARD_defconfig
delete mode 100644 configs/P2010RDB_SPIFLASH_defconfig
delete mode 100644 configs/P2010RDB_defconfig
delete mode 100644 configs/P2020RDB_36BIT_SDCARD_defconfig
delete mode 100644 configs/P2020RDB_36BIT_SPIFLASH_defconfig
delete mode 100644 configs/P2020RDB_36BIT_defconfig
delete mode 100644 configs/P2020RDB_NAND_defconfig
delete mode 100644 configs/P2020RDB_SDCARD_defconfig
delete mode 100644 configs/P2020RDB_SPIFLASH_defconfig
delete mode 100644 configs/P2020RDB_defconfig
delete mode 100644 include/configs/P1_P2_RDB.h
diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig
index 7501eb4..009d830 100644
--- a/arch/powerpc/cpu/mpc85xx/Kconfig
+++ b/arch/powerpc/cpu/mpc85xx/Kconfig
@@ -85,11 +85,6 @@ config TARGET_P1022DS
config TARGET_P1023RDB
bool "Support P1023RDB"
-config TARGET_P1_P2_RDB
- bool "Support P1_P2_RDB"
- select SUPPORT_SPL
- select SUPPORT_TPL
-
config TARGET_P1_P2_RDB_PC
bool "Support p1_p2_rdb_pc"
select SUPPORT_SPL
@@ -184,7 +179,6 @@ source "board/freescale/mpc8572ds/Kconfig"
source "board/freescale/p1010rdb/Kconfig"
source "board/freescale/p1022ds/Kconfig"
source "board/freescale/p1023rdb/Kconfig"
-source "board/freescale/p1_p2_rdb/Kconfig"
source "board/freescale/p1_p2_rdb_pc/Kconfig"
source "board/freescale/p1_twr/Kconfig"
source "board/freescale/p2020come/Kconfig"
diff --git a/board/freescale/p1_p2_rdb/Kconfig b/board/freescale/p1_p2_rdb/Kconfig
deleted file mode 100644
index d7ad35d..0000000
--- a/board/freescale/p1_p2_rdb/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_P1_P2_RDB
-
-config SYS_BOARD
- default "p1_p2_rdb"
-
-config SYS_VENDOR
- default "freescale"
-
-config SYS_CONFIG_NAME
- default "P1_P2_RDB"
-
-endif
diff --git a/board/freescale/p1_p2_rdb/MAINTAINERS b/board/freescale/p1_p2_rdb/MAINTAINERS
deleted file mode 100644
index aabf587..0000000
--- a/board/freescale/p1_p2_rdb/MAINTAINERS
+++ /dev/null
@@ -1,37 +0,0 @@
-P1_P2_RDB BOARD
-#M: -
-S: Maintained
-F: board/freescale/p1_p2_rdb/
-F: include/configs/P1_P2_RDB.h
-F: configs/P1011RDB_defconfig
-F: configs/P1011RDB_36BIT_defconfig
-F: configs/P1011RDB_36BIT_SDCARD_defconfig
-F: configs/P1011RDB_36BIT_SPIFLASH_defconfig
-F: configs/P1011RDB_NAND_defconfig
-F: configs/P1011RDB_SDCARD_defconfig
-F: configs/P1011RDB_SPIFLASH_defconfig
-F: configs/P1020RDB_defconfig
-F: configs/P1020RDB_36BIT_defconfig
-F: configs/P1020RDB_36BIT_SDCARD_defconfig
-F: configs/P1020RDB_36BIT_SPIFLASH_defconfig
-F: configs/P1020RDB_NAND_defconfig
-F: configs/P1020RDB_SDCARD_defconfig
-F: configs/P1020RDB_SPIFLASH_defconfig
-F: configs/P2010RDB_defconfig
-F: configs/P2010RDB_36BIT_defconfig
-F: configs/P2010RDB_36BIT_SDCARD_defconfig
-F: configs/P2010RDB_36BIT_SPIFLASH_defconfig
-F: configs/P2010RDB_NAND_defconfig
-F: configs/P2010RDB_SDCARD_defconfig
-F: configs/P2010RDB_SPIFLASH_defconfig
-F: configs/P2020RDB_36BIT_defconfig
-F: configs/P2020RDB_36BIT_SDCARD_defconfig
-F: configs/P2020RDB_36BIT_SPIFLASH_defconfig
-F: configs/P2020RDB_NAND_defconfig
-F: configs/P2020RDB_SDCARD_defconfig
-F: configs/P2020RDB_SPIFLASH_defconfig
-
-P2020RDB BOARD
-M: Poonam Aggrwal <poonam.aggrwal@freescale.com>
-S: Maintained
-F: configs/P2020RDB_defconfig
diff --git a/board/freescale/p1_p2_rdb/Makefile b/board/freescale/p1_p2_rdb/Makefile
deleted file mode 100644
index a97bf45..0000000
--- a/board/freescale/p1_p2_rdb/Makefile
+++ /dev/null
@@ -1,30 +0,0 @@
-#
-# Copyright 2009 Freescale Semiconductor, Inc.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-MINIMAL=
-
-ifdef CONFIG_SPL_BUILD
-ifdef CONFIG_SPL_INIT_MINIMAL
-MINIMAL=y
-endif
-endif
-
-ifdef MINIMAL
-
-obj-y += spl_minimal.o tlb.o law.o
-
-else
-ifdef CONFIG_SPL_BUILD
-obj-y += spl.o
-else
-obj-y += p1_p2_rdb.o
-obj-$(CONFIG_PCI) += pci.o
-endif
-obj-y += ddr.o
-obj-y += law.o
-obj-y += tlb.o
-
-endif
diff --git a/board/freescale/p1_p2_rdb/README b/board/freescale/p1_p2_rdb/README
deleted file mode 100644
index cd66e58..0000000
--- a/board/freescale/p1_p2_rdb/README
+++ /dev/null
@@ -1,145 +0,0 @@
-Overview
---------
-P2020RDB is a Low End Dual core platform supporting the P2020 processor
-of QorIQ series. P2020 is an e500 based dual core SOC.
-
-Building U-boot
------------
-To build the u-boot for P2020RDB:
- make P2020RDB_config
- make
-
-NOR Flash Banks
------------
-RDB board for P2020 has two flash banks. They are both present on boot.
-
-Booting by default is always from the boot bank at 0xef00_0000.
-
-Memory Map
-----------
-0xef00_0000 - 0xef7f_ffff Alternate bank 8MB
-0xe800_0000 - 0xefff_ffff Boot bank 8MB
-
-0xef74_0000 - 0xef7f_ffff Alternate u-boot address 768KB
-0xeff4_0000 - 0xefff_ffff Boot u-boot address 768KB
-
-Switch settings to boot from the NOR flash banks
-------------------------------------------------
-SW4[8]=0 default NOR Flash bank
-SW4[8]=1 Alternate NOR Flash bank
-
-Flashing Images
----------------
-To place a new u-boot image in the alternate flash bank and then boot
-with that new image temporarily, use this:
- tftp 1000000 u-boot.bin
- erase ef740000 ef7fffff
- cp.b 1000000 ef740000 c0000
-
-Now to boot from the alternate bank change the SW4[8] from 0 to 1.
-
-To program the image in the boot flash bank:
- tftp 1000000 u-boot.bin
- protect off all
- erase eff40000 ffffffff
- cp.b 1000000 eff40000 c0000
-
-Using the Device Tree Source File
----------------------------------
-To create the DTB (Device Tree Binary) image file,
-use a command similar to this:
-
- dtc -b 0 -f -I dts -O dtb p2020rdb.dts > p2020rdb.dtb
-
-Likely, that .dts file will come from here;
-
- linux-2.6/arch/powerpc/boot/dts/p2020rdb.dts
-
-Booting Linux
--------------
-Place a linux uImage in the TFTP disk area.
-
- tftp 1000000 uImage.p2020rdb
- tftp 2000000 rootfs.ext2.gz.uboot
- tftp c00000 p2020rdb.dtb
- bootm 1000000 2000000 c00000
-
-Implementing AMP(Asymmetric MultiProcessing)
----------------------------------------------
-1. Build kernel image for core0:
-
- a. $ make 85xx/p1_p2_rdb_defconfig
-
- b. $ make menuconfig
- - un-select "Processor support"->
- "Symetric multi-processing support"
-
- c. $ make uImage
-
- d. $ cp arch/powerpc/boot/uImage /tftpboot/uImage.core0
-
-2. Build kernel image for core1:
-
- a. $ make 85xx/p1_p2_rdb_defconfig
-
- b. $ make menuconfig
- - Un-select "Processor support"->
- "Symetric multi-processing support"
- - Select "Advanced setup" ->
- "Prompt for advanced kernel configuration options"
- - Select
- "Set physical address where the kernel is loaded"
- and set it to 0x20000000, assuming core1 will
- start from 512MB.
- - Select "Set custom page offset address"
- - Select "Set custom kernel base address"
- - Select "Set maximum low memory"
- - "Exit" and save the selection.
-
- c. $ make uImage
-
- d. $ cp arch/powerpc/boot/uImage /tftpboot/uImage.core1
-
-3. Create dtb for core0:
-
- $ dtc -I dts -O dtb -f -b 0
- arch/powerpc/boot/dts/p2020rdb_camp_core0.dts >
- /tftpboot/p2020rdb_camp_core0.dtb
-
-4. Create dtb for core1:
-
- $ dtc -I dts -O dtb -f -b 1
- arch/powerpc/boot/dts/p2020rdb_camp_core1.dts >
- /tftpboot/p2020rdb_camp_core1.dtb
-
-5. Bring up two cores separately:
-
- a. Power on the board, under u-boot prompt:
- => setenv <serverip>
- => setenv <ipaddr>
- => setenv bootargs root=/dev/ram rw console=ttyS0,115200
- b. Bring up core1's kernel first:
- => setenv bootm_low 0x20000000
- => setenv bootm_size 0x10000000
- => tftp 21000000 uImage.core1
- => tftp 22000000 ramdiskfile
- => tftp 20c00000 p2020rdb_camp_core1.dtb
- => interrupts off
- => bootm start 21000000 22000000 20c00000
- => bootm loados
- => bootm ramdisk
- => bootm fdt
- => fdt boardsetup
- => fdt chosen $initrd_start $initrd_end
- => bootm prep
- => cpu 1 release $bootm_low - $fdtaddr -
- c. Bring up core0's kernel(on the same u-boot console):
- => setenv bootm_low 0
- => setenv bootm_size 0x20000000
- => tftp 1000000 uImage.core0
- => tftp 2000000 ramdiskfile
- => tftp c00000 p2020rdb_camp_core0.dtb
- => bootm 1000000 2000000 c00000
-
-Please note only core0 will run u-boot, core1 starts kernel directly
-after "cpu release" command is issued.
diff --git a/board/freescale/p1_p2_rdb/ddr.c b/board/freescale/p1_p2_rdb/ddr.c
deleted file mode 100644
index 98ee5f1..0000000
--- a/board/freescale/p1_p2_rdb/ddr.c
+++ /dev/null
@@ -1,221 +0,0 @@
-/*
- * Copyright 2009, 2011 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/mmu.h>
-#include <asm/immap_85xx.h>
-#include <asm/processor.h>
-#include <fsl_ddr_sdram.h>
-#include <asm/io.h>
-#include <asm/fsl_law.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define CONFIG_SYS_DDR_CS0_BNDS 0x0000003F
-#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202
-#define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000
-#define CONFIG_SYS_DDR_INIT_ADDR 0x00000000
-#define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000
-#define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000
-#define CONFIG_SYS_DDR_ZQ_CONTROL 0x00000000
-#define CONFIG_SYS_DDR_WRLVL_CONTROL 0x00000000
-#define CONFIG_SYS_DDR_SR_CNTR 0x00000000
-#define CONFIG_SYS_DDR_RCW_1 0x00000000
-#define CONFIG_SYS_DDR_RCW_2 0x00000000
-#define CONFIG_SYS_DDR_CONTROL 0x43000000 /* Type = DDR2*/
-#define CONFIG_SYS_DDR_CONTROL_2 0x24401000
-#define CONFIG_SYS_DDR_TIMING_4 0x00000000
-#define CONFIG_SYS_DDR_TIMING_5 0x00000000
-
-#define CONFIG_SYS_DDR_TIMING_3_400 0x00010000
-#define CONFIG_SYS_DDR_TIMING_0_400 0x00260802
-#define CONFIG_SYS_DDR_TIMING_1_400 0x39355322
-#define CONFIG_SYS_DDR_TIMING_2_400 0x1f9048ca
-#define CONFIG_SYS_DDR_CLK_CTRL_400 0x02800000
-#define CONFIG_SYS_DDR_MODE_1_400 0x00480432
-#define CONFIG_SYS_DDR_MODE_2_400 0x00000000
-#define CONFIG_SYS_DDR_INTERVAL_400 0x06180100
-
-#define CONFIG_SYS_DDR_TIMING_3_533 0x00020000
-#define CONFIG_SYS_DDR_TIMING_0_533 0x00260802
-#define CONFIG_SYS_DDR_TIMING_1_533 0x4c47c432
-#define CONFIG_SYS_DDR_TIMING_2_533 0x0f9848ce
-#define CONFIG_SYS_DDR_CLK_CTRL_533 0x02800000
-#define CONFIG_SYS_DDR_MODE_1_533 0x00040642
-#define CONFIG_SYS_DDR_MODE_2_533 0x00000000
-#define CONFIG_SYS_DDR_INTERVAL_533 0x08200100
-
-#define CONFIG_SYS_DDR_TIMING_3_667 0x00030000
-#define CONFIG_SYS_DDR_TIMING_0_667 0x55770802
-#define CONFIG_SYS_DDR_TIMING_1_667 0x5f599543
-#define CONFIG_SYS_DDR_TIMING_2_667 0x0fa074d1
-#define CONFIG_SYS_DDR_CLK_CTRL_667 0x03000000
-#define CONFIG_SYS_DDR_MODE_1_667 0x00040852
-#define CONFIG_SYS_DDR_MODE_2_667 0x00000000
-#define CONFIG_SYS_DDR_INTERVAL_667 0x0a280100
-
-#define CONFIG_SYS_DDR_TIMING_3_800 0x00040000
-#define CONFIG_SYS_DDR_TIMING_0_800 0x00770802
-#define CONFIG_SYS_DDR_TIMING_1_800 0x6f6b6543
-#define CONFIG_SYS_DDR_TIMING_2_800 0x0fa074d1
-#define CONFIG_SYS_DDR_CLK_CTRL_800 0x02800000
-#define CONFIG_SYS_DDR_MODE_1_800 0x00040852
-#define CONFIG_SYS_DDR_MODE_2_800 0x00000000
-#define CONFIG_SYS_DDR_INTERVAL_800 0x0c300100
-
-fsl_ddr_cfg_regs_t ddr_cfg_regs_400 = {
- .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
- .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
- .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
- .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_400,
- .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_400,
- .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_400,
- .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_400,
- .ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL,
- .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2,
- .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_400,
- .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_400,
- .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
- .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_400,
- .ddr_data_init = CONFIG_MEM_INIT_VALUE,
- .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_400,
- .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
- .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
- .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
- .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
- .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL,
- .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL,
- .ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR,
- .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
- .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
-};
-
-fsl_ddr_cfg_regs_t ddr_cfg_regs_533 = {
- .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
- .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
- .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
- .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_533,
- .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_533,
- .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_533,
- .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_533,
- .ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL,
- .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2,
- .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_533,
- .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_533,
- .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
- .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_533,
- .ddr_data_init = CONFIG_MEM_INIT_VALUE,
- .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_533,
- .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
- .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
- .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
- .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
- .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL,
- .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL,
- .ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR,
- .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
- .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
-};
-
-fsl_ddr_cfg_regs_t ddr_cfg_regs_667 = {
- .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
- .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
- .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
- .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_667,
- .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_667,
- .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_667,
- .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_667,
- .ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL,
- .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2,
- .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_667,
- .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_667,
- .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
- .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_667,
- .ddr_data_init = CONFIG_MEM_INIT_VALUE,
- .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_667,
- .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
- .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
- .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
- .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
- .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL,
- .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL,
- .ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR,
- .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
- .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
-};
-
-fsl_ddr_cfg_regs_t ddr_cfg_regs_800 = {
- .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
- .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
- .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
- .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_800,
- .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_800,
- .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_800,
- .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_800,
- .ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL,
- .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2,
- .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_800,
- .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_800,
- .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
- .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_800,
- .ddr_data_init = CONFIG_MEM_INIT_VALUE,
- .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_800,
- .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
- .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
- .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
- .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
- .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL,
- .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL,
- .ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR,
- .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
- .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
-};
-
-/*
- * Fixed sdram init -- doesn't use serial presence detect.
- */
-
-phys_size_t fixed_sdram (void)
-{
- fsl_ddr_cfg_regs_t ddr_cfg_regs;
- size_t ddr_size;
- struct cpu_type *cpu;
- ulong ddr_freq, ddr_freq_mhz;
-
- cpu = gd->arch.cpu;
-
- ddr_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
-
-#if defined(CONFIG_SYS_RAMBOOT)
- return ddr_size;
-#endif
- ddr_freq = get_ddr_freq(0);
- ddr_freq_mhz = ddr_freq / 1000000;
-
- printf("Configuring DDR for %ld T/s data rate\n", ddr_freq);
-
- if(ddr_freq_mhz <= 400)
- memcpy(&ddr_cfg_regs, &ddr_cfg_regs_400, sizeof(ddr_cfg_regs));
- else if(ddr_freq_mhz <= 533)
- memcpy(&ddr_cfg_regs, &ddr_cfg_regs_533, sizeof(ddr_cfg_regs));
- else if(ddr_freq_mhz <= 667)
- memcpy(&ddr_cfg_regs, &ddr_cfg_regs_667, sizeof(ddr_cfg_regs));
- else if(ddr_freq_mhz <= 800)
- memcpy(&ddr_cfg_regs, &ddr_cfg_regs_800, sizeof(ddr_cfg_regs));
- else
- panic("Unsupported DDR data rate %ld T/s\n", ddr_freq);
-
- /* P1020 and it's derivatives support max 32bit DDR width */
- if (cpu->soc_ver == SVR_P1020 || cpu->soc_ver == SVR_P1011) {
- ddr_cfg_regs.ddr_sdram_cfg |= SDRAM_CFG_32_BE;
- ddr_cfg_regs.cs[0].bnds = 0x0000001F;
- }
-
- fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0, 0);
-
- set_ddr_laws(0, ddr_size, LAW_TRGT_IF_DDR_1);
- return ddr_size;
-}
diff --git a/board/freescale/p1_p2_rdb/law.c b/board/freescale/p1_p2_rdb/law.c
deleted file mode 100644
index b60a27f..0000000
--- a/board/freescale/p1_p2_rdb/law.c
+++ /dev/null
@@ -1,17 +0,0 @@
-/*
- * Copyright 2009-2010 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/fsl_law.h>
-#include <asm/mmu.h>
-
-struct law_entry law_table[] = {
- SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_LBC),
- SET_LAW(CONFIG_SYS_VSC7385_BASE_PHYS, LAW_SIZE_128K, LAW_TRGT_IF_LBC),
- SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
-};
-
-int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/freescale/p1_p2_rdb/p1_p2_rdb.c b/board/freescale/p1_p2_rdb/p1_p2_rdb.c
deleted file mode 100644
index 61ed466..0000000
--- a/board/freescale/p1_p2_rdb/p1_p2_rdb.c
+++ /dev/null
@@ -1,303 +0,0 @@
-/*
- * Copyright 2009-2011 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <command.h>
-#include <asm/processor.h>
-#include <asm/mmu.h>
-#include <asm/cache.h>
-#include <asm/immap_85xx.h>
-#include <asm/fsl_serdes.h>
-#include <asm/io.h>
-#include <miiphy.h>
-#include <libfdt.h>
-#include <fdt_support.h>
-#include <fsl_mdio.h>
-#include <tsec.h>
-#include <vsc7385.h>
-#include <netdev.h>
-#include <rtc.h>
-#include <i2c.h>
-#include <hwconfig.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define VSC7385_RST_SET 0x00080000
-#define SLIC_RST_SET 0x00040000
-#define SGMII_PHY_RST_SET 0x00020000
-#define PCIE_RST_SET 0x00010000
-#define RGMII_PHY_RST_SET 0x02000000
-
-#define USB_RST_CLR 0x04000000
-#define USB2_PORT_OUT_EN 0x01000000
-
-#define GPIO_DIR 0x060f0000
-
-#define BOARD_PERI_RST_SET VSC7385_RST_SET | SLIC_RST_SET | \
- SGMII_PHY_RST_SET | PCIE_RST_SET | \
- RGMII_PHY_RST_SET
-
-#define SYSCLK_MASK 0x00200000
-#define BOARDREV_MASK 0x10100000
-#define BOARDREV_C 0x00100000
-#define BOARDREV_D 0x00000000
-
-#define SYSCLK_66 66666666
-#define SYSCLK_100 100000000
-
-unsigned long get_board_sys_clk(ulong dummy)
-{
- volatile ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
- u32 val_gpdat, sysclk_gpio;
-
- val_gpdat = in_be32(&pgpio->gpdat);
- sysclk_gpio = val_gpdat & SYSCLK_MASK;
-
- if(sysclk_gpio == 0)
- return SYSCLK_66;
- else
- return SYSCLK_100;
-
- return 0;
-}
-
-#ifdef CONFIG_MMC
-int board_early_init_f (void)
-{
- volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-
- setbits_be32(&gur->pmuxcr,
- (MPC85xx_PMUXCR_SDHC_CD |
- MPC85xx_PMUXCR_SDHC_WP));
- return 0;
-}
-#endif
-
-int checkboard (void)
-{
- u32 val_gpdat, board_rev_gpio;
- volatile ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
- char board_rev = 0;
- struct cpu_type *cpu;
-
- val_gpdat = in_be32(&pgpio->gpdat);
- board_rev_gpio = val_gpdat & BOARDREV_MASK;
- if (board_rev_gpio == BOARDREV_C)
- board_rev = 'C';
- else if (board_rev_gpio == BOARDREV_D)
- board_rev = 'D';
- else
- panic ("Unexpected Board REV %x detected!!\n", board_rev_gpio);
-
- cpu = gd->arch.cpu;
- printf ("Board: %sRDB Rev%c\n", cpu->name, board_rev);
-
- setbits_be32(&pgpio->gpdir, GPIO_DIR);
-
-/*
- * Bringing the following peripherals out of reset via GPIOs
- * 0 = reset and 1 = out of reset
- * GPIO12 - Reset to Ethernet Switch
- * GPIO13 - Reset to SLIC/SLAC devices
- * GPIO14 - Reset to SGMII_PHY_N
- * GPIO15 - Reset to PCIe slots
- * GPIO6 - Reset to RGMII PHY
- * GPIO5 - Reset to USB3300 devices 1 = reset and 0 = out of reset
- */
- clrsetbits_be32(&pgpio->gpdat, USB_RST_CLR, BOARD_PERI_RST_SET);
-
- return 0;
-}
-
-int misc_init_r(void)
-{
-#if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
- ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
- ccsr_gpio_t *gpio = (void *)CONFIG_SYS_MPC85xx_GPIO_ADDR;
-
- setbits_be32(&gpio->gpdir, USB2_PORT_OUT_EN);
- setbits_be32(&gpio->gpdat, USB2_PORT_OUT_EN);
- setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_ELBC_OFF_USB2_ON);
-#endif
- return 0;
-}
-
-int board_early_init_r(void)
-{
- const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
- int flash_esel = find_tlb_idx((void *)flashbase, 1);
- volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
- unsigned int orig_bus = i2c_get_bus_num();
- u8 i2c_data;
-
- i2c_set_bus_num(1);
- if (i2c_read(CONFIG_SYS_I2C_PCA9557_ADDR, 0,
- 1, &i2c_data, sizeof(i2c_data)) == 0) {
- if (i2c_data & 0x2)
- puts("NOR Flash Bank : Secondary\n");
- else
- puts("NOR Flash Bank : Primary\n");
-
- if (i2c_data & 0x1) {
- setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_SD_DATA);
- puts("SD/MMC : 8-bit Mode\n");
- puts("eSPI : Disabled\n");
- } else {
- puts("SD/MMC : 4-bit Mode\n");
- puts("eSPI : Enabled\n");
- }
- } else {
- puts("Failed reading I2C Chip 0x18 on bus 1\n");
- }
- i2c_set_bus_num(orig_bus);
-
- /*
- * Remap Boot flash region to caching-inhibited
- * so that flash can be erased properly.
- */
-
- /* Flush d-cache and invalidate i-cache of any FLASH data */
- flush_dcache();
- invalidate_icache();
-
- if (flash_esel == -1) {
- /* very unlikely unless something is messed up */
- puts("Error: Could not find TLB for FLASH BASE\n");
- flash_esel = 2; /* give our best effort to continue */
- } else {
- /* invalidate existing TLB entry for flash */
- disable_tlb(flash_esel);
- }
-
- set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, flash_esel, BOOKE_PAGESZ_16M, 1);
- rtc_reset();
- return 0;
-}
-
-
-#ifdef CONFIG_TSEC_ENET
-int board_eth_init(bd_t *bis)
-{
- struct fsl_pq_mdio_info mdio_info;
- struct tsec_info_struct tsec_info[4];
- int num = 0;
- char *tmp;
- unsigned int vscfw_addr;
-
-#ifdef CONFIG_TSEC1
- SET_STD_TSEC_INFO(tsec_info[num], 1);
- num++;
-#endif
-#ifdef CONFIG_TSEC2
- SET_STD_TSEC_INFO(tsec_info[num], 2);
- num++;
-#endif
-#ifdef CONFIG_TSEC3
- SET_STD_TSEC_INFO(tsec_info[num], 3);
- if (is_serdes_configured(SGMII_TSEC3)) {
- puts("eTSEC3 is in sgmii mode.\n");
- tsec_info[num].flags |= TSEC_SGMII;
- }
- num++;
-#endif
- if (!num) {
- printf("No TSECs initialized\n");
- return 0;
- }
-#ifdef CONFIG_VSC7385_ENET
-/* If a VSC7385 microcode image is present, then upload it. */
- if ((tmp = getenv ("vscfw_addr")) != NULL) {
- vscfw_addr = simple_strtoul (tmp, NULL, 16);
- printf("uploading VSC7385 microcode from %x\n", vscfw_addr);
- if (vsc7385_upload_firmware((void *) vscfw_addr,
- CONFIG_VSC7385_IMAGE_SIZE))
- puts("Failure uploading VSC7385 microcode.\n");
- } else
- puts("No address specified for VSC7385 microcode.\n");
-#endif
-
- mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
- mdio_info.name = DEFAULT_MII_NAME;
- fsl_pq_mdio_init(bis, &mdio_info);
-
- tsec_eth_init(bis, tsec_info, num);
-
- return pci_eth_init(bis);
-}
-#endif
-
-#if defined(CONFIG_OF_BOARD_SETUP)
-extern void ft_pci_board_setup(void *blob);
-
-int ft_board_setup(void *blob, bd_t *bd)
-{
- const char *soc_usb_compat = "fsl-usb2-dr";
- int err, usb1_off, usb2_off;
- phys_addr_t base;
- phys_size_t size;
-
- ft_cpu_setup(blob, bd);
-
- base = getenv_bootm_low();
- size = getenv_bootm_size();
-
-#if defined(CONFIG_PCI)
- ft_pci_board_setup(blob);
-#endif /* #if defined(CONFIG_PCI) */
-
- fdt_fixup_memory(blob, (u64)base, (u64)size);
-
-#if defined(CONFIG_HAS_FSL_DR_USB)
- fdt_fixup_dr_usb(blob, bd);
-#endif
-
-#if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
- /* Delete eLBC node as it is muxed with USB2 controller */
- if (hwconfig("usb2")) {
- const char *soc_elbc_compat = "fsl,p1020-elbc";
- int off = fdt_node_offset_by_compatible(blob, -1,
- soc_elbc_compat);
- if (off < 0) {
- printf("WARNING: could not find compatible node %s\n",
- soc_elbc_compat);
- return off;
- }
- err = fdt_del_node(blob, off);
- if (err < 0) {
- printf("WARNING: could not remove %s\n",
- soc_elbc_compat);
- return err;
- }
- return 0;
- }
-#endif
- /* Delete USB2 node as it is muxed with eLBC */
- usb1_off = fdt_node_offset_by_compatible(blob, -1,
- soc_usb_compat);
- if (usb1_off < 0) {
- printf("WARNING: could not find compatible node %s\n",
- soc_usb_compat);
- return usb1_off;
- }
- usb2_off = fdt_node_offset_by_compatible(blob, usb1_off,
- soc_usb_compat);
- if (usb2_off < 0) {
- printf("WARNING: could not find compatible node %s\n",
- soc_usb_compat);
- return usb2_off;
- }
- err = fdt_del_node(blob, usb2_off);
- if (err < 0) {
- printf("WARNING: could not remove %s\n", soc_usb_compat);
- return err;
- }
-
- return 0;
-}
-
-#endif
diff --git a/board/freescale/p1_p2_rdb/pci.c b/board/freescale/p1_p2_rdb/pci.c
deleted file mode 100644
index 745ebb1..0000000
--- a/board/freescale/p1_p2_rdb/pci.c
+++ /dev/null
@@ -1,27 +0,0 @@
-/*
- * Copyright 2009-2010 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <command.h>
-#include <pci.h>
-#include <asm/immap_85xx.h>
-#include <asm/fsl_serdes.h>
-#include <asm/io.h>
-#include <asm/fsl_pci.h>
-#include <libfdt.h>
-#include <fdt_support.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-void pci_init_board(void)
-{
- fsl_pcie_init_board(0);
-}
-
-void ft_pci_board_setup(void *blob)
-{
- FT_FSL_PCI_SETUP;
-}
diff --git a/board/freescale/p1_p2_rdb/spl.c b/board/freescale/p1_p2_rdb/spl.c
deleted file mode 100644
index f30c5fe..0000000
--- a/board/freescale/p1_p2_rdb/spl.c
+++ /dev/null
@@ -1,141 +0,0 @@
-/*
- * Copyright 2013 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <ns16550.h>
-#include <malloc.h>
-#include <mmc.h>
-#include <nand.h>
-#include <i2c.h>
-#include <fsl_esdhc.h>
-#include <spi_flash.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define SYSCLK_MASK 0x00200000
-#define BOARDREV_MASK 0x10100000
-
-#define SYSCLK_66 66666666
-#define SYSCLK_100 100000000
-
-unsigned long get_board_sys_clk(ulong dummy)
-{
- ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
- u32 val_gpdat, sysclk_gpio;
-
- val_gpdat = in_be32(&pgpio->gpdat);
- sysclk_gpio = val_gpdat & SYSCLK_MASK;
-
- if (sysclk_gpio == 0)
- return SYSCLK_66;
- else
- return SYSCLK_100;
-
- return 0;
-}
-
-phys_size_t get_effective_memsize(void)
-{
- return CONFIG_SYS_L2_SIZE;
-}
-
-void board_init_f(ulong bootflag)
-{
- u32 plat_ratio, bus_clk;
- ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
-
- console_init_f();
-
- /* Set pmuxcr to allow both i2c1 and i2c2 */
- setbits_be32(&gur->pmuxcr, in_be32(&gur->pmuxcr) | 0x1000);
- setbits_be32(&gur->pmuxcr,
- in_be32(&gur->pmuxcr) | MPC85xx_PMUXCR_SD_DATA);
-
- /* Read back the register to synchronize the write. */
- in_be32(&gur->pmuxcr);
-
-#ifdef CONFIG_SPL_SPI_BOOT
- clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_SD_DATA);
-#endif
-
- /* initialize selected port with appropriate baud rate */
- plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
- plat_ratio >>= 1;
- bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio;
- gd->bus_clk = bus_clk;
-
- NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
- bus_clk / 16 / CONFIG_BAUDRATE);
-#ifdef CONFIG_SPL_MMC_BOOT
- puts("\nSD boot...\n");
-#elif defined(CONFIG_SPL_SPI_BOOT)
- puts("\nSPI Flash boot...\n");
-#endif
-
- /* copy code to RAM and jump to it - this should not return */
- /* NOTE - code has to be copied out of NAND buffer before
- * other blocks can be read.
- */
- relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE);
-}
-
-void board_init_r(gd_t *gd, ulong dest_addr)
-{
- /* Pointer is writable since we allocated a register for it */
- gd = (gd_t *)CONFIG_SPL_GD_ADDR;
- bd_t *bd;
-
- memset(gd, 0, sizeof(gd_t));
- bd = (bd_t *)(CONFIG_SPL_GD_ADDR + sizeof(gd_t));
- memset(bd, 0, sizeof(bd_t));
- gd->bd = bd;
- bd->bi_memstart = CONFIG_SYS_INIT_L2_ADDR;
- bd->bi_memsize = CONFIG_SYS_L2_SIZE;
-
- probecpu();
- get_clocks();
- mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
- CONFIG_SPL_RELOC_MALLOC_SIZE);
-
-#ifdef CONFIG_SPL_MMC_BOOT
- mmc_initialize(bd);
-#endif
- /* relocate environment function pointers etc. */
-#ifdef CONFIG_SPL_NAND_BOOT
- nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
- (uchar *)CONFIG_ENV_ADDR);
-#endif
-#ifdef CONFIG_SPL_NAND_BOOT
- nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
- (uchar *)CONFIG_ENV_ADDR);
-#endif
-#ifdef CONFIG_SPL_MMC_BOOT
- mmc_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
- (uchar *)CONFIG_ENV_ADDR);
-#endif
-#ifdef CONFIG_SPL_SPI_BOOT
- spi_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
- (uchar *)CONFIG_ENV_ADDR);
-#endif
-
- gd->env_addr = (ulong)(CONFIG_ENV_ADDR);
- gd->env_valid = 1;
-
- gd->ram_size = initdram(0);
-#ifdef CONFIG_SPL_NAND_BOOT
- puts("Tertiary program loader running in sram...");
-#else
- puts("Second program loader running in sram...\n");
-#endif
-
-#ifdef CONFIG_SPL_MMC_BOOT
- mmc_boot();
-#elif defined(CONFIG_SPL_SPI_BOOT)
- spi_boot();
-#elif defined(CONFIG_SPL_NAND_BOOT)
- nand_boot();
-#endif
-}
diff --git a/board/freescale/p1_p2_rdb/spl_minimal.c b/board/freescale/p1_p2_rdb/spl_minimal.c
deleted file mode 100644
index 96a4d1c..0000000
--- a/board/freescale/p1_p2_rdb/spl_minimal.c
+++ /dev/null
@@ -1,84 +0,0 @@
-/*
- * Copyright 2011 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <ns16550.h>
-#include <asm/io.h>
-#include <nand.h>
-#include <linux/compiler.h>
-#include <asm/fsl_law.h>
-#include <fsl_ddr_sdram.h>
-#include <asm/global_data.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-#define SYSCLK_MASK 0x00200000
-#define BOARDREV_MASK 0x10100000
-
-#define SYSCLK_66 66666666
-#define SYSCLK_100 100000000
-
-unsigned long get_board_sys_clk(ulong dummy)
-{
- ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
- u32 val_gpdat, sysclk_gpio;
-
- val_gpdat = in_be32(&pgpio->gpdat);
- sysclk_gpio = val_gpdat & SYSCLK_MASK;
-
- if (sysclk_gpio == 0)
- return SYSCLK_66;
- else
- return SYSCLK_100;
-
- return 0;
-}
-
-void board_init_f(ulong bootflag)
-{
- u32 plat_ratio;
- ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
-
-#if defined(CONFIG_SYS_NAND_BR_PRELIM) && defined(CONFIG_SYS_NAND_OR_PRELIM)
- set_lbc_br(0, CONFIG_SYS_NAND_BR_PRELIM);
- set_lbc_or(0, CONFIG_SYS_NAND_OR_PRELIM);
-#endif
-
- /* initialize selected port with appropriate baud rate */
- plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
- plat_ratio >>= 1;
- gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio;
-
- NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
- gd->bus_clk / 16 / CONFIG_BAUDRATE);
-
- puts("\nNAND boot... ");
-
- /* copy code to RAM and jump to it - this should not return */
- /* NOTE - code has to be copied out of NAND buffer before
- * other blocks can be read.
- */
- relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE);
-}
-
-void board_init_r(gd_t *gd, ulong dest_addr)
-{
- puts("\nSecond program loader running in sram...");
- nand_boot();
-}
-
-void putc(char c)
-{
- if (c == '\n')
- NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, '\r');
-
- NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, c);
-}
-
-void puts(const char *str)
-{
- while (*str)
- putc(*str++);
-}
diff --git a/board/freescale/p1_p2_rdb/tlb.c b/board/freescale/p1_p2_rdb/tlb.c
deleted file mode 100644
index 73f5729..0000000
--- a/board/freescale/p1_p2_rdb/tlb.c
+++ /dev/null
@@ -1,91 +0,0 @@
-/*
- * Copyright 2011 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/mmu.h>
-
-struct fsl_e_tlb_entry tlb_table[] = {
- /* TLB 0 - for temp stack in cache */
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
- CONFIG_SYS_INIT_RAM_ADDR_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 ,
- CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 ,
- CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 ,
- CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
-
- /* TLB 1 */
- /* *I*** - Covers boot page */
- SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 0, BOOKE_PAGESZ_4K, 1),
-
- /* *I*G* - CCSRBAR */
- SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 1, BOOKE_PAGESZ_1M, 1),
-
-#ifndef CONFIG_SPL_BUILD
- /* W**G* - Flash/promjet, localbus */
- /* This will be changed to *I*G* after relocation to RAM. */
- SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
- MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
- 0, 2, BOOKE_PAGESZ_16M, 1),
-
-#if defined(CONFIG_PCI)
- /* *I*G* - PCI */
- SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 3, BOOKE_PAGESZ_1G, 1),
-
- /* *I*G* - PCI I/O */
- SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 4, BOOKE_PAGESZ_256K, 1),
-
-#endif /* #if defined(CONFIG_PCI) */
-#endif
- /* *I*G - NAND */
- SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 5, BOOKE_PAGESZ_1M, 1),
-
- /* *I*G - VSC7385 Switch */
- SET_TLB_ENTRY(1, CONFIG_SYS_VSC7385_BASE, CONFIG_SYS_VSC7385_BASE_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 6, BOOKE_PAGESZ_1M, 1),
-
-#ifdef CONFIG_SYS_INIT_L2_ADDR
- /* *I*G - L2SRAM */
- SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G,
- 0, 11, BOOKE_PAGESZ_256K, 1),
-#if CONFIG_SYS_L2_SIZE >= (256 << 10)
- SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR + 0x40000,
- CONFIG_SYS_INIT_L2_ADDR_PHYS + 0x40000,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 12, BOOKE_PAGESZ_256K, 1),
-#endif
-#endif
-
-#if defined(CONFIG_SYS_RAMBOOT) || \
- (defined(CONFIG_SPL) && !defined(CONFIG_SPL_COMMON_INIT_DDR))
- SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 7, BOOKE_PAGESZ_1G, 1)
-#endif
-};
-
-int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/configs/P1011RDB_36BIT_SDCARD_defconfig b/configs/P1011RDB_36BIT_SDCARD_defconfig
deleted file mode 100644
index 7205bef..0000000
--- a/configs/P1011RDB_36BIT_SDCARD_defconfig
+++ /dev/null
@@ -1,5 +0,0 @@
-CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="P1011RDB,36BIT,SDCARD"
-+S:CONFIG_PPC=y
-+S:CONFIG_MPC85xx=y
-+S:CONFIG_TARGET_P1_P2_RDB=y
diff --git a/configs/P1011RDB_36BIT_SPIFLASH_defconfig b/configs/P1011RDB_36BIT_SPIFLASH_defconfig
deleted file mode 100644
index 8b3806e..0000000
--- a/configs/P1011RDB_36BIT_SPIFLASH_defconfig
+++ /dev/null
@@ -1,5 +0,0 @@
-CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="P1011RDB,36BIT,SPIFLASH"
-+S:CONFIG_PPC=y
-+S:CONFIG_MPC85xx=y
-+S:CONFIG_TARGET_P1_P2_RDB=y
diff --git a/configs/P1011RDB_36BIT_defconfig b/configs/P1011RDB_36BIT_defconfig
deleted file mode 100644
index c47f2e2..0000000
--- a/configs/P1011RDB_36BIT_defconfig
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_SYS_EXTRA_OPTIONS="P1011RDB,36BIT"
-CONFIG_PPC=y
-CONFIG_MPC85xx=y
-CONFIG_TARGET_P1_P2_RDB=y
diff --git a/configs/P1011RDB_NAND_defconfig b/configs/P1011RDB_NAND_defconfig
deleted file mode 100644
index aac0190..0000000
--- a/configs/P1011RDB_NAND_defconfig
+++ /dev/null
@@ -1,6 +0,0 @@
-CONFIG_SPL=y
-CONFIG_TPL=y
-CONFIG_SYS_EXTRA_OPTIONS="P1011RDB,NAND"
-+ST:CONFIG_PPC=y
-+ST:CONFIG_MPC85xx=y
-+ST:CONFIG_TARGET_P1_P2_RDB=y
diff --git a/configs/P1011RDB_SDCARD_defconfig b/configs/P1011RDB_SDCARD_defconfig
deleted file mode 100644
index 16e872f..0000000
--- a/configs/P1011RDB_SDCARD_defconfig
+++ /dev/null
@@ -1,5 +0,0 @@
-CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="P1011RDB,SDCARD"
-+S:CONFIG_PPC=y
-+S:CONFIG_MPC85xx=y
-+S:CONFIG_TARGET_P1_P2_RDB=y
diff --git a/configs/P1011RDB_SPIFLASH_defconfig b/configs/P1011RDB_SPIFLASH_defconfig
deleted file mode 100644
index d14820f..0000000
--- a/configs/P1011RDB_SPIFLASH_defconfig
+++ /dev/null
@@ -1,5 +0,0 @@
-CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="P1011RDB,SPIFLASH"
-+S:CONFIG_PPC=y
-+S:CONFIG_MPC85xx=y
-+S:CONFIG_TARGET_P1_P2_RDB=y
diff --git a/configs/P1011RDB_defconfig b/configs/P1011RDB_defconfig
deleted file mode 100644
index d14868a..0000000
--- a/configs/P1011RDB_defconfig
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_SYS_EXTRA_OPTIONS="P1011RDB"
-CONFIG_PPC=y
-CONFIG_MPC85xx=y
-CONFIG_TARGET_P1_P2_RDB=y
diff --git a/configs/P1020RDB_36BIT_SDCARD_defconfig b/configs/P1020RDB_36BIT_SDCARD_defconfig
deleted file mode 100644
index a18563e..0000000
--- a/configs/P1020RDB_36BIT_SDCARD_defconfig
+++ /dev/null
@@ -1,5 +0,0 @@
-CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="P1020RDB,36BIT,SDCARD"
-+S:CONFIG_PPC=y
-+S:CONFIG_MPC85xx=y
-+S:CONFIG_TARGET_P1_P2_RDB=y
diff --git a/configs/P1020RDB_36BIT_SPIFLASH_defconfig b/configs/P1020RDB_36BIT_SPIFLASH_defconfig
deleted file mode 100644
index aa145fc..0000000
--- a/configs/P1020RDB_36BIT_SPIFLASH_defconfig
+++ /dev/null
@@ -1,5 +0,0 @@
-CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="P1020RDB,36BIT,SPIFLASH"
-+S:CONFIG_PPC=y
-+S:CONFIG_MPC85xx=y
-+S:CONFIG_TARGET_P1_P2_RDB=y
diff --git a/configs/P1020RDB_36BIT_defconfig b/configs/P1020RDB_36BIT_defconfig
deleted file mode 100644
index 844651f..0000000
--- a/configs/P1020RDB_36BIT_defconfig
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_SYS_EXTRA_OPTIONS="P1020RDB,36BIT"
-CONFIG_PPC=y
-CONFIG_MPC85xx=y
-CONFIG_TARGET_P1_P2_RDB=y
diff --git a/configs/P1020RDB_NAND_defconfig b/configs/P1020RDB_NAND_defconfig
deleted file mode 100644
index 441241b..0000000
--- a/configs/P1020RDB_NAND_defconfig
+++ /dev/null
@@ -1,6 +0,0 @@
-CONFIG_SPL=y
-CONFIG_TPL=y
-CONFIG_SYS_EXTRA_OPTIONS="P1020RDB,NAND"
-+ST:CONFIG_PPC=y
-+ST:CONFIG_MPC85xx=y
-+ST:CONFIG_TARGET_P1_P2_RDB=y
diff --git a/configs/P1020RDB_SDCARD_defconfig b/configs/P1020RDB_SDCARD_defconfig
deleted file mode 100644
index 1349bea..0000000
--- a/configs/P1020RDB_SDCARD_defconfig
+++ /dev/null
@@ -1,5 +0,0 @@
-CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="P1020RDB,SDCARD"
-+S:CONFIG_PPC=y
-+S:CONFIG_MPC85xx=y
-+S:CONFIG_TARGET_P1_P2_RDB=y
diff --git a/configs/P1020RDB_SPIFLASH_defconfig b/configs/P1020RDB_SPIFLASH_defconfig
deleted file mode 100644
index 7eb8696..0000000
--- a/configs/P1020RDB_SPIFLASH_defconfig
+++ /dev/null
@@ -1,5 +0,0 @@
-CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="P1020RDB,SPIFLASH"
-+S:CONFIG_PPC=y
-+S:CONFIG_MPC85xx=y
-+S:CONFIG_TARGET_P1_P2_RDB=y
diff --git a/configs/P1020RDB_defconfig b/configs/P1020RDB_defconfig
deleted file mode 100644
index fc58ac9..0000000
--- a/configs/P1020RDB_defconfig
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_SYS_EXTRA_OPTIONS="P1020RDB"
-CONFIG_PPC=y
-CONFIG_MPC85xx=y
-CONFIG_TARGET_P1_P2_RDB=y
diff --git a/configs/P2010RDB_36BIT_SDCARD_defconfig b/configs/P2010RDB_36BIT_SDCARD_defconfig
deleted file mode 100644
index 1381e8e..0000000
--- a/configs/P2010RDB_36BIT_SDCARD_defconfig
+++ /dev/null
@@ -1,5 +0,0 @@
-CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="P2010RDB,36BIT,SDCARD"
-+S:CONFIG_PPC=y
-+S:CONFIG_MPC85xx=y
-+S:CONFIG_TARGET_P1_P2_RDB=y
diff --git a/configs/P2010RDB_36BIT_SPIFLASH_defconfig b/configs/P2010RDB_36BIT_SPIFLASH_defconfig
deleted file mode 100644
index 53ebca1..0000000
--- a/configs/P2010RDB_36BIT_SPIFLASH_defconfig
+++ /dev/null
@@ -1,5 +0,0 @@
-CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="P2010RDB,36BIT,SPIFLASH"
-+S:CONFIG_PPC=y
-+S:CONFIG_MPC85xx=y
-+S:CONFIG_TARGET_P1_P2_RDB=y
diff --git a/configs/P2010RDB_36BIT_defconfig b/configs/P2010RDB_36BIT_defconfig
deleted file mode 100644
index de29dcb..0000000
--- a/configs/P2010RDB_36BIT_defconfig
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_SYS_EXTRA_OPTIONS="P2010RDB,36BIT"
-CONFIG_PPC=y
-CONFIG_MPC85xx=y
-CONFIG_TARGET_P1_P2_RDB=y
diff --git a/configs/P2010RDB_NAND_defconfig b/configs/P2010RDB_NAND_defconfig
deleted file mode 100644
index bc91a67..0000000
--- a/configs/P2010RDB_NAND_defconfig
+++ /dev/null
@@ -1,6 +0,0 @@
-CONFIG_SPL=y
-CONFIG_TPL=y
-CONFIG_SYS_EXTRA_OPTIONS="P2010RDB,NAND"
-+ST:CONFIG_PPC=y
-+ST:CONFIG_MPC85xx=y
-+ST:CONFIG_TARGET_P1_P2_RDB=y
diff --git a/configs/P2010RDB_SDCARD_defconfig b/configs/P2010RDB_SDCARD_defconfig
deleted file mode 100644
index fd4ade7..0000000
--- a/configs/P2010RDB_SDCARD_defconfig
+++ /dev/null
@@ -1,5 +0,0 @@
-CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="P2010RDB,SDCARD"
-+S:CONFIG_PPC=y
-+S:CONFIG_MPC85xx=y
-+S:CONFIG_TARGET_P1_P2_RDB=y
diff --git a/configs/P2010RDB_SPIFLASH_defconfig b/configs/P2010RDB_SPIFLASH_defconfig
deleted file mode 100644
index 9631864..0000000
--- a/configs/P2010RDB_SPIFLASH_defconfig
+++ /dev/null
@@ -1,5 +0,0 @@
-CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="P2010RDB,SPIFLASH"
-+S:CONFIG_PPC=y
-+S:CONFIG_MPC85xx=y
-+S:CONFIG_TARGET_P1_P2_RDB=y
diff --git a/configs/P2010RDB_defconfig b/configs/P2010RDB_defconfig
deleted file mode 100644
index 3b3352a..0000000
--- a/configs/P2010RDB_defconfig
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_SYS_EXTRA_OPTIONS="P2010RDB"
-CONFIG_PPC=y
-CONFIG_MPC85xx=y
-CONFIG_TARGET_P1_P2_RDB=y
diff --git a/configs/P2020RDB_36BIT_SDCARD_defconfig b/configs/P2020RDB_36BIT_SDCARD_defconfig
deleted file mode 100644
index 43cc2e3..0000000
--- a/configs/P2020RDB_36BIT_SDCARD_defconfig
+++ /dev/null
@@ -1,5 +0,0 @@
-CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="P2020RDB,36BIT,SDCARD"
-+S:CONFIG_PPC=y
-+S:CONFIG_MPC85xx=y
-+S:CONFIG_TARGET_P1_P2_RDB=y
diff --git a/configs/P2020RDB_36BIT_SPIFLASH_defconfig b/configs/P2020RDB_36BIT_SPIFLASH_defconfig
deleted file mode 100644
index f1199b6..0000000
--- a/configs/P2020RDB_36BIT_SPIFLASH_defconfig
+++ /dev/null
@@ -1,5 +0,0 @@
-CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="P2020RDB,36BIT,SPIFLASH"
-+S:CONFIG_PPC=y
-+S:CONFIG_MPC85xx=y
-+S:CONFIG_TARGET_P1_P2_RDB=y
diff --git a/configs/P2020RDB_36BIT_defconfig b/configs/P2020RDB_36BIT_defconfig
deleted file mode 100644
index 87490fd..0000000
--- a/configs/P2020RDB_36BIT_defconfig
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_SYS_EXTRA_OPTIONS="P2020RDB,36BIT"
-CONFIG_PPC=y
-CONFIG_MPC85xx=y
-CONFIG_TARGET_P1_P2_RDB=y
diff --git a/configs/P2020RDB_NAND_defconfig b/configs/P2020RDB_NAND_defconfig
deleted file mode 100644
index 70ee084..0000000
--- a/configs/P2020RDB_NAND_defconfig
+++ /dev/null
@@ -1,6 +0,0 @@
-CONFIG_SPL=y
-CONFIG_TPL=y
-CONFIG_SYS_EXTRA_OPTIONS="P2020RDB,NAND"
-+ST:CONFIG_PPC=y
-+ST:CONFIG_MPC85xx=y
-+ST:CONFIG_TARGET_P1_P2_RDB=y
diff --git a/configs/P2020RDB_SDCARD_defconfig b/configs/P2020RDB_SDCARD_defconfig
deleted file mode 100644
index 2bf5773..0000000
--- a/configs/P2020RDB_SDCARD_defconfig
+++ /dev/null
@@ -1,5 +0,0 @@
-CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="P2020RDB,SDCARD"
-+S:CONFIG_PPC=y
-+S:CONFIG_MPC85xx=y
-+S:CONFIG_TARGET_P1_P2_RDB=y
diff --git a/configs/P2020RDB_SPIFLASH_defconfig b/configs/P2020RDB_SPIFLASH_defconfig
deleted file mode 100644
index 290ebd2..0000000
--- a/configs/P2020RDB_SPIFLASH_defconfig
+++ /dev/null
@@ -1,5 +0,0 @@
-CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="P2020RDB,SPIFLASH"
-+S:CONFIG_PPC=y
-+S:CONFIG_MPC85xx=y
-+S:CONFIG_TARGET_P1_P2_RDB=y
diff --git a/configs/P2020RDB_defconfig b/configs/P2020RDB_defconfig
deleted file mode 100644
index cc39735..0000000
--- a/configs/P2020RDB_defconfig
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_SYS_EXTRA_OPTIONS="P2020RDB"
-CONFIG_PPC=y
-CONFIG_MPC85xx=y
-CONFIG_TARGET_P1_P2_RDB=y
diff --git a/doc/README.scrapyard b/doc/README.scrapyard
index 3b201b7..f436a8e 100644
--- a/doc/README.scrapyard
+++ b/doc/README.scrapyard
@@ -12,6 +12,10 @@ The list should be sorted in reverse chronological order.
Board Arch CPU Commit Removed Last known maintainer/contact
=================================================================================================
+P2020RDB powerpc mpc85xx - - Poonam Aggrwal <poonam.aggrwal@freescale.com>
+P2010RDB powerpc mpc85xx - -
+P1020RDB powerpc mpc85xx - -
+P1011RDB powerpc mpc85xx - -
MPC8360EMDS powerpc mpc83xx - - Dave Liu <daveliu@freescale.com>
MPC8360ERDK powerpc mpc83xx - - Anton Vorontsov <avorontsov@ru.mvista.com>
P3G4 powerpc 74xx_7xx d928664f 2015-01-16 Wolfgang Denk <wd@denx.de>
diff --git a/include/configs/P1_P2_RDB.h b/include/configs/P1_P2_RDB.h
deleted file mode 100644
index c75638a..0000000
--- a/include/configs/P1_P2_RDB.h
+++ /dev/null
@@ -1,808 +0,0 @@
-/*
- * Copyright 2009-2011 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * P1 P2 RDB board configuration file
- * This file is intended to address a set of Low End and Ultra Low End
- * Freescale SOCs of QorIQ series(RDB platforms).
- * Currently only P2020RDB
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#ifdef CONFIG_36BIT
-#define CONFIG_PHYS_64BIT
-#endif
-
-#ifdef CONFIG_P1011RDB
-#define CONFIG_P1011
-#define CONFIG_SYS_L2_SIZE (256 << 10)
-#endif
-#ifdef CONFIG_P1020RDB
-#define CONFIG_P1020
-#define CONFIG_SYS_L2_SIZE (256 << 10)
-#endif
-#ifdef CONFIG_P2010RDB
-#define CONFIG_P2010
-#define CONFIG_SYS_L2_SIZE (512 << 10)
-#endif
-#ifdef CONFIG_P2020RDB
-#define CONFIG_P2020
-#define CONFIG_SYS_L2_SIZE (512 << 10)
-#endif
-
-#ifdef CONFIG_SDCARD
-#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
-#define CONFIG_SPL_ENV_SUPPORT
-#define CONFIG_SPL_SERIAL_SUPPORT
-#define CONFIG_SPL_MMC_SUPPORT
-#define CONFIG_SPL_MMC_MINIMAL
-#define CONFIG_SPL_FLUSH_IMAGE
-#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
-#define CONFIG_SPL_LIBGENERIC_SUPPORT
-#define CONFIG_SPL_LIBCOMMON_SUPPORT
-#define CONFIG_SPL_I2C_SUPPORT
-#define CONFIG_SYS_TEXT_BASE 0x11001000
-#define CONFIG_SPL_TEXT_BASE 0xf8f81000
-#define CONFIG_SPL_PAD_TO 0x20000
-#define CONFIG_SPL_MAX_SIZE (128 * 1024)
-#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
-#define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000)
-#define CONFIG_SYS_MMC_U_BOOT_START (0x11000000)
-#define CONFIG_SYS_MMC_U_BOOT_OFFS (129 << 10)
-#define CONFIG_SYS_MPC85XX_NO_RESETVEC
-#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
-#define CONFIG_SPL_MMC_BOOT
-#ifdef CONFIG_SPL_BUILD
-#define CONFIG_SPL_COMMON_INIT_DDR
-#endif
-#endif
-
-#ifdef CONFIG_SPIFLASH
-#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
-#define CONFIG_SPL_ENV_SUPPORT
-#define CONFIG_SPL_SERIAL_SUPPORT
-#define CONFIG_SPL_SPI_SUPPORT
-#define CONFIG_SPL_SPI_FLASH_SUPPORT
-#define CONFIG_SPL_SPI_FLASH_MINIMAL
-#define CONFIG_SPL_FLUSH_IMAGE
-#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
-#define CONFIG_SPL_LIBGENERIC_SUPPORT
-#define CONFIG_SPL_LIBCOMMON_SUPPORT
-#define CONFIG_SPL_I2C_SUPPORT
-#define CONFIG_SYS_TEXT_BASE 0x11001000
-#define CONFIG_SPL_TEXT_BASE 0xf8f81000
-#define CONFIG_SPL_PAD_TO 0x20000
-#define CONFIG_SPL_MAX_SIZE (128 * 1024)
-#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
-#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000)
-#define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000)
-#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (128 << 10)
-#define CONFIG_SYS_MPC85XX_NO_RESETVEC
-#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
-#define CONFIG_SPL_SPI_BOOT
-#ifdef CONFIG_SPL_BUILD
-#define CONFIG_SPL_COMMON_INIT_DDR
-#endif
-#endif
-
-#ifdef CONFIG_NAND
-#ifdef CONFIG_TPL_BUILD
-#define CONFIG_SPL_NAND_BOOT
-#define CONFIG_SPL_FLUSH_IMAGE
-#define CONFIG_SPL_ENV_SUPPORT
-#define CONFIG_SPL_NAND_INIT
-#define CONFIG_SPL_SERIAL_SUPPORT
-#define CONFIG_SPL_LIBGENERIC_SUPPORT
-#define CONFIG_SPL_LIBCOMMON_SUPPORT
-#define CONFIG_SPL_I2C_SUPPORT
-#define CONFIG_SPL_NAND_SUPPORT
-#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
-#define CONFIG_SPL_COMMON_INIT_DDR
-#define CONFIG_SPL_MAX_SIZE (128 << 10)
-#define CONFIG_SPL_TEXT_BASE 0xf8f81000
-#define CONFIG_SYS_MPC85XX_NO_RESETVEC
-#define CONFIG_SYS_NAND_U_BOOT_SIZE (832 << 10)
-#define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000)
-#define CONFIG_SYS_NAND_U_BOOT_START (0x11000000)
-#define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10)
-#elif defined(CONFIG_SPL_BUILD)
-#define CONFIG_SPL_INIT_MINIMAL
-#define CONFIG_SPL_SERIAL_SUPPORT
-#define CONFIG_SPL_NAND_SUPPORT
-#define CONFIG_SPL_FLUSH_IMAGE
-#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
-#define CONFIG_SPL_TEXT_BASE 0xff800000
-#define CONFIG_SPL_MAX_SIZE 4096
-#define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10)
-#define CONFIG_SYS_NAND_U_BOOT_DST 0xf8f80000
-#define CONFIG_SYS_NAND_U_BOOT_START 0xf8f80000
-#define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10)
-#endif /* not CONFIG_TPL_BUILD */
-
-#define CONFIG_SPL_PAD_TO 0x20000
-#define CONFIG_TPL_PAD_TO 0x20000
-#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
-#define CONFIG_SYS_TEXT_BASE 0x11001000
-#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
-#endif
-
-#ifndef CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_TEXT_BASE 0xeff40000
-#endif
-
-#ifndef CONFIG_RESET_VECTOR_ADDRESS
-#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
-#endif
-
-#ifndef CONFIG_SYS_MONITOR_BASE
-#ifdef CONFIG_SPL_BUILD
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
-#else
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
-#endif
-#endif
-
-/* High Level Configuration Options */
-#define CONFIG_BOOKE 1 /* BOOKE */
-#define CONFIG_E500 1 /* BOOKE e500 family */
-#define CONFIG_FSL_ELBC 1 /* Enable eLBC Support */
-
-#define CONFIG_PCI 1 /* Enable PCI/PCIE */
-#if defined(CONFIG_PCI)
-#define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */
-#define CONFIG_PCIE2 1 /* PCIE controler 2 (slot 2) */
-#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
-#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
-#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
-#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
-#endif /* #if defined(CONFIG_PCI) */
-#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
-#define CONFIG_TSEC_ENET /* tsec ethernet support */
-#define CONFIG_ENV_OVERWRITE
-
-#if defined(CONFIG_PCI)
-#define CONFIG_E1000 1 /* E1000 pci Ethernet card*/
-#endif
-
-#ifndef __ASSEMBLY__
-extern unsigned long get_board_sys_clk(unsigned long dummy);
-#endif
-#define CONFIG_DDR_CLK_FREQ 66666666 /* DDRCLK on P1_P2 RDB */
-#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /*sysclk for P1_P2 RDB */
-
-#if defined(CONFIG_P2020) || defined(CONFIG_P1020)
-#define CONFIG_MP
-#endif
-
-#define CONFIG_HWCONFIG
-
-/*
- * These can be toggled for performance analysis, otherwise use default.
- */
-#define CONFIG_L2_CACHE /* toggle L2 cache */
-#define CONFIG_BTB /* toggle branch predition */
-
-#define CONFIG_ADDR_STREAMING /* toggle addr streaming */
-
-#define CONFIG_ENABLE_36BIT_PHYS 1
-
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_ADDR_MAP 1
-#define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
-#endif
-
-#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x1fffffff
-#define CONFIG_PANIC_HANG /* do not reset board on panic */
-
-/*
- * Config the L2 Cache as L2 SRAM
-*/
-#if defined(CONFIG_SPL_BUILD)
-#if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
-#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
-#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
-#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
-#define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000
-#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024)
-#define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 116 * 1024)
-#define CONFIG_SPL_RELOC_STACK_SIZE (32 << 10)
-#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 148 * 1024)
-#if defined(CONFIG_P2020RDB)
-#define CONFIG_SPL_RELOC_MALLOC_SIZE (364 << 10)
-#else
-#define CONFIG_SPL_RELOC_MALLOC_SIZE (108 << 10)
-#endif
-#elif defined(CONFIG_NAND)
-#ifdef CONFIG_TPL_BUILD
-#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
-#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
-#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
-#define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000
-#define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024)
-#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024)
-#define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10)
-#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024)
-#else
-#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
-#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
-#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
-#define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x2000)
-#define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
-#endif /* CONFIG_TPL_BUILD */
-#endif
-#endif
-
-#ifdef CONFIG_SPL_BUILD
-#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
-#endif
-
-/* DDR Setup */
-#define CONFIG_SYS_FSL_DDR2
-#undef CONFIG_FSL_DDR_INTERACTIVE
-#undef CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
-
-#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
-
-#if defined(CONFIG_P1011RDB) || defined(CONFIG_P1020RDB)
-/*
- * P1020 and it's derivatives support max 32bit DDR width
- * So Reduce available DDR size
-*/
-#define CONFIG_SYS_SDRAM_SIZE 512
-#else
-#define CONFIG_SYS_SDRAM_SIZE 1024
-#endif
-#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
-
-#define CONFIG_NUM_DDR_CONTROLLERS 1
-#define CONFIG_DIMM_SLOTS_PER_CTLR 1
-#define CONFIG_CHIP_SELECTS_PER_CTRL 1
-
-#define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d
-#define CONFIG_SYS_DDR_ERR_DIS 0x00000000
-#define CONFIG_SYS_DDR_SBE 0x00FF0000
-
-/*
- * Memory map
- *
- * 0x0000_0000 0x3fff_ffff DDR 1G cacheablen
- * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable
- * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable
- *
- * Localbus cacheable (TBD)
- * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable
- *
- * Localbus non-cacheable
- * 0xef00_0000 0xefff_ffff FLASH 16M non-cacheable
- * 0xffa0_0000 0xffaf_ffff NAND 1M non-cacheable
- * 0xffb0_0000 0xffbf_ffff VSC7385 switch 1M non-cacheable
- * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0
- * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
- */
-
-/*
- * Local Bus Definitions
- */
-#define CONFIG_SYS_FLASH_BASE 0xef000000 /* start of FLASH 16M */
-
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_FLASH_BASE_PHYS 0xfef000000ull
-#else
-#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
-#endif
-
-#define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
- BR_PS_16 | BR_V)
-#define CONFIG_FLASH_OR_PRELIM 0xff000ff7
-
-#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
-#define CONFIG_SYS_FLASH_QUIET_TEST
-#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
-
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */
-#undef CONFIG_SYS_FLASH_CHECKSUM
-#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
-
-#define CONFIG_FLASH_CFI_DRIVER
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_SYS_FLASH_EMPTY_INFO
-#define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
-
-#define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
-#define CONFIG_MISC_INIT_R
-#define CONFIG_HWCONFIG
-
-#define CONFIG_SYS_INIT_RAM_LOCK 1
-#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
-/* The assembler doesn't like typecast */
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
- ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
- CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
-#else
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR /* Initial L1 address */
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
-#endif
-#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */
-
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \
- - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
-#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc*/
-
-#define CONFIG_SYS_NAND_BASE 0xff800000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull
-#else
-#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
-#endif
-
-#define CONFIG_CMD_NAND
-#define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE}
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_MTD_NAND_VERIFY_WRITE
-#define CONFIG_NAND_FSL_ELBC 1
-#define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024)
-
-/* NAND flash config */
-#define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
- | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
- | BR_PS_8 /* Port Size = 8 bit */ \
- | BR_MS_FCM /* MSEL = FCM */ \
- | BR_V) /* valid */
-
-#define CONFIG_SYS_NAND_OR_PRELIM (0xFFF80000 /* length 32K */ \
- | OR_FCM_CSCT \
- | OR_FCM_CST \
- | OR_FCM_CHT \
- | OR_FCM_SCY_1 \
- | OR_FCM_TRLX \
- | OR_FCM_EHTR)
-
-#ifdef CONFIG_NAND
-#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
-#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
-#define CONFIG_SYS_BR1_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
-#define CONFIG_SYS_OR1_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
-#else
-#define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
-#define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
-#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
-#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
-#endif
-
-#define CONFIG_SYS_VSC7385_BASE 0xffb00000
-
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_VSC7385_BASE_PHYS 0xfffb00000ull
-#else
-#define CONFIG_SYS_VSC7385_BASE_PHYS CONFIG_SYS_VSC7385_BASE
-#endif
-
-#define CONFIG_SYS_BR2_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_VSC7385_BASE) \
- | BR_PS_8 | BR_V)
-#define CONFIG_SYS_OR2_PRELIM (OR_AM_128KB | OR_GPCM_CSNT | OR_GPCM_XACS | \
- OR_GPCM_SCY_15 | OR_GPCM_SETA | OR_GPCM_TRLX | \
- OR_GPCM_EHTR | OR_GPCM_EAD)
-
-/* Serial Port - controlled on board with jumper J8
- * open - index 2
- * shorted - index 1
- */
-#define CONFIG_CONS_INDEX 1
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
-#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)
-#define CONFIG_NS16550_MIN_FUNCTIONS
-#endif
-
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */
-
-#define CONFIG_SYS_BAUDRATE_TABLE \
- {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
-
-#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
-#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
-
-/* Use the HUSH parser */
-#define CONFIG_SYS_HUSH_PARSER
-
-/*
- * Pass open firmware flat tree
- */
-#define CONFIG_OF_LIBFDT 1
-#define CONFIG_OF_BOARD_SETUP 1
-#define CONFIG_OF_STDOUT_VIA_ALIAS 1
-
-/* new uImage format support */
-#define CONFIG_FIT 1
-#define CONFIG_FIT_VERBOSE 1 /* enable fit_format_{error,warning}() */
-
-/* I2C */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_FSL
-#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
-#define CONFIG_SYS_FSL_I2C_SPEED 400000
-#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
-#define CONFIG_SYS_FSL_I2C2_SPEED 400000
-#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
-#define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} }
-
-/*
- * I2C2 EEPROM
- */
-#define CONFIG_ID_EEPROM
-#ifdef CONFIG_ID_EEPROM
-#define CONFIG_SYS_I2C_EEPROM_NXID
-#endif
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x52
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-#define CONFIG_SYS_EEPROM_BUS_NUM 1
-
-#define CONFIG_SYS_I2C_PCA9557_ADDR 0x18
-
-#define CONFIG_RTC_DS1337
-#define CONFIG_SYS_RTC_DS1337_NOOSC
-#define CONFIG_SYS_I2C_RTC_ADDR 0x68
-
-/* eSPI - Enhanced SPI */
-#define CONFIG_FSL_ESPI
-#define CONFIG_SPI_FLASH
-#define CONFIG_SPI_FLASH_SPANSION
-#define CONFIG_CMD_SF
-#define CONFIG_SF_DEFAULT_SPEED 10000000
-#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
-
-/*
- * General PCI
- * Memory space is mapped 1-1, but I/O space must start from 0.
- */
-
-#if defined(CONFIG_PCI)
-/* controller 2, Slot 2, tgtid 2, Base address 9000 */
-#define CONFIG_SYS_PCIE2_NAME "Slot 1"
-#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000
-#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
-#else
-#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
-#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
-#endif
-#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
-#define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
-#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull
-#else
-#define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
-#endif
-#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
-
-/* controller 1, Slot 1, tgtid 1, Base address a000 */
-#define CONFIG_SYS_PCIE1_NAME "Slot 2"
-#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
-#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
-#else
-#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
-#define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
-#endif
-#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
-#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000
-#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull
-#else
-#define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000
-#endif
-#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
-
-#define CONFIG_PCI_PNP /* do pci plug-and-play */
-
-#undef CONFIG_EEPRO100
-#undef CONFIG_TULIP
-#undef CONFIG_RTL8139
-
-#ifdef CONFIG_RTL8139
-/* This macro is used by RTL8139 but not defined in PPC architecture */
-#define KSEG1ADDR(x) (x)
-#define _IO_BASE 0x00000000
-#endif
-
-
-#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
-#define CONFIG_DOS_PARTITION
-
-#endif /* CONFIG_PCI */
-
-
-#if defined(CONFIG_TSEC_ENET)
-#define CONFIG_MII 1 /* MII PHY management */
-#define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
-#define CONFIG_TSEC1 1
-#define CONFIG_TSEC1_NAME "eTSEC1"
-#define CONFIG_TSEC2 1
-#define CONFIG_TSEC2_NAME "eTSEC2"
-#define CONFIG_TSEC3 1
-#define CONFIG_TSEC3_NAME "eTSEC3"
-
-#define TSEC1_PHY_ADDR 2
-#define TSEC2_PHY_ADDR 0
-#define TSEC3_PHY_ADDR 1
-
-#define CONFIG_VSC7385_ENET
-
-#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
-#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
-#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
-
-#define TSEC1_PHYIDX 0
-#define TSEC2_PHYIDX 0
-#define TSEC3_PHYIDX 0
-
-/* Vitesse 7385 */
-
-#ifdef CONFIG_VSC7385_ENET
-/* The size of the VSC7385 firmware image */
-#define CONFIG_VSC7385_IMAGE_SIZE 8192
-#endif
-
-#define CONFIG_ETHPRIME "eTSEC1"
-
-#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
-
-#endif /* CONFIG_TSEC_ENET */
-
-/*
- * Environment
- */
-#ifdef CONFIG_SPIFLASH
-#define CONFIG_ENV_IS_IN_SPI_FLASH
-#define CONFIG_ENV_SPI_BUS 0
-#define CONFIG_ENV_SPI_CS 0
-#define CONFIG_ENV_SPI_MAX_HZ 10000000
-#define CONFIG_ENV_SPI_MODE 0
-#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
-#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
-#define CONFIG_ENV_SECT_SIZE 0x10000
-#define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
-#elif defined(CONFIG_SDCARD)
-#define CONFIG_ENV_IS_IN_MMC
-#define CONFIG_FSL_FIXED_MMC_LOCATION
-#define CONFIG_ENV_SIZE 0x2000
-#define CONFIG_SYS_MMC_ENV_DEV 0
-#define CONFIG_ENV_OFFSET (512 * 0x800)
-#define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
-#elif defined(CONFIG_NAND)
-#ifdef CONFIG_TPL_BUILD
-#define CONFIG_ENV_SIZE 0x2000
-#define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
-#else
-#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
-#endif
-#define CONFIG_ENV_IS_IN_NAND
-#define CONFIG_ENV_OFFSET (1024 * 1024)
-#define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE)
-#elif defined(CONFIG_SYS_RAMBOOT)
-#define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */
-#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
-#define CONFIG_ENV_SIZE 0x2000
-#else
-#define CONFIG_ENV_IS_IN_FLASH
-#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE 0x2000
-#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
-#endif
-
-
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_DATE
-#define CONFIG_CMD_ELF
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_IRQ
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_SETEXPR
-#define CONFIG_CMD_REGINFO
-
-#if defined(CONFIG_PCI)
-#define CONFIG_CMD_NET
-#define CONFIG_CMD_PCI
-#endif
-
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-
-#define CONFIG_MMC 1
-
-#ifdef CONFIG_MMC
-#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
-#define CONFIG_CMD_MMC
-#define CONFIG_DOS_PARTITION
-#define CONFIG_FSL_ESDHC
-#define CONFIG_GENERIC_MMC
-#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
-#ifdef CONFIG_P2020
-#define CONFIG_SYS_FSL_ESDHC_USE_PIO /* P2020 eSDHC DMA is not functional*/
-#endif
-#endif
-
-#define CONFIG_HAS_FSL_DR_USB
-
-#if defined(CONFIG_HAS_FSL_DR_USB)
-#define CONFIG_USB_EHCI
-
-#ifdef CONFIG_USB_EHCI
-#define CONFIG_CMD_USB
-#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
-#define CONFIG_USB_EHCI_FSL
-#define CONFIG_USB_STORAGE
-#endif
-#endif
-
-#if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI)
-#define CONFIG_CMD_EXT2
-#define CONFIG_CMD_FAT
-#define CONFIG_DOS_PARTITION
-#endif
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_CMDLINE_EDITING /* Command-line editing */
-#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
-#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
- /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 64 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (64 << 20)/* Initial Memory map for Linux*/
-#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
-#endif
-
-/*
- * Environment Configuration
- */
-
-#if defined(CONFIG_TSEC_ENET)
-#define CONFIG_HAS_ETH0
-#define CONFIG_HAS_ETH1
-#define CONFIG_HAS_ETH2
-#endif
-
-#define CONFIG_HOSTNAME P2020RDB
-#define CONFIG_ROOTPATH "/opt/nfsroot"
-#define CONFIG_BOOTFILE "uImage"
-#define CONFIG_UBOOTPATH u-boot.bin/* U-Boot image on TFTP server */
-
-/* default location for tftp and bootm */
-#define CONFIG_LOADADDR 1000000
-
-#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
-#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
-
-#define CONFIG_BAUDRATE 115200
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "netdev=eth0\0" \
- "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
- "loadaddr=1000000\0" \
- "tftpflash=tftpboot $loadaddr $uboot; " \
- "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
- " +$filesize; " \
- "erase " __stringify(CONFIG_SYS_TEXT_BASE) \
- " +$filesize; " \
- "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
- " $filesize; " \
- "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
- " +$filesize; " \
- "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
- " $filesize\0" \
- "consoledev=ttyS0\0" \
- "ramdiskaddr=2000000\0" \
- "ramdiskfile=rootfs.ext2.gz.uboot\0" \
- "fdtaddr=c00000\0" \
- "fdtfile=p2020rdb.dtb\0" \
- "bdev=sda1\0" \
- "jffs2nor=mtdblock3\0" \
- "norbootaddr=ef080000\0" \
- "norfdtaddr=ef040000\0" \
- "jffs2nand=mtdblock9\0" \
- "nandbootaddr=100000\0" \
- "nandfdtaddr=80000\0" \
- "nandimgsize=400000\0" \
- "nandfdtsize=80000\0" \
- "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" \
- "vscfw_addr=ef000000\0" \
- "othbootargs=ramdisk_size=600000\0" \
- "usbfatboot=setenv bootargs root=/dev/ram rw " \
- "console=$consoledev,$baudrate $othbootargs; " \
- "usb start;" \
- "fatload usb 0:2 $loadaddr $bootfile;" \
- "fatload usb 0:2 $fdtaddr $fdtfile;" \
- "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \
- "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \
- "usbext2boot=setenv bootargs root=/dev/ram rw " \
- "console=$consoledev,$baudrate $othbootargs; " \
- "usb start;" \
- "ext2load usb 0:4 $loadaddr $bootfile;" \
- "ext2load usb 0:4 $fdtaddr $fdtfile;" \
- "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \
- "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \
- "norboot=setenv bootargs root=/dev/$jffs2nor rw " \
- "console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;" \
- "bootm $norbootaddr - $norfdtaddr\0" \
- "nandboot=setenv bootargs root=/dev/$jffs2nand rw rootfstype=jffs2 " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "nand read 2000000 $nandbootaddr $nandimgsize;" \
- "nand read 3000000 $nandfdtaddr $nandfdtsize;" \
- "bootm 2000000 - 3000000;\0"
-
-#define CONFIG_NFSBOOTCOMMAND \
- "setenv bootargs root=/dev/nfs rw " \
- "nfsroot=$serverip:$rootpath " \
- "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr - $fdtaddr"
-
-#define CONFIG_HDBOOT \
- "setenv bootargs root=/dev/$bdev rw rootdelay=30 " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "usb start;" \
- "ext2load usb 0:1 $loadaddr /boot/$bootfile;" \
- "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \
- "bootm $loadaddr - $fdtaddr"
-
-#define CONFIG_RAMBOOTCOMMAND \
- "setenv bootargs root=/dev/ram rw " \
- "console=$consoledev,$baudrate $othbootargs; " \
- "tftp $ramdiskaddr $ramdiskfile;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr $ramdiskaddr $fdtaddr"
-
-#define CONFIG_BOOTCOMMAND CONFIG_HDBOOT
-
-#endif /* __CONFIG_H */
--
1.9.1
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [U-Boot] [PATCH 3/8] powerpc: mpc85xx: remove P2020COME board support
2015-01-22 15:24 [U-Boot] [PATCH 0/8] powerpc: drop more non-generic boards Masahiro Yamada
2015-01-22 15:24 ` [U-Boot] [PATCH 1/8] powerpc: mpc83xx: remove MPC8360ERDK, EMPC8360EMDS support Masahiro Yamada
2015-01-22 15:24 ` [U-Boot] [PATCH 2/8] powerpc: mpc85xx: remove P1_P2_RDB boards Masahiro Yamada
@ 2015-01-22 15:24 ` Masahiro Yamada
2015-01-22 17:52 ` Ira Snyder
2015-01-23 21:57 ` Tom Rini
2015-01-22 15:24 ` [U-Boot] [PATCH 4/8] powerpc: mpc85xx: remove P2020DS " Masahiro Yamada
` (4 subsequent siblings)
7 siblings, 2 replies; 19+ messages in thread
From: Masahiro Yamada @ 2015-01-22 15:24 UTC (permalink / raw)
To: u-boot
This board is still a non-generic board.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Ira W. Snyder <iws@ovro.caltech.edu>
---
arch/powerpc/cpu/mpc85xx/Kconfig | 4 -
board/freescale/p2020come/Kconfig | 12 -
board/freescale/p2020come/MAINTAINERS | 7 -
board/freescale/p2020come/Makefile | 10 -
board/freescale/p2020come/ddr.c | 29 --
board/freescale/p2020come/law.c | 23 --
board/freescale/p2020come/p2020come.c | 275 -----------------
board/freescale/p2020come/tlb.c | 83 ------
configs/P2020COME_SDCARD_defconfig | 4 -
configs/P2020COME_SPIFLASH_defconfig | 4 -
doc/README.scrapyard | 1 +
include/configs/P2020COME.h | 547 ----------------------------------
12 files changed, 1 insertion(+), 998 deletions(-)
delete mode 100644 board/freescale/p2020come/Kconfig
delete mode 100644 board/freescale/p2020come/MAINTAINERS
delete mode 100644 board/freescale/p2020come/Makefile
delete mode 100644 board/freescale/p2020come/ddr.c
delete mode 100644 board/freescale/p2020come/law.c
delete mode 100644 board/freescale/p2020come/p2020come.c
delete mode 100644 board/freescale/p2020come/tlb.c
delete mode 100644 configs/P2020COME_SDCARD_defconfig
delete mode 100644 configs/P2020COME_SPIFLASH_defconfig
delete mode 100644 include/configs/P2020COME.h
diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig
index 009d830..e643f91 100644
--- a/arch/powerpc/cpu/mpc85xx/Kconfig
+++ b/arch/powerpc/cpu/mpc85xx/Kconfig
@@ -93,9 +93,6 @@ config TARGET_P1_P2_RDB_PC
config TARGET_P1_TWR
bool "Support p1_twr"
-config TARGET_P2020COME
- bool "Support P2020COME"
-
config TARGET_P2020DS
bool "Support P2020DS"
@@ -181,7 +178,6 @@ source "board/freescale/p1022ds/Kconfig"
source "board/freescale/p1023rdb/Kconfig"
source "board/freescale/p1_p2_rdb_pc/Kconfig"
source "board/freescale/p1_twr/Kconfig"
-source "board/freescale/p2020come/Kconfig"
source "board/freescale/p2020ds/Kconfig"
source "board/freescale/p2041rdb/Kconfig"
source "board/freescale/qemu-ppce500/Kconfig"
diff --git a/board/freescale/p2020come/Kconfig b/board/freescale/p2020come/Kconfig
deleted file mode 100644
index 8ce5cf1..0000000
--- a/board/freescale/p2020come/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_P2020COME
-
-config SYS_BOARD
- default "p2020come"
-
-config SYS_VENDOR
- default "freescale"
-
-config SYS_CONFIG_NAME
- default "P2020COME"
-
-endif
diff --git a/board/freescale/p2020come/MAINTAINERS b/board/freescale/p2020come/MAINTAINERS
deleted file mode 100644
index ab3ef94..0000000
--- a/board/freescale/p2020come/MAINTAINERS
+++ /dev/null
@@ -1,7 +0,0 @@
-P2020COME BOARD
-M: Ira W. Snyder <iws@ovro.caltech.edu>
-S: Maintained
-F: board/freescale/p2020come/
-F: include/configs/P2020COME.h
-F: configs/P2020COME_SDCARD_defconfig
-F: configs/P2020COME_SPIFLASH_defconfig
diff --git a/board/freescale/p2020come/Makefile b/board/freescale/p2020come/Makefile
deleted file mode 100644
index 4857136..0000000
--- a/board/freescale/p2020come/Makefile
+++ /dev/null
@@ -1,10 +0,0 @@
-#
-# Copyright 2009 Freescale Semiconductor, Inc.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y += p2020come.o
-obj-y += ddr.o
-obj-y += law.o
-obj-y += tlb.o
diff --git a/board/freescale/p2020come/ddr.c b/board/freescale/p2020come/ddr.c
deleted file mode 100644
index b642e12..0000000
--- a/board/freescale/p2020come/ddr.c
+++ /dev/null
@@ -1,29 +0,0 @@
-/*
- * Copyright 2009, 2011 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#include <common.h>
-
-#include <fsl_ddr_sdram.h>
-#include <fsl_ddr_dimm_params.h>
-
-void fsl_ddr_board_options(memctl_options_t *popts,
- dimm_params_t *pdimm,
- unsigned int ctrl_num)
-{
- if (ctrl_num) {
- printf("Wrong parameter for controller number %d", ctrl_num);
- return;
- }
-
- if (!pdimm->n_ranks)
- return;
-
- /*
- * Set DDR_SDRAM_CLK_CNTL = 0x02800000
- *
- * Clock is launched 5/8 applied cycle after address/command
- */
- popts->clk_adjust = 5;
-}
diff --git a/board/freescale/p2020come/law.c b/board/freescale/p2020come/law.c
deleted file mode 100644
index 7048a08..0000000
--- a/board/freescale/p2020come/law.c
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * Copyright 2009 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/fsl_law.h>
-#include <asm/mmu.h>
-
-/*
- * Create a dummy LAW entry for the DDR SDRAM which will be replaced when
- * the DDR SPD setup code runs.
- *
- * This table would be empty, except that it is used before the BSS section is
- * initialized, and therefore must have at least one entry to push it into
- * the DATA section.
- */
-struct law_entry law_table[] = {
- SET_LAW(CONFIG_SYS_SDRAM_BASE, LAW_SIZE_4K, LAW_TRGT_IF_DDR),
-};
-
-int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/freescale/p2020come/p2020come.c b/board/freescale/p2020come/p2020come.c
deleted file mode 100644
index 1db37e3..0000000
--- a/board/freescale/p2020come/p2020come.c
+++ /dev/null
@@ -1,275 +0,0 @@
-/*
- * Copyright 2009,2012 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <hwconfig.h>
-#include <command.h>
-#include <asm/processor.h>
-#include <asm/mmu.h>
-#include <asm/cache.h>
-#include <asm/immap_85xx.h>
-#include <asm/mpc85xx_gpio.h>
-#include <asm/fsl_serdes.h>
-#include <asm/io.h>
-#include <miiphy.h>
-#include <libfdt.h>
-#include <fdt_support.h>
-#include <fsl_mdio.h>
-#include <tsec.h>
-#include <vsc7385.h>
-#include <netdev.h>
-#include <mmc.h>
-#include <malloc.h>
-#include <i2c.h>
-
-#if defined(CONFIG_PCI)
-#include <asm/fsl_pci.h>
-#include <pci.h>
-#endif
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#if defined(CONFIG_PCI)
-void pci_init_board(void)
-{
- fsl_pcie_init_board(0);
-}
-
-void ft_pci_board_setup(void *blob)
-{
- FT_FSL_PCI_SETUP;
-}
-#endif
-
-#define BOARD_PERI_RST_SET (VSC7385_RST_SET | SLIC_RST_SET | \
- SGMII_PHY_RST_SET | PCIE_RST_SET | \
- RGMII_PHY_RST_SET)
-
-#define SYSCLK_MASK 0x00200000
-#define BOARDREV_MASK 0x10100000
-#define BOARDREV_B 0x10100000
-#define BOARDREV_C 0x00100000
-#define BOARDREV_D 0x00000000
-
-#define SYSCLK_66 66666666
-#define SYSCLK_50 50000000
-#define SYSCLK_100 100000000
-
-unsigned long get_board_sys_clk(ulong dummy)
-{
- ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
- u32 ddr_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO;
-
- ddr_ratio >>= MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
- switch (ddr_ratio) {
- case 0x0C:
- return SYSCLK_66;
- case 0x0A:
- case 0x08:
- return SYSCLK_100;
- default:
- puts("ERROR: unknown DDR ratio\n");
- return SYSCLK_100;
- }
-}
-
-unsigned long get_board_ddr_clk(ulong dummy)
-{
- ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
- u32 ddr_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO;
-
- ddr_ratio >>= MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
- switch (ddr_ratio) {
- case 0x0C:
- case 0x0A:
- return SYSCLK_66;
- case 0x08:
- return SYSCLK_100;
- default:
- puts("ERROR: unknown DDR ratio\n");
- return SYSCLK_100;
- }
-}
-
-#ifdef CONFIG_MMC
-int board_early_init_f(void)
-{
- ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-
- setbits_be32(&gur->pmuxcr,
- (MPC85xx_PMUXCR_SDHC_CD |
- MPC85xx_PMUXCR_SDHC_WP));
-
- /* All the device are enable except for SRIO12 */
- setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_SRIO);
- return 0;
-}
-#endif
-
-#define GPIO_DIR 0x0f3a0000
-#define GPIO_ODR 0x00000000
-#define GPIO_DAT 0x001a0000
-
-int checkboard(void)
-{
- ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR + 0xC00);
-
- /*
- * GPIO
- * 0 - 3: CarryBoard Input;
- * 4 - 7: CarryBoard Output;
- * 8 : Mux as SDHC_CD (card detection)
- * 9 : Mux as SDHC_WP
- * 10 : Clear Watchdog timer
- * 11 : LED Input
- * 12 : Output to 1
- * 13 : Open Drain
- * 14 : LED Output
- * 15 : Switch Input
- *
- * Set GPIOs 11, 12, 14 to 1.
- */
- out_be32(&pgpio->gpodr, GPIO_ODR);
- mpc85xx_gpio_set(0xffffffff, GPIO_DIR, GPIO_DAT);
-
- puts("Board: Freescale COM Express P2020\n");
- return 0;
-}
-
-#define M41ST85W_I2C_BUS 1
-#define M41ST85W_I2C_ADDR 0x68
-#define M41ST85W_ERROR(fmt, args...) printf("ERROR: M41ST85W: " fmt, ##args)
-
-static void m41st85w_clear_bit(u8 reg, u8 mask, const char *name)
-{
- u8 data;
-
- if (i2c_read(M41ST85W_I2C_ADDR, reg, 1, &data, 1)) {
- M41ST85W_ERROR("unable to read %s bit\n", name);
- return;
- }
-
- if (data & mask) {
- data &= ~mask;
- if (i2c_write(M41ST85W_I2C_ADDR, reg, 1, &data, 1)) {
- M41ST85W_ERROR("unable to clear %s bit\n", name);
- return;
- }
- }
-}
-
-#define M41ST85W_REG_SEC2 0x01
-#define M41ST85W_REG_SEC2_ST 0x80
-
-#define M41ST85W_REG_ALHOUR 0x0c
-#define M41ST85W_REG_ALHOUR_HT 0x40
-
-/*
- * The P2020COME board has a STMicro M41ST85W RTC/watchdog
- * at i2c bus 1 address 0x68.
- */
-static void start_rtc(void)
-{
- unsigned int bus = i2c_get_bus_num();
-
- if (i2c_set_bus_num(M41ST85W_I2C_BUS)) {
- M41ST85W_ERROR("unable to set i2c bus\n");
- goto out;
- }
-
- /* ensure ST (stop) and HT (halt update) bits are cleared */
- m41st85w_clear_bit(M41ST85W_REG_SEC2, M41ST85W_REG_SEC2_ST, "ST");
- m41st85w_clear_bit(M41ST85W_REG_ALHOUR, M41ST85W_REG_ALHOUR_HT, "HT");
-
-out:
- /* reset the i2c bus */
- i2c_set_bus_num(bus);
-}
-
-int board_early_init_r(void)
-{
- start_rtc();
- return 0;
-}
-
-#define M41ST85W_REG_WATCHDOG 0x09
-#define M41ST85W_REG_WATCHDOG_WDS 0x80
-#define M41ST85W_REG_WATCHDOG_BMB0 0x04
-
-void board_reset(void)
-{
- u8 data = M41ST85W_REG_WATCHDOG_WDS | M41ST85W_REG_WATCHDOG_BMB0;
-
- /* set the hardware watchdog timeout to 1/16 second, then hang */
- i2c_set_bus_num(M41ST85W_I2C_BUS);
- i2c_write(M41ST85W_I2C_ADDR, M41ST85W_REG_WATCHDOG, 1, &data, 1);
-
- while (1)
- /* hang */;
-}
-
-#ifdef CONFIG_TSEC_ENET
-int board_eth_init(bd_t *bis)
-{
- struct fsl_pq_mdio_info mdio_info;
- struct tsec_info_struct tsec_info[4];
- int num = 0;
-
-#ifdef CONFIG_TSEC1
- SET_STD_TSEC_INFO(tsec_info[num], 1);
- num++;
-#endif
-#ifdef CONFIG_TSEC2
- SET_STD_TSEC_INFO(tsec_info[num], 2);
- num++;
-#endif
-#ifdef CONFIG_TSEC3
- SET_STD_TSEC_INFO(tsec_info[num], 3);
- if (is_serdes_configured(SGMII_TSEC3)) {
- puts("eTSEC3 is in sgmii mode.");
- tsec_info[num].flags |= TSEC_SGMII;
- }
- num++;
-#endif
- if (!num) {
- printf("No TSECs initialized\n");
- return 0;
- }
-
- mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
- mdio_info.name = DEFAULT_MII_NAME;
- fsl_pq_mdio_init(bis, &mdio_info);
-
- tsec_eth_init(bis, tsec_info, num);
-
- return pci_eth_init(bis);
-}
-#endif
-
-#if defined(CONFIG_OF_BOARD_SETUP)
-int ft_board_setup(void *blob, bd_t *bd)
-{
- phys_addr_t base;
- phys_size_t size;
-
- ft_cpu_setup(blob, bd);
-
- base = getenv_bootm_low();
- size = getenv_bootm_size();
-
-#if defined(CONFIG_PCI)
- ft_pci_board_setup(blob);
-#endif
-
- fdt_fixup_memory(blob, (u64)base, (u64)size);
-
-#ifdef CONFIG_HAS_FSL_DR_USB
- fdt_fixup_dr_usb(blob, bd);
-#endif
-
- return 0;
-}
-#endif
diff --git a/board/freescale/p2020come/tlb.c b/board/freescale/p2020come/tlb.c
deleted file mode 100644
index 08a1e34..0000000
--- a/board/freescale/p2020come/tlb.c
+++ /dev/null
@@ -1,83 +0,0 @@
-/*
- * Copyright 2011 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/mmu.h>
-
-struct fsl_e_tlb_entry tlb_table[] = {
- /* TLB 0 - for temp stack in cache */
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
- CONFIG_SYS_INIT_RAM_ADDR_PHYS,
- MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 ,
- CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
- MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 ,
- CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
- MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 ,
- CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
- MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
-
- /* TLB 1 */
- /* *I*** - Covers boot page */
- SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 0, BOOKE_PAGESZ_4K, 1),
-
- /* *I*G* - CCSRBAR */
- SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
- MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 1, BOOKE_PAGESZ_1M, 1),
-
-#if defined(CONFIG_PCI)
- /* *I*G* - PCI3 - PCI2 0x8000,0000 - 0xbfff,ffff, size = 1G */
- SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT, CONFIG_SYS_PCIE3_MEM_PHYS,
- MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 2, BOOKE_PAGESZ_1G, 1),
-
- /* *I*G* - PCI1 0xC000,0000 - 0xcfff,ffff, size = 256M */
- SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_VIRT,
- MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 3, BOOKE_PAGESZ_256M, 1),
-
- /* *I*G* - PCI1 0xD000,0000 - 0xDFFF,FFFF, size = 256M */
- SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x10000000,
- CONFIG_SYS_PCIE1_MEM_PHYS + 0x10000000,
- MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 4, BOOKE_PAGESZ_256M, 1),
-
- /*
- * *I*G* - PCI I/O
- *
- * PCI3 => 0xFFC10000
- * PCI2 => 0xFFC2,0000
- * PCI1 => 0xFFC3,0000
- */
- SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_IO_VIRT, CONFIG_SYS_PCIE3_IO_PHYS,
- MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 5, BOOKE_PAGESZ_256K, 1),
-#endif /* #if defined(CONFIG_PCI) */
-
-#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR)
- /* *I*G - DDR3 2G Part 1: 0 - 0x3fff,ffff , size = 1G */
- SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 6, BOOKE_PAGESZ_256K, 1),
-
- /* DDR3 2G Part 2: 0x4000,0000 - 0x7fff,ffff , size = 1G */
- SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR + 0x40000,
- CONFIG_SYS_INIT_L2_ADDR_PHYS + 0x40000,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 7, BOOKE_PAGESZ_256K, 1),
-#endif
-};
-
-int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/configs/P2020COME_SDCARD_defconfig b/configs/P2020COME_SDCARD_defconfig
deleted file mode 100644
index c186fcb..0000000
--- a/configs/P2020COME_SDCARD_defconfig
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_SYS_EXTRA_OPTIONS="SDCARD"
-CONFIG_PPC=y
-CONFIG_MPC85xx=y
-CONFIG_TARGET_P2020COME=y
diff --git a/configs/P2020COME_SPIFLASH_defconfig b/configs/P2020COME_SPIFLASH_defconfig
deleted file mode 100644
index 17ce136..0000000
--- a/configs/P2020COME_SPIFLASH_defconfig
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH"
-CONFIG_PPC=y
-CONFIG_MPC85xx=y
-CONFIG_TARGET_P2020COME=y
diff --git a/doc/README.scrapyard b/doc/README.scrapyard
index f436a8e..5733c5a 100644
--- a/doc/README.scrapyard
+++ b/doc/README.scrapyard
@@ -12,6 +12,7 @@ The list should be sorted in reverse chronological order.
Board Arch CPU Commit Removed Last known maintainer/contact
=================================================================================================
+P2020COME powerpc mpc85xx - - Ira W. Snyder <iws@ovro.caltech.edu>
P2020RDB powerpc mpc85xx - - Poonam Aggrwal <poonam.aggrwal@freescale.com>
P2010RDB powerpc mpc85xx - -
P1020RDB powerpc mpc85xx - -
diff --git a/include/configs/P2020COME.h b/include/configs/P2020COME.h
deleted file mode 100644
index d414b84..0000000
--- a/include/configs/P2020COME.h
+++ /dev/null
@@ -1,547 +0,0 @@
-/*
- * Copyright 2009-2010,2012 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/* The P2020COME board is only booted via the Freescale On-Chip ROM */
-#define CONFIG_SYS_RAMBOOT
-#define CONFIG_SYS_EXTRA_ENV_RELOC
-
-#define CONFIG_SYS_TEXT_BASE 0xf8f80000
-#define CONFIG_RESET_VECTOR_ADDRESS 0xf8fffffc
-
-#ifdef CONFIG_SDCARD
-#define CONFIG_RAMBOOT_SDCARD 1
-#endif
-
-#ifdef CONFIG_SPIFLASH
-#define CONFIG_RAMBOOT_SPIFLASH 1
-#endif
-
-#ifndef CONFIG_SYS_MONITOR_BASE
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
-#endif
-
-/* High Level Configuration Options */
-#define CONFIG_BOOKE 1 /* BOOKE */
-#define CONFIG_E500 1 /* BOOKE e500 family */
-#define CONFIG_P2020 1
-#define CONFIG_P2020COME 1
-#define CONFIG_FSL_ELBC 1 /* Enable eLBC Support */
-#define CONFIG_MP
-
-#define CONFIG_PCI 1 /* Enable PCI/PCIE */
-#if defined(CONFIG_PCI)
-#define CONFIG_PCIE1 1 /* PCIE controller 1 (slot 1) */
-#define CONFIG_PCIE2 1 /* PCIE controller 2 (slot 2) */
-#define CONFIG_PCIE3 1 /* PCIE controller 3 (slot 3) */
-
-#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
-#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
-#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
-#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
-#endif /* #if defined(CONFIG_PCI) */
-#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
-#define CONFIG_TSEC_ENET /* tsec ethernet support */
-#define CONFIG_ENV_OVERWRITE
-
-#if defined(CONFIG_PCI)
-#define CONFIG_E1000 1 /* E1000 pci Ethernet card */
-#endif
-
-#ifndef __ASSEMBLY__
-extern unsigned long get_board_ddr_clk(unsigned long dummy);
-extern unsigned long get_board_sys_clk(unsigned long dummy);
-#endif
-
-/*
- * For P2020COME DDRCLK and SYSCLK are from the same oscillator
- * For DA phase the SYSCLK is 66MHz
- * For EA phase the SYSCLK is 100MHz
- */
-#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk(0)
-#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0)
-
-#define CONFIG_HWCONFIG
-
-/*
- * These can be toggled for performance analysis, otherwise use default.
- */
-#define CONFIG_L2_CACHE /* toggle L2 cache */
-#define CONFIG_BTB /* toggle branch prediction */
-
-#define CONFIG_ADDR_STREAMING /* toggle addr streaming */
-
-#define CONFIG_ENABLE_36BIT_PHYS 1
-
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_ADDR_MAP 1
-#define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
-#endif
-
-#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x1fffffff
-#define CONFIG_PANIC_HANG /* do not reset board on panic */
-
- /*
- * Config the L2 Cache as L2 SRAM
- */
-#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_INIT_L2_ADDR_PHYS 0xff8f80000ull
-#else
-#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
-#endif
-#define CONFIG_SYS_L2_SIZE (512 << 10)
-#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR \
- + CONFIG_SYS_L2_SIZE)
-
-#define CONFIG_SYS_CCSRBAR 0xffe00000
-#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
-
-/* DDR Setup */
-#define CONFIG_SYS_FSL_DDR3
-#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
-#define CONFIG_DDR_SPD
-
-#define CONFIG_DDR_ECC
-#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
-#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
-
-#define CONFIG_SYS_SDRAM_SIZE 2048ULL /* DDR size on P2020COME */
-#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
-
-#define CONFIG_NUM_DDR_CONTROLLERS 1
-#define CONFIG_DIMM_SLOTS_PER_CTLR 1
-#define CONFIG_CHIP_SELECTS_PER_CTRL 2
-
-#define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d
-#define CONFIG_SYS_DDR_ERR_DIS 0x00000000
-#define CONFIG_SYS_DDR_SBE 0x00ff0000
-
-#define CONFIG_SYS_SPD_BUS_NUM 1
-#define SPD_EEPROM_ADDRESS 0x53
-
-/*
- * Memory map
- *
- * 0x0000_0000 0x7fff_ffff DDR3 2G Cacheable
- * 0x8000_0000 0x9fff_ffff PCI Express 3 Mem 1G non-cacheable
- * 0xa000_0000 0xbfff_ffff PCI Express 2 Mem 1G non-cacheable
- * 0xc000_0000 0xdfff_ffff PCI Express 1 Mem 1G non-cacheable
- * 0xffc1_0000 0xffc1_ffff PCI Express 3 IO 64K non-cacheable
- * 0xffc2_0000 0xffc2_ffff PCI Express 2 IO 64K non-cacheable
- * 0xffc3_0000 0xffc3_ffff PCI Express 1 IO 64K non-cacheable
- *
- * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0
- * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
- */
-
-/*
- * Local Bus Definitions
- */
-
-/* There is no NOR Flash on P2020COME */
-#define CONFIG_SYS_NO_FLASH
-
-#define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
-#define CONFIG_HWCONFIG
-
-#define CONFIG_SYS_INIT_RAM_LOCK 1
-#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
-/* the assembler doesn't like typecast */
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
- ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
- CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
-#else
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
-#endif
-#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
-
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \
- - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
-#define CONFIG_SYS_MALLOC_LEN (1024 * 1024)
-
-/* Serial Port - controlled on board with jumper J8
- * open - index 2
- * shorted - index 1
- */
-#define CONFIG_CONS_INDEX 1
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
-
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */
-
-#define CONFIG_SYS_BAUDRATE_TABLE \
- {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
-
-#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
-#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
-
-/* Use the HUSH parser */
-#define CONFIG_SYS_HUSH_PARSER
-
-/*
- * Pass open firmware flat tree
- */
-#define CONFIG_OF_LIBFDT 1
-#define CONFIG_OF_BOARD_SETUP 1
-#define CONFIG_OF_STDOUT_VIA_ALIAS 1
-
-/* new uImage format support */
-#define CONFIG_FIT 1
-#define CONFIG_FIT_VERBOSE 1
-
-/* I2C */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_FSL
-#define CONFIG_SYS_FSL_I2C_SPEED 400000
-#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
-#define CONFIG_SYS_FSL_I2C2_SPEED 400000
-#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
-#define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} }
-
-/*
- * I2C2 EEPROM
- */
-#define CONFIG_ID_EEPROM
-#ifdef CONFIG_ID_EEPROM
-#define CONFIG_SYS_I2C_EEPROM_NXID
-#endif
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
-#define CONFIG_SYS_I2C_EEPROM_ADDR2 0x18
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-#define CONFIG_SYS_EEPROM_BUS_NUM 0
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
-
-/*
- * eSPI - Enhanced SPI
- */
-#define CONFIG_FSL_ESPI
-#define CONFIG_SPI_FLASH
-#define CONFIG_SPI_FLASH_STMICRO
-#define CONFIG_CMD_SF
-#define CONFIG_SF_DEFAULT_SPEED 10000000
-#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
-
-/*
- * General PCI
- * Memory space is mapped 1-1, but I/O space must start from 0.
- */
-#if defined(CONFIG_PCI)
-
-/* controller 3, Slot 3, tgtid 3, Base address 8000 */
-#define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000
-#define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000
-#define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000
-#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
-#define CONFIG_SYS_PCIE3_IO_VIRT 0xffc10000
-#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
-#define CONFIG_SYS_PCIE3_IO_PHYS 0xffc10000
-#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
-
-/* controller 2, Slot 2, tgtid 2, Base address 9000 */
-#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
-#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
-#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
-#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
-#define CONFIG_SYS_PCIE2_IO_VIRT 0xffc20000
-#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
-#define CONFIG_SYS_PCIE2_IO_PHYS 0xffc20000
-#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
-
-/* controller 1, Slot 1, tgtid 1, Base address a000 */
-#define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000
-#define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000
-#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000
-#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
-#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc30000
-#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
-#define CONFIG_SYS_PCIE1_IO_PHYS 0xffc30000
-#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
-
-#define CONFIG_PCI_PNP /* do pci plug-and-play */
-
-#undef CONFIG_EEPRO100
-#undef CONFIG_TULIP
-#undef CONFIG_RTL8139
-
-#ifdef CONFIG_RTL8139
-/* This macro is used by RTL8139 but not defined in PPC architecture */
-#define KSEG1ADDR(x) (x)
-#define _IO_BASE 0x00000000
-#endif
-
-#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
-#define CONFIG_DOS_PARTITION
-
-#endif /* CONFIG_PCI */
-
-#if defined(CONFIG_TSEC_ENET)
-#define CONFIG_MII 1 /* MII PHY management */
-#define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
-#define CONFIG_TSEC1 1
-#define CONFIG_TSEC1_NAME "eTSEC1"
-#define CONFIG_TSEC2 1
-#define CONFIG_TSEC2_NAME "eTSEC2"
-#define CONFIG_TSEC3 1
-#define CONFIG_TSEC3_NAME "eTSEC3"
-
-#define TSEC1_PHY_ADDR 0
-#define TSEC2_PHY_ADDR 2
-#define TSEC3_PHY_ADDR 1
-
-#undef CONFIG_VSC7385_ENET
-
-#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
-#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
-#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
-
-#define TSEC1_PHYIDX 0
-#define TSEC2_PHYIDX 0
-#define TSEC3_PHYIDX 0
-
-#define CONFIG_ETHPRIME "eTSEC1"
-
-#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
-
-#endif /* CONFIG_TSEC_ENET */
-
-/*
- * Environment
- */
-#if defined(CONFIG_RAMBOOT_SDCARD)
- #define CONFIG_ENV_IS_IN_MMC 1
- #define CONFIG_FSL_FIXED_MMC_LOCATION
- #define CONFIG_ENV_SIZE 0x2000
- #define CONFIG_SYS_MMC_ENV_DEV 0
-#elif defined(CONFIG_RAMBOOT_SPIFLASH)
- #define CONFIG_ENV_IS_IN_SPI_FLASH
- #define CONFIG_ENV_SPI_BUS 0
- #define CONFIG_ENV_SPI_CS 0
- #define CONFIG_ENV_SPI_MAX_HZ 10000000
- #define CONFIG_ENV_SPI_MODE 0
- #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
- #define CONFIG_ENV_SECT_SIZE 0x10000
- #define CONFIG_ENV_SIZE 0x2000
-#endif
-
-#define CONFIG_LOADS_ECHO 1
-#define CONFIG_SYS_LOADS_BAUD_CHANGE 1
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_ELF
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_IRQ
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_SETEXPR
-#define CONFIG_CMD_REGINFO
-
-#if defined(CONFIG_PCI)
-#define CONFIG_CMD_NET
-#define CONFIG_CMD_PCI
-#endif
-
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-
-#define CONFIG_MMC 1
-
-#ifdef CONFIG_MMC
-#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
-#define CONFIG_CMD_MMC
-#define CONFIG_DOS_PARTITION
-#define CONFIG_FSL_ESDHC
-#define CONFIG_GENERIC_MMC
-#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
-#define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
-#endif /* CONFIG_MMC */
-
-#define CONFIG_HAS_FSL_DR_USB
-#ifdef CONFIG_HAS_FSL_DR_USB
-#define CONFIG_USB_EHCI
-
-#ifdef CONFIG_USB_EHCI
-#define CONFIG_CMD_USB
-#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
-#define CONFIG_USB_EHCI_FSL
-#define CONFIG_USB_STORAGE
-#endif
-#endif
-
-#if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI)
-#define CONFIG_CMD_EXT2
-#define CONFIG_CMD_FAT
-#define CONFIG_DOS_PARTITION
-#endif
-
-/* Misc Extra Settings */
-#define CONFIG_CMD_DHCP 1
-
-#define CONFIG_CMD_DATE 1
-#define CONFIG_RTC_M41T62 1
-#define CONFIG_SYS_RTC_BUS_NUM 1
-#define CONFIG_SYS_I2C_RTC_ADDR 0x68
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_CMDLINE_EDITING /* Command-line editing */
-#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */
-#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
- /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 64 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (64 << 20)
-#define CONFIG_SYS_BOOTM_LEN (64 << 20)
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
-#endif
-
-/*
- * Environment Configuration
- */
-
-/* The mac addresses for all ethernet interface */
-#if defined(CONFIG_TSEC_ENET)
-#define CONFIG_HAS_ETH0
-#define CONFIG_HAS_ETH1
-#define CONFIG_HAS_ETH2
-#define CONFIG_HAS_ETH3
-#endif
-
-#define CONFIG_HOSTNAME unknown
-#define CONFIG_ROOTPATH "/opt/nfsroot"
-#define CONFIG_BOOTFILE "uImage"
-#define CONFIG_UBOOTPATH u-boot.bin
-
-/* default location for tftp and bootm */
-#define CONFIG_LOADADDR 1000000
-
-#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
-#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
-
-#define CONFIG_BAUDRATE 115200
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "hwconfig=fsl_ddr:ecc=on\0" \
- "bootcmd=run sdboot\0" \
- "sdboot=setenv bootargs root=/dev/mmcblk0p2 rw " \
- "rootdelay=$rootdelaysecond console=$consoledev,$baudrate "\
- "$othbootargs; mmcinfo; " \
- "ext2load mmc 0:2 $loadaddr /boot/$bootfile; " \
- "ext2load mmc 0:2 $fdtaddr /boot/$fdtfile; " \
- "bootm $loadaddr - $fdtaddr\0" \
- "sdfatboot=setenv bootargs root=/dev/ram rw " \
- "rootdelay=$rootdelaysecond console=$consoledev,$baudrate "\
- "$othbootargs; mmcinfo; " \
- "fatload mmc 0:1 $loadaddr $bootfile; " \
- "fatload mmc 0:1 $fdtaddr $fdtfile; " \
- "fatload mmc 0:1 $ramdiskaddr $ramdiskfile; " \
- "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \
- "usbboot=setenv bootargs root=/dev/sda1 rw " \
- "rootdelay=$rootdelaysecond console=$consoledev,$baudrate "\
- "$othbootargs; " \
- "usb start; " \
- "ext2load usb 0:1 $loadaddr /boot/$bootfile; " \
- "ext2load usb 0:1 $fdtaddr /boot/$fdtfile; " \
- "bootm $loadaddr - $fdtaddr\0" \
- "usbfatboot=setenv bootargs root=/dev/ram rw " \
- "console=$consoledev,$baudrate $othbootargs; " \
- "usb start; " \
- "fatload usb 0:2 $loadaddr $bootfile; " \
- "fatload usb 0:2 $fdtaddr $fdtfile; " \
- "fatload usb 0:2 $ramdiskaddr $ramdiskfile; " \
- "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \
- "usbext2boot=setenv bootargs root=/dev/ram rw " \
- "console=$consoledev,$baudrate $othbootargs; " \
- "usb start; " \
- "ext2load usb 0:4 $loadaddr $bootfile; " \
- "ext2load usb 0:4 $fdtaddr $fdtfile; " \
- "ext2load usb 0:4 $ramdiskaddr $ramdiskfile; " \
- "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \
- "upgradespi=sf probe 0; " \
- "setenv startaddr 0; " \
- "setenv erasesize a0000; " \
- "tftp 1000000 $tftppath/$uboot_spi; " \
- "sf erase $startaddr $erasesize; " \
- "sf write 1000000 $startaddr $filesize; " \
- "sf erase 100000 120000\0" \
- "clearspienv=sf probe 0;sf erase 100000 20000\0" \
- "othbootargs=ramdisk_size=700000 cache-sram-size=0x10000\0" \
- "netdev=eth0\0" \
- "rootdelaysecond=15\0" \
- "uboot_nor=u-boot-nor.bin\0" \
- "uboot_spi=u-boot-p2020.spi\0" \
- "uboot_sd=u-boot-p2020.bin\0" \
- "consoledev=ttyS0\0" \
- "ramdiskaddr=2000000\0" \
- "ramdiskfile=rootfs-dev.ext2.img\0" \
- "fdtaddr=c00000\0" \
- "fdtfile=uImage-2.6.32-p2020.dtb\0" \
- "tftppath=p2020\0"
-
-#define CONFIG_HDBOOT \
- "setenv bootargs root=/dev/$bdev rw rootdelay=30 " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "usb start;" \
- "ext2load usb 0:1 $loadaddr /boot/$bootfile;" \
- "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \
- "bootm $loadaddr - $fdtaddr"
-
-#define CONFIG_NFSBOOTCOMMAND \
- "setenv bootargs root=/dev/nfs rw " \
- "nfsroot=$serverip:$rootpath " \
- "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off "\
- "console=$consoledev,$baudrate $othbootargs;" \
- "tftp $loadaddr $tftppath/$bootfile;" \
- "tftp $fdtaddr $tftppath/$fdtfile;" \
- "bootm $loadaddr - $fdtaddr"
-
-
-#define CONFIG_RAMBOOTCOMMAND \
- "setenv bootargs root=/dev/ram rw " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "tftp $ramdiskaddr $tftppath/$ramdiskfile;" \
- "tftp $loadaddr $tftppath/$bootfile;" \
- "tftp $fdtaddr $tftppath/$fdtfile;" \
- "bootm $loadaddr $ramdiskaddr $fdtaddr"
-
-#define CONFIG_BOOTCOMMAND CONFIG_HDBOOT
-
-#endif /* __CONFIG_H */
--
1.9.1
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [U-Boot] [PATCH 4/8] powerpc: mpc85xx: remove P2020DS board support
2015-01-22 15:24 [U-Boot] [PATCH 0/8] powerpc: drop more non-generic boards Masahiro Yamada
` (2 preceding siblings ...)
2015-01-22 15:24 ` [U-Boot] [PATCH 3/8] powerpc: mpc85xx: remove P2020COME board support Masahiro Yamada
@ 2015-01-22 15:24 ` Masahiro Yamada
2015-01-23 21:57 ` Tom Rini
2015-01-22 15:24 ` [U-Boot] [PATCH 5/8] powerpc: ppc4xx: remove PPChameleonEVB, CATcenter boards Masahiro Yamada
` (3 subsequent siblings)
7 siblings, 1 reply; 19+ messages in thread
From: Masahiro Yamada @ 2015-01-22 15:24 UTC (permalink / raw)
To: u-boot
This board is still a non-generic board.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
---
arch/powerpc/cpu/mpc85xx/Kconfig | 4 -
board/freescale/p2020ds/Kconfig | 12 -
board/freescale/p2020ds/MAINTAINERS | 10 -
board/freescale/p2020ds/Makefile | 12 -
board/freescale/p2020ds/ddr.c | 129 -------
board/freescale/p2020ds/law.c | 20 -
board/freescale/p2020ds/p2020ds.c | 263 -------------
board/freescale/p2020ds/tlb.c | 90 -----
configs/P2020DS_36BIT_defconfig | 4 -
configs/P2020DS_DDR2_defconfig | 4 -
configs/P2020DS_SDCARD_defconfig | 4 -
configs/P2020DS_SPIFLASH_defconfig | 4 -
configs/P2020DS_defconfig | 3 -
doc/README.scrapyard | 1 +
include/configs/P2020DS.h | 751 ------------------------------------
15 files changed, 1 insertion(+), 1310 deletions(-)
delete mode 100644 board/freescale/p2020ds/Kconfig
delete mode 100644 board/freescale/p2020ds/MAINTAINERS
delete mode 100644 board/freescale/p2020ds/Makefile
delete mode 100644 board/freescale/p2020ds/ddr.c
delete mode 100644 board/freescale/p2020ds/law.c
delete mode 100644 board/freescale/p2020ds/p2020ds.c
delete mode 100644 board/freescale/p2020ds/tlb.c
delete mode 100644 configs/P2020DS_36BIT_defconfig
delete mode 100644 configs/P2020DS_DDR2_defconfig
delete mode 100644 configs/P2020DS_SDCARD_defconfig
delete mode 100644 configs/P2020DS_SPIFLASH_defconfig
delete mode 100644 configs/P2020DS_defconfig
delete mode 100644 include/configs/P2020DS.h
diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig
index e643f91..adb5bd3 100644
--- a/arch/powerpc/cpu/mpc85xx/Kconfig
+++ b/arch/powerpc/cpu/mpc85xx/Kconfig
@@ -93,9 +93,6 @@ config TARGET_P1_P2_RDB_PC
config TARGET_P1_TWR
bool "Support p1_twr"
-config TARGET_P2020DS
- bool "Support P2020DS"
-
config TARGET_P2041RDB
bool "Support P2041RDB"
@@ -178,7 +175,6 @@ source "board/freescale/p1022ds/Kconfig"
source "board/freescale/p1023rdb/Kconfig"
source "board/freescale/p1_p2_rdb_pc/Kconfig"
source "board/freescale/p1_twr/Kconfig"
-source "board/freescale/p2020ds/Kconfig"
source "board/freescale/p2041rdb/Kconfig"
source "board/freescale/qemu-ppce500/Kconfig"
source "board/freescale/t102xqds/Kconfig"
diff --git a/board/freescale/p2020ds/Kconfig b/board/freescale/p2020ds/Kconfig
deleted file mode 100644
index e527ec9..0000000
--- a/board/freescale/p2020ds/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_P2020DS
-
-config SYS_BOARD
- default "p2020ds"
-
-config SYS_VENDOR
- default "freescale"
-
-config SYS_CONFIG_NAME
- default "P2020DS"
-
-endif
diff --git a/board/freescale/p2020ds/MAINTAINERS b/board/freescale/p2020ds/MAINTAINERS
deleted file mode 100644
index cb61fc5..0000000
--- a/board/freescale/p2020ds/MAINTAINERS
+++ /dev/null
@@ -1,10 +0,0 @@
-P2020DS BOARD
-#M: -
-S: Maintained
-F: board/freescale/p2020ds/
-F: include/configs/P2020DS.h
-F: configs/P2020DS_defconfig
-F: configs/P2020DS_36BIT_defconfig
-F: configs/P2020DS_DDR2_defconfig
-F: configs/P2020DS_SDCARD_defconfig
-F: configs/P2020DS_SPIFLASH_defconfig
diff --git a/board/freescale/p2020ds/Makefile b/board/freescale/p2020ds/Makefile
deleted file mode 100644
index ee00806..0000000
--- a/board/freescale/p2020ds/Makefile
+++ /dev/null
@@ -1,12 +0,0 @@
-#
-# Copyright 2007-2009 Freescale Semiconductor, Inc.
-# (C) Copyright 2001-2006
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y += p2020ds.o
-obj-y += ddr.o
-obj-y += law.o
-obj-y += tlb.o
diff --git a/board/freescale/p2020ds/ddr.c b/board/freescale/p2020ds/ddr.c
deleted file mode 100644
index debe70b..0000000
--- a/board/freescale/p2020ds/ddr.c
+++ /dev/null
@@ -1,129 +0,0 @@
-/*
- * Copyright 2008-2009 Freescale Semiconductor, Inc.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * Version 2 as published by the Free Software Foundation.
- */
-
-#include <common.h>
-
-#include <fsl_ddr_sdram.h>
-#include <fsl_ddr_dimm_params.h>
-
-struct board_specific_parameters {
- u32 n_ranks;
- u32 datarate_mhz_high;
- u32 clk_adjust;
- u32 cpo;
- u32 write_data_delay;
- u32 force_2t;
-};
-
-
-/*
- * This table contains all valid speeds we want to override with board
- * specific parameters. datarate_mhz_high values need to be in ascending order
- * for each n_ranks group.
- *
- * ranges for parameters:
- * wr_data_delay = 0-6
- * clk adjust = 0-8
- * cpo 2-0x1E (30)
- */
-static const struct board_specific_parameters dimm0[] = {
- /*
- * memory controller 0
- * num| hi| clk| cpo|wrdata|2T
- * ranks| mhz|adjst| | delay|
- */
-#ifdef CONFIG_SYS_FSL_DDR2
- {2, 549, 4, 0x1f, 2, 0},
- {2, 680, 4, 0x1f, 3, 0},
- {2, 850, 4, 0x1f, 4, 0},
- {1, 549, 4, 0x1f, 2, 0},
- {1, 680, 4, 0x1f, 3, 0},
- {1, 850, 4, 0x1f, 4, 0},
-#else
- {2, 850, 6, 0x1f, 4, 0},
- {1, 850, 4, 0x1f, 4, 0},
-#endif
- {}
-};
-
-void fsl_ddr_board_options(memctl_options_t *popts,
- dimm_params_t *pdimm,
- unsigned int ctrl_num)
-{
- const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
- ulong ddr_freq;
- int i;
-
- if (ctrl_num) {
- printf("Wrong parameter for controller number %d", ctrl_num);
- return;
- }
- if (!pdimm->n_ranks)
- return;
-
- /*
- * set odt_rd_cfg and odt_wr_cfg. If the there is only one dimm in
- * that controller, set odt_wr_cfg to 4 for CS0, and 0 to CS1. If
- * there are two dimms in the controller, set odt_rd_cfg to 3 and
- * odt_wr_cfg to 3 for the even CS, 0 for the odd CS.
- */
- for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
- popts->cs_local_opts[i].odt_rd_cfg = 0;
- popts->cs_local_opts[i].odt_wr_cfg = 1;
- }
-
- pbsp = dimm0;
-
- /* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
- * freqency and n_banks specified in board_specific_parameters table.
- */
- ddr_freq = get_ddr_freq(0) / 1000000;
- while (pbsp->datarate_mhz_high) {
- if (pbsp->n_ranks == pdimm->n_ranks) {
- if (ddr_freq <= pbsp->datarate_mhz_high) {
- popts->clk_adjust = pbsp->clk_adjust;
- popts->cpo_override = pbsp->cpo;
- popts->write_data_delay =
- pbsp->write_data_delay;
- popts->twot_en = pbsp->force_2t;
- goto found;
- }
- pbsp_highest = pbsp;
- }
- pbsp++;
- }
-
- if (pbsp_highest) {
- printf("Error: board specific timing not found "
- "for data rate %lu MT/s!\n"
- "Trying to use the highest speed (%u) parameters\n",
- ddr_freq, pbsp_highest->datarate_mhz_high);
- popts->clk_adjust = pbsp_highest->clk_adjust;
- popts->cpo_override = pbsp_highest->cpo;
- popts->write_data_delay = pbsp_highest->write_data_delay;
- popts->twot_en = pbsp_highest->force_2t;
- } else {
- panic("DIMM is not supported by this board");
- }
-
-found:
- /*
- * Factors to consider for half-strength driver enable:
- * - number of DIMMs installed
- */
- popts->half_strength_driver_enable = 0;
- popts->wrlvl_en = 1;
- /* Write leveling override */
- popts->wrlvl_override = 1;
- popts->wrlvl_sample = 0xa;
- popts->wrlvl_start = 0x8;
- /* Rtt and Rtt_WR override */
- popts->rtt_override = 1;
- popts->rtt_override_value = DDR3_RTT_120_OHM;
- popts->rtt_wr_override_value = 0; /* Rtt_WR= dynamic ODT off */
-}
diff --git a/board/freescale/p2020ds/law.c b/board/freescale/p2020ds/law.c
deleted file mode 100644
index 9cd4da9..0000000
--- a/board/freescale/p2020ds/law.c
+++ /dev/null
@@ -1,20 +0,0 @@
-/*
- * Copyright 2008-2010 Freescale Semiconductor, Inc.
- *
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/fsl_law.h>
-#include <asm/mmu.h>
-
-struct law_entry law_table[] = {
- SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
- SET_LAW(PIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_LBC),
- SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
-};
-
-int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/freescale/p2020ds/p2020ds.c b/board/freescale/p2020ds/p2020ds.c
deleted file mode 100644
index 5d18e8d..0000000
--- a/board/freescale/p2020ds/p2020ds.c
+++ /dev/null
@@ -1,263 +0,0 @@
-/*
- * Copyright 2007-2012 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <command.h>
-#include <pci.h>
-#include <asm/processor.h>
-#include <asm/mmu.h>
-#include <asm/cache.h>
-#include <asm/immap_85xx.h>
-#include <asm/fsl_pci.h>
-#include <fsl_ddr_sdram.h>
-#include <asm/io.h>
-#include <asm/fsl_serdes.h>
-#include <miiphy.h>
-#include <libfdt.h>
-#include <fdt_support.h>
-#include <fsl_mdio.h>
-#include <tsec.h>
-#include <asm/fsl_law.h>
-#include <netdev.h>
-
-#include "../common/ngpixis.h"
-#include "../common/sgmii_riser.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int board_early_init_f(void)
-{
-#ifdef CONFIG_MMC
- ccsr_gur_t *gur = (ccsr_gur_t *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-
- setbits_be32(&gur->pmuxcr,
- (MPC85xx_PMUXCR_SDHC_CD |
- MPC85xx_PMUXCR_SDHC_WP));
-#endif
-
- return 0;
-}
-
-int checkboard(void)
-{
- u8 sw;
-
- printf("Board: P2020DS Sys ID: 0x%02x, "
- "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
- in_8(&pixis->id), in_8(&pixis->arch), in_8(&pixis->scver));
-
- sw = in_8(&PIXIS_SW(PIXIS_LBMAP_SWITCH));
- sw = (sw & PIXIS_LBMAP_MASK) >> PIXIS_LBMAP_SHIFT;
-
- if (sw < 0x8)
- /* The lower two bits are the actual vbank number */
- printf("vBank: %d\n", sw & 3);
- else
- puts("Promjet\n");
-
- return 0;
-}
-
-#if !defined(CONFIG_DDR_SPD)
-/*
- * Fixed sdram init -- doesn't use serial presence detect.
- */
-
-phys_size_t fixed_sdram(void)
-{
- struct ccsr_ddr __iomem *ddr =
- (struct ccsr_ddr __iomem *)CONFIG_SYS_FSL_DDR_ADDR;
- uint d_init;
-
- ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
- ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
- ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
- ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1;
- ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2;
- ddr->sdram_md_cntl = CONFIG_SYS_DDR_MODE_CTRL;
- ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
- ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT;
- ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL;
- ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2;
- ddr->ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL;
- ddr->ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL;
- ddr->ddr_cdr1 = CONFIG_SYS_DDR_CDR1;
- ddr->timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4;
- ddr->timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5;
-
- if (!strcmp("performance", getenv("perf_mode"))) {
- /* Performance Mode Values */
-
- ddr->cs1_config = CONFIG_SYS_DDR_CS1_CONFIG_PERF;
- ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS_PERF;
- ddr->cs1_bnds = CONFIG_SYS_DDR_CS1_BNDS_PERF;
- ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_PERF;
- ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_PERF;
-
- asm("sync;isync");
-
- udelay(500);
-
- ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL_PERF;
- } else {
- /* Stable Mode Values */
-
- ddr->cs1_config = CONFIG_SYS_DDR_CS1_CONFIG;
- ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
- ddr->cs1_bnds = CONFIG_SYS_DDR_CS1_BNDS;
- ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
- ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
-
- /* ECC will be assumed in stable mode */
- ddr->err_int_en = CONFIG_SYS_DDR_ERR_INT_EN;
- ddr->err_disable = CONFIG_SYS_DDR_ERR_DIS;
- ddr->err_sbe = CONFIG_SYS_DDR_SBE;
-
- asm("sync;isync");
-
- udelay(500);
-
- ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL;
- }
-
-#if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
- d_init = 1;
- debug("DDR - 1st controller: memory initializing\n");
- /*
- * Poll until memory is initialized.
- * 512 Meg at 400 might hit this 200 times or so.
- */
- while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0)
- udelay(1000);
- debug("DDR: memory initialized\n\n");
- asm("sync; isync");
- udelay(500);
-#endif
-
- if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE,
- CONFIG_SYS_SDRAM_SIZE * 1024 * 1024,
- LAW_TRGT_IF_DDR) < 0) {
- printf("ERROR setting Local Access Windows for DDR\n");
- return 0;
- };
-
- return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
-}
-
-#endif
-
-#ifdef CONFIG_PCI
-void pci_init_board(void)
-{
- fsl_pcie_init_board(0);
-}
-#endif
-
-int board_early_init_r(void)
-{
- const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
- int flash_esel = find_tlb_idx((void *)flashbase, 1);
-
- /*
- * Remap Boot flash + PROMJET region to caching-inhibited
- * so that flash can be erased properly.
- */
-
- /* Flush d-cache and invalidate i-cache of any FLASH data */
- flush_dcache();
- invalidate_icache();
-
- if (flash_esel == -1) {
- /* very unlikely unless something is messed up */
- puts("Error: Could not find TLB for FLASH BASE\n");
- flash_esel = 2; /* give our best effort to continue */
- } else {
- /* invalidate existing TLB entry for flash + promjet */
- disable_tlb(flash_esel);
- }
-
- set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, flash_esel, BOOKE_PAGESZ_256M, 1);
-
- return 0;
-}
-
-#ifdef CONFIG_TSEC_ENET
-int board_eth_init(bd_t *bis)
-{
- struct fsl_pq_mdio_info mdio_info;
- struct tsec_info_struct tsec_info[4];
- int num = 0;
-
-#ifdef CONFIG_TSEC1
- SET_STD_TSEC_INFO(tsec_info[num], 1);
- num++;
-#endif
-#ifdef CONFIG_TSEC2
- SET_STD_TSEC_INFO(tsec_info[num], 2);
- if (is_serdes_configured(SGMII_TSEC2)) {
- puts("eTSEC2 is in sgmii mode.\n");
- tsec_info[num].flags |= TSEC_SGMII;
- }
- num++;
-#endif
-#ifdef CONFIG_TSEC3
- SET_STD_TSEC_INFO(tsec_info[num], 3);
- if (is_serdes_configured(SGMII_TSEC3)) {
- puts("eTSEC3 is in sgmii mode.\n");
- tsec_info[num].flags |= TSEC_SGMII;
-}
- num++;
-#endif
-
- if (!num) {
- printf("No TSECs initialized\n");
-
- return 0;
- }
-
-#ifdef CONFIG_FSL_SGMII_RISER
- fsl_sgmii_riser_init(tsec_info, num);
-#endif
-
- mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
- mdio_info.name = DEFAULT_MII_NAME;
-
- fsl_pq_mdio_init(bis, &mdio_info);
-
- tsec_eth_init(bis, tsec_info, num);
-
- return pci_eth_init(bis);
-}
-#endif
-
-#if defined(CONFIG_OF_BOARD_SETUP)
-int ft_board_setup(void *blob, bd_t *bd)
-{
- phys_addr_t base;
- phys_size_t size;
-
- ft_cpu_setup(blob, bd);
-
- base = getenv_bootm_low();
- size = getenv_bootm_size();
-
- fdt_fixup_memory(blob, (u64)base, (u64)size);
-
-#ifdef CONFIG_HAS_FSL_DR_USB
- fdt_fixup_dr_usb(blob, bd);
-#endif
-
- FT_FSL_PCI_SETUP;
-
-#ifdef CONFIG_FSL_SGMII_RISER
- fsl_sgmii_riser_fdt_fixup(blob);
-#endif
-
- return 0;
-}
-#endif
diff --git a/board/freescale/p2020ds/tlb.c b/board/freescale/p2020ds/tlb.c
deleted file mode 100644
index 02da6e8..0000000
--- a/board/freescale/p2020ds/tlb.c
+++ /dev/null
@@ -1,90 +0,0 @@
-/*
- * Copyright 2008-2011 Freescale Semiconductor, Inc.
- *
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/mmu.h>
-
-struct fsl_e_tlb_entry tlb_table[] = {
- /* TLB 0 - for temp stack in cache */
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
- CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
- CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
- CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
-
- /* TLB 1 */
- /* *I*** - Covers boot page */
- SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 0, BOOKE_PAGESZ_4K, 1),
-
- /* *I*G* - CCSRBAR */
- SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 1, BOOKE_PAGESZ_1M, 1),
-
- /* W**G* - Flash/promjet, localbus */
- /* This will be changed to *I*G* after relocation to RAM. */
- SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
- MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
- 0, 2, BOOKE_PAGESZ_256M, 1),
-
- /* *I*G* - PCI */
- SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT, CONFIG_SYS_PCIE3_MEM_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 3, BOOKE_PAGESZ_1G, 1),
-
- /* *I*G* - PCI */
- SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT + 0x40000000,
- CONFIG_SYS_PCIE3_MEM_PHYS + 0x40000000,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 4, BOOKE_PAGESZ_256M, 1),
-
- SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT + 0x50000000,
- CONFIG_SYS_PCIE3_MEM_PHYS + 0x50000000,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 5, BOOKE_PAGESZ_256M, 1),
-
- /* *I*G* - PCI I/O */
- SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_IO_VIRT, CONFIG_SYS_PCIE3_IO_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 6, BOOKE_PAGESZ_256K, 1),
-
- /* *I*G - NAND */
- SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 7, BOOKE_PAGESZ_1M, 1),
-
- SET_TLB_ENTRY(1, PIXIS_BASE, PIXIS_BASE_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 8, BOOKE_PAGESZ_4K, 1),
-
-#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR)
- /* *I*G - L2SRAM */
- SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 9, BOOKE_PAGESZ_256K, 1),
- SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR + 0x40000,
- CONFIG_SYS_INIT_L2_ADDR_PHYS + 0x40000,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 10, BOOKE_PAGESZ_256K, 1),
-#endif
-};
-
-int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/configs/P2020DS_36BIT_defconfig b/configs/P2020DS_36BIT_defconfig
deleted file mode 100644
index 359c446..0000000
--- a/configs/P2020DS_36BIT_defconfig
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_SYS_EXTRA_OPTIONS="36BIT"
-CONFIG_PPC=y
-CONFIG_MPC85xx=y
-CONFIG_TARGET_P2020DS=y
diff --git a/configs/P2020DS_DDR2_defconfig b/configs/P2020DS_DDR2_defconfig
deleted file mode 100644
index 00b6731..0000000
--- a/configs/P2020DS_DDR2_defconfig
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_SYS_EXTRA_OPTIONS="DDR2"
-CONFIG_PPC=y
-CONFIG_MPC85xx=y
-CONFIG_TARGET_P2020DS=y
diff --git a/configs/P2020DS_SDCARD_defconfig b/configs/P2020DS_SDCARD_defconfig
deleted file mode 100644
index 89aef3a..0000000
--- a/configs/P2020DS_SDCARD_defconfig
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_SYS_EXTRA_OPTIONS="SDCARD"
-CONFIG_PPC=y
-CONFIG_MPC85xx=y
-CONFIG_TARGET_P2020DS=y
diff --git a/configs/P2020DS_SPIFLASH_defconfig b/configs/P2020DS_SPIFLASH_defconfig
deleted file mode 100644
index 503328c..0000000
--- a/configs/P2020DS_SPIFLASH_defconfig
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH"
-CONFIG_PPC=y
-CONFIG_MPC85xx=y
-CONFIG_TARGET_P2020DS=y
diff --git a/configs/P2020DS_defconfig b/configs/P2020DS_defconfig
deleted file mode 100644
index f2ac6d9..0000000
--- a/configs/P2020DS_defconfig
+++ /dev/null
@@ -1,3 +0,0 @@
-CONFIG_PPC=y
-CONFIG_MPC85xx=y
-CONFIG_TARGET_P2020DS=y
diff --git a/doc/README.scrapyard b/doc/README.scrapyard
index 5733c5a..719b970 100644
--- a/doc/README.scrapyard
+++ b/doc/README.scrapyard
@@ -12,6 +12,7 @@ The list should be sorted in reverse chronological order.
Board Arch CPU Commit Removed Last known maintainer/contact
=================================================================================================
+P2020DS powerpc mpc85xx - -
P2020COME powerpc mpc85xx - - Ira W. Snyder <iws@ovro.caltech.edu>
P2020RDB powerpc mpc85xx - - Poonam Aggrwal <poonam.aggrwal@freescale.com>
P2010RDB powerpc mpc85xx - -
diff --git a/include/configs/P2020DS.h b/include/configs/P2020DS.h
deleted file mode 100644
index 820b633..0000000
--- a/include/configs/P2020DS.h
+++ /dev/null
@@ -1,751 +0,0 @@
-/*
- * Copyright 2007-2012 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * p2020ds board configuration file
- *
- */
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include "../board/freescale/common/ics307_clk.h"
-
-#ifdef CONFIG_36BIT
-#define CONFIG_PHYS_64BIT
-#endif
-
-#ifdef CONFIG_SDCARD
-#define CONFIG_SYS_RAMBOOT
-#define CONFIG_SYS_EXTRA_ENV_RELOC
-#define CONFIG_SYS_TEXT_BASE 0xf8f40000
-#define CONFIG_RESET_VECTOR_ADDRESS 0xf8fffffc
-#endif
-
-#ifdef CONFIG_SPIFLASH
-#define CONFIG_SYS_RAMBOOT
-#define CONFIG_SYS_EXTRA_ENV_RELOC
-#define CONFIG_SYS_TEXT_BASE 0xf8f40000
-#define CONFIG_RESET_VECTOR_ADDRESS 0xf8fffffc
-#endif
-
-/* High Level Configuration Options */
-#define CONFIG_BOOKE 1 /* BOOKE */
-#define CONFIG_E500 1 /* BOOKE e500 family */
-#define CONFIG_P2020 1
-#define CONFIG_P2020DS 1
-#define CONFIG_MP 1 /* support multiple processors */
-
-#ifndef CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_TEXT_BASE 0xeff40000
-#endif
-
-#ifndef CONFIG_RESET_VECTOR_ADDRESS
-#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
-#endif
-
-#define CONFIG_SYS_SRIO
-#define CONFIG_SRIO1 /* SRIO port 1 */
-#define CONFIG_SRIO2 /* SRIO port 2 */
-
-#define CONFIG_FSL_ELBC 1 /* Has Enhanced localbus controller */
-#define CONFIG_PCI 1 /* Enable PCI/PCIE */
-#define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */
-#define CONFIG_PCIE2 1 /* PCIE controler 2 (slot 2) */
-#define CONFIG_PCIE3 1 /* PCIE controler 3 (ULI bridge) */
-#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
-#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
-#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
-#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
-
-#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
-#define CONFIG_E1000 1 /* Defind e1000 pci Ethernet card*/
-
-#define CONFIG_TSEC_ENET /* tsec ethernet support */
-#define CONFIG_ENV_OVERWRITE
-
-#define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */
-#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() /* ddrclk for MPC85xx */
-#define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */
-
-/*
- * These can be toggled for performance analysis, otherwise use default.
- */
-#define CONFIG_L2_CACHE /* toggle L2 cache */
-#define CONFIG_BTB /* toggle branch predition */
-
-#define CONFIG_BOARD_EARLY_INIT_F /* Call board_pre_init */
-
-#define CONFIG_ENABLE_36BIT_PHYS 1
-
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_ADDR_MAP 1
-#define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
-#endif
-
-#define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */
-#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x00400000
-#define CONFIG_PANIC_HANG /* do not reset board on panic */
-
-/*
- * Config the L2 Cache
- */
-#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_INIT_L2_ADDR_PHYS 0xff8f80000ull
-#else
-#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
-#endif
-#define CONFIG_SYS_L2_SIZE (512 << 10)
-#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
-
-#define CONFIG_SYS_CCSRBAR 0xffe00000
-#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
-
-/* DDR Setup */
-#define CONFIG_VERY_BIG_RAM
-#ifdef CONFIG_DDR2
-#define CONFIG_SYS_FSL_DDR2
-#else
-#define CONFIG_SYS_FSL_DDR3 1
-#endif
-
-/* ECC will be enabled based on perf_mode environment variable */
-/* #define CONFIG_DDR_ECC */
-
-#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
-#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
-
-#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
-
-#define CONFIG_NUM_DDR_CONTROLLERS 1
-#define CONFIG_DIMM_SLOTS_PER_CTLR 1
-#define CONFIG_CHIP_SELECTS_PER_CTRL 2
-
-/* I2C addresses of SPD EEPROMs */
-#define CONFIG_DDR_SPD
-#define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD EEPROM located on I2C bus 0 */
-#define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
-
-/* These are used when DDR doesn't use SPD. */
-#define CONFIG_SYS_SDRAM_SIZE 1024 /* DDR is 1GB */
-
-/* Default settings for "stable" mode */
-#define CONFIG_SYS_DDR_CS0_BNDS 0x0000003F
-#define CONFIG_SYS_DDR_CS1_BNDS 0x00000000
-#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202
-#define CONFIG_SYS_DDR_CS1_CONFIG 0x00000000
-#define CONFIG_SYS_DDR_TIMING_3 0x00020000
-#define CONFIG_SYS_DDR_TIMING_0 0x00330804
-#define CONFIG_SYS_DDR_TIMING_1 0x6f6b4846
-#define CONFIG_SYS_DDR_TIMING_2 0x0fa890d4
-#define CONFIG_SYS_DDR_MODE_1 0x00421422
-#define CONFIG_SYS_DDR_MODE_2 0x00000000
-#define CONFIG_SYS_DDR_MODE_CTRL 0x00000000
-#define CONFIG_SYS_DDR_INTERVAL 0x61800100
-#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
-#define CONFIG_SYS_DDR_CLK_CTRL 0x02000000
-#define CONFIG_SYS_DDR_TIMING_4 0x00220001
-#define CONFIG_SYS_DDR_TIMING_5 0x03402400
-#define CONFIG_SYS_DDR_ZQ_CNTL 0x89080600
-#define CONFIG_SYS_DDR_WRLVL_CNTL 0x8655A608
-#define CONFIG_SYS_DDR_CONTROL 0xE7000000 /* Type = DDR3: ECC enabled, No Interleaving */
-#define CONFIG_SYS_DDR_CONTROL2 0x24400011
-#define CONFIG_SYS_DDR_CDR1 0x00040000
-#define CONFIG_SYS_DDR_CDR2 0x00000000
-
-#define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d
-#define CONFIG_SYS_DDR_ERR_DIS 0x00000000
-#define CONFIG_SYS_DDR_SBE 0x00010000
-
-/* Settings that differ for "performance" mode */
-#define CONFIG_SYS_DDR_CS0_BNDS_PERF 0x0000007F /* Interleaving Enabled */
-#define CONFIG_SYS_DDR_CS1_BNDS_PERF 0x00000000 /* Interleaving Enabled */
-#define CONFIG_SYS_DDR_CS1_CONFIG_PERF 0x80014202
-#define CONFIG_SYS_DDR_TIMING_1_PERF 0x5d5b4543
-#define CONFIG_SYS_DDR_TIMING_2_PERF 0x0fa890ce
-#define CONFIG_SYS_DDR_CONTROL_PERF 0xC7004000 /* Type = DDR3: ECC disabled, cs0-cs1 interleaving */
-
-/*
- * The following set of values were tested for DDR2
- * with a DDR3 to DDR2 interposer
- *
-#define CONFIG_SYS_DDR_TIMING_3 0x00000000
-#define CONFIG_SYS_DDR_TIMING_0 0x00260802
-#define CONFIG_SYS_DDR_TIMING_1 0x3935d322
-#define CONFIG_SYS_DDR_TIMING_2 0x14904cc8
-#define CONFIG_SYS_DDR_MODE_1 0x00480432
-#define CONFIG_SYS_DDR_MODE_2 0x00000000
-#define CONFIG_SYS_DDR_INTERVAL 0x06180100
-#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
-#define CONFIG_SYS_DDR_CLK_CTRL 0x03800000
-#define CONFIG_SYS_DDR_OCD_CTRL 0x00000000
-#define CONFIG_SYS_DDR_OCD_STATUS 0x00000000
-#define CONFIG_SYS_DDR_CONTROL 0xC3008000
-#define CONFIG_SYS_DDR_CONTROL2 0x04400010
- *
- */
-
-/*
- * Memory map
- *
- * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable
- * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable
- * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable
- * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable
- *
- * Localbus cacheable (TBD)
- * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable
- *
- * Localbus non-cacheable
- * 0xe000_0000 0xe80f_ffff Promjet/free 128M non-cacheable
- * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable
- * 0xffa0_0000 0xffaf_ffff NAND 1M non-cacheable
- * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0
- * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0
- * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
- */
-
-/*
- * Local Bus Definitions
- */
-#define CONFIG_SYS_FLASH_BASE 0xe0000000 /* start of FLASH 128M */
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull
-#else
-#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
-#endif
-
-#define CONFIG_FLASH_BR_PRELIM \
- (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000) | BR_PS_16 | BR_V)
-#define CONFIG_FLASH_OR_PRELIM 0xf8000ff7
-
-#define CONFIG_SYS_BR1_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
-#define CONFIG_SYS_OR1_PRELIM 0xf8000ff7
-
-#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
-#define CONFIG_SYS_FLASH_QUIET_TEST
-#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
-
-#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
-#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
-
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
-
-#define CONFIG_FLASH_CFI_DRIVER
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_SYS_FLASH_EMPTY_INFO
-#define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
-
-#define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
-
-#define CONFIG_HWCONFIG /* enable hwconfig */
-#define CONFIG_FSL_NGPIXIS /* use common ngPIXIS code */
-
-#ifdef CONFIG_FSL_NGPIXIS
-#define PIXIS_BASE 0xffdf0000 /* PIXIS registers */
-#ifdef CONFIG_PHYS_64BIT
-#define PIXIS_BASE_PHYS 0xfffdf0000ull
-#else
-#define PIXIS_BASE_PHYS PIXIS_BASE
-#endif
-
-#define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V)
-#define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */
-
-#define PIXIS_LBMAP_SWITCH 7
-#define PIXIS_LBMAP_MASK 0xf0
-#define PIXIS_LBMAP_SHIFT 4
-#define PIXIS_LBMAP_ALTBANK 0x20
-#endif
-
-#define CONFIG_SYS_INIT_RAM_LOCK 1
-#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
-/* The assembler doesn't like typecast */
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
- ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
- CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
-#else
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR /* Initial L1 address */
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
-#endif
-#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */
-
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
-#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
-
-#define CONFIG_SYS_NAND_BASE 0xffa00000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull
-#else
-#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
-#endif
-#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE,\
- CONFIG_SYS_NAND_BASE + 0x40000, \
- CONFIG_SYS_NAND_BASE + 0x80000,\
- CONFIG_SYS_NAND_BASE + 0xC0000}
-#define CONFIG_SYS_MAX_NAND_DEVICE 4
-#define CONFIG_MTD_NAND_VERIFY_WRITE
-#define CONFIG_CMD_NAND 1
-#define CONFIG_NAND_FSL_ELBC 1
-#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
-
-/* NAND flash config */
-#define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
- | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
- | BR_PS_8 /* Port Size = 8bit */ \
- | BR_MS_FCM /* MSEL = FCM */ \
- | BR_V) /* valid */
-#define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \
- | OR_FCM_PGS /* Large Page*/ \
- | OR_FCM_CSCT \
- | OR_FCM_CST \
- | OR_FCM_CHT \
- | OR_FCM_SCY_1 \
- | OR_FCM_TRLX \
- | OR_FCM_EHTR)
-
-#define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
-#define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
-#define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
-#define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
-
-#define CONFIG_SYS_BR4_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x40000) \
- | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
- | BR_PS_8 /* Port Size = 8bit */ \
- | BR_MS_FCM /* MSEL = FCM */ \
- | BR_V) /* valid */
-#define CONFIG_SYS_OR4_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
-#define CONFIG_SYS_BR5_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x80000) \
- | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
- | BR_PS_8 /* Port Size = 8bit */ \
- | BR_MS_FCM /* MSEL = FCM */ \
- | BR_V) /* valid */
-#define CONFIG_SYS_OR5_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
-
-#define CONFIG_SYS_BR6_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0xc0000) \
- | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
- | BR_PS_8 /* Port Size = 8bit */ \
- | BR_MS_FCM /* MSEL = FCM */ \
- | BR_V) /* valid */
-#define CONFIG_SYS_OR6_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
-
-/* Serial Port - controlled on board with jumper J8
- * open - index 2
- * shorted - index 1
- */
-#define CONFIG_CONS_INDEX 1
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
-
-#define CONFIG_SYS_BAUDRATE_TABLE \
- {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
-
-#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
-#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
-
-/* Use the HUSH parser */
-#define CONFIG_SYS_HUSH_PARSER
-
-/*
- * Pass open firmware flat tree
- */
-#define CONFIG_OF_LIBFDT 1
-#define CONFIG_OF_BOARD_SETUP 1
-#define CONFIG_OF_STDOUT_VIA_ALIAS 1
-
-/* I2C */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_FSL
-#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
-#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
-#define CONFIG_SYS_FSL_I2C_SPEED 400000
-#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C2_SPEED 400000
-#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
-#define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} }
-
-/*
- * I2C2 EEPROM
- */
-#define CONFIG_ID_EEPROM
-#ifdef CONFIG_ID_EEPROM
-#define CONFIG_SYS_I2C_EEPROM_NXID
-#endif
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-#define CONFIG_SYS_EEPROM_BUS_NUM 0
-
-/*
- * eSPI - Enhanced SPI
- */
-#define CONFIG_FSL_ESPI
-
-#define CONFIG_SPI_FLASH
-#define CONFIG_SPI_FLASH_SPANSION
-
-#define CONFIG_CMD_SF
-#define CONFIG_SF_DEFAULT_SPEED 10000000
-#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
-
-/*
- * General PCI
- * Memory space is mapped 1-1, but I/O space must start from 0.
- */
-
-/* controller 3, Slot 1, tgtid 3, Base address b000 */
-#define CONFIG_SYS_PCIE3_NAME "Slot 1"
-#define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
-#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc00000000ull
-#else
-#define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000
-#define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000
-#endif
-#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
-#define CONFIG_SYS_PCIE3_IO_VIRT 0xffc00000
-#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc00000ull
-#else
-#define CONFIG_SYS_PCIE3_IO_PHYS 0xffc00000
-#endif
-#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
-
-/* controller 2, direct to uli, tgtid 2, Base address 9000 */
-#define CONFIG_SYS_PCIE2_NAME "ULI"
-#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
-#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
-#else
-#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
-#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
-#endif
-#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
-#define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
-#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull
-#else
-#define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
-#endif
-#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
-
-/* controller 1, Slot 2, tgtid 1, Base address a000 */
-#define CONFIG_SYS_PCIE1_NAME "Slot 2"
-#define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
-#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull
-#else
-#define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000
-#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000
-#endif
-#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
-#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000
-#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc20000ull
-#else
-#define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000
-#endif
-#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
-
-#if defined(CONFIG_PCI)
-
-/*PCIE video card used*/
-#define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_VIRT
-
-/* video */
-#undef CONFIG_VIDEO
-
-#if defined(CONFIG_VIDEO)
-#define CONFIG_BIOSEMU
-#define CONFIG_CFB_CONSOLE
-#define CONFIG_VIDEO_SW_CURSOR
-#define CONFIG_VGA_AS_SINGLE_DEVICE
-#define CONFIG_ATI_RADEON_FB
-#define CONFIG_VIDEO_LOGO
-/*#define CONFIG_CONSOLE_CURSOR*/
-#define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET
-#endif
-
-/* SRIO1 uses the same window as PCIE2 mem window */
-#define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull
-#else
-#define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000
-#endif
-#define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 512M */
-
-/* SRIO2 uses the same window as PCIE1 mem window */
-#define CONFIG_SYS_SRIO2_MEM_VIRT 0xc0000000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_SRIO2_MEM_PHYS 0xc40000000ull
-#else
-#define CONFIG_SYS_SRIO2_MEM_PHYS 0xc0000000
-#endif
-#define CONFIG_SYS_SRIO2_MEM_SIZE 0x20000000 /* 512M */
-
-#define CONFIG_PCI_PNP /* do pci plug-and-play */
-#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
-#define CONFIG_DOS_PARTITION
-#define CONFIG_SCSI_AHCI
-
-#ifdef CONFIG_SCSI_AHCI
-#define CONFIG_LIBATA
-#define CONFIG_SATA_ULI5288
-#define CONFIG_SYS_SCSI_MAX_SCSI_ID 4
-#define CONFIG_SYS_SCSI_MAX_LUN 1
-#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN)
-#define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE
-#endif /* SCSI */
-
-#endif /* CONFIG_PCI */
-
-
-#if defined(CONFIG_TSEC_ENET)
-
-#define CONFIG_MII 1 /* MII PHY management */
-#define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
-#define CONFIG_TSEC1 1
-#define CONFIG_TSEC1_NAME "eTSEC1"
-#define CONFIG_TSEC2 1
-#define CONFIG_TSEC2_NAME "eTSEC2"
-#define CONFIG_TSEC3 1
-#define CONFIG_TSEC3_NAME "eTSEC3"
-
-#define CONFIG_FSL_SGMII_RISER 1
-#define SGMII_RISER_PHY_OFFSET 0x1b
-
-#ifdef CONFIG_FSL_SGMII_RISER
-#define CONFIG_SYS_TBIPA_VALUE 0x10 /* avoid conflict with eTSEC4 paddr */
-#endif
-
-#define TSEC1_PHY_ADDR 0
-#define TSEC2_PHY_ADDR 1
-#define TSEC3_PHY_ADDR 2
-
-#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
-#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
-#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
-
-#define TSEC1_PHYIDX 0
-#define TSEC2_PHYIDX 0
-#define TSEC3_PHYIDX 0
-
-#define CONFIG_ETHPRIME "eTSEC1"
-
-#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
-#endif /* CONFIG_TSEC_ENET */
-
-/*
- * Environment
- */
-#if defined(CONFIG_SDCARD)
-#define CONFIG_ENV_IS_IN_MMC
-#define CONFIG_FSL_FIXED_MMC_LOCATION
-#define CONFIG_ENV_SIZE 0x2000
-#define CONFIG_SYS_MMC_ENV_DEV 0
-#elif defined(CONFIG_SPIFLASH)
-#define CONFIG_ENV_IS_IN_SPI_FLASH
-#define CONFIG_ENV_SPI_BUS 0
-#define CONFIG_ENV_SPI_CS 0
-#define CONFIG_ENV_SPI_MAX_HZ 10000000
-#define CONFIG_ENV_SPI_MODE 0
-#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
-#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
-#define CONFIG_ENV_SECT_SIZE 0x10000
-#else
-#define CONFIG_ENV_IS_IN_FLASH 1
-#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE 0x2000
-#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
-#endif
-
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_IRQ
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_ELF
-#define CONFIG_CMD_IRQ
-#define CONFIG_CMD_SETEXPR
-#define CONFIG_CMD_REGINFO
-
-#if defined(CONFIG_PCI)
-#define CONFIG_CMD_PCI
-#define CONFIG_CMD_NET
-#define CONFIG_CMD_SCSI
-#define CONFIG_CMD_EXT2
-#endif
-
-/*
- * USB
- */
-#define CONFIG_HAS_FSL_DR_USB
-#ifdef CONFIG_HAS_FSL_DR_USB
-#define CONFIG_USB_EHCI
-
-#ifdef CONFIG_USB_EHCI
-#define CONFIG_CMD_USB
-#define CONFIG_USB_STORAGE
-#define CONFIG_USB_EHCI_FSL
-#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
-#endif
-#endif
-
-/*
- * SDHC/MMC
- */
-#define CONFIG_MMC
-
-#ifdef CONFIG_MMC
-#define CONFIG_FSL_ESDHC
-#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
-#define CONFIG_CMD_MMC
-#define CONFIG_GENERIC_MMC
-#endif
-
-#if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI)
-#define CONFIG_CMD_EXT2
-#define CONFIG_CMD_FAT
-#define CONFIG_DOS_PARTITION
-#endif
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_CMDLINE_EDITING /* Command-line editing */
-#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
-#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 64 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/
-#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
-#endif
-
-/*
- * Environment Configuration
- */
-
-/* The mac addresses for all ethernet interface */
-#if defined(CONFIG_TSEC_ENET)
-#define CONFIG_HAS_ETH0
-#define CONFIG_HAS_ETH1
-#define CONFIG_HAS_ETH2
-#endif
-
-#define CONFIG_IPADDR 192.168.1.254
-
-#define CONFIG_HOSTNAME unknown
-#define CONFIG_ROOTPATH "/opt/nfsroot"
-#define CONFIG_BOOTFILE "uImage"
-#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
-
-#define CONFIG_SERVERIP 192.168.1.1
-#define CONFIG_GATEWAYIP 192.168.1.1
-#define CONFIG_NETMASK 255.255.255.0
-
-/* default location for tftp and bootm */
-#define CONFIG_LOADADDR 1000000
-
-#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
-
-#define CONFIG_BAUDRATE 115200
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
-"perf_mode=performance\0" \
- "hwconfig=fsl_ddr:ctlr_intlv=bank,bank_intlv=cs0_cs1;" \
- "usb1:dr_mode=host,phy_type=ulpi\0" \
-"netdev=eth0\0" \
-"uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
-"tftpflash=tftpboot $loadaddr $uboot; " \
- "protect off " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
- "erase " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
- "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize; " \
- "protect on " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
- "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize\0" \
-"satabootcmd=setenv bootargs root=/dev/$bdev rw " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr - $fdtaddr" \
-"consoledev=ttyS0\0" \
-"ramdiskaddr=2000000\0" \
-"ramdiskfile=p2020ds/ramdisk.uboot\0" \
-"fdtaddr=c00000\0" \
-"othbootargs=cache-sram-size=0x10000\0" \
-"fdtfile=p2020ds/p2020ds.dtb\0" \
-"bdev=sda3\0" \
-"partition=scsi 0:0\0"
-
-#define CONFIG_HDBOOT \
- "setenv bootargs root=/dev/$bdev rw " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "ext2load $partition $loadaddr $bootfile;" \
- "ext2load $partition $fdtaddr $fdtfile;" \
- "bootm $loadaddr - $fdtaddr"
-
-#define CONFIG_NFSBOOTCOMMAND \
- "setenv bootargs root=/dev/nfs rw " \
- "nfsroot=$serverip:$rootpath " \
- "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr - $fdtaddr"
-
-#define CONFIG_RAMBOOTCOMMAND \
- "setenv bootargs root=/dev/ram rw " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "tftp $ramdiskaddr $ramdiskfile;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr $ramdiskaddr $fdtaddr"
-
-#define CONFIG_BOOTCOMMAND CONFIG_HDBOOT
-
-#endif /* __CONFIG_H */
--
1.9.1
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [U-Boot] [PATCH 5/8] powerpc: ppc4xx: remove PPChameleonEVB, CATcenter boards
2015-01-22 15:24 [U-Boot] [PATCH 0/8] powerpc: drop more non-generic boards Masahiro Yamada
` (3 preceding siblings ...)
2015-01-22 15:24 ` [U-Boot] [PATCH 4/8] powerpc: mpc85xx: remove P2020DS " Masahiro Yamada
@ 2015-01-22 15:24 ` Masahiro Yamada
2015-01-22 15:41 ` Stefan Roese
2015-01-23 21:57 ` Tom Rini
2015-01-22 15:24 ` [U-Boot] [PATCH 6/8] powerpc: mpc5xxx: remove Total5200 board support Masahiro Yamada
` (2 subsequent siblings)
7 siblings, 2 replies; 19+ messages in thread
From: Masahiro Yamada @ 2015-01-22 15:24 UTC (permalink / raw)
To: u-boot
These boards are still non-generic boards.
It is a good thing that we can drop board-specific hack code
from drivers/mtd/nand/nand_base.c
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Andrea "llandre" Marson <andrea.marson@dave-tech.it>
---
arch/powerpc/cpu/ppc4xx/Kconfig | 7 -
board/dave/PPChameleonEVB/Kconfig | 25 -
board/dave/PPChameleonEVB/MAINTAINERS | 20 -
board/dave/PPChameleonEVB/Makefile | 8 -
board/dave/PPChameleonEVB/PPChameleonEVB.c | 231 ---------
board/dave/PPChameleonEVB/flash.c | 99 ----
board/dave/PPChameleonEVB/nand.c | 99 ----
board/dave/PPChameleonEVB/u-boot.lds | 115 -----
configs/CATcenter_25_defconfig | 4 -
configs/CATcenter_33_defconfig | 4 -
configs/CATcenter_defconfig | 4 -
configs/PPChameleonEVB_BA_25_defconfig | 4 -
configs/PPChameleonEVB_BA_33_defconfig | 4 -
configs/PPChameleonEVB_HI_25_defconfig | 4 -
configs/PPChameleonEVB_HI_33_defconfig | 4 -
configs/PPChameleonEVB_ME_25_defconfig | 4 -
configs/PPChameleonEVB_ME_33_defconfig | 4 -
configs/PPChameleonEVB_defconfig | 3 -
doc/README.scrapyard | 2 +
drivers/mtd/nand/nand_base.c | 5 -
include/configs/CATcenter.h | 750 ----------------------------
include/configs/PPChameleonEVB.h | 777 -----------------------------
22 files changed, 2 insertions(+), 2175 deletions(-)
delete mode 100644 board/dave/PPChameleonEVB/Kconfig
delete mode 100644 board/dave/PPChameleonEVB/MAINTAINERS
delete mode 100644 board/dave/PPChameleonEVB/Makefile
delete mode 100644 board/dave/PPChameleonEVB/PPChameleonEVB.c
delete mode 100644 board/dave/PPChameleonEVB/flash.c
delete mode 100644 board/dave/PPChameleonEVB/nand.c
delete mode 100644 board/dave/PPChameleonEVB/u-boot.lds
delete mode 100644 configs/CATcenter_25_defconfig
delete mode 100644 configs/CATcenter_33_defconfig
delete mode 100644 configs/CATcenter_defconfig
delete mode 100644 configs/PPChameleonEVB_BA_25_defconfig
delete mode 100644 configs/PPChameleonEVB_BA_33_defconfig
delete mode 100644 configs/PPChameleonEVB_HI_25_defconfig
delete mode 100644 configs/PPChameleonEVB_HI_33_defconfig
delete mode 100644 configs/PPChameleonEVB_ME_25_defconfig
delete mode 100644 configs/PPChameleonEVB_ME_33_defconfig
delete mode 100644 configs/PPChameleonEVB_defconfig
delete mode 100644 include/configs/CATcenter.h
delete mode 100644 include/configs/PPChameleonEVB.h
diff --git a/arch/powerpc/cpu/ppc4xx/Kconfig b/arch/powerpc/cpu/ppc4xx/Kconfig
index a40ae3b..5db5e34 100644
--- a/arch/powerpc/cpu/ppc4xx/Kconfig
+++ b/arch/powerpc/cpu/ppc4xx/Kconfig
@@ -101,12 +101,6 @@ config TARGET_FX12MM
config TARGET_V5FX30TEVAL
bool "Support v5fx30teval"
-config TARGET_CATCENTER
- bool "Support CATcenter"
-
-config TARGET_PPCHAMELEONEVB
- bool "Support PPChameleonEVB"
-
config TARGET_CPCI2DP
bool "Support CPCI2DP"
@@ -199,7 +193,6 @@ source "board/avnet/fx12mm/Kconfig"
source "board/avnet/v5fx30teval/Kconfig"
source "board/csb272/Kconfig"
source "board/csb472/Kconfig"
-source "board/dave/PPChameleonEVB/Kconfig"
source "board/esd/cpci2dp/Kconfig"
source "board/esd/cpci405/Kconfig"
source "board/esd/plu405/Kconfig"
diff --git a/board/dave/PPChameleonEVB/Kconfig b/board/dave/PPChameleonEVB/Kconfig
deleted file mode 100644
index bfe0011..0000000
--- a/board/dave/PPChameleonEVB/Kconfig
+++ /dev/null
@@ -1,25 +0,0 @@
-if TARGET_CATCENTER
-
-config SYS_BOARD
- default "PPChameleonEVB"
-
-config SYS_VENDOR
- default "dave"
-
-config SYS_CONFIG_NAME
- default "CATcenter"
-
-endif
-
-if TARGET_PPCHAMELEONEVB
-
-config SYS_BOARD
- default "PPChameleonEVB"
-
-config SYS_VENDOR
- default "dave"
-
-config SYS_CONFIG_NAME
- default "PPChameleonEVB"
-
-endif
diff --git a/board/dave/PPChameleonEVB/MAINTAINERS b/board/dave/PPChameleonEVB/MAINTAINERS
deleted file mode 100644
index d43c6d0..0000000
--- a/board/dave/PPChameleonEVB/MAINTAINERS
+++ /dev/null
@@ -1,20 +0,0 @@
-PPCHAMELEONEVB BOARD
-#M: -
-S: Maintained
-F: board/dave/PPChameleonEVB/
-F: include/configs/CATcenter.h
-F: configs/CATcenter_defconfig
-F: configs/CATcenter_25_defconfig
-F: configs/CATcenter_33_defconfig
-
-PPCHAMELEONEVB BOARD
-M: Andrea "llandre" Marson <andrea.marson@dave-tech.it>
-S: Maintained
-F: include/configs/PPChameleonEVB.h
-F: configs/PPChameleonEVB_defconfig
-F: configs/PPChameleonEVB_BA_25_defconfig
-F: configs/PPChameleonEVB_BA_33_defconfig
-F: configs/PPChameleonEVB_HI_25_defconfig
-F: configs/PPChameleonEVB_HI_33_defconfig
-F: configs/PPChameleonEVB_ME_25_defconfig
-F: configs/PPChameleonEVB_ME_33_defconfig
diff --git a/board/dave/PPChameleonEVB/Makefile b/board/dave/PPChameleonEVB/Makefile
deleted file mode 100644
index 31edc4a..0000000
--- a/board/dave/PPChameleonEVB/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y = PPChameleonEVB.o flash.o nand.o
diff --git a/board/dave/PPChameleonEVB/PPChameleonEVB.c b/board/dave/PPChameleonEVB/PPChameleonEVB.c
deleted file mode 100644
index c9ab50e..0000000
--- a/board/dave/PPChameleonEVB/PPChameleonEVB.c
+++ /dev/null
@@ -1,231 +0,0 @@
-/*
- * (C) Copyright 2003
- * DAVE Srl
- * http://www.dave-tech.it
- * http://www.wawnet.biz
- * mailto:info at wawnet.biz
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/processor.h>
-#include <command.h>
-#include <malloc.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/* ------------------------------------------------------------------------- */
-
-int board_early_init_f (void)
-{
- out32(GPIO0_OR, CONFIG_SYS_NAND0_CE); /* set initial outputs */
- out32(GPIO0_OR, CONFIG_SYS_NAND1_CE); /* set initial outputs */
-
- /*
- * IRQ 0-15 405GP internally generated; active high; level sensitive
- * IRQ 16 405GP internally generated; active low; level sensitive
- * IRQ 17-24 RESERVED
- * IRQ 25 (EXT IRQ 0)
- * IRQ 26 (EXT IRQ 1)
- * IRQ 27 (EXT IRQ 2)
- * IRQ 28 (EXT IRQ 3)
- * IRQ 29 (EXT IRQ 4)
- * IRQ 30 (EXT IRQ 5)
- * IRQ 31 (EXT IRQ 6)
- */
- mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
- mtdcr(UIC0ER, 0x00000000); /* disable all ints */
- mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/
- mtdcr(UIC0PR, 0xFFFFFF80); /* set int polarities */
- mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */
- mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority*/
- mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
-
- /*
- * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us
- */
-#if 1 /* test-only */
- mtebc (EBC0_CFG, 0xa8400000); /* ebc always driven */
-#else
- mtebc (EBC0_CFG, 0x28400000); /* ebc in high-z */
-#endif
- return 0;
-}
-
-/* ------------------------------------------------------------------------- */
-
-int misc_init_f (void)
-{
- return 0; /* dummy implementation */
-}
-
-extern flash_info_t flash_info[]; /* info for FLASH chips */
-
-int misc_init_r (void)
-{
- /* adjust flash start and size as well as the offset */
- gd->bd->bi_flashstart = 0 - flash_info[0].size;
- gd->bd->bi_flashoffset= flash_info[0].size - CONFIG_SYS_MONITOR_LEN;
-#if 0
- volatile unsigned short *fpga_mode =
- (unsigned short *)((ulong)CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL);
- volatile unsigned char *duart0_mcr =
- (unsigned char *)((ulong)DUART0_BA + 4);
- volatile unsigned char *duart1_mcr =
- (unsigned char *)((ulong)DUART1_BA + 4);
-
- bd_t *bd = gd->bd;
- char * tmp; /* Temporary char pointer */
- unsigned char *dst;
- ulong len = sizeof(fpgadata);
- int status;
- int index;
- int i;
- unsigned long CPC0_CR0Reg;
-
- dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE);
- if (gunzip (dst, CONFIG_SYS_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
- printf ("GUNZIP ERROR - must RESET board to recover\n");
- do_reset (NULL, 0, 0, NULL);
- }
-
- status = fpga_boot(dst, len);
- if (status != 0) {
- printf("\nFPGA: Booting failed ");
- switch (status) {
- case ERROR_FPGA_PRG_INIT_LOW:
- printf("(Timeout: INIT not low after asserting PROGRAM*)\n ");
- break;
- case ERROR_FPGA_PRG_INIT_HIGH:
- printf("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
- break;
- case ERROR_FPGA_PRG_DONE:
- printf("(Timeout: DONE not high after programming FPGA)\n ");
- break;
- }
-
- /* display infos on fpgaimage */
- index = 15;
- for (i=0; i<4; i++) {
- len = dst[index];
- printf("FPGA: %s\n", &(dst[index+1]));
- index += len+3;
- }
- putc ('\n');
- /* delayed reboot */
- for (i=20; i>0; i--) {
- printf("Rebooting in %2d seconds \r",i);
- for (index=0;index<1000;index++)
- udelay(1000);
- }
- putc ('\n');
- do_reset(NULL, 0, 0, NULL);
- }
-
- puts("FPGA: ");
-
- /* display infos on fpgaimage */
- index = 15;
- for (i=0; i<4; i++) {
- len = dst[index];
- printf("%s ", &(dst[index+1]));
- index += len+3;
- }
- putc ('\n');
-
- free(dst);
-
- /*
- * Reset FPGA via FPGA_DATA pin
- */
- SET_FPGA(FPGA_PRG | FPGA_CLK);
- udelay(1000); /* wait 1ms */
- SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);
- udelay(1000); /* wait 1ms */
-#endif
-
-#if 0
- /*
- * Enable power on PS/2 interface
- */
- *fpga_mode |= CONFIG_SYS_FPGA_CTRL_PS2_RESET;
-
- /*
- * Enable interrupts in exar duart mcr[3]
- */
- *duart0_mcr = 0x08;
- *duart1_mcr = 0x08;
-#endif
- return (0);
-}
-
-/*
- * Check Board Identity:
- */
-
-int checkboard (void)
-{
- char str[64];
- int i = getenv_f("serial#", str, sizeof(str));
-
- puts ("Board: ");
-
- if (i == -1) {
- puts ("### No HW ID - assuming PPChameleonEVB");
- } else {
- puts(str);
- }
-
- putc ('\n');
-
- return 0;
-}
-
-/* ------------------------------------------------------------------------- */
-
-int testdram (void)
-{
- /* TODO: XXX XXX XXX */
- printf ("test: 16 MB - ok\n");
-
- return (0);
-}
-
-/* ------------------------------------------------------------------------- */
-
-#ifdef CONFIG_CFB_CONSOLE
-# ifdef CONFIG_CONSOLE_EXTRA_INFO
-# include <video_fb.h>
-extern GraphicDevice smi;
-
-void video_get_info_str (int line_number, char *info)
-{
- uint pvr = get_pvr ();
-
- /* init video info strings for graphic console */
- switch (line_number) {
- case 1:
- switch (pvr) {
- case PVR_405EP_RB:
- sprintf (info, " AMCC PowerPC 405EP Rev. B");
- break;
- default:
- sprintf (info, " AMCC PowerPC 405EP Rev. <unknown>");
- break;
- }
- return;
- case 2:
- sprintf (info, " DAVE Srl PPChameleonEVB - www.dave-tech.it");
- return;
- case 3:
- sprintf (info, " %s", smi.modeIdent);
- return;
- }
-
- /* no more info lines */
- *info = 0;
- return;
-}
-# endif /* CONFIG_CONSOLE_EXTRA_INFO */
-#endif /* CONFIG_CFB_CONSOLE */
diff --git a/board/dave/PPChameleonEVB/flash.c b/board/dave/PPChameleonEVB/flash.c
deleted file mode 100644
index 771151b..0000000
--- a/board/dave/PPChameleonEVB/flash.c
+++ /dev/null
@@ -1,99 +0,0 @@
-/*
- * (C) Copyright 2001
- * Stefan Roese, esd gmbh germany, stefan.roese at esd-electronics.com
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/ppc4xx.h>
-#include <asm/processor.h>
-
-/*
- * include common flash code (for esd boards)
- */
-#include "../common/flash.c"
-
-/*-----------------------------------------------------------------------
- * Functions
- */
-static ulong flash_get_size (vu_long * addr, flash_info_t * info);
-static void flash_get_offsets (ulong base, flash_info_t * info);
-
-/*-----------------------------------------------------------------------
- */
-
-unsigned long flash_init (void)
-{
-#ifdef __DEBUG_START_FROM_SRAM__
- return CONFIG_SYS_DUMMY_FLASH_SIZE;
-#else
- unsigned long size;
- int i;
- uint pbcr;
- unsigned long base;
- int size_val = 0;
-
- debug("[%s, %d] Entering ...\n", __FUNCTION__, __LINE__);
- debug("[%s, %d] flash_info = 0x%p ...\n", __func__, __LINE__,
- flash_info);
-
- /* Init: no FLASHes known */
- for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
- flash_info[i].flash_id = FLASH_UNKNOWN;
- }
-
- /* Static FLASH Bank configuration here - FIXME XXX */
-
- debug("[%s, %d] Calling flash_get_size ...\n", __FUNCTION__, __LINE__);
- size = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
-
- if (flash_info[0].flash_id == FLASH_UNKNOWN) {
- printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
- size, size<<20);
- }
-
- debug("[%s, %d] Test point ...\n", __FUNCTION__, __LINE__);
-
- /* Setup offsets */
- flash_get_offsets (-size, &flash_info[0]);
- debug("[%s, %d] Test point ...\n", __FUNCTION__, __LINE__);
-
- /* Re-do sizing to get full correct info */
- mtdcr(EBC0_CFGADDR, PB0CR);
- pbcr = mfdcr(EBC0_CFGDATA);
- mtdcr(EBC0_CFGADDR, PB0CR);
- base = -size;
- switch (size) {
- case 1 << 20:
- size_val = 0;
- break;
- case 2 << 20:
- size_val = 1;
- break;
- case 4 << 20:
- size_val = 2;
- break;
- case 8 << 20:
- size_val = 3;
- break;
- case 16 << 20:
- size_val = 4;
- break;
- }
- pbcr = (pbcr & 0x0001ffff) | base | (size_val << 17);
- mtdcr(EBC0_CFGDATA, pbcr);
- debug("[%s, %d] Test point ...\n", __FUNCTION__, __LINE__);
-
- /* Monitor protection ON by default */
- (void)flash_protect(FLAG_PROTECT_SET,
- -CONFIG_SYS_MONITOR_LEN,
- 0xffffffff,
- &flash_info[0]);
-
- debug("[%s, %d] Test point ...\n", __FUNCTION__, __LINE__);
- flash_info[0].size = size;
-
- return (size);
-#endif
-}
diff --git a/board/dave/PPChameleonEVB/nand.c b/board/dave/PPChameleonEVB/nand.c
deleted file mode 100644
index a191a0c..0000000
--- a/board/dave/PPChameleonEVB/nand.c
+++ /dev/null
@@ -1,99 +0,0 @@
-/*
- * (C) Copyright 2006 DENX Software Engineering
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-
-#if defined(CONFIG_CMD_NAND)
-
-#include <nand.h>
-
-/*
- * hardware specific access to control-lines
- * function borrowed from Linux 2.6 (drivers/mtd/nand/ppchameleonevb.c)
- */
-static void ppchameleonevb_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
-{
- struct nand_chip *this = mtd->priv;
- ulong base = (ulong) this->IO_ADDR_W;
-
- if (ctrl & NAND_CTRL_CHANGE) {
- if ( ctrl & NAND_CLE )
- MACRO_NAND_CTL_SETCLE((unsigned long)base);
- else
- MACRO_NAND_CTL_CLRCLE((unsigned long)base);
- if ( ctrl & NAND_ALE )
- MACRO_NAND_CTL_CLRCLE((unsigned long)base);
- else
- MACRO_NAND_CTL_CLRALE((unsigned long)base);
- if ( ctrl & NAND_NCE )
- MACRO_NAND_ENABLE_CE((unsigned long)base);
- else
- MACRO_NAND_DISABLE_CE((unsigned long)base);
- }
-
- if (cmd != NAND_CMD_NONE)
- writeb(cmd, this->IO_ADDR_W);
-}
-
-
-/*
- * read device ready pin
- * function +/- borrowed from Linux 2.6 (drivers/mtd/nand/ppchameleonevb.c)
- */
-static int ppchameleonevb_device_ready(struct mtd_info *mtdinfo)
-{
- struct nand_chip *this = mtdinfo->priv;
- ulong rb_gpio_pin;
-
- /* use the base addr to find out which chip are we dealing with */
- switch((ulong) this->IO_ADDR_W) {
- case CONFIG_SYS_NAND0_BASE:
- rb_gpio_pin = CONFIG_SYS_NAND0_RDY;
- break;
- case CONFIG_SYS_NAND1_BASE:
- rb_gpio_pin = CONFIG_SYS_NAND1_RDY;
- break;
- default: /* this should never happen */
- return 0;
- break;
- }
-
- if (in32(GPIO0_IR) & rb_gpio_pin)
- return 1;
- return 0;
-}
-
-
-/*
- * Board-specific NAND initialization. The following members of the
- * argument are board-specific (per include/linux/mtd/nand.h):
- * - IO_ADDR_R?: address to read the 8 I/O lines of the flash device
- * - IO_ADDR_W?: address to write the 8 I/O lines of the flash device
- * - cmd_ctrl: hardwarespecific function for accesing control-lines
- * - dev_ready: hardwarespecific function for accesing device ready/busy line
- * - enable_hwecc?: function to enable (reset) hardware ecc generator. Must
- * only be provided if a hardware ECC is available
- * - ecc.mode: mode of ecc, see defines
- * - chip_delay: chip dependent delay for transfering data from array to
- * read regs (tR)
- * - options: various chip options. They can partly be set to inform
- * nand_scan about special functionality. See the defines for further
- * explanation
- * Members with a "?" were not set in the merged testing-NAND branch,
- * so they are not set here either.
- */
-int board_nand_init(struct nand_chip *nand)
-{
-
- nand->cmd_ctrl = ppchameleonevb_hwcontrol;
- nand->dev_ready = ppchameleonevb_device_ready;
- nand->ecc.mode = NAND_ECC_SOFT;
- nand->chip_delay = NAND_BIG_DELAY_US;
- nand->options = NAND_SAMSUNG_LP_OPTIONS;
- return 0;
-}
-#endif
diff --git a/board/dave/PPChameleonEVB/u-boot.lds b/board/dave/PPChameleonEVB/u-boot.lds
deleted file mode 100644
index 94b7076..0000000
--- a/board/dave/PPChameleonEVB/u-boot.lds
+++ /dev/null
@@ -1,115 +0,0 @@
-/*
- * Copyright 2007-2009 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include "config.h"
-
-#ifndef RESET_VECTOR_ADDRESS
-#define RESET_VECTOR_ADDRESS 0xfffffffc
-#endif
-
-OUTPUT_ARCH(powerpc)
-
-PHDRS
-{
- text PT_LOAD;
- bss PT_LOAD;
-}
-
-SECTIONS
-{
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .text :
- {
- *(.text*)
- } :text
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- } :text
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x00FF) & 0xFFFFFF00;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- _GOT2_TABLE_ = .;
- KEEP(*(.got2))
- KEEP(*(.got))
- PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4);
- _FIXUP_TABLE_ = .;
- KEEP(*(.fixup))
- }
- __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
- __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
-
- .data :
- {
- *(.data*)
- *(.sdata*)
- }
- _edata = .;
- PROVIDE (edata = .);
-
- . = .;
-
- . = ALIGN(4);
- .u_boot_list : {
- KEEP(*(SORT(.u_boot_list*)));
- }
-
- . = .;
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(256);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(256);
- __init_end = .;
-
- ppcenv_assert = ASSERT(. < 0xFFFF8000, ".bss section too big, overlaps .ppcenv section. Please update your confguration: CONFIG_SYS_MONITOR_BASE, CONFIG_SYS_MONITOR_LEN and CONFIG_SYS_TEXT_BASE may need to be modified.");
- . = 0xFFFF8000;
- .ppcenv :
- {
- common/env_embedded.o(.ppcenv);
- }
-
- .resetvec RESET_VECTOR_ADDRESS :
- {
- KEEP(*(.resetvec))
- } :text = 0xffff
-
- . = RESET_VECTOR_ADDRESS + 0x4;
-
- /*
- * Make sure that the bss segment isn't linked at 0x0, otherwise its
- * address won't be updated during relocation fixups. Note that
- * this is a temporary fix. Code to dynamically the fixup the bss
- * location will be added in the future. When the bss relocation
- * fixup code is present this workaround should be removed.
- */
-#if (RESET_VECTOR_ADDRESS == 0xfffffffc)
- . |= 0x10;
-#endif
-
- __bss_start = .;
- .bss (NOLOAD) :
- {
- *(.bss*)
- *(.sbss*)
- *(COMMON)
- } :bss
-
- . = ALIGN(4);
- __bss_end = . ;
- PROVIDE (end = .);
-}
diff --git a/configs/CATcenter_25_defconfig b/configs/CATcenter_25_defconfig
deleted file mode 100644
index 1a8903c..0000000
--- a/configs/CATcenter_25_defconfig
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_SYS_EXTRA_OPTIONS="PPCHAMELEON_MODULE_MODEL=1,PPCHAMELEON_CLK_25"
-CONFIG_PPC=y
-CONFIG_4xx=y
-CONFIG_TARGET_CATCENTER=y
diff --git a/configs/CATcenter_33_defconfig b/configs/CATcenter_33_defconfig
deleted file mode 100644
index 4b0eb8d..0000000
--- a/configs/CATcenter_33_defconfig
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_SYS_EXTRA_OPTIONS="PPCHAMELEON_MODULE_MODEL=1,PPCHAMELEON_CLK_33"
-CONFIG_PPC=y
-CONFIG_4xx=y
-CONFIG_TARGET_CATCENTER=y
diff --git a/configs/CATcenter_defconfig b/configs/CATcenter_defconfig
deleted file mode 100644
index 53e00ad..0000000
--- a/configs/CATcenter_defconfig
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_SYS_EXTRA_OPTIONS="PPCHAMELEON_MODULE_MODEL=1"
-CONFIG_PPC=y
-CONFIG_4xx=y
-CONFIG_TARGET_CATCENTER=y
diff --git a/configs/PPChameleonEVB_BA_25_defconfig b/configs/PPChameleonEVB_BA_25_defconfig
deleted file mode 100644
index e367299..0000000
--- a/configs/PPChameleonEVB_BA_25_defconfig
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_SYS_EXTRA_OPTIONS="PPCHAMELEON_MODULE_MODEL=0,PPCHAMELEON_CLK_25"
-CONFIG_PPC=y
-CONFIG_4xx=y
-CONFIG_TARGET_PPCHAMELEONEVB=y
diff --git a/configs/PPChameleonEVB_BA_33_defconfig b/configs/PPChameleonEVB_BA_33_defconfig
deleted file mode 100644
index f4041c9..0000000
--- a/configs/PPChameleonEVB_BA_33_defconfig
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_SYS_EXTRA_OPTIONS="PPCHAMELEON_MODULE_MODEL=0,PPCHAMELEON_CLK_33"
-CONFIG_PPC=y
-CONFIG_4xx=y
-CONFIG_TARGET_PPCHAMELEONEVB=y
diff --git a/configs/PPChameleonEVB_HI_25_defconfig b/configs/PPChameleonEVB_HI_25_defconfig
deleted file mode 100644
index a9de221..0000000
--- a/configs/PPChameleonEVB_HI_25_defconfig
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_SYS_EXTRA_OPTIONS="PPCHAMELEON_MODULE_MODEL=2,PPCHAMELEON_CLK_25"
-CONFIG_PPC=y
-CONFIG_4xx=y
-CONFIG_TARGET_PPCHAMELEONEVB=y
diff --git a/configs/PPChameleonEVB_HI_33_defconfig b/configs/PPChameleonEVB_HI_33_defconfig
deleted file mode 100644
index 882262b..0000000
--- a/configs/PPChameleonEVB_HI_33_defconfig
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_SYS_EXTRA_OPTIONS="PPCHAMELEON_MODULE_MODEL=2,PPCHAMELEON_CLK_33"
-CONFIG_PPC=y
-CONFIG_4xx=y
-CONFIG_TARGET_PPCHAMELEONEVB=y
diff --git a/configs/PPChameleonEVB_ME_25_defconfig b/configs/PPChameleonEVB_ME_25_defconfig
deleted file mode 100644
index f9a0440..0000000
--- a/configs/PPChameleonEVB_ME_25_defconfig
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_SYS_EXTRA_OPTIONS="PPCHAMELEON_MODULE_MODEL=1,PPCHAMELEON_CLK_25"
-CONFIG_PPC=y
-CONFIG_4xx=y
-CONFIG_TARGET_PPCHAMELEONEVB=y
diff --git a/configs/PPChameleonEVB_ME_33_defconfig b/configs/PPChameleonEVB_ME_33_defconfig
deleted file mode 100644
index 8ee09b8..0000000
--- a/configs/PPChameleonEVB_ME_33_defconfig
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_SYS_EXTRA_OPTIONS="PPCHAMELEON_MODULE_MODEL=1,PPCHAMELEON_CLK_33"
-CONFIG_PPC=y
-CONFIG_4xx=y
-CONFIG_TARGET_PPCHAMELEONEVB=y
diff --git a/configs/PPChameleonEVB_defconfig b/configs/PPChameleonEVB_defconfig
deleted file mode 100644
index 2d83330..0000000
--- a/configs/PPChameleonEVB_defconfig
+++ /dev/null
@@ -1,3 +0,0 @@
-CONFIG_PPC=y
-CONFIG_4xx=y
-CONFIG_TARGET_PPCHAMELEONEVB=y
diff --git a/doc/README.scrapyard b/doc/README.scrapyard
index 719b970..976fca1 100644
--- a/doc/README.scrapyard
+++ b/doc/README.scrapyard
@@ -12,6 +12,8 @@ The list should be sorted in reverse chronological order.
Board Arch CPU Commit Removed Last known maintainer/contact
=================================================================================================
+CATcenter powerpc ppc4xx - -
+PPChameleonEVB powerpc ppc4xx - - Andrea "llandre" Marson <andrea.marson@dave-tech.it>
P2020DS powerpc mpc85xx - -
P2020COME powerpc mpc85xx - - Ira W. Snyder <iws@ovro.caltech.edu>
P2020RDB powerpc mpc85xx - - Poonam Aggrwal <poonam.aggrwal@freescale.com>
diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c
index 63bdf65..6db6566 100644
--- a/drivers/mtd/nand/nand_base.c
+++ b/drivers/mtd/nand/nand_base.c
@@ -1065,11 +1065,6 @@ static int nand_wait(struct mtd_info *mtd, struct nand_chip *chip)
}
}
#endif
-#ifdef PPCHAMELON_NAND_TIMER_HACK
- time_start = get_timer(0);
- while (get_timer(time_start) < 10)
- ;
-#endif /* PPCHAMELON_NAND_TIMER_HACK */
led_trigger_event(nand_led_trigger, LED_OFF);
status = (int)chip->read_byte(mtd);
diff --git a/include/configs/CATcenter.h b/include/configs/CATcenter.h
deleted file mode 100644
index 27539d2..0000000
--- a/include/configs/CATcenter.h
+++ /dev/null
@@ -1,750 +0,0 @@
-/*
- * ueberarbeitet durch Christoph Seyfert
- *
- * (C) Copyright 2004-2005 DENX Software Engineering,
- * Wolfgang Grandegger <wg@denx.de>
- * (C) Copyright 2003
- * DAVE Srl
- *
- * http://www.dave-tech.it
- * http://www.wawnet.biz
- * mailto:info at wawnet.biz
- *
- * Credits: Stefan Roese, Wolfgang Denk
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#define CONFIG_PPCHAMELEON_MODULE_BA 0 /* Basic Model */
-#define CONFIG_PPCHAMELEON_MODULE_ME 1 /* Medium Model */
-#define CONFIG_PPCHAMELEON_MODULE_HI 2 /* High-End Model */
-#ifndef CONFIG_PPCHAMELEON_MODULE_MODEL
-#define CONFIG_PPCHAMELEON_MODULE_MODEL CONFIG_PPCHAMELEON_MODULE_BA
-#endif
-
-/* Only one of the following two symbols must be defined (default is 25 MHz)
- * CONFIG_PPCHAMELEON_CLK_25
- * CONFIG_PPCHAMELEON_CLK_33
- */
-#if (!defined(CONFIG_PPCHAMELEON_CLK_25) && !defined(CONFIG_PPCHAMELEON_CLK_33))
-#define CONFIG_PPCHAMELEON_CLK_25
-#endif
-
-#if (defined(CONFIG_PPCHAMELEON_CLK_25) && defined(CONFIG_PPCHAMELEON_CLK_33))
-#error "* Two external frequencies (SysClk) are defined! *"
-#endif
-
-#undef CONFIG_PPCHAMELEON_SMI712
-
-/*
- * Debug stuff
- */
-#undef __DEBUG_START_FROM_SRAM__
-#define __DISABLE_MACHINE_EXCEPTION__
-
-#ifdef __DEBUG_START_FROM_SRAM__
-#define CONFIG_SYS_DUMMY_FLASH_SIZE 1024*1024*4
-#endif
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_405EP 1 /* This is a PPC405 CPU */
-#define CONFIG_PPCHAMELEONEVB 1 /* ...on a PPChameleonEVB board */
-
-#define CONFIG_SYS_TEXT_BASE 0xFFFB0000 /* Reserve 320 kB for Monitor */
-#define CONFIG_SYS_LDSCRIPT "board/dave/PPChameleonEVB/u-boot.lds"
-
-#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
-#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
-
-#ifdef CONFIG_PPCHAMELEON_CLK_25
-# define CONFIG_SYS_CLK_FREQ 25000000 /* external frequency to pll */
-#elif (defined (CONFIG_PPCHAMELEON_CLK_33))
-#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
-#else
-# error "* External frequency (SysClk) not defined! *"
-#endif
-
-#define CONFIG_CONS_INDEX 2 /* Use UART1 */
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-#define CONFIG_SYS_NS16550_CLK get_serial_clock()
-#define CONFIG_BAUDRATE 115200
-#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
-
-#define CONFIG_VERSION_VARIABLE 1 /* add version variable */
-#define CONFIG_IDENT_STRING "1"
-
-#undef CONFIG_BOOTARGS
-
-/* Ethernet stuff */
-#define CONFIG_ENV_OVERWRITE /* Let the user to change the Ethernet MAC addresses */
-#define CONFIG_ETHADDR 00:50:C2:1E:AF:FE
-#define CONFIG_HAS_ETH1
-#define CONFIG_ETH1ADDR 00:50:C2:1E:AF:FD
-
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
-
-
-#define CONFIG_PPC4xx_EMAC
-#undef CONFIG_EXT_PHY
-
-#define CONFIG_MII 1 /* MII PHY management */
-#ifndef CONFIG_EXT_PHY
-#define CONFIG_PHY_ADDR 1 /* EMAC0 PHY address */
-#define CONFIG_PHY1_ADDR 16 /* EMAC1 PHY address */
-#else
-#define CONFIG_PHY_ADDR 2 /* PHY address */
-#endif
-#define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ
-
-#define CONFIG_TIMESTAMP /* Print image info with timestamp */
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_ELF
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_IRQ
-#define CONFIG_CMD_JFFS2
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_NAND
-#define CONFIG_CMD_NFS
-#define CONFIG_CMD_SNTP
-
-
-#define CONFIG_MAC_PARTITION
-#define CONFIG_DOS_PARTITION
-
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-
-#define CONFIG_RTC_MC146818 /* DS1685 is MC146818 compatible*/
-#define CONFIG_SYS_RTC_REG_BASE_ADDR 0xF0000500 /* RTC Base Address */
-
-#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-
-#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */
-
-#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/
-
-#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
-
-#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */
-#define CONFIG_SYS_BASE_BAUD 691200
-
-/* The following table includes the supported baudrates */
-#define CONFIG_SYS_BAUDRATE_TABLE \
- { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
- 57600, 115200, 230400, 460800, 921600 }
-
-#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
-#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
-
-#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
-
-/*-----------------------------------------------------------------------
- * NAND-FLASH stuff
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_NAND0_BASE 0xFF400000
-#define CONFIG_SYS_NAND1_BASE 0xFF000000
-#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND0_BASE }
-#define NAND_BIG_DELAY_US 25
-
-/* For CATcenter there is only NAND on the module */
-#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
-#define NAND_NO_RB
-
-#define CONFIG_SYS_NAND0_CE (0x80000000 >> 1) /* our CE is GPIO1 */
-#define CONFIG_SYS_NAND0_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */
-#define CONFIG_SYS_NAND0_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */
-#define CONFIG_SYS_NAND0_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */
-
-#define CONFIG_SYS_NAND1_CE (0x80000000 >> 14) /* our CE is GPIO14 */
-#define CONFIG_SYS_NAND1_CLE (0x80000000 >> 15) /* our CLE is GPIO15 */
-#define CONFIG_SYS_NAND1_ALE (0x80000000 >> 16) /* our ALE is GPIO16 */
-#define CONFIG_SYS_NAND1_RDY (0x80000000 >> 31) /* our RDY is GPIO31 */
-
-
-#define MACRO_NAND_DISABLE_CE(nandptr) do \
-{ \
- switch((unsigned long)nandptr) \
- { \
- case CONFIG_SYS_NAND0_BASE: \
- out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND0_CE); \
- break; \
- case CONFIG_SYS_NAND1_BASE: \
- out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND1_CE); \
- break; \
- } \
-} while(0)
-
-#define MACRO_NAND_ENABLE_CE(nandptr) do \
-{ \
- switch((unsigned long)nandptr) \
- { \
- case CONFIG_SYS_NAND0_BASE: \
- out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_NAND0_CE); \
- break; \
- case CONFIG_SYS_NAND1_BASE: \
- out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_NAND1_CE); \
- break; \
- } \
-} while(0)
-
-#define MACRO_NAND_CTL_CLRALE(nandptr) do \
-{ \
- switch((unsigned long)nandptr) \
- { \
- case CONFIG_SYS_NAND0_BASE: \
- out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_NAND0_ALE); \
- break; \
- case CONFIG_SYS_NAND1_BASE: \
- out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_NAND1_ALE); \
- break; \
- } \
-} while(0)
-
-#define MACRO_NAND_CTL_SETALE(nandptr) do \
-{ \
- switch((unsigned long)nandptr) \
- { \
- case CONFIG_SYS_NAND0_BASE: \
- out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND0_ALE); \
- break; \
- case CONFIG_SYS_NAND1_BASE: \
- out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND1_ALE); \
- break; \
- } \
-} while(0)
-
-#define MACRO_NAND_CTL_CLRCLE(nandptr) do \
-{ \
- switch((unsigned long)nandptr) \
- { \
- case CONFIG_SYS_NAND0_BASE: \
- out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_NAND0_CLE); \
- break; \
- case CONFIG_SYS_NAND1_BASE: \
- out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_NAND1_CLE); \
- break; \
- } \
-} while(0)
-
-#define MACRO_NAND_CTL_SETCLE(nandptr) do { \
- switch((unsigned long)nandptr) { \
- case CONFIG_SYS_NAND0_BASE: \
- out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND0_CLE); \
- break; \
- case CONFIG_SYS_NAND1_BASE: \
- out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND1_CLE); \
- break; \
- } \
-} while(0)
-
-#ifdef NAND_NO_RB
-/* constant delay (see also tR in the datasheet) */
-#define NAND_WAIT_READY(nand) do { \
- udelay(12); \
-} while (0)
-#else
-/* use the R/B pin */
-/* TBD */
-#endif
-
-#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
-#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
-#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0)
-#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr))
-
-/*-----------------------------------------------------------------------
- * PCI stuff
- *-----------------------------------------------------------------------
- */
-#if 0 /* No PCI on CATcenter */
-#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
-#define PCI_HOST_FORCE 1 /* configure as pci host */
-#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
-
-#define CONFIG_PCI /* include pci support */
-#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
-#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */
-#undef CONFIG_PCI_PNP /* do pci plug-and-play */
- /* resource configuration */
-
-#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */
-
-#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1014 /* PCI Vendor ID: IBM */
-#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0000 /* PCI Device ID: --- */
-#define CONFIG_SYS_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/
-
-#define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */
-#define CONFIG_SYS_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */
-#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
-#define CONFIG_SYS_PCI_PTM2LA 0xffc00000 /* point to flash */
-#define CONFIG_SYS_PCI_PTM2MS 0xffc00001 /* 4MB, enable */
-#define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
-#endif /* No PCI */
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_FLASH_BASE 0xFFFC0000
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */
-#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */
-
-#define CONFIG_SYS_FLASH_WORD_SIZE unsigned short /* flash word size (width) */
-#define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */
-#define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */
-/*
- * The following defines are added for buggy IOP480 byte interface.
- * All other boards should use the standard values (CPCI405 etc.)
- */
-#define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */
-#define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */
-#define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */
-
-#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
-
-/*-----------------------------------------------------------------------
- * Environment Variable setup
- */
-#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
-#define CONFIG_ENV_ADDR 0xFFFF8000 /* environment starts@the first small sector */
-#define CONFIG_ENV_SECT_SIZE 0x2000 /* 8196 bytes may be used for env vars*/
-#define CONFIG_ENV_ADDR_REDUND 0xFFFFA000
-#define CONFIG_ENV_SIZE_REDUND 0x2000
-
-#define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */
-
-#define CONFIG_SYS_NVRAM_BASE_ADDR 0xF0000500 /* NVRAM base address */
-#define CONFIG_SYS_NVRAM_SIZE 242 /* NVRAM size */
-
-/*-----------------------------------------------------------------------
- * I2C EEPROM (CAT24WC16) for environment
- */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_PPC4XX
-#define CONFIG_SYS_I2C_PPC4XX_CH0
-#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
-#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
-
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
-/* mask of address bits that overflow into the "EEPROM chip address" */
-/*#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07*/
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */
- /* 16 byte page write mode using*/
- /* last 4 bits of the address */
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
-
-/*
- * Init Memory Controller:
- *
- * BR0/1 and OR0/1 (FLASH)
- */
-
-#define FLASH_BASE0_PRELIM 0xFFC00000 /* FLASH bank #0 */
-
-/*-----------------------------------------------------------------------
- * External Bus Controller (EBC) Setup
- */
-
-/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */
-#define CONFIG_SYS_EBC_PB0AP 0x92015480
-#define CONFIG_SYS_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
-
-/* Memory Bank 1 (External SRAM) initialization */
-/* Since this must replace NOR Flash, we use the same settings for CS0 */
-#define CONFIG_SYS_EBC_PB1AP 0x92015480
-#define CONFIG_SYS_EBC_PB1CR 0xFF85A000 /* BAS=0xFF8,BS=4MB,BU=R/W,BW=8bit */
-
-/* Memory Bank 2 (Flash Bank 1, NAND-FLASH) initialization */
-#define CONFIG_SYS_EBC_PB2AP 0x92015480
-#define CONFIG_SYS_EBC_PB2CR 0xFF458000 /* BAS=0xFF4,BS=4MB,BU=R/W,BW=8bit */
-
-/* Memory Bank 3 (Flash Bank 2, NAND-FLASH) initialization */
-#define CONFIG_SYS_EBC_PB3AP 0x92015480
-#define CONFIG_SYS_EBC_PB3CR 0xFF058000 /* BAS=0xFF0,BS=4MB,BU=R/W,BW=8bit */
-
-#ifdef CONFIG_PPCHAMELEON_SMI712
-/*
- * Video console (graphic: SMI LynxEM)
- */
-#define CONFIG_VIDEO
-#define CONFIG_CFB_CONSOLE
-#define CONFIG_VIDEO_SMI_LYNXEM
-#define CONFIG_VIDEO_LOGO
-/*#define CONFIG_VIDEO_BMP_LOGO*/
-#define CONFIG_CONSOLE_EXTRA_INFO
-#define CONFIG_VGA_AS_SINGLE_DEVICE
-/* This is the base address (on 405EP-side) used to generate I/O accesses on PCI bus */
-#define CONFIG_SYS_ISA_IO 0xE8000000
-/* see also drivers/video/videomodes.c */
-#define CONFIG_SYS_DEFAULT_VIDEO_MODE 0x303
-#endif
-
-/*-----------------------------------------------------------------------
- * FPGA stuff
- */
-/* FPGA internal regs */
-#define CONFIG_SYS_FPGA_MODE 0x00
-#define CONFIG_SYS_FPGA_STATUS 0x02
-#define CONFIG_SYS_FPGA_TS 0x04
-#define CONFIG_SYS_FPGA_TS_LOW 0x06
-#define CONFIG_SYS_FPGA_TS_CAP0 0x10
-#define CONFIG_SYS_FPGA_TS_CAP0_LOW 0x12
-#define CONFIG_SYS_FPGA_TS_CAP1 0x14
-#define CONFIG_SYS_FPGA_TS_CAP1_LOW 0x16
-#define CONFIG_SYS_FPGA_TS_CAP2 0x18
-#define CONFIG_SYS_FPGA_TS_CAP2_LOW 0x1a
-#define CONFIG_SYS_FPGA_TS_CAP3 0x1c
-#define CONFIG_SYS_FPGA_TS_CAP3_LOW 0x1e
-
-/* FPGA Mode Reg */
-#define CONFIG_SYS_FPGA_MODE_CF_RESET 0x0001
-#define CONFIG_SYS_FPGA_MODE_TS_IRQ_ENABLE 0x0100
-#define CONFIG_SYS_FPGA_MODE_TS_IRQ_CLEAR 0x1000
-#define CONFIG_SYS_FPGA_MODE_TS_CLEAR 0x2000
-
-/* FPGA Status Reg */
-#define CONFIG_SYS_FPGA_STATUS_DIP0 0x0001
-#define CONFIG_SYS_FPGA_STATUS_DIP1 0x0002
-#define CONFIG_SYS_FPGA_STATUS_DIP2 0x0004
-#define CONFIG_SYS_FPGA_STATUS_FLASH 0x0008
-#define CONFIG_SYS_FPGA_STATUS_TS_IRQ 0x1000
-
-#define CONFIG_SYS_FPGA_SPARTAN2 1 /* using Xilinx Spartan 2 now */
-#define CONFIG_SYS_FPGA_MAX_SIZE 128*1024 /* 128kByte is enough for XC2S50E*/
-
-/* FPGA program pin configuration */
-#define CONFIG_SYS_FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */
-#define CONFIG_SYS_FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */
-#define CONFIG_SYS_FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */
-#define CONFIG_SYS_FPGA_INIT 0x00010000 /* FPGA init pin (ppc input) */
-#define CONFIG_SYS_FPGA_DONE 0x00008000 /* FPGA done pin (ppc input) */
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in data cache)
- */
-/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
-#define CONFIG_SYS_TEMP_STACK_OCM 1
-
-/* On Chip Memory location */
-#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
-#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
-#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */
-#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */
-
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Definitions for GPIO setup (PPC405EP specific)
- *
- * GPIO0[0] - External Bus Controller BLAST output
- * GPIO0[1-9] - Instruction trace outputs -> GPIO
- * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
- * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO
- * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
- * GPIO0[24-27] - UART0 control signal inputs/outputs
- * GPIO0[28-29] - UART1 data signal input/output
- * GPIO0[30] - EMAC0 input
- * GPIO0[31] - EMAC1 reject packet as output
- */
-#define CONFIG_SYS_GPIO0_OSRL 0x40000550
-#define CONFIG_SYS_GPIO0_OSRH 0x00000110
-#define CONFIG_SYS_GPIO0_ISR1L 0x00000000
-/*#define CONFIG_SYS_GPIO0_ISR1H 0x15555445*/
-#define CONFIG_SYS_GPIO0_ISR1H 0x15555444
-#define CONFIG_SYS_GPIO0_TSRL 0x00000000
-#define CONFIG_SYS_GPIO0_TSRH 0x00000000
-#define CONFIG_SYS_GPIO0_TCR 0xF7FF8014
-
-#define CONFIG_NO_SERIAL_EEPROM
-
-/*--------------------------------------------------------------------*/
-
-#ifdef CONFIG_NO_SERIAL_EEPROM
-
-/*
-!-----------------------------------------------------------------------
-! Defines for entry options.
-! Note: Because the 405EP SDRAM controller does not support ECC, ECC DIMMs that
-! are plugged in the board will be utilized as non-ECC DIMMs.
-!-----------------------------------------------------------------------
-*/
-#undef AUTO_MEMORY_CONFIG
-#define DIMM_READ_ADDR 0xAB
-#define DIMM_WRITE_ADDR 0xAA
-
-/* Defines for CPC0_PLLMR1 Register fields */
-#define PLL_ACTIVE 0x80000000
-#define CPC0_PLLMR1_SSCS 0x80000000
-#define PLL_RESET 0x40000000
-#define CPC0_PLLMR1_PLLR 0x40000000
- /* Feedback multiplier */
-#define PLL_FBKDIV 0x00F00000
-#define CPC0_PLLMR1_FBDV 0x00F00000
-#define PLL_FBKDIV_16 0x00000000
-#define PLL_FBKDIV_1 0x00100000
-#define PLL_FBKDIV_2 0x00200000
-#define PLL_FBKDIV_3 0x00300000
-#define PLL_FBKDIV_4 0x00400000
-#define PLL_FBKDIV_5 0x00500000
-#define PLL_FBKDIV_6 0x00600000
-#define PLL_FBKDIV_7 0x00700000
-#define PLL_FBKDIV_8 0x00800000
-#define PLL_FBKDIV_9 0x00900000
-#define PLL_FBKDIV_10 0x00A00000
-#define PLL_FBKDIV_11 0x00B00000
-#define PLL_FBKDIV_12 0x00C00000
-#define PLL_FBKDIV_13 0x00D00000
-#define PLL_FBKDIV_14 0x00E00000
-#define PLL_FBKDIV_15 0x00F00000
- /* Forward A divisor */
-#define PLL_FWDDIVA 0x00070000
-#define CPC0_PLLMR1_FWDVA 0x00070000
-#define PLL_FWDDIVA_8 0x00000000
-#define PLL_FWDDIVA_7 0x00010000
-#define PLL_FWDDIVA_6 0x00020000
-#define PLL_FWDDIVA_5 0x00030000
-#define PLL_FWDDIVA_4 0x00040000
-#define PLL_FWDDIVA_3 0x00050000
-#define PLL_FWDDIVA_2 0x00060000
-#define PLL_FWDDIVA_1 0x00070000
- /* Forward B divisor */
-#define PLL_FWDDIVB 0x00007000
-#define CPC0_PLLMR1_FWDVB 0x00007000
-#define PLL_FWDDIVB_8 0x00000000
-#define PLL_FWDDIVB_7 0x00001000
-#define PLL_FWDDIVB_6 0x00002000
-#define PLL_FWDDIVB_5 0x00003000
-#define PLL_FWDDIVB_4 0x00004000
-#define PLL_FWDDIVB_3 0x00005000
-#define PLL_FWDDIVB_2 0x00006000
-#define PLL_FWDDIVB_1 0x00007000
- /* PLL tune bits */
-#define PLL_TUNE_MASK 0x000003FF
-#define PLL_TUNE_2_M_3 0x00000133 /* 2 <= M <= 3 */
-#define PLL_TUNE_4_M_6 0x00000134 /* 3 < M <= 6 */
-#define PLL_TUNE_7_M_10 0x00000138 /* 6 < M <= 10 */
-#define PLL_TUNE_11_M_14 0x0000013C /* 10 < M <= 14 */
-#define PLL_TUNE_15_M_40 0x0000023E /* 14 < M <= 40 */
-#define PLL_TUNE_VCO_LOW 0x00000000 /* 500MHz <= VCO <= 800MHz */
-#define PLL_TUNE_VCO_HI 0x00000080 /* 800MHz < VCO <= 1000MHz */
-
-/* Defines for CPC0_PLLMR0 Register fields */
- /* CPU divisor */
-#define PLL_CPUDIV 0x00300000
-#define CPC0_PLLMR0_CCDV 0x00300000
-#define PLL_CPUDIV_1 0x00000000
-#define PLL_CPUDIV_2 0x00100000
-#define PLL_CPUDIV_3 0x00200000
-#define PLL_CPUDIV_4 0x00300000
- /* PLB divisor */
-#define PLL_PLBDIV 0x00030000
-#define CPC0_PLLMR0_CBDV 0x00030000
-#define PLL_PLBDIV_1 0x00000000
-#define PLL_PLBDIV_2 0x00010000
-#define PLL_PLBDIV_3 0x00020000
-#define PLL_PLBDIV_4 0x00030000
- /* OPB divisor */
-#define PLL_OPBDIV 0x00003000
-#define CPC0_PLLMR0_OPDV 0x00003000
-#define PLL_OPBDIV_1 0x00000000
-#define PLL_OPBDIV_2 0x00001000
-#define PLL_OPBDIV_3 0x00002000
-#define PLL_OPBDIV_4 0x00003000
- /* EBC divisor */
-#define PLL_EXTBUSDIV 0x00000300
-#define CPC0_PLLMR0_EPDV 0x00000300
-#define PLL_EXTBUSDIV_2 0x00000000
-#define PLL_EXTBUSDIV_3 0x00000100
-#define PLL_EXTBUSDIV_4 0x00000200
-#define PLL_EXTBUSDIV_5 0x00000300
- /* MAL divisor */
-#define PLL_MALDIV 0x00000030
-#define CPC0_PLLMR0_MPDV 0x00000030
-#define PLL_MALDIV_1 0x00000000
-#define PLL_MALDIV_2 0x00000010
-#define PLL_MALDIV_3 0x00000020
-#define PLL_MALDIV_4 0x00000030
- /* PCI divisor */
-#define PLL_PCIDIV 0x00000003
-#define CPC0_PLLMR0_PPFD 0x00000003
-#define PLL_PCIDIV_1 0x00000000
-#define PLL_PCIDIV_2 0x00000001
-#define PLL_PCIDIV_3 0x00000002
-#define PLL_PCIDIV_4 0x00000003
-
-#ifdef CONFIG_PPCHAMELEON_CLK_25
-/* CPU - PLB/SDRAM - EBC - OPB - PCI (assuming a 25.0 MHz input clock to the 405EP) */
-#define PPCHAMELEON_PLLMR0_133_133_33_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_1 | \
- PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \
- PLL_MALDIV_1 | PLL_PCIDIV_4)
-#define PPCHAMELEON_PLLMR1_133_133_33_66_33 (PLL_FBKDIV_8 | \
- PLL_FWDDIVA_6 | PLL_FWDDIVB_4 | \
- PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
-
-#define PPCHAMELEON_PLLMR0_200_100_50_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \
- PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \
- PLL_MALDIV_1 | PLL_PCIDIV_4)
-#define PPCHAMELEON_PLLMR1_200_100_50_33 (PLL_FBKDIV_8 | \
- PLL_FWDDIVA_4 | PLL_FWDDIVB_4 | \
- PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
-
-#define PPCHAMELEON_PLLMR0_266_133_33_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \
- PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \
- PLL_MALDIV_1 | PLL_PCIDIV_4)
-#define PPCHAMELEON_PLLMR1_266_133_33_66_33 (PLL_FBKDIV_8 | \
- PLL_FWDDIVA_3 | PLL_FWDDIVB_4 | \
- PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
-
-#define PPCHAMELEON_PLLMR0_333_111_37_55_55 (PLL_CPUDIV_1 | PLL_PLBDIV_3 | \
- PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \
- PLL_MALDIV_1 | PLL_PCIDIV_2)
-#define PPCHAMELEON_PLLMR1_333_111_37_55_55 (PLL_FBKDIV_10 | \
- PLL_FWDDIVA_3 | PLL_FWDDIVB_4 | \
- PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI)
-
-#elif (defined (CONFIG_PPCHAMELEON_CLK_33))
-
-/* CPU - PLB/SDRAM - EBC - OPB - PCI (assuming a 33.3MHz input clock to the 405EP) */
-#define PPCHAMELEON_PLLMR0_133_133_33_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_1 | \
- PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \
- PLL_MALDIV_1 | PLL_PCIDIV_4)
-#define PPCHAMELEON_PLLMR1_133_133_33_66_33 (PLL_FBKDIV_4 | \
- PLL_FWDDIVA_6 | PLL_FWDDIVB_6 | \
- PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
-
-#define PPCHAMELEON_PLLMR0_200_100_50_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \
- PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \
- PLL_MALDIV_1 | PLL_PCIDIV_4)
-#define PPCHAMELEON_PLLMR1_200_100_50_33 (PLL_FBKDIV_6 | \
- PLL_FWDDIVA_4 | PLL_FWDDIVB_4 | \
- PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
-
-#define PPCHAMELEON_PLLMR0_266_133_33_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \
- PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \
- PLL_MALDIV_1 | PLL_PCIDIV_4)
-#define PPCHAMELEON_PLLMR1_266_133_33_66_33 (PLL_FBKDIV_8 | \
- PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
- PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
-
-#define PPCHAMELEON_PLLMR0_333_111_37_55_55 (PLL_CPUDIV_1 | PLL_PLBDIV_3 | \
- PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \
- PLL_MALDIV_1 | PLL_PCIDIV_2)
-#define PPCHAMELEON_PLLMR1_333_111_37_55_55 (PLL_FBKDIV_10 | \
- PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
- PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI)
-
-#else
-#error "* External frequency (SysClk) not defined! *"
-#endif
-
-#if (CONFIG_PPCHAMELEON_MODULE_MODEL == CONFIG_PPCHAMELEON_MODULE_HI)
-/* Model HI */
-#define PLLMR0_DEFAULT PPCHAMELEON_PLLMR0_333_111_37_55_55
-#define PLLMR1_DEFAULT PPCHAMELEON_PLLMR1_333_111_37_55_55
-#define CONFIG_SYS_OPB_FREQ 55555555
-/* Model ME */
-#elif (CONFIG_PPCHAMELEON_MODULE_MODEL == CONFIG_PPCHAMELEON_MODULE_ME)
-#define PLLMR0_DEFAULT PPCHAMELEON_PLLMR0_266_133_33_66_33
-#define PLLMR1_DEFAULT PPCHAMELEON_PLLMR1_266_133_33_66_33
-#define CONFIG_SYS_OPB_FREQ 66666666
-#else
-/* Model BA (default) */
-#define PLLMR0_DEFAULT PPCHAMELEON_PLLMR0_133_133_33_66_33
-#define PLLMR1_DEFAULT PPCHAMELEON_PLLMR1_133_133_33_66_33
-#define CONFIG_SYS_OPB_FREQ 66666666
-#endif
-
-#endif /* CONFIG_NO_SERIAL_EEPROM */
-
-#define CONFIG_JFFS2_NAND 1 /* jffs2 on nand support */
-#define NAND_CACHE_PAGES 16 /* size of nand cache in 512 bytes pages */
-
-/*
- * JFFS2 partitions
- *
- */
-/* No command line, one static partition */
-#undef CONFIG_CMD_MTDPARTS
-#define CONFIG_JFFS2_DEV "nand"
-#define CONFIG_JFFS2_PART_SIZE 0x00200000
-#define CONFIG_JFFS2_PART_OFFSET 0x00000000
-
-/* mtdparts command line support
- *
- * Note: fake mtd_id used, no linux mtd map file
- */
-/*
-#define CONFIG_CMD_MTDPARTS
-#define MTDIDS_DEFAULT "nand0=catcenter"
-#define MTDPARTS_DEFAULT "mtdparts=catcenter:2m(nand)"
-*/
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/PPChameleonEVB.h b/include/configs/PPChameleonEVB.h
deleted file mode 100644
index e277d0d..0000000
--- a/include/configs/PPChameleonEVB.h
+++ /dev/null
@@ -1,777 +0,0 @@
-/*
- * (C) Copyright 2003-2005
- * Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
- *
- * (C) Copyright 2003
- * DAVE Srl
- *
- * http://www.dave-tech.it
- * http://www.wawnet.biz
- * mailto:info at wawnet.biz
- *
- * Credits: Stefan Roese, Wolfgang Denk
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#define CONFIG_PPCHAMELEON_MODULE_BA 0 /* Basic Model */
-#define CONFIG_PPCHAMELEON_MODULE_ME 1 /* Medium Model */
-#define CONFIG_PPCHAMELEON_MODULE_HI 2 /* High-End Model */
-#ifndef CONFIG_PPCHAMELEON_MODULE_MODEL
-#define CONFIG_PPCHAMELEON_MODULE_MODEL CONFIG_PPCHAMELEON_MODULE_BA
-#endif
-
-
-/* Only one of the following two symbols must be defined (default is 25 MHz)
- * CONFIG_PPCHAMELEON_CLK_25
- * CONFIG_PPCHAMELEON_CLK_33
- */
-#if (!defined(CONFIG_PPCHAMELEON_CLK_25) && !defined(CONFIG_PPCHAMELEON_CLK_33))
-#define CONFIG_PPCHAMELEON_CLK_25
-#endif
-
-#if (defined(CONFIG_PPCHAMELEON_CLK_25) && defined(CONFIG_PPCHAMELEON_CLK_33))
-#error "* Two external frequencies (SysClk) are defined! *"
-#endif
-
-#undef CONFIG_PPCHAMELEON_SMI712
-
-/*
- * Debug stuff
- */
-#undef __DEBUG_START_FROM_SRAM__
-#define __DISABLE_MACHINE_EXCEPTION__
-
-#ifdef __DEBUG_START_FROM_SRAM__
-#define CONFIG_SYS_DUMMY_FLASH_SIZE 1024*1024*4
-#endif
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_405EP 1 /* This is a PPC405 CPU */
-#define CONFIG_PPCHAMELEONEVB 1 /* ...on a PPChameleonEVB board */
-
-#define CONFIG_SYS_TEXT_BASE 0xFFFB0000 /* Reserve 320 kB for Monitor */
-#define CONFIG_SYS_LDSCRIPT "board/dave/PPChameleonEVB/u-boot.lds"
-
-#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
-#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
-
-
-#ifdef CONFIG_PPCHAMELEON_CLK_25
-# define CONFIG_SYS_CLK_FREQ 25000000 /* external frequency to pll */
-#elif (defined (CONFIG_PPCHAMELEON_CLK_33))
-# define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
-#else
-# error "* External frequency (SysClk) not defined! *"
-#endif
-
-#define CONFIG_BAUDRATE 115200
-#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
-
-#undef CONFIG_BOOTARGS
-
-/* Ethernet stuff */
-#define CONFIG_ENV_OVERWRITE /* Let the user to change the Ethernet MAC addresses */
-#define CONFIG_ETHADDR 00:50:c2:1e:af:fe
-#define CONFIG_HAS_ETH1
-#define CONFIG_ETH1ADDR 00:50:c2:1e:af:fd
-
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
-
-#undef CONFIG_EXT_PHY
-
-#define CONFIG_PPC4xx_EMAC
-#define CONFIG_MII 1 /* MII PHY management */
-#ifndef CONFIG_EXT_PHY
-#define CONFIG_PHY_ADDR 1 /* EMAC0 PHY address */
-#define CONFIG_PHY1_ADDR 2 /* EMAC1 PHY address */
-#else
-#define CONFIG_PHY_ADDR 2 /* PHY address */
-#endif
-#define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_DATE
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_ELF
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_IRQ
-#define CONFIG_CMD_JFFS2
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_NAND
-#define CONFIG_CMD_NFS
-#define CONFIG_CMD_PCI
-#define CONFIG_CMD_SNTP
-
-
-#define CONFIG_MAC_PARTITION
-#define CONFIG_DOS_PARTITION
-
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-
-#define CONFIG_RTC_M41T11 1 /* uses a M41T00 RTC */
-#define CONFIG_SYS_I2C_RTC_ADDR 0x68
-#define CONFIG_SYS_M41T11_BASE_YEAR 1900
-
-/*
- * SDRAM configuration (please see cpu/ppc/sdram.[ch])
- */
-#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
-
-/* SDRAM timings used in datasheet */
-#define CONFIG_SYS_SDRAM_CL 2
-#define CONFIG_SYS_SDRAM_tRP 20
-#define CONFIG_SYS_SDRAM_tRC 65
-#define CONFIG_SYS_SDRAM_tRCD 20
-#undef CONFIG_SYS_SDRAM_tRFC
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-
-#undef CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */
-
-#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/
-
-#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
-
-#define CONFIG_CONS_INDEX 1 /* Use UART0 */
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-#define CONFIG_SYS_NS16550_CLK get_serial_clock()
-
-#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */
-#define CONFIG_SYS_BASE_BAUD 691200
-
-/* The following table includes the supported baudrates */
-#define CONFIG_SYS_BAUDRATE_TABLE \
- { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
- 57600, 115200, 230400, 460800, 921600 }
-
-#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
-#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
-
-#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
-
-/*-----------------------------------------------------------------------
- * NAND-FLASH stuff
- *-----------------------------------------------------------------------
- */
-
-/*
- * nand device 1 on dave (PPChameleonEVB) needs more time,
- * so we just introduce additional wait in nand_wait(),
- * effectively for both devices.
- */
-#define PPCHAMELON_NAND_TIMER_HACK
-
-#define CONFIG_SYS_NAND0_BASE 0xFF400000
-#define CONFIG_SYS_NAND1_BASE 0xFF000000
-#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND0_BASE, CONFIG_SYS_NAND1_BASE }
-#define NAND_BIG_DELAY_US 25
-#define CONFIG_SYS_MAX_NAND_DEVICE 2 /* Max number of NAND devices */
-
-#define CONFIG_SYS_NAND0_CE (0x80000000 >> 1) /* our CE is GPIO1 */
-#define CONFIG_SYS_NAND0_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */
-#define CONFIG_SYS_NAND0_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */
-#define CONFIG_SYS_NAND0_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */
-
-#define CONFIG_SYS_NAND1_CE (0x80000000 >> 14) /* our CE is GPIO14 */
-#define CONFIG_SYS_NAND1_RDY (0x80000000 >> 31) /* our RDY is GPIO31 */
-#define CONFIG_SYS_NAND1_CLE (0x80000000 >> 15) /* our CLE is GPIO15 */
-#define CONFIG_SYS_NAND1_ALE (0x80000000 >> 16) /* our ALE is GPIO16 */
-
-#define MACRO_NAND_DISABLE_CE(nandptr) do \
-{ \
- switch((unsigned long)nandptr) \
- { \
- case CONFIG_SYS_NAND0_BASE: \
- out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND0_CE); \
- break; \
- case CONFIG_SYS_NAND1_BASE: \
- out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND1_CE); \
- break; \
- } \
-} while(0)
-
-#define MACRO_NAND_ENABLE_CE(nandptr) do \
-{ \
- switch((unsigned long)nandptr) \
- { \
- case CONFIG_SYS_NAND0_BASE: \
- out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_NAND0_CE); \
- break; \
- case CONFIG_SYS_NAND1_BASE: \
- out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_NAND1_CE); \
- break; \
- } \
-} while(0)
-
-#define MACRO_NAND_CTL_CLRALE(nandptr) do \
-{ \
- switch((unsigned long)nandptr) \
- { \
- case CONFIG_SYS_NAND0_BASE: \
- out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_NAND0_ALE); \
- break; \
- case CONFIG_SYS_NAND1_BASE: \
- out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_NAND1_ALE); \
- break; \
- } \
-} while(0)
-
-#define MACRO_NAND_CTL_SETALE(nandptr) do \
-{ \
- switch((unsigned long)nandptr) \
- { \
- case CONFIG_SYS_NAND0_BASE: \
- out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND0_ALE); \
- break; \
- case CONFIG_SYS_NAND1_BASE: \
- out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND1_ALE); \
- break; \
- } \
-} while(0)
-
-#define MACRO_NAND_CTL_CLRCLE(nandptr) do \
-{ \
- switch((unsigned long)nandptr) \
- { \
- case CONFIG_SYS_NAND0_BASE: \
- out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_NAND0_CLE); \
- break; \
- case CONFIG_SYS_NAND1_BASE: \
- out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_NAND1_CLE); \
- break; \
- } \
-} while(0)
-
-#define MACRO_NAND_CTL_SETCLE(nandptr) do { \
- switch((unsigned long)nandptr) { \
- case CONFIG_SYS_NAND0_BASE: \
- out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND0_CLE); \
- break; \
- case CONFIG_SYS_NAND1_BASE: \
- out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND1_CLE); \
- break; \
- } \
-} while(0)
-
-/*-----------------------------------------------------------------------
- * PCI stuff
- *-----------------------------------------------------------------------
- */
-#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
-#define PCI_HOST_FORCE 1 /* configure as pci host */
-#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
-
-#define CONFIG_PCI /* include pci support */
-#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
-#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */
-#undef CONFIG_PCI_PNP /* do pci plug-and-play */
- /* resource configuration */
-
-#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */
-
-#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1014 /* PCI Vendor ID: IBM */
-#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0000 /* PCI Device ID: --- */
-#define CONFIG_SYS_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/
-
-#define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */
-#define CONFIG_SYS_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */
-#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
-#define CONFIG_SYS_PCI_PTM2LA 0xffc00000 /* point to flash */
-#define CONFIG_SYS_PCI_PTM2MS 0xffc00001 /* 4MB, enable */
-#define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-
-/* Reserve 256 kB for Monitor */
-/*
-#define CONFIG_SYS_FLASH_BASE 0xFFFC0000
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
-*/
-
-/* Reserve 320 kB for Monitor */
-#define CONFIG_SYS_FLASH_BASE 0xFFFB0000
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_MONITOR_LEN (320 * 1024)
-
-#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */
-
-#define CONFIG_SYS_FLASH_WORD_SIZE unsigned short /* flash word size (width) */
-#define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */
-#define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */
-/*
- * The following defines are added for buggy IOP480 byte interface.
- * All other boards should use the standard values (CPCI405 etc.)
- */
-#define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */
-#define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */
-#define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */
-
-#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
-
-/*-----------------------------------------------------------------------
- * Environment Variable setup
- */
-#ifdef ENVIRONMENT_IN_EEPROM
-
-#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
-#define CONFIG_ENV_OFFSET 0x100 /* environment starts at the beginning of the EEPROM */
-#define CONFIG_ENV_SIZE 0x700 /* 2048-256 bytes may be used for env vars (total size of a CAT24WC16 is 2048 bytes)*/
-
-#else /* DEFAULT: environment in flash, using redundand flash sectors */
-
-#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
-#define CONFIG_ENV_ADDR 0xFFFF8000 /* environment starts@the first small sector */
-#define CONFIG_ENV_SECT_SIZE 0x2000 /* 8196 bytes may be used for env vars*/
-#define CONFIG_ENV_ADDR_REDUND 0xFFFFA000
-#define CONFIG_ENV_SIZE_REDUND 0x2000
-
-#define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */
-
-#endif /* ENVIRONMENT_IN_EEPROM */
-
-
-#define CONFIG_SYS_NVRAM_BASE_ADDR 0xF0000500 /* NVRAM base address */
-#define CONFIG_SYS_NVRAM_SIZE 242 /* NVRAM size */
-
-/*-----------------------------------------------------------------------
- * I2C EEPROM (CAT24WC16) for environment
- */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_PPC4XX
-#define CONFIG_SYS_I2C_PPC4XX_CH0
-#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
-#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
-
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
-/* mask of address bits that overflow into the "EEPROM chip address" */
-/*#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07*/
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */
- /* 16 byte page write mode using*/
- /* last 4 bits of the address */
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
-
-/*
- * Init Memory Controller:
- *
- * BR0/1 and OR0/1 (FLASH)
- */
-
-#define FLASH_BASE0_PRELIM 0xFFC00000 /* FLASH bank #0 */
-
-/*-----------------------------------------------------------------------
- * External Bus Controller (EBC) Setup
- */
-
-/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */
-#define CONFIG_SYS_EBC_PB0AP 0x92015480
-#define CONFIG_SYS_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
-
-/* Memory Bank 1 (External SRAM) initialization */
-/* Since this must replace NOR Flash, we use the same settings for CS0 */
-#define CONFIG_SYS_EBC_PB1AP 0x92015480
-#define CONFIG_SYS_EBC_PB1CR 0xFF85A000 /* BAS=0xFF8,BS=4MB,BU=R/W,BW=8bit */
-
-/* Memory Bank 2 (Flash Bank 1, NAND-FLASH) initialization */
-#define CONFIG_SYS_EBC_PB2AP 0x92015480
-#define CONFIG_SYS_EBC_PB2CR 0xFF458000 /* BAS=0xFF4,BS=4MB,BU=R/W,BW=8bit */
-
-/* Memory Bank 3 (Flash Bank 2, NAND-FLASH) initialization */
-#define CONFIG_SYS_EBC_PB3AP 0x92015480
-#define CONFIG_SYS_EBC_PB3CR 0xFF058000 /* BAS=0xFF0,BS=4MB,BU=R/W,BW=8bit */
-
-#ifdef CONFIG_PPCHAMELEON_SMI712
-/*
- * Video console (graphic: SMI LynxEM)
- */
-#define CONFIG_VIDEO
-#define CONFIG_CFB_CONSOLE
-#define CONFIG_VIDEO_SMI_LYNXEM
-#define CONFIG_VIDEO_LOGO
-/*#define CONFIG_VIDEO_BMP_LOGO*/
-#define CONFIG_CONSOLE_EXTRA_INFO
-#define CONFIG_VGA_AS_SINGLE_DEVICE
-/* This is the base address (on 405EP-side) used to generate I/O accesses on PCI bus */
-#define CONFIG_SYS_ISA_IO 0xE8000000
-/* see also drivers/video/videomodes.c */
-#define CONFIG_SYS_DEFAULT_VIDEO_MODE 0x303
-#endif
-
-/*-----------------------------------------------------------------------
- * FPGA stuff
- */
-/* FPGA internal regs */
-#define CONFIG_SYS_FPGA_MODE 0x00
-#define CONFIG_SYS_FPGA_STATUS 0x02
-#define CONFIG_SYS_FPGA_TS 0x04
-#define CONFIG_SYS_FPGA_TS_LOW 0x06
-#define CONFIG_SYS_FPGA_TS_CAP0 0x10
-#define CONFIG_SYS_FPGA_TS_CAP0_LOW 0x12
-#define CONFIG_SYS_FPGA_TS_CAP1 0x14
-#define CONFIG_SYS_FPGA_TS_CAP1_LOW 0x16
-#define CONFIG_SYS_FPGA_TS_CAP2 0x18
-#define CONFIG_SYS_FPGA_TS_CAP2_LOW 0x1a
-#define CONFIG_SYS_FPGA_TS_CAP3 0x1c
-#define CONFIG_SYS_FPGA_TS_CAP3_LOW 0x1e
-
-/* FPGA Mode Reg */
-#define CONFIG_SYS_FPGA_MODE_CF_RESET 0x0001
-#define CONFIG_SYS_FPGA_MODE_TS_IRQ_ENABLE 0x0100
-#define CONFIG_SYS_FPGA_MODE_TS_IRQ_CLEAR 0x1000
-#define CONFIG_SYS_FPGA_MODE_TS_CLEAR 0x2000
-
-/* FPGA Status Reg */
-#define CONFIG_SYS_FPGA_STATUS_DIP0 0x0001
-#define CONFIG_SYS_FPGA_STATUS_DIP1 0x0002
-#define CONFIG_SYS_FPGA_STATUS_DIP2 0x0004
-#define CONFIG_SYS_FPGA_STATUS_FLASH 0x0008
-#define CONFIG_SYS_FPGA_STATUS_TS_IRQ 0x1000
-
-#define CONFIG_SYS_FPGA_SPARTAN2 1 /* using Xilinx Spartan 2 now */
-#define CONFIG_SYS_FPGA_MAX_SIZE 128*1024 /* 128kByte is enough for XC2S50E*/
-
-/* FPGA program pin configuration */
-#define CONFIG_SYS_FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */
-#define CONFIG_SYS_FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */
-#define CONFIG_SYS_FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */
-#define CONFIG_SYS_FPGA_INIT 0x00010000 /* FPGA init pin (ppc input) */
-#define CONFIG_SYS_FPGA_DONE 0x00008000 /* FPGA done pin (ppc input) */
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in data cache)
- */
-/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
-#define CONFIG_SYS_TEMP_STACK_OCM 1
-
-/* On Chip Memory location */
-#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
-#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
-#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */
-#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */
-
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Definitions for GPIO setup (PPC405EP specific)
- *
- * GPIO0[0] - External Bus Controller BLAST output
- * GPIO0[1-9] - Instruction trace outputs -> GPIO
- * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
- * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO
- * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
- * GPIO0[24-27] - UART0 control signal inputs/outputs
- * GPIO0[28-29] - UART1 data signal input/output
- * GPIO0[30] - EMAC0 input
- * GPIO0[31] - EMAC1 reject packet as output
- */
-#define CONFIG_SYS_GPIO0_OSRL 0x40000550
-#define CONFIG_SYS_GPIO0_OSRH 0x00000110
-#define CONFIG_SYS_GPIO0_ISR1L 0x00000000
-/*#define CONFIG_SYS_GPIO0_ISR1H 0x15555445*/
-#define CONFIG_SYS_GPIO0_ISR1H 0x15555444
-#define CONFIG_SYS_GPIO0_TSRL 0x00000000
-#define CONFIG_SYS_GPIO0_TSRH 0x00000000
-#define CONFIG_SYS_GPIO0_TCR 0xF7FF8014
-
-#define CONFIG_NO_SERIAL_EEPROM
-
-/*--------------------------------------------------------------------*/
-
-#ifdef CONFIG_NO_SERIAL_EEPROM
-
-/*
-!-----------------------------------------------------------------------
-! Defines for entry options.
-! Note: Because the 405EP SDRAM controller does not support ECC, ECC DIMMs that
-! are plugged in the board will be utilized as non-ECC DIMMs.
-!-----------------------------------------------------------------------
-*/
-#undef AUTO_MEMORY_CONFIG
-#define DIMM_READ_ADDR 0xAB
-#define DIMM_WRITE_ADDR 0xAA
-
-/* Defines for CPC0_PLLMR1 Register fields */
-#define PLL_ACTIVE 0x80000000
-#define CPC0_PLLMR1_SSCS 0x80000000
-#define PLL_RESET 0x40000000
-#define CPC0_PLLMR1_PLLR 0x40000000
- /* Feedback multiplier */
-#define PLL_FBKDIV 0x00F00000
-#define CPC0_PLLMR1_FBDV 0x00F00000
-#define PLL_FBKDIV_16 0x00000000
-#define PLL_FBKDIV_1 0x00100000
-#define PLL_FBKDIV_2 0x00200000
-#define PLL_FBKDIV_3 0x00300000
-#define PLL_FBKDIV_4 0x00400000
-#define PLL_FBKDIV_5 0x00500000
-#define PLL_FBKDIV_6 0x00600000
-#define PLL_FBKDIV_7 0x00700000
-#define PLL_FBKDIV_8 0x00800000
-#define PLL_FBKDIV_9 0x00900000
-#define PLL_FBKDIV_10 0x00A00000
-#define PLL_FBKDIV_11 0x00B00000
-#define PLL_FBKDIV_12 0x00C00000
-#define PLL_FBKDIV_13 0x00D00000
-#define PLL_FBKDIV_14 0x00E00000
-#define PLL_FBKDIV_15 0x00F00000
- /* Forward A divisor */
-#define PLL_FWDDIVA 0x00070000
-#define CPC0_PLLMR1_FWDVA 0x00070000
-#define PLL_FWDDIVA_8 0x00000000
-#define PLL_FWDDIVA_7 0x00010000
-#define PLL_FWDDIVA_6 0x00020000
-#define PLL_FWDDIVA_5 0x00030000
-#define PLL_FWDDIVA_4 0x00040000
-#define PLL_FWDDIVA_3 0x00050000
-#define PLL_FWDDIVA_2 0x00060000
-#define PLL_FWDDIVA_1 0x00070000
- /* Forward B divisor */
-#define PLL_FWDDIVB 0x00007000
-#define CPC0_PLLMR1_FWDVB 0x00007000
-#define PLL_FWDDIVB_8 0x00000000
-#define PLL_FWDDIVB_7 0x00001000
-#define PLL_FWDDIVB_6 0x00002000
-#define PLL_FWDDIVB_5 0x00003000
-#define PLL_FWDDIVB_4 0x00004000
-#define PLL_FWDDIVB_3 0x00005000
-#define PLL_FWDDIVB_2 0x00006000
-#define PLL_FWDDIVB_1 0x00007000
- /* PLL tune bits */
-#define PLL_TUNE_MASK 0x000003FF
-#define PLL_TUNE_2_M_3 0x00000133 /* 2 <= M <= 3 */
-#define PLL_TUNE_4_M_6 0x00000134 /* 3 < M <= 6 */
-#define PLL_TUNE_7_M_10 0x00000138 /* 6 < M <= 10 */
-#define PLL_TUNE_11_M_14 0x0000013C /* 10 < M <= 14 */
-#define PLL_TUNE_15_M_40 0x0000023E /* 14 < M <= 40 */
-#define PLL_TUNE_VCO_LOW 0x00000000 /* 500MHz <= VCO <= 800MHz */
-#define PLL_TUNE_VCO_HI 0x00000080 /* 800MHz < VCO <= 1000MHz */
-
-/* Defines for CPC0_PLLMR0 Register fields */
- /* CPU divisor */
-#define PLL_CPUDIV 0x00300000
-#define CPC0_PLLMR0_CCDV 0x00300000
-#define PLL_CPUDIV_1 0x00000000
-#define PLL_CPUDIV_2 0x00100000
-#define PLL_CPUDIV_3 0x00200000
-#define PLL_CPUDIV_4 0x00300000
- /* PLB divisor */
-#define PLL_PLBDIV 0x00030000
-#define CPC0_PLLMR0_CBDV 0x00030000
-#define PLL_PLBDIV_1 0x00000000
-#define PLL_PLBDIV_2 0x00010000
-#define PLL_PLBDIV_3 0x00020000
-#define PLL_PLBDIV_4 0x00030000
- /* OPB divisor */
-#define PLL_OPBDIV 0x00003000
-#define CPC0_PLLMR0_OPDV 0x00003000
-#define PLL_OPBDIV_1 0x00000000
-#define PLL_OPBDIV_2 0x00001000
-#define PLL_OPBDIV_3 0x00002000
-#define PLL_OPBDIV_4 0x00003000
- /* EBC divisor */
-#define PLL_EXTBUSDIV 0x00000300
-#define CPC0_PLLMR0_EPDV 0x00000300
-#define PLL_EXTBUSDIV_2 0x00000000
-#define PLL_EXTBUSDIV_3 0x00000100
-#define PLL_EXTBUSDIV_4 0x00000200
-#define PLL_EXTBUSDIV_5 0x00000300
- /* MAL divisor */
-#define PLL_MALDIV 0x00000030
-#define CPC0_PLLMR0_MPDV 0x00000030
-#define PLL_MALDIV_1 0x00000000
-#define PLL_MALDIV_2 0x00000010
-#define PLL_MALDIV_3 0x00000020
-#define PLL_MALDIV_4 0x00000030
- /* PCI divisor */
-#define PLL_PCIDIV 0x00000003
-#define CPC0_PLLMR0_PPFD 0x00000003
-#define PLL_PCIDIV_1 0x00000000
-#define PLL_PCIDIV_2 0x00000001
-#define PLL_PCIDIV_3 0x00000002
-#define PLL_PCIDIV_4 0x00000003
-
-#ifdef CONFIG_PPCHAMELEON_CLK_25
-/* CPU - PLB/SDRAM - EBC - OPB - PCI (assuming a 25.0 MHz input clock to the 405EP) */
-#define PPCHAMELEON_PLLMR0_133_133_33_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_1 | \
- PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \
- PLL_MALDIV_1 | PLL_PCIDIV_4)
-#define PPCHAMELEON_PLLMR1_133_133_33_66_33 (PLL_FBKDIV_8 | \
- PLL_FWDDIVA_6 | PLL_FWDDIVB_4 | \
- PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
-
-#define PPCHAMELEON_PLLMR0_200_100_50_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \
- PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \
- PLL_MALDIV_1 | PLL_PCIDIV_4)
-#define PPCHAMELEON_PLLMR1_200_100_50_33 (PLL_FBKDIV_8 | \
- PLL_FWDDIVA_4 | PLL_FWDDIVB_4 | \
- PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
-
-#define PPCHAMELEON_PLLMR0_266_133_33_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \
- PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \
- PLL_MALDIV_1 | PLL_PCIDIV_4)
-#define PPCHAMELEON_PLLMR1_266_133_33_66_33 (PLL_FBKDIV_8 | \
- PLL_FWDDIVA_3 | PLL_FWDDIVB_4 | \
- PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
-
-#define PPCHAMELEON_PLLMR0_333_111_37_55_55 (PLL_CPUDIV_1 | PLL_PLBDIV_3 | \
- PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \
- PLL_MALDIV_1 | PLL_PCIDIV_2)
-#define PPCHAMELEON_PLLMR1_333_111_37_55_55 (PLL_FBKDIV_10 | \
- PLL_FWDDIVA_3 | PLL_FWDDIVB_4 | \
- PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI)
-
-#elif (defined (CONFIG_PPCHAMELEON_CLK_33))
-
-/* CPU - PLB/SDRAM - EBC - OPB - PCI (assuming a 33.3MHz input clock to the 405EP) */
-#define PPCHAMELEON_PLLMR0_133_133_33_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_1 | \
- PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \
- PLL_MALDIV_1 | PLL_PCIDIV_4)
-#define PPCHAMELEON_PLLMR1_133_133_33_66_33 (PLL_FBKDIV_4 | \
- PLL_FWDDIVA_6 | PLL_FWDDIVB_6 | \
- PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
-
-#define PPCHAMELEON_PLLMR0_200_100_50_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \
- PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \
- PLL_MALDIV_1 | PLL_PCIDIV_4)
-#define PPCHAMELEON_PLLMR1_200_100_50_33 (PLL_FBKDIV_6 | \
- PLL_FWDDIVA_4 | PLL_FWDDIVB_4 | \
- PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
-
-#define PPCHAMELEON_PLLMR0_266_133_33_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \
- PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \
- PLL_MALDIV_1 | PLL_PCIDIV_4)
-#define PPCHAMELEON_PLLMR1_266_133_33_66_33 (PLL_FBKDIV_8 | \
- PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
- PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
-
-#define PPCHAMELEON_PLLMR0_333_111_37_55_55 (PLL_CPUDIV_1 | PLL_PLBDIV_3 | \
- PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \
- PLL_MALDIV_1 | PLL_PCIDIV_2)
-#define PPCHAMELEON_PLLMR1_333_111_37_55_55 (PLL_FBKDIV_10 | \
- PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
- PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI)
-
-#else
-#error "* External frequency (SysClk) not defined! *"
-#endif
-
-#if (CONFIG_PPCHAMELEON_MODULE_MODEL == CONFIG_PPCHAMELEON_MODULE_HI)
-/* Model HI */
-#define PLLMR0_DEFAULT PPCHAMELEON_PLLMR0_333_111_37_55_55
-#define PLLMR1_DEFAULT PPCHAMELEON_PLLMR1_333_111_37_55_55
-#define CONFIG_SYS_OPB_FREQ 55555555
-/* Model ME */
-#elif (CONFIG_PPCHAMELEON_MODULE_MODEL == CONFIG_PPCHAMELEON_MODULE_ME)
-#define PLLMR0_DEFAULT PPCHAMELEON_PLLMR0_266_133_33_66_33
-#define PLLMR1_DEFAULT PPCHAMELEON_PLLMR1_266_133_33_66_33
-#define CONFIG_SYS_OPB_FREQ 66666666
-#else
-/* Model BA (default) */
-#define PLLMR0_DEFAULT PPCHAMELEON_PLLMR0_133_133_33_66_33
-#define PLLMR1_DEFAULT PPCHAMELEON_PLLMR1_133_133_33_66_33
-#define CONFIG_SYS_OPB_FREQ 66666666
-#endif
-
-#endif /* CONFIG_NO_SERIAL_EEPROM */
-
-#define CONFIG_JFFS2_NAND 1 /* jffs2 on nand support */
-#define NAND_CACHE_PAGES 16 /* size of nand cache in 512 bytes pages */
-
-/*
- * JFFS2 partitions
- */
-
-/* No command line, one static partition */
-#undef CONFIG_CMD_MTDPARTS
-#define CONFIG_JFFS2_DEV "nand0"
-#define CONFIG_JFFS2_PART_SIZE 0x00400000
-#define CONFIG_JFFS2_PART_OFFSET 0x00000000
-
-/* mtdparts command line support */
-/*
-#define CONFIG_CMD_MTDPARTS
-#define MTDIDS_DEFAULT "nor0=PPChameleon-0,nand0=ppchameleonevb-nand"
-*/
-
-/* 256 kB U-boot image */
-/*
-#define MTDPARTS_DEFAULT "mtdparts=PPChameleon-0:1m(kernel1),1m(kernel2)," \
- "1792k(user),256k(u-boot);" \
- "ppchameleonevb-nand:-(nand)"
-*/
-
-/* 320 kB U-boot image */
-/*
-#define MTDPARTS_DEFAULT "mtdparts=PPChameleon-0:1m(kernel1),1m(kernel2)," \
- "1728k(user),320k(u-boot);" \
- "ppchameleonevb-nand:-(nand)"
-*/
-
-#endif /* __CONFIG_H */
--
1.9.1
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [U-Boot] [PATCH 6/8] powerpc: mpc5xxx: remove Total5200 board support
2015-01-22 15:24 [U-Boot] [PATCH 0/8] powerpc: drop more non-generic boards Masahiro Yamada
` (4 preceding siblings ...)
2015-01-22 15:24 ` [U-Boot] [PATCH 5/8] powerpc: ppc4xx: remove PPChameleonEVB, CATcenter boards Masahiro Yamada
@ 2015-01-22 15:24 ` Masahiro Yamada
2015-01-23 21:57 ` Tom Rini
2015-01-22 15:24 ` [U-Boot] [PATCH 7/8] powerpc: mpc5xxx: PM520 " Masahiro Yamada
2015-01-22 15:24 ` [U-Boot] [PATCH 8/8] powerpc: remove icecube_5200, Lite5200, cpci5200, mecp5200, pf5200 Masahiro Yamada
7 siblings, 1 reply; 19+ messages in thread
From: Masahiro Yamada @ 2015-01-22 15:24 UTC (permalink / raw)
To: u-boot
This board is still a non-generic board.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
---
arch/powerpc/cpu/mpc5xxx/Kconfig | 4 -
board/total5200/Kconfig | 9 -
board/total5200/MAINTAINERS | 9 -
board/total5200/Makefile | 8 -
board/total5200/mt48lc16m16a2-75.h | 14 --
board/total5200/mt48lc32m16a2-75.h | 19 --
board/total5200/sdram.c | 159 -------------
board/total5200/sdram.h | 18 --
board/total5200/total5200.c | 276 ----------------------
configs/Total5200_Rev2_defconfig | 4 -
configs/Total5200_Rev2_lowboot_defconfig | 4 -
configs/Total5200_defconfig | 4 -
configs/Total5200_lowboot_defconfig | 4 -
doc/README.scrapyard | 1 +
drivers/net/mpc5xxx_fec.c | 5 -
drivers/video/cfb_console.c | 3 -
drivers/video/sed13806.c | 5 -
include/configs/Total5200.h | 386 -------------------------------
18 files changed, 1 insertion(+), 931 deletions(-)
delete mode 100644 board/total5200/Kconfig
delete mode 100644 board/total5200/MAINTAINERS
delete mode 100644 board/total5200/Makefile
delete mode 100644 board/total5200/mt48lc16m16a2-75.h
delete mode 100644 board/total5200/mt48lc32m16a2-75.h
delete mode 100644 board/total5200/sdram.c
delete mode 100644 board/total5200/sdram.h
delete mode 100644 board/total5200/total5200.c
delete mode 100644 configs/Total5200_Rev2_defconfig
delete mode 100644 configs/Total5200_Rev2_lowboot_defconfig
delete mode 100644 configs/Total5200_defconfig
delete mode 100644 configs/Total5200_lowboot_defconfig
delete mode 100644 include/configs/Total5200.h
diff --git a/arch/powerpc/cpu/mpc5xxx/Kconfig b/arch/powerpc/cpu/mpc5xxx/Kconfig
index e2e9cb7..9585c80 100644
--- a/arch/powerpc/cpu/mpc5xxx/Kconfig
+++ b/arch/powerpc/cpu/mpc5xxx/Kconfig
@@ -47,9 +47,6 @@ config TARGET_MUNICES
config TARGET_PM520
bool "Support PM520"
-config TARGET_TOTAL5200
- bool "Support Total5200"
-
config TARGET_V38B
bool "Support v38b"
@@ -119,7 +116,6 @@ source "board/motionpro/Kconfig"
source "board/munices/Kconfig"
source "board/phytec/pcm030/Kconfig"
source "board/pm520/Kconfig"
-source "board/total5200/Kconfig"
source "board/tqc/tqm5200/Kconfig"
source "board/v38b/Kconfig"
diff --git a/board/total5200/Kconfig b/board/total5200/Kconfig
deleted file mode 100644
index ffa9516..0000000
--- a/board/total5200/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_TOTAL5200
-
-config SYS_BOARD
- default "total5200"
-
-config SYS_CONFIG_NAME
- default "Total5200"
-
-endif
diff --git a/board/total5200/MAINTAINERS b/board/total5200/MAINTAINERS
deleted file mode 100644
index afb0058..0000000
--- a/board/total5200/MAINTAINERS
+++ /dev/null
@@ -1,9 +0,0 @@
-TOTAL5200 BOARD
-#M: -
-S: Maintained
-F: board/total5200/
-F: include/configs/Total5200.h
-F: configs/Total5200_defconfig
-F: configs/Total5200_lowboot_defconfig
-F: configs/Total5200_Rev2_defconfig
-F: configs/Total5200_Rev2_lowboot_defconfig
diff --git a/board/total5200/Makefile b/board/total5200/Makefile
deleted file mode 100644
index 527557c..0000000
--- a/board/total5200/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2003-2006
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := total5200.o sdram.o
diff --git a/board/total5200/mt48lc16m16a2-75.h b/board/total5200/mt48lc16m16a2-75.h
deleted file mode 100644
index 068a9a6..0000000
--- a/board/total5200/mt48lc16m16a2-75.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/*
- * (C) Copyright 2004
- * Mark Jonas, Freescale Semiconductor, mark.jonas at freescale.com.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#define SDRAM_DDR 0 /* is SDR */
-
-/* Settings for XLB = 132 MHz */
-#define SDRAM_MODE 0x00CD0000
-#define SDRAM_CONTROL 0x504F0000
-#define SDRAM_CONFIG1 0xD2322800
-#define SDRAM_CONFIG2 0x8AD70000
diff --git a/board/total5200/mt48lc32m16a2-75.h b/board/total5200/mt48lc32m16a2-75.h
deleted file mode 100644
index 0377417..0000000
--- a/board/total5200/mt48lc32m16a2-75.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/*
- * (C) Copyright 2004
- * Mark Jonas, Freescale Semiconductor, mark.jonas at freescale.com.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * Micron MT48LC32M16A2-75 is compatible to:
- * - Infineon HYB39S512160AT-75
- */
-
-#define SDRAM_DDR 0 /* is SDR */
-
-/* Settings for XLB = 132 MHz */
-#define SDRAM_MODE 0x00CD0000
-#define SDRAM_CONTROL 0x514F0000
-#define SDRAM_CONFIG1 0xD2322800
-#define SDRAM_CONFIG2 0x8AD70000
diff --git a/board/total5200/sdram.c b/board/total5200/sdram.c
deleted file mode 100644
index dbe3587..0000000
--- a/board/total5200/sdram.c
+++ /dev/null
@@ -1,159 +0,0 @@
-/*
- * (C) Copyright 2003-2004
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- *
- * (C) Copyright 2004
- * Mark Jonas, Freescale Semiconductor, mark.jonas at freescale.com.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <mpc5xxx.h>
-
-#include "sdram.h"
-
-#ifndef CONFIG_SYS_RAMBOOT
-static void mpc5xxx_sdram_start (sdram_conf_t *sdram_conf, int hi_addr)
-{
- long hi_addr_bit = hi_addr ? 0x01000000 : 0;
-
- /* unlock mode register */
- *(vu_long *)MPC5XXX_SDRAM_CTRL = sdram_conf->control | 0x80000000 | hi_addr_bit;
- __asm__ volatile ("sync");
-
- /* precharge all banks */
- *(vu_long *)MPC5XXX_SDRAM_CTRL = sdram_conf->control | 0x80000002 | hi_addr_bit;
- __asm__ volatile ("sync");
-
- if (sdram_conf->ddr) {
- /* set mode register: extended mode */
- *(vu_long *)MPC5XXX_SDRAM_MODE = sdram_conf->emode;
- __asm__ volatile ("sync");
-
- /* set mode register: reset DLL */
- *(vu_long *)MPC5XXX_SDRAM_MODE = sdram_conf->mode | 0x04000000;
- __asm__ volatile ("sync");
- }
-
- /* precharge all banks */
- *(vu_long *)MPC5XXX_SDRAM_CTRL = sdram_conf->control | 0x80000002 | hi_addr_bit;
- __asm__ volatile ("sync");
-
- /* auto refresh */
- *(vu_long *)MPC5XXX_SDRAM_CTRL = sdram_conf->control | 0x80000004 | hi_addr_bit;
- __asm__ volatile ("sync");
-
- /* set mode register */
- *(vu_long *)MPC5XXX_SDRAM_MODE = sdram_conf->mode;
- __asm__ volatile ("sync");
-
- /* normal operation */
- *(vu_long *)MPC5XXX_SDRAM_CTRL = sdram_conf->control | hi_addr_bit;
- __asm__ volatile ("sync");
-}
-#endif
-
-/*
- * ATTENTION: Although partially referenced initdram does NOT make real use
- * use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE
- * is something else than 0x00000000.
- */
-
-long int mpc5xxx_sdram_init (sdram_conf_t *sdram_conf)
-{
- ulong dramsize = 0;
- ulong dramsize2 = 0;
-#ifndef CONFIG_SYS_RAMBOOT
- ulong test1, test2;
-
- /* setup SDRAM chip selects */
- *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e;/* 2G at 0x0 */
- *(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x80000000;/* disabled */
- __asm__ volatile ("sync");
-
- /* setup config registers */
- *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = sdram_conf->config1;
- *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = sdram_conf->config2;
- __asm__ volatile ("sync");
-
- if (sdram_conf->ddr) {
- /* set tap delay */
- *(vu_long *)MPC5XXX_CDM_PORCFG = sdram_conf->tapdelay;
- __asm__ volatile ("sync");
- }
-
- /* find RAM size using SDRAM CS0 only */
- mpc5xxx_sdram_start(sdram_conf, 0);
- test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
- mpc5xxx_sdram_start(sdram_conf, 1);
- test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
- if (test1 > test2) {
- mpc5xxx_sdram_start(sdram_conf, 0);
- dramsize = test1;
- } else {
- dramsize = test2;
- }
-
- /* memory smaller than 1MB is impossible */
- if (dramsize < (1 << 20)) {
- dramsize = 0;
- }
-
- /* set SDRAM CS0 size according to the amount of RAM found */
- if (dramsize > 0) {
- *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 + __builtin_ffs(dramsize >> 20) - 1;
- } else {
- *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
- }
-
- /* let SDRAM CS1 start right after CS0 */
- *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;/* 2G */
-
- /* find RAM size using SDRAM CS1 only */
- mpc5xxx_sdram_start(sdram_conf, 0);
- test1 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
- mpc5xxx_sdram_start(sdram_conf, 1);
- test2 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
- if (test1 > test2) {
- mpc5xxx_sdram_start(sdram_conf, 0);
- dramsize2 = test1;
- } else {
- dramsize2 = test2;
- }
-
- /* memory smaller than 1MB is impossible */
- if (dramsize2 < (1 << 20)) {
- dramsize2 = 0;
- }
-
- /* set SDRAM CS1 size according to the amount of RAM found */
- if (dramsize2 > 0) {
- *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize
- | (0x13 + __builtin_ffs(dramsize2 >> 20) - 1);
- } else {
- *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
- }
-
-#else /* CONFIG_SYS_RAMBOOT */
-
- /* retrieve size of memory connected to SDRAM CS0 */
- dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
- if (dramsize >= 0x13) {
- dramsize = (1 << (dramsize - 0x13)) << 20;
- } else {
- dramsize = 0;
- }
-
- /* retrieve size of memory connected to SDRAM CS1 */
- dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF;
- if (dramsize2 >= 0x13) {
- dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
- } else {
- dramsize2 = 0;
- }
-
-#endif /* CONFIG_SYS_RAMBOOT */
-
- return dramsize + dramsize2;
-}
diff --git a/board/total5200/sdram.h b/board/total5200/sdram.h
deleted file mode 100644
index 3758f5c9..0000000
--- a/board/total5200/sdram.h
+++ /dev/null
@@ -1,18 +0,0 @@
-/*
- * (C) Copyright 2004
- * Mark Jonas, Freescale Semiconductor, mark.jonas at freescale.com.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-typedef struct {
- ulong ddr;
- ulong mode;
- ulong emode;
- ulong control;
- ulong config1;
- ulong config2;
- ulong tapdelay;
-} sdram_conf_t;
-
-long int mpc5xxx_sdram_init (sdram_conf_t *sdram_conf);
diff --git a/board/total5200/total5200.c b/board/total5200/total5200.c
deleted file mode 100644
index 345a186..0000000
--- a/board/total5200/total5200.c
+++ /dev/null
@@ -1,276 +0,0 @@
-/*
- * (C) Copyright 2003-2004
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- *
- * (C) Copyright 2004
- * Mark Jonas, Freescale Semiconductor, mark.jonas@freescale.com.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <mpc5xxx.h>
-#include <pci.h>
-#include <netdev.h>
-
-#include "sdram.h"
-
-#if CONFIG_TOTAL5200_REV==2
-#include "mt48lc32m16a2-75.h"
-#else
-#include "mt48lc16m16a2-75.h"
-#endif
-
-phys_size_t initdram (int board_type)
-{
- sdram_conf_t sdram_conf;
-
- sdram_conf.ddr = SDRAM_DDR;
- sdram_conf.mode = SDRAM_MODE;
- sdram_conf.emode = 0;
- sdram_conf.control = SDRAM_CONTROL;
- sdram_conf.config1 = SDRAM_CONFIG1;
- sdram_conf.config2 = SDRAM_CONFIG2;
- sdram_conf.tapdelay = 0;
- return mpc5xxx_sdram_init (&sdram_conf);
-}
-
-int checkboard (void)
-{
-#if CONFIG_TOTAL5200_REV==2
- puts ("Board: Total5200 Rev.2 ");
-#else
- puts ("Board: Total5200 ");
-#endif
-
- /*
- * Retrieve FPGA Revision.
- */
- printf ("(FPGA %08lX)\n", *(vu_long *) (CONFIG_SYS_FPGA_BASE + 0x400));
-
- /*
- * Take all peripherals in power-up mode.
- */
-#if CONFIG_TOTAL5200_REV==2
- *(vu_char *) (CONFIG_SYS_CPLD_BASE + 0x46) = 0x70;
-#else
- *(vu_long *) (CONFIG_SYS_CPLD_BASE + 0x400) = 0x70;
-#endif
-
- return 0;
-}
-
-#ifdef CONFIG_PCI
-static struct pci_controller hose;
-
-extern void pci_mpc5xxx_init(struct pci_controller *);
-
-void pci_init_board(void)
-{
- pci_mpc5xxx_init(&hose);
-}
-#endif
-
-#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET)
-
-/* IRDA_1 aka PSC6_3 (pin C13) */
-#define GPIO_IRDA_1 0x20000000UL
-
-void init_ide_reset (void)
-{
- debug ("init_ide_reset\n");
-
- /* Configure IRDA_1 (PSC6_3) as GPIO output for ATA reset */
- *(vu_long *) MPC5XXX_GPIO_ENABLE |= GPIO_IRDA_1;
- *(vu_long *) MPC5XXX_GPIO_DIR |= GPIO_IRDA_1;
-}
-
-void ide_set_reset (int idereset)
-{
- debug ("ide_reset(%d)\n", idereset);
-
- if (idereset) {
- *(vu_long *) MPC5XXX_GPIO_DATA_O &= ~GPIO_IRDA_1;
- } else {
- *(vu_long *) MPC5XXX_GPIO_DATA_O |= GPIO_IRDA_1;
- }
-}
-#endif
-
-#ifdef CONFIG_VIDEO_SED13806
-#include <sed13806.h>
-
-#define DISPLAY_WIDTH 640
-#define DISPLAY_HEIGHT 480
-
-#ifdef CONFIG_VIDEO_SED13806_8BPP
-#error CONFIG_VIDEO_SED13806_8BPP not supported.
-#endif /* CONFIG_VIDEO_SED13806_8BPP */
-
-#ifdef CONFIG_VIDEO_SED13806_16BPP
-static const S1D_REGS init_regs [] =
-{
- {0x0001,0x00}, /* Miscellaneous Register */
- {0x01FC,0x00}, /* Display Mode Register */
- {0x0004,0x00}, /* General IO Pins Configuration Register 0 */
- {0x0005,0x00}, /* General IO Pins Configuration Register 1 */
- {0x0008,0x00}, /* General IO Pins Control Register 0 */
- {0x0009,0x00}, /* General IO Pins Control Register 1 */
- {0x0010,0x02}, /* Memory Clock Configuration Register */
- {0x0014,0x02}, /* LCD Pixel Clock Configuration Register */
- {0x0018,0x02}, /* CRT/TV Pixel Clock Configuration Register */
- {0x001C,0x02}, /* MediaPlug Clock Configuration Register */
- {0x001E,0x01}, /* CPU To Memory Wait State Select Register */
- {0x0021,0x03}, /* DRAM Refresh Rate Register */
- {0x002A,0x00}, /* DRAM Timings Control Register 0 */
- {0x002B,0x01}, /* DRAM Timings Control Register 1 */
- {0x0020,0x80}, /* Memory Configuration Register */
- {0x0030,0x25}, /* Panel Type Register */
- {0x0031,0x00}, /* MOD Rate Register */
- {0x0032,0x4F}, /* LCD Horizontal Display Width Register */
- {0x0034,0x13}, /* LCD Horizontal Non-Display Period Register */
- {0x0035,0x01}, /* TFT FPLINE Start Position Register */
- {0x0036,0x0B}, /* TFT FPLINE Pulse Width Register */
- {0x0038,0xDF}, /* LCD Vertical Display Height Register 0 */
- {0x0039,0x01}, /* LCD Vertical Display Height Register 1 */
- {0x003A,0x2C}, /* LCD Vertical Non-Display Period Register */
- {0x003B,0x0A}, /* TFT FPFRAME Start Position Register */
- {0x003C,0x01}, /* TFT FPFRAME Pulse Width Register */
- {0x0040,0x05}, /* LCD Display Mode Register */
- {0x0041,0x00}, /* LCD Miscellaneous Register */
- {0x0042,0x00}, /* LCD Display Start Address Register 0 */
- {0x0043,0x00}, /* LCD Display Start Address Register 1 */
- {0x0044,0x00}, /* LCD Display Start Address Register 2 */
- {0x0046,0x80}, /* LCD Memory Address Offset Register 0 */
- {0x0047,0x02}, /* LCD Memory Address Offset Register 1 */
- {0x0048,0x00}, /* LCD Pixel Panning Register */
- {0x004A,0x00}, /* LCD Display FIFO High Threshold Control Register */
- {0x004B,0x00}, /* LCD Display FIFO Low Threshold Control Register */
- {0x0050,0x4F}, /* CRT/TV Horizontal Display Width Register */
- {0x0052,0x13}, /* CRT/TV Horizontal Non-Display Period Register */
- {0x0053,0x01}, /* CRT/TV HRTC Start Position Register */
- {0x0054,0x0B}, /* CRT/TV HRTC Pulse Width Register */
- {0x0056,0xDF}, /* CRT/TV Vertical Display Height Register 0 */
- {0x0057,0x01}, /* CRT/TV Vertical Display Height Register 1 */
- {0x0058,0x2B}, /* CRT/TV Vertical Non-Display Period Register */
- {0x0059,0x09}, /* CRT/TV VRTC Start Position Register */
- {0x005A,0x01}, /* CRT/TV VRTC Pulse Width Register */
- {0x005B,0x10}, /* TV Output Control Register */
- {0x0060,0x05}, /* CRT/TV Display Mode Register */
- {0x0062,0x00}, /* CRT/TV Display Start Address Register 0 */
- {0x0063,0x00}, /* CRT/TV Display Start Address Register 1 */
- {0x0064,0x00}, /* CRT/TV Display Start Address Register 2 */
- {0x0066,0x80}, /* CRT/TV Memory Address Offset Register 0 */
- {0x0067,0x02}, /* CRT/TV Memory Address Offset Register 1 */
- {0x0068,0x00}, /* CRT/TV Pixel Panning Register */
- {0x006A,0x00}, /* CRT/TV Display FIFO High Threshold Control Register */
- {0x006B,0x00}, /* CRT/TV Display FIFO Low Threshold Control Register */
- {0x0070,0x00}, /* LCD Ink/Cursor Control Register */
- {0x0071,0x01}, /* LCD Ink/Cursor Start Address Register */
- {0x0072,0x00}, /* LCD Cursor X Position Register 0 */
- {0x0073,0x00}, /* LCD Cursor X Position Register 1 */
- {0x0074,0x00}, /* LCD Cursor Y Position Register 0 */
- {0x0075,0x00}, /* LCD Cursor Y Position Register 1 */
- {0x0076,0x00}, /* LCD Ink/Cursor Blue Color 0 Register */
- {0x0077,0x00}, /* LCD Ink/Cursor Green Color 0 Register */
- {0x0078,0x00}, /* LCD Ink/Cursor Red Color 0 Register */
- {0x007A,0x1F}, /* LCD Ink/Cursor Blue Color 1 Register */
- {0x007B,0x3F}, /* LCD Ink/Cursor Green Color 1 Register */
- {0x007C,0x1F}, /* LCD Ink/Cursor Red Color 1 Register */
- {0x007E,0x00}, /* LCD Ink/Cursor FIFO Threshold Register */
- {0x0080,0x00}, /* CRT/TV Ink/Cursor Control Register */
- {0x0081,0x01}, /* CRT/TV Ink/Cursor Start Address Register */
- {0x0082,0x00}, /* CRT/TV Cursor X Position Register 0 */
- {0x0083,0x00}, /* CRT/TV Cursor X Position Register 1 */
- {0x0084,0x00}, /* CRT/TV Cursor Y Position Register 0 */
- {0x0085,0x00}, /* CRT/TV Cursor Y Position Register 1 */
- {0x0086,0x00}, /* CRT/TV Ink/Cursor Blue Color 0 Register */
- {0x0087,0x00}, /* CRT/TV Ink/Cursor Green Color 0 Register */
- {0x0088,0x00}, /* CRT/TV Ink/Cursor Red Color 0 Register */
- {0x008A,0x1F}, /* CRT/TV Ink/Cursor Blue Color 1 Register */
- {0x008B,0x3F}, /* CRT/TV Ink/Cursor Green Color 1 Register */
- {0x008C,0x1F}, /* CRT/TV Ink/Cursor Red Color 1 Register */
- {0x008E,0x00}, /* CRT/TV Ink/Cursor FIFO Threshold Register */
- {0x0100,0x00}, /* BitBlt Control Register 0 */
- {0x0101,0x00}, /* BitBlt Control Register 1 */
- {0x0102,0x00}, /* BitBlt ROP Code/Color Expansion Register */
- {0x0103,0x00}, /* BitBlt Operation Register */
- {0x0104,0x00}, /* BitBlt Source Start Address Register 0 */
- {0x0105,0x00}, /* BitBlt Source Start Address Register 1 */
- {0x0106,0x00}, /* BitBlt Source Start Address Register 2 */
- {0x0108,0x00}, /* BitBlt Destination Start Address Register 0 */
- {0x0109,0x00}, /* BitBlt Destination Start Address Register 1 */
- {0x010A,0x00}, /* BitBlt Destination Start Address Register 2 */
- {0x010C,0x00}, /* BitBlt Memory Address Offset Register 0 */
- {0x010D,0x00}, /* BitBlt Memory Address Offset Register 1 */
- {0x0110,0x00}, /* BitBlt Width Register 0 */
- {0x0111,0x00}, /* BitBlt Width Register 1 */
- {0x0112,0x00}, /* BitBlt Height Register 0 */
- {0x0113,0x00}, /* BitBlt Height Register 1 */
- {0x0114,0x00}, /* BitBlt Background Color Register 0 */
- {0x0115,0x00}, /* BitBlt Background Color Register 1 */
- {0x0118,0x00}, /* BitBlt Foreground Color Register 0 */
- {0x0119,0x00}, /* BitBlt Foreground Color Register 1 */
- {0x01E0,0x00}, /* Look-Up Table Mode Register */
- {0x01E2,0x00}, /* Look-Up Table Address Register */
- {0x01E4,0x00}, /* Look-Up Table Data Register */
- {0x01F0,0x00}, /* Power Save Configuration Register */
- {0x01F1,0x00}, /* Power Save Status Register */
- {0x01F4,0x00}, /* CPU-to-Memory Access Watchdog Timer Register */
- {0x01FC,0x01}, /* Display Mode Register */
- {0, 0}
-};
-#endif /* CONFIG_VIDEO_SED13806_16BPP */
-
-#ifdef CONFIG_CONSOLE_EXTRA_INFO
-/* Return text to be printed besides the logo. */
-void video_get_info_str (int line_number, char *info)
-{
- if (line_number == 1) {
-#if CONFIG_TOTAL5200_REV==1
- strcpy (info, " Total5200");
-#elif CONFIG_TOTAL5200_REV==2
- strcpy (info, " Total5200 Rev.2");
-#else
-#error CONFIG_TOTAL5200_REV must be 1 or 2.
-#endif
- } else {
- info [0] = '\0';
- }
-}
-#endif
-
-/* Returns SED13806 base address. First thing called in the driver. */
-unsigned int board_video_init (void)
-{
- return CONFIG_SYS_LCD_BASE;
-}
-
-/* Called after initializing the SED13806 and before clearing the screen. */
-void board_validate_screen (unsigned int base)
-{
-}
-
-/* Return a pointer to the initialization sequence. */
-const S1D_REGS *board_get_regs (void)
-{
- return init_regs;
-}
-
-int board_get_width (void)
-{
- return DISPLAY_WIDTH;
-}
-
-int board_get_height (void)
-{
- return DISPLAY_HEIGHT;
-}
-
-#endif /* CONFIG_VIDEO_SED13806 */
-
-int board_eth_init(bd_t *bis)
-{
- cpu_eth_init(bis); /* Built in FEC comes first */
- return pci_eth_init(bis);
-}
diff --git a/configs/Total5200_Rev2_defconfig b/configs/Total5200_Rev2_defconfig
deleted file mode 100644
index 9f27734..0000000
--- a/configs/Total5200_Rev2_defconfig
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_SYS_EXTRA_OPTIONS="TOTAL5200_REV=2"
-CONFIG_PPC=y
-CONFIG_MPC5xxx=y
-CONFIG_TARGET_TOTAL5200=y
diff --git a/configs/Total5200_Rev2_lowboot_defconfig b/configs/Total5200_Rev2_lowboot_defconfig
deleted file mode 100644
index 15b27b3..0000000
--- a/configs/Total5200_Rev2_lowboot_defconfig
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_SYS_EXTRA_OPTIONS="TOTAL5200_REV=2,SYS_TEXT_BASE=0xFE000000"
-CONFIG_PPC=y
-CONFIG_MPC5xxx=y
-CONFIG_TARGET_TOTAL5200=y
diff --git a/configs/Total5200_defconfig b/configs/Total5200_defconfig
deleted file mode 100644
index 5aaae49..0000000
--- a/configs/Total5200_defconfig
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_SYS_EXTRA_OPTIONS="TOTAL5200_REV=1"
-CONFIG_PPC=y
-CONFIG_MPC5xxx=y
-CONFIG_TARGET_TOTAL5200=y
diff --git a/configs/Total5200_lowboot_defconfig b/configs/Total5200_lowboot_defconfig
deleted file mode 100644
index 4c9195e..0000000
--- a/configs/Total5200_lowboot_defconfig
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_SYS_EXTRA_OPTIONS="TOTAL5200_REV=1,SYS_TEXT_BASE=0xFE000000"
-CONFIG_PPC=y
-CONFIG_MPC5xxx=y
-CONFIG_TARGET_TOTAL5200=y
diff --git a/doc/README.scrapyard b/doc/README.scrapyard
index 976fca1..0c4dbd0 100644
--- a/doc/README.scrapyard
+++ b/doc/README.scrapyard
@@ -12,6 +12,7 @@ The list should be sorted in reverse chronological order.
Board Arch CPU Commit Removed Last known maintainer/contact
=================================================================================================
+Total5200 powerpc mpc5xxx - -
CATcenter powerpc ppc4xx - -
PPChameleonEVB powerpc ppc4xx - - Andrea "llandre" Marson <andrea.marson@dave-tech.it>
P2020DS powerpc mpc85xx - -
diff --git a/drivers/net/mpc5xxx_fec.c b/drivers/net/mpc5xxx_fec.c
index d9d6f4f..d2a8ae0 100644
--- a/drivers/net/mpc5xxx_fec.c
+++ b/drivers/net/mpc5xxx_fec.c
@@ -407,13 +407,8 @@ static int mpc5xxx_fec_init_phy(struct eth_device *dev, bd_t * bis)
*/
if (fec->xcv_type == SEVENWIRE) {
/* 10MBit with 7-wire operation */
-#if defined(CONFIG_TOTAL5200)
- /* 7-wire and USB2 on Ethernet */
- *(vu_long *)MPC5XXX_GPS_PORT_CONFIG |= 0x00030000;
-#else /* !CONFIG_TOTAL5200 */
/* 7-wire only */
*(vu_long *)MPC5XXX_GPS_PORT_CONFIG |= 0x00020000;
-#endif /* CONFIG_TOTAL5200 */
} else {
/* 100MBit with MD operation */
*(vu_long *)MPC5XXX_GPS_PORT_CONFIG |= 0x00050000;
diff --git a/drivers/video/cfb_console.c b/drivers/video/cfb_console.c
index cbe6b9f..d4226e3 100644
--- a/drivers/video/cfb_console.c
+++ b/drivers/video/cfb_console.c
@@ -117,10 +117,7 @@
* Defines for the SED13806 driver
*/
#ifdef CONFIG_VIDEO_SED13806
-
-#ifndef CONFIG_TOTAL5200
#define VIDEO_FB_LITTLE_ENDIAN
-#endif
#define VIDEO_HW_RECTFILL
#define VIDEO_HW_BITBLT
#endif
diff --git a/drivers/video/sed13806.c b/drivers/video/sed13806.c
index da653c0..cd7fac6 100644
--- a/drivers/video/sed13806.c
+++ b/drivers/video/sed13806.c
@@ -18,13 +18,8 @@
#define writeByte(ptrReg,value) \
*(volatile unsigned char *)(sed13806.isaBase + ptrReg) = value
-#ifdef CONFIG_TOTAL5200
-#define writeWord(ptrReg,value) \
- (*(volatile unsigned short *)(sed13806.isaBase + ptrReg) = value)
-#else
#define writeWord(ptrReg,value) \
(*(volatile unsigned short *)(sed13806.isaBase + ptrReg) = ((value >> 8 ) & 0xff) | ((value << 8) & 0xff00))
-#endif
GraphicDevice sed13806;
diff --git a/include/configs/Total5200.h b/include/configs/Total5200.h
deleted file mode 100644
index a58eeca..0000000
--- a/include/configs/Total5200.h
+++ /dev/null
@@ -1,386 +0,0 @@
-/*
- * (C) Copyright 2003-2004
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- *
- * (C) Copyright 2004
- * Mark Jonas, Freescale Semiconductor, mark.jonas at freescale.com.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * Check valid setting of revision define.
- * Total5100 and Total5200 Rev.1 are identical except for the processor.
- */
-#if (CONFIG_TOTAL5200_REV!=1 && CONFIG_TOTAL5200_REV!=2)
-#error CONFIG_TOTAL5200_REV must be 1 or 2
-#endif
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_MPC5200 1 /* This is a MPC5200 CPU */
-#define CONFIG_TOTAL5200 1 /* ... on Total5200 board */
-
-/*
- * Valid values for CONFIG_SYS_TEXT_BASE are:
- * 0xFFF00000 boot high (standard configuration)
- * 0xFE000000 boot low
- * 0x00100000 boot from RAM (for testing only)
- */
-#ifndef CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_TEXT_BASE 0xFFF00000
-#endif
-
-#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
-
-#define CONFIG_HIGH_BATS 1 /* High BATs supported */
-
-/*
- * Serial console configuration
- */
-#define CONFIG_PSC_CONSOLE 3 /* console is on PSC3 */
-#define CONFIG_BAUDRATE 115200 /* ...@115200 bps */
-#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
-
-/*
- * Video console
- */
-#define CONFIG_VIDEO
-#define CONFIG_VIDEO_SED13806
-#define CONFIG_VIDEO_SED13806_16BPP
-
-#define CONFIG_CFB_CONSOLE
-#define CONFIG_VIDEO_LOGO
-/* #define CONFIG_VIDEO_BMP_LOGO */
-#define CONFIG_CONSOLE_EXTRA_INFO
-#define CONFIG_VGA_AS_SINGLE_DEVICE
-#define CONFIG_VIDEO_SW_CURSOR
-#define CONFIG_SPLASH_SCREEN
-
-
-/*
- * PCI Mapping:
- * 0x40000000 - 0x4fffffff - PCI Memory
- * 0x50000000 - 0x50ffffff - PCI IO Space
- */
-#define CONFIG_PCI 1
-#define CONFIG_PCI_PNP 1
-#define CONFIG_PCI_SCAN_SHOW 1
-#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
-
-#define CONFIG_PCI_MEM_BUS 0x40000000
-#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
-#define CONFIG_PCI_MEM_SIZE 0x10000000
-
-#define CONFIG_PCI_IO_BUS 0x50000000
-#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
-#define CONFIG_PCI_IO_SIZE 0x01000000
-
-#define CONFIG_MII 1
-#define CONFIG_EEPRO100 1
-#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
-#define CONFIG_NS8382X 1
-
-/* Partitions */
-#define CONFIG_MAC_PARTITION
-#define CONFIG_DOS_PARTITION
-
-/* USB */
-#define CONFIG_USB_OHCI
-#define CONFIG_USB_STORAGE
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_PCI
-
-#define CONFIG_CMD_BMP
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_IDE
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_USB
-
-
-#if (CONFIG_SYS_TEXT_BASE == 0xFE000000) /* Boot low */
-# define CONFIG_SYS_LOWBOOT 1
-#endif
-
-/*
- * Autobooting
- */
-#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
-
-#define CONFIG_PREBOOT \
- "setenv stdout serial;setenv stderr serial;" \
- "echo;" \
- "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
- "echo"
-
-#undef CONFIG_BOOTARGS
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "netdev=eth0\0" \
- "nfsargs=setenv bootargs root=/dev/nfs rw " \
- "nfsroot=${serverip}:${rootpath}\0" \
- "ramargs=setenv bootargs root=/dev/ram rw\0" \
- "addip=setenv bootargs ${bootargs} " \
- "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
- ":${hostname}:${netdev}:off panic=1\0" \
- "flash_nfs=run nfsargs addip;" \
- "bootm ${kernel_addr}\0" \
- "flash_self=run ramargs addip;" \
- "bootm ${kernel_addr} ${ramdisk_addr}\0" \
- "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
- "rootpath=/opt/eldk/ppc_82xx\0" \
- "bootfile=/tftpboot/MPC5200/uImage\0" \
- ""
-
-#define CONFIG_BOOTCOMMAND "run flash_self"
-
-/*
- * IPB Bus clocking configuration.
- */
-#undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
-
-/*
- * I2C configuration
- */
-#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
-#define CONFIG_SYS_I2C_MODULE 1 /* Select I2C module #1 or #2 */
-
-#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */
-#define CONFIG_SYS_I2C_SLAVE 0x7F
-
-/*
- * EEPROM configuration
- */
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 70
-
-/*
- * Flash configuration
- */
-#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
-#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
-#if CONFIG_TOTAL5200_REV==2
-# define CONFIG_SYS_MAX_FLASH_BANKS 3 /* max num of flash banks */
-# define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS5_START, CONFIG_SYS_CS4_START, CONFIG_SYS_BOOTCS_START }
-#else
-# define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */
-# define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_BOOTCS_START }
-#endif
-#define CONFIG_SYS_FLASH_EMPTY_INFO
-#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max num of sects on one chip */
-
-#if CONFIG_TOTAL5200_REV==1
-# define CONFIG_SYS_FLASH_BASE 0xFE000000
-# define CONFIG_SYS_FLASH_SIZE 0x02000000
-#elif CONFIG_TOTAL5200_REV==2
-# define CONFIG_SYS_FLASH_BASE 0xFA000000
-# define CONFIG_SYS_FLASH_SIZE 0x06000000
-#endif /* CONFIG_TOTAL5200_REV */
-
-#if defined(CONFIG_SYS_LOWBOOT)
-# define CONFIG_ENV_ADDR 0xFE040000
-#else /* CONFIG_SYS_LOWBOOT */
-# define CONFIG_ENV_ADDR 0xFFF40000
-#endif /* CONFIG_SYS_LOWBOOT */
-
-/*
- * Environment settings
- */
-#define CONFIG_ENV_IS_IN_FLASH 1
-#define CONFIG_ENV_SIZE 0x40000
-#define CONFIG_ENV_SECT_SIZE 0x40000
-#define CONFIG_ENV_OVERWRITE 1
-
-/*
- * Memory map
- */
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
-#define CONFIG_SYS_MBAR 0xF0000000 /* 64 kB */
-#define CONFIG_SYS_FPGA_BASE 0xF0010000 /* 64 kB */
-#define CONFIG_SYS_CPLD_BASE 0xF0020000 /* 64 kB */
-#define CONFIG_SYS_LCD_BASE 0xF1000000 /* 4096 kB */
-
-/* Use SRAM until RAM will be available */
-#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
-#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE /* Size of used area in DPRAM */
-
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
-#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
-# define CONFIG_SYS_RAMBOOT 1
-#endif
-
-#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
-#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-
-/*
- * Ethernet configuration
- */
-#define CONFIG_MPC5xxx_FEC 1
-#define CONFIG_MPC5xxx_FEC_SEVENWIRE
-/* dummy, 7-wire FEC does not have phy address */
-#define CONFIG_PHY_ADDR 0x00
-
-/*
- * GPIO configuration
- *
- * CS1: SDRAM CS1 disabled, gpio_wkup_6 enabled 0
- * Reserved 0
- * ALTs: CAN1/2 on PSC2, SPI on PSC3 00
- * CS7: Interrupt GPIO on PSC3_5 0
- * CS8: Interrupt GPIO on PSC3_4 0
- * ATA: reset default, changed in ATA driver 00
- * IR_USB_CLK: IrDA/USB 48MHz clock gen. int., pin is GPIO 0
- * IRDA: reset default, changed in IrDA driver 000
- * ETHER: reset default, changed in Ethernet driver 0000
- * PCI_DIS: reset default, changed in PCI driver 0
- * USB_SE: reset default, changed in USB driver 0
- * USB: reset default, changed in USB driver 00
- * PSC3: SPI and UART functionality without CD 1100
- * Reserved 0
- * PSC2: CAN1/2 001
- * Reserved 0
- * PSC1: reset default, changed in AC'97 driver 000
- *
- */
-#define CONFIG_SYS_GPS_PORT_CONFIG 0x00000C10
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
-
-#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
-
-#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
-#if defined(CONFIG_CMD_KGDB)
-# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
-#endif
-
-
-/*
- * Various low-level settings
- */
-#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
-#define CONFIG_SYS_HID0_FINAL HID0_ICE
-
-#if CONFIG_TOTAL5200_REV==1
-# define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
-# define CONFIG_SYS_BOOTCS_SIZE 0x02000000 /* 32 MB */
-# define CONFIG_SYS_BOOTCS_CFG 0x0004DF00 /* 4WS, MX, AL, CE, AS_25, DS_32 */
-# define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
-# define CONFIG_SYS_CS0_SIZE 0x02000000 /* 32 MB */
-#else
-# define CONFIG_SYS_BOOTCS_START (CONFIG_SYS_CS4_START + CONFIG_SYS_CS4_SIZE)
-# define CONFIG_SYS_BOOTCS_SIZE 0x02000000 /* 32 MB */
-# define CONFIG_SYS_BOOTCS_CFG 0x0004DF00 /* 4WS, MX, AL, CE, AS_25, DS_32 */
-# define CONFIG_SYS_CS4_START (CONFIG_SYS_CS5_START + CONFIG_SYS_CS5_SIZE)
-# define CONFIG_SYS_CS4_SIZE 0x02000000 /* 32 MB */
-# define CONFIG_SYS_CS4_CFG 0x0004DF00 /* 4WS, MX, AL, CE, AS_25, DS_32 */
-# define CONFIG_SYS_CS5_START CONFIG_SYS_FLASH_BASE
-# define CONFIG_SYS_CS5_SIZE 0x02000000 /* 32 MB */
-# define CONFIG_SYS_CS5_CFG 0x0004DF00 /* 4WS, MX, AL, CE, AS_25, DS_32 */
-#endif
-
-#define CONFIG_SYS_CS1_START CONFIG_SYS_FPGA_BASE
-#define CONFIG_SYS_CS1_SIZE 0x00010000 /* 64 kB */
-#define CONFIG_SYS_CS1_CFG 0x0019FF00 /* 25WS, MX, AL, AA, CE, AS_25, DS_32 */
-
-#define CONFIG_SYS_CS2_START CONFIG_SYS_LCD_BASE
-#define CONFIG_SYS_CS2_SIZE 0x00400000 /* 4096 kB */
-#define CONFIG_SYS_CS2_CFG 0x0032FD0C /* 50WS, MX, AL, AA, CE, AS_25, DS_16, endian swapping */
-
-#if CONFIG_TOTAL5200_REV==1
-# define CONFIG_SYS_CS3_START CONFIG_SYS_CPLD_BASE
-# define CONFIG_SYS_CS3_SIZE 0x00010000 /* 64 kB */
-# define CONFIG_SYS_CS3_CFG 0x000ADF00 /* 10WS, MX, AL, CE, AS_25, DS_32 */
-#else
-# define CONFIG_SYS_CS3_START CONFIG_SYS_CPLD_BASE
-# define CONFIG_SYS_CS3_SIZE 0x00010000 /* 64 kB */
-# define CONFIG_SYS_CS3_CFG 0x000AD800 /* 10WS, MX, AL, CE, AS_24, DS_8 */
-#endif
-
-#define CONFIG_SYS_CS_BURST 0x00000000
-#define CONFIG_SYS_CS_DEADCYCLE 0x33333333
-
-/*-----------------------------------------------------------------------
- * USB stuff
- *-----------------------------------------------------------------------
- */
-#define CONFIG_USB_CLOCK 0x0001BBBB
-#define CONFIG_USB_CONFIG 0x00001000
-
-/*-----------------------------------------------------------------------
- * IDE/ATA stuff Supports IDE harddisk
- *-----------------------------------------------------------------------
- */
-
-#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
-
-#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
-#undef CONFIG_IDE_LED /* LED for ide not supported */
-
-#define CONFIG_IDE_RESET /* reset for ide supported */
-#define CONFIG_IDE_PREINIT
-
-#define CONFIG_SYS_ATA_CS_ON_I2C2
-#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
-#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
-
-#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
-
-#define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA
-
-/* Offset for data I/O */
-#define CONFIG_SYS_ATA_DATA_OFFSET (0x0060)
-
-/* Offset for normal register accesses */
-#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET)
-
-/* Offset for alternate registers */
-#define CONFIG_SYS_ATA_ALT_OFFSET (0x005C)
-
-/* Interval between registers */
-#define CONFIG_SYS_ATA_STRIDE 4
-
-#endif /* __CONFIG_H */
--
1.9.1
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [U-Boot] [PATCH 7/8] powerpc: mpc5xxx: PM520 board support
2015-01-22 15:24 [U-Boot] [PATCH 0/8] powerpc: drop more non-generic boards Masahiro Yamada
` (5 preceding siblings ...)
2015-01-22 15:24 ` [U-Boot] [PATCH 6/8] powerpc: mpc5xxx: remove Total5200 board support Masahiro Yamada
@ 2015-01-22 15:24 ` Masahiro Yamada
2015-01-23 21:57 ` Tom Rini
2015-01-22 15:24 ` [U-Boot] [PATCH 8/8] powerpc: remove icecube_5200, Lite5200, cpci5200, mecp5200, pf5200 Masahiro Yamada
7 siblings, 1 reply; 19+ messages in thread
From: Masahiro Yamada @ 2015-01-22 15:24 UTC (permalink / raw)
To: u-boot
This board is still a non-generic board.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Josef Wagner <Wagner@Microsys.de>
---
arch/powerpc/cpu/mpc5xxx/Kconfig | 4 -
board/pm520/Kconfig | 9 -
board/pm520/MAINTAINERS | 9 -
board/pm520/Makefile | 8 -
board/pm520/flash.c | 659 ------------------------------------
board/pm520/mt46v16m16-75.h | 16 -
board/pm520/mt48lc16m16a2-75.h | 14 -
board/pm520/pm520.c | 253 --------------
configs/PM520_DDR_defconfig | 4 -
configs/PM520_ROMBOOT_DDR_defconfig | 4 -
configs/PM520_ROMBOOT_defconfig | 4 -
configs/PM520_defconfig | 3 -
doc/README.scrapyard | 1 +
include/configs/PM520.h | 342 -------------------
14 files changed, 1 insertion(+), 1329 deletions(-)
delete mode 100644 board/pm520/Kconfig
delete mode 100644 board/pm520/MAINTAINERS
delete mode 100644 board/pm520/Makefile
delete mode 100644 board/pm520/flash.c
delete mode 100644 board/pm520/mt46v16m16-75.h
delete mode 100644 board/pm520/mt48lc16m16a2-75.h
delete mode 100644 board/pm520/pm520.c
delete mode 100644 configs/PM520_DDR_defconfig
delete mode 100644 configs/PM520_ROMBOOT_DDR_defconfig
delete mode 100644 configs/PM520_ROMBOOT_defconfig
delete mode 100644 configs/PM520_defconfig
delete mode 100644 include/configs/PM520.h
diff --git a/arch/powerpc/cpu/mpc5xxx/Kconfig b/arch/powerpc/cpu/mpc5xxx/Kconfig
index 9585c80..077225a 100644
--- a/arch/powerpc/cpu/mpc5xxx/Kconfig
+++ b/arch/powerpc/cpu/mpc5xxx/Kconfig
@@ -44,9 +44,6 @@ config TARGET_MOTIONPRO
config TARGET_MUNICES
bool "Support munices"
-config TARGET_PM520
- bool "Support PM520"
-
config TARGET_V38B
bool "Support v38b"
@@ -115,7 +112,6 @@ source "board/jupiter/Kconfig"
source "board/motionpro/Kconfig"
source "board/munices/Kconfig"
source "board/phytec/pcm030/Kconfig"
-source "board/pm520/Kconfig"
source "board/tqc/tqm5200/Kconfig"
source "board/v38b/Kconfig"
diff --git a/board/pm520/Kconfig b/board/pm520/Kconfig
deleted file mode 100644
index 3f0a258..0000000
--- a/board/pm520/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_PM520
-
-config SYS_BOARD
- default "pm520"
-
-config SYS_CONFIG_NAME
- default "PM520"
-
-endif
diff --git a/board/pm520/MAINTAINERS b/board/pm520/MAINTAINERS
deleted file mode 100644
index 7b255bc..0000000
--- a/board/pm520/MAINTAINERS
+++ /dev/null
@@ -1,9 +0,0 @@
-PM520 BOARD
-M: Josef Wagner <Wagner@Microsys.de>
-S: Maintained
-F: board/pm520/
-F: include/configs/PM520.h
-F: configs/PM520_defconfig
-F: configs/PM520_DDR_defconfig
-F: configs/PM520_ROMBOOT_defconfig
-F: configs/PM520_ROMBOOT_DDR_defconfig
diff --git a/board/pm520/Makefile b/board/pm520/Makefile
deleted file mode 100644
index 8b5a7eb..0000000
--- a/board/pm520/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2003-2006
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := pm520.o flash.o
diff --git a/board/pm520/flash.c b/board/pm520/flash.c
deleted file mode 100644
index 89c9f02..0000000
--- a/board/pm520/flash.c
+++ /dev/null
@@ -1,659 +0,0 @@
-/*
- * (C) Copyright 2001
- * Kyle Harris, Nexus Technologies, Inc. kharris at nexus-tech.net
- *
- * (C) Copyright 2001-2004
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <linux/byteorder/swab.h>
-
-
-flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
-
-/* Board support for 1 or 2 flash devices */
-#define FLASH_PORT_WIDTH32
-#undef FLASH_PORT_WIDTH16
-
-#ifdef FLASH_PORT_WIDTH16
-#define FLASH_PORT_WIDTH ushort
-#define FLASH_PORT_WIDTHV vu_short
-#define SWAP(x) (x)
-#else
-#define FLASH_PORT_WIDTH ulong
-#define FLASH_PORT_WIDTHV vu_long
-#define SWAP(x) (x)
-#endif
-
-/* Intel-compatible flash ID */
-#define INTEL_COMPAT 0x00890089
-#define INTEL_ALT 0x00B000B0
-
-/* Intel-compatible flash commands */
-#define INTEL_PROGRAM 0x00100010
-#define INTEL_ERASE 0x00200020
-#define INTEL_CLEAR 0x00500050
-#define INTEL_LOCKBIT 0x00600060
-#define INTEL_PROTECT 0x00010001
-#define INTEL_STATUS 0x00700070
-#define INTEL_READID 0x00900090
-#define INTEL_CONFIRM 0x00D000D0
-#define INTEL_RESET 0xFFFFFFFF
-
-/* Intel-compatible flash status bits */
-#define INTEL_FINISHED 0x00800080
-#define INTEL_OK 0x00800080
-
-#define FPW FLASH_PORT_WIDTH
-#define FPWV FLASH_PORT_WIDTHV
-
-#define mb() __asm__ __volatile__ ("" : : : "memory")
-
-/*-----------------------------------------------------------------------
- * Functions
- */
-static ulong flash_get_size (FPW *addr, flash_info_t *info);
-static int write_data (flash_info_t *info, ulong dest, FPW data);
-static void flash_get_offsets (ulong base, flash_info_t *info);
-void inline spin_wheel (void);
-static void flash_sync_real_protect (flash_info_t * info);
-static unsigned char intel_sector_protected (flash_info_t *info, ushort sector);
-
-/*-----------------------------------------------------------------------
- */
-
-unsigned long flash_init (void)
-{
- int i;
- ulong size = 0;
- extern void flash_preinit(void);
- extern void flash_afterinit(ulong, ulong);
- ulong flashbase = CONFIG_SYS_FLASH_BASE;
-
- flash_preinit();
-
- for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
- switch (i) {
- case 0:
- memset(&flash_info[i], 0, sizeof(flash_info_t));
- flash_get_size ((FPW *) flashbase, &flash_info[i]);
- flash_get_offsets (flash_info[i].start[0], &flash_info[i]);
- break;
- default:
- panic ("configured to many flash banks!\n");
- break;
- }
- size += flash_info[i].size;
-
- /* get the h/w and s/w protection status in sync */
- flash_sync_real_protect(&flash_info[i]);
- }
-
- /* Protect monitor and environment sectors
- */
-#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
-#ifndef CONFIG_BOOT_ROM
- flash_protect ( FLAG_PROTECT_SET,
- CONFIG_SYS_MONITOR_BASE,
- CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1,
- &flash_info[0] );
-#endif
-#endif
-
-#ifdef CONFIG_ENV_IS_IN_FLASH
- flash_protect ( FLAG_PROTECT_SET,
- CONFIG_ENV_ADDR,
- CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0] );
-#endif
-
- flash_afterinit(flash_info[0].start[0], flash_info[0].size);
-
- return size;
-}
-
-/*-----------------------------------------------------------------------
- */
-static void flash_get_offsets (ulong base, flash_info_t *info)
-{
- int i;
-
- if (info->flash_id == FLASH_UNKNOWN) {
- return;
- }
-
- if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
- for (i = 0; i < info->sector_count; i++) {
- info->start[i] = base + (i * PHYS_FLASH_SECT_SIZE);
- }
- }
-}
-
-/*-----------------------------------------------------------------------
- */
-void flash_print_info (flash_info_t *info)
-{
- int i;
-
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("missing or unknown FLASH type\n");
- return;
- }
-
- switch (info->flash_id & FLASH_VENDMASK) {
- case FLASH_MAN_INTEL:
- printf ("INTEL ");
- break;
- default:
- printf ("Unknown Vendor ");
- break;
- }
-
- switch (info->flash_id & FLASH_TYPEMASK) {
- case FLASH_28F256J3A:
- printf ("28F256J3A\n");
- break;
-
- case FLASH_28F128J3A:
- printf ("28F128J3A\n");
- break;
-
- case FLASH_28F640J3A:
- printf ("28F640J3A\n");
- break;
-
- case FLASH_28F320J3A:
- printf ("28F320J3A\n");
- break;
-
- default:
- printf ("Unknown Chip Type\n");
- break;
- }
-
- printf (" Size: %ld MB in %d Sectors\n",
- info->size >> 20, info->sector_count);
-
- printf (" Sector Start Addresses:");
- for (i = 0; i < info->sector_count; ++i) {
- if ((i % 5) == 0)
- printf ("\n ");
- printf (" %08lX%s",
- info->start[i],
- info->protect[i] ? " (RO)" : " ");
- }
- printf ("\n");
- return;
-}
-
-/*
- * The following code cannot be run from FLASH!
- */
-static ulong flash_get_size (FPW *addr, flash_info_t *info)
-{
- volatile FPW value;
-
- /* Write auto select command: read Manufacturer ID */
- addr[0x5555] = (FPW) 0x00AA00AA;
- addr[0x2AAA] = (FPW) 0x00550055;
- addr[0x5555] = (FPW) 0x00900090;
-
- mb ();
- udelay(100);
-
- value = addr[0];
-
- switch (value) {
-
- case (FPW) INTEL_MANUFACT:
- info->flash_id = FLASH_MAN_INTEL;
- break;
-
- default:
- info->flash_id = FLASH_UNKNOWN;
- info->sector_count = 0;
- info->size = 0;
- addr[0] = (FPW) 0x00FF00FF; /* restore read mode */
- return (0); /* no or unknown flash */
- }
-
- mb ();
- value = addr[1]; /* device ID */
-
- switch (value) {
-
- case (FPW) INTEL_ID_28F256J3A:
- info->flash_id += FLASH_28F256J3A;
- /* In U-Boot we support only 32 MB (no bank-switching) */
- info->sector_count = 256 / 2;
- info->size = 0x04000000 / 2;
- info->start[0] = CONFIG_SYS_FLASH_BASE + 0x02000000;
- break; /* => 32 MB */
-
- case (FPW) INTEL_ID_28F128J3A:
- info->flash_id += FLASH_28F128J3A;
- info->sector_count = 128;
- info->size = 0x02000000;
- info->start[0] = CONFIG_SYS_FLASH_BASE + 0x02000000;
- break; /* => 32 MB */
-
- case (FPW) INTEL_ID_28F640J3A:
- info->flash_id += FLASH_28F640J3A;
- info->sector_count = 64;
- info->size = 0x01000000;
- info->start[0] = CONFIG_SYS_FLASH_BASE + 0x03000000;
- break; /* => 16 MB */
-
- case (FPW) INTEL_ID_28F320J3A:
- info->flash_id += FLASH_28F320J3A;
- info->sector_count = 32;
- info->size = 0x800000;
- info->start[0] = CONFIG_SYS_FLASH_BASE + 0x03800000;
- break; /* => 8 MB */
-
- default:
- info->flash_id = FLASH_UNKNOWN;
- break;
- }
-
- if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) {
- printf ("** ERROR: sector count %d > max (%d) **\n",
- info->sector_count, CONFIG_SYS_MAX_FLASH_SECT);
- info->sector_count = CONFIG_SYS_MAX_FLASH_SECT;
- }
-
- addr[0] = (FPW) 0x00FF00FF; /* restore read mode */
-
- return (info->size);
-}
-
-
-/*
- * This function gets the u-boot flash sector protection status
- * (flash_info_t.protect[]) in sync with the sector protection
- * status stored in hardware.
- */
-static void flash_sync_real_protect (flash_info_t * info)
-{
- int i;
-
- switch (info->flash_id & FLASH_TYPEMASK) {
-
- case FLASH_28F256J3A:
- case FLASH_28F128J3A:
- case FLASH_28F640J3A:
- case FLASH_28F320J3A:
- for (i = 0; i < info->sector_count; ++i) {
- info->protect[i] = intel_sector_protected(info, i);
- }
- break;
- default:
- /* no h/w protect support */
- break;
- }
-}
-
-
-/*
- * checks if "sector" in bank "info" is protected. Should work on intel
- * strata flash chips 28FxxxJ3x in 8-bit mode.
- * Returns 1 if sector is protected (or timed-out while trying to read
- * protection status), 0 if it is not.
- */
-static unsigned char intel_sector_protected (flash_info_t *info, ushort sector)
-{
- FPWV *addr;
- FPWV *lock_conf_addr;
- ulong start;
- unsigned char ret;
-
- /*
- * first, wait for the WSM to be finished. The rationale for
- * waiting for the WSM to become idle for at most
- * CONFIG_SYS_FLASH_ERASE_TOUT is as follows. The WSM can be busy
- * because of: (1) erase, (2) program or (3) lock bit
- * configuration. So we just wait for the longest timeout of
- * the (1)-(3), i.e. the erase timeout.
- */
-
- /* wait at least 35ns (W12) before issuing Read Status Register */
- udelay(1);
- addr = (FPWV *) info->start[sector];
- *addr = (FPW) INTEL_STATUS;
-
- start = get_timer (0);
- while ((*addr & (FPW) INTEL_FINISHED) != (FPW) INTEL_FINISHED) {
- if (get_timer (start) > CONFIG_SYS_FLASH_ERASE_TOUT) {
- *addr = (FPW) INTEL_RESET; /* restore read mode */
- printf("WSM busy too long, can't get prot status\n");
- return 1;
- }
- }
-
- /* issue the Read Identifier Codes command */
- *addr = (FPW) INTEL_READID;
-
- /* wait at least 35ns (W12) before reading */
- udelay(1);
-
- /* Intel example code uses offset of 2 for 16 bit flash */
- lock_conf_addr = (FPWV *) info->start[sector] + 2;
- ret = (*lock_conf_addr & (FPW) INTEL_PROTECT) ? 1 : 0;
-
- /* put flash back in read mode */
- *addr = (FPW) INTEL_RESET;
-
- return ret;
-}
-
-/*-----------------------------------------------------------------------
- */
-
-int flash_erase (flash_info_t *info, int s_first, int s_last)
-{
- int flag, prot, sect;
- ulong type, start;
- int rcode = 0;
-
- if ((s_first < 0) || (s_first > s_last)) {
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("- missing\n");
- } else {
- printf ("- no sectors to erase\n");
- }
- return 1;
- }
-
- type = (info->flash_id & FLASH_VENDMASK);
- if ((type != FLASH_MAN_INTEL)) {
- printf ("Can't erase unknown flash type %08lx - aborted\n",
- info->flash_id);
- return 1;
- }
-
- prot = 0;
- for (sect = s_first; sect <= s_last; ++sect) {
- if (info->protect[sect]) {
- prot++;
- }
- }
-
- if (prot) {
- printf ("- Warning: %d protected sectors will not be erased!\n",
- prot);
- } else {
- printf ("\n");
- }
-
- start = get_timer (0);
-
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts ();
-
- /* Start erase on unprotected sectors */
- for (sect = s_first; sect <= s_last; sect++) {
- if (info->protect[sect] == 0) { /* not protected */
- FPWV *addr = (FPWV *) (info->start[sect]);
- FPW status;
-
- printf ("Erasing sector %2d ... ", sect);
-
- /* arm simple, non interrupt dependent timer */
- start = get_timer(0);
-
- *addr = (FPW) 0x00500050; /* clear status register */
- *addr = (FPW) 0x00200020; /* erase setup */
- *addr = (FPW) 0x00D000D0; /* erase confirm */
-
- while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
- if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT) {
- printf ("Timeout\n");
- *addr = (FPW) 0x00B000B0; /* suspend erase */
- *addr = (FPW) 0x00FF00FF; /* reset to read mode */
- rcode = 1;
- break;
- }
- }
-
- *addr = 0x00500050; /* clear status register cmd. */
- *addr = 0x00FF00FF; /* resest to read mode */
-
- printf (" done\n");
- }
- }
-
- if (flag)
- enable_interrupts();
-
- return rcode;
-}
-
-/*-----------------------------------------------------------------------
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- * 4 - Flash not identified
- */
-
-int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
-{
- ulong cp, wp;
- FPW data;
- int count, i, l, rc, port_width;
-
- if (info->flash_id == FLASH_UNKNOWN) {
- return 4;
- }
-/* get lower word aligned address */
-#ifdef FLASH_PORT_WIDTH16
- wp = (addr & ~1);
- port_width = 2;
-#else
- wp = (addr & ~3);
- port_width = 4;
-#endif
-
- /*
- * handle unaligned start bytes
- */
- if ((l = addr - wp) != 0) {
- data = 0;
- for (i = 0, cp = wp; i < l; ++i, ++cp) {
- data = (data << 8) | (*(uchar *) cp);
- }
- for (; i < port_width && cnt > 0; ++i) {
- data = (data << 8) | *src++;
- --cnt;
- ++cp;
- }
- for (; cnt == 0 && i < port_width; ++i, ++cp) {
- data = (data << 8) | (*(uchar *) cp);
- }
-
- if ((rc = write_data (info, wp, SWAP (data))) != 0) {
- return (rc);
- }
- wp += port_width;
- }
-
- /*
- * handle word aligned part
- */
- count = 0;
- while (cnt >= port_width) {
- data = 0;
- for (i = 0; i < port_width; ++i) {
- data = (data << 8) | *src++;
- }
- if ((rc = write_data (info, wp, SWAP (data))) != 0) {
- return (rc);
- }
- wp += port_width;
- cnt -= port_width;
- if (count++ > 0x800) {
- spin_wheel ();
- count = 0;
- }
- }
-
- if (cnt == 0) {
- return (0);
- }
-
- /*
- * handle unaligned tail bytes
- */
- data = 0;
- for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) {
- data = (data << 8) | *src++;
- --cnt;
- }
- for (; i < port_width; ++i, ++cp) {
- data = (data << 8) | (*(uchar *) cp);
- }
-
- return (write_data (info, wp, SWAP (data)));
-}
-
-/*-----------------------------------------------------------------------
- * Write a word or halfword to Flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-static int write_data (flash_info_t *info, ulong dest, FPW data)
-{
- FPWV *addr = (FPWV *) dest;
- ulong status;
- ulong start;
- int flag;
- int rcode = 0;
-
- /* Check if Flash is (sufficiently) erased */
- if ((*addr & data) != data) {
- printf ("not erased@%08lx (%lx)\n", (ulong) addr, *addr);
- return (2);
- }
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts ();
-
- *addr = (FPW) 0x00400040; /* write setup */
- *addr = data;
-
- /* arm simple, non interrupt dependent timer */
- start = get_timer(0);
-
- /* wait while polling the status register */
- while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
- if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
- rcode = 1;
- break;
- }
- }
-
- *addr = (FPW) 0x00FF00FF; /* restore read mode */
-
- if (flag)
- enable_interrupts();
-
- return rcode;
-}
-
-void inline spin_wheel (void)
-{
- static int p = 0;
- static char w[] = "\\/-";
-
- printf ("\010%c", w[p]);
- (++p == 3) ? (p = 0) : 0;
-}
-
-/*-----------------------------------------------------------------------
- * Set/Clear sector's lock bit, returns:
- * 0 - OK
- * 1 - Error (timeout, voltage problems, etc.)
- */
-int flash_real_protect (flash_info_t *info, long sector, int prot)
-{
- ulong start;
- int i;
- int rc = 0;
- vu_long *addr = (vu_long *)(info->start[sector]);
- int flag = disable_interrupts();
-
- *addr = INTEL_CLEAR; /* Clear status register */
- if (prot) { /* Set sector lock bit */
- *addr = INTEL_LOCKBIT; /* Sector lock bit */
- *addr = INTEL_PROTECT; /* set */
- }
- else { /* Clear sector lock bit */
- *addr = INTEL_LOCKBIT; /* All sectors lock bits */
- *addr = INTEL_CONFIRM; /* clear */
- }
-
- start = get_timer(0);
-
- while ((*addr & INTEL_FINISHED) != INTEL_FINISHED) {
- if (get_timer(start) > CONFIG_SYS_FLASH_UNLOCK_TOUT) {
- printf("Flash lock bit operation timed out\n");
- rc = 1;
- break;
- }
- }
-
- if (*addr != INTEL_OK) {
- printf("Flash lock bit operation failed at %08X, CSR=%08X\n",
- (uint)addr, (uint)*addr);
- rc = 1;
- }
-
- if (!rc)
- info->protect[sector] = prot;
-
- /*
- * Clear lock bit command clears all sectors lock bits, so
- * we have to restore lock bits of protected sectors.
- * WARNING: code below re-locks sectors only for one bank (info).
- * This causes problems on boards where several banks share
- * the same chip, as sectors in othere banks will be unlocked
- * but not re-locked. It works fine on pm520 though, as there
- * is only one chip and one bank.
- */
- if (!prot)
- {
- for (i = 0; i < info->sector_count; i++)
- {
- if (info->protect[i])
- {
- start = get_timer(0);
- addr = (vu_long *)(info->start[i]);
- *addr = INTEL_LOCKBIT; /* Sector lock bit */
- *addr = INTEL_PROTECT; /* set */
- while ((*addr & INTEL_FINISHED) != INTEL_FINISHED)
- {
- if (get_timer(start) > CONFIG_SYS_FLASH_UNLOCK_TOUT)
- {
- printf("Flash lock bit operation timed out\n");
- rc = 1;
- break;
- }
- }
- }
- }
- /*
- * get the s/w sector protection status in sync with the h/w,
- * in case something went wrong during the re-locking.
- */
- flash_sync_real_protect(info); /* resets flash to read mode */
- }
-
- if (flag)
- enable_interrupts();
-
- *addr = INTEL_RESET; /* Reset to read array mode */
-
- return rc;
-}
diff --git a/board/pm520/mt46v16m16-75.h b/board/pm520/mt46v16m16-75.h
deleted file mode 100644
index 9068fbf..0000000
--- a/board/pm520/mt46v16m16-75.h
+++ /dev/null
@@ -1,16 +0,0 @@
-/*
- * (C) Copyright 2004
- * Mark Jonas, Freescale Semiconductor, mark.jonas at motorola.com.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#define SDRAM_DDR 1 /* is DDR */
-
-/* Settings for XLB = 132 MHz */
-#define SDRAM_MODE 0x018D0000
-#define SDRAM_EMODE 0x40090000
-#define SDRAM_CONTROL 0x714f0f00
-#define SDRAM_CONFIG1 0x73722930
-#define SDRAM_CONFIG2 0x47770000
-#define SDRAM_TAPDELAY 0x10000000
diff --git a/board/pm520/mt48lc16m16a2-75.h b/board/pm520/mt48lc16m16a2-75.h
deleted file mode 100644
index 0133eaa..0000000
--- a/board/pm520/mt48lc16m16a2-75.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/*
- * (C) Copyright 2004
- * Mark Jonas, Freescale Semiconductor, mark.jonas at motorola.com.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#define SDRAM_DDR 0 /* is SDR */
-
-/* Settings for XLB = 132 MHz */
-#define SDRAM_MODE 0x00CD0000
-#define SDRAM_CONTROL 0x504F0000
-#define SDRAM_CONFIG1 0xD2322800
-#define SDRAM_CONFIG2 0x8AD70000
diff --git a/board/pm520/pm520.c b/board/pm520/pm520.c
deleted file mode 100644
index 4ec4505..0000000
--- a/board/pm520/pm520.c
+++ /dev/null
@@ -1,253 +0,0 @@
-/*
- * (C) Copyright 2003-2004
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- *
- * (C) Copyright 2004
- * Mark Jonas, Freescale Semiconductor, mark.jonas at motorola.com.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <mpc5xxx.h>
-#include <pci.h>
-#include <netdev.h>
-
-#if defined(CONFIG_MPC5200_DDR)
-#include "mt46v16m16-75.h"
-#else
-#include "mt48lc16m16a2-75.h"
-#endif
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#ifndef CONFIG_SYS_RAMBOOT
-static void sdram_start (int hi_addr)
-{
- long hi_addr_bit = hi_addr ? 0x01000000 : 0;
-
- /* unlock mode register */
- *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | hi_addr_bit;
- __asm__ volatile ("sync");
-
- /* precharge all banks */
- *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
- __asm__ volatile ("sync");
-
-#if SDRAM_DDR
- /* set mode register: extended mode */
- *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
- __asm__ volatile ("sync");
-
- /* set mode register: reset DLL */
- *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
- __asm__ volatile ("sync");
-#endif
-
- /* precharge all banks */
- *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
- __asm__ volatile ("sync");
-
- /* auto refresh */
- *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | hi_addr_bit;
- __asm__ volatile ("sync");
-
- /* set mode register */
- *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE;
- __asm__ volatile ("sync");
-
- /* normal operation */
- *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
- __asm__ volatile ("sync");
-}
-#endif
-
-/*
- * ATTENTION: Although partially referenced initdram does NOT make real use
- * use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE
- * is something else than 0x00000000.
- */
-
-phys_size_t initdram (int board_type)
-{
- ulong dramsize = 0;
- ulong dramsize2 = 0;
-#ifndef CONFIG_SYS_RAMBOOT
- ulong test1, test2;
-
- /* setup SDRAM chip selects */
- *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e;/* 2G at 0x0 */
- *(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x80000000;/* disabled */
- __asm__ volatile ("sync");
-
- /* setup config registers */
- *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
- *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
- __asm__ volatile ("sync");
-
-#if SDRAM_DDR
- /* set tap delay */
- *(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
- __asm__ volatile ("sync");
-#endif
-
- /* find RAM size using SDRAM CS0 only */
- sdram_start(0);
- test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
- sdram_start(1);
- test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
- if (test1 > test2) {
- sdram_start(0);
- dramsize = test1;
- } else {
- dramsize = test2;
- }
-
- /* memory smaller than 1MB is impossible */
- if (dramsize < (1 << 20)) {
- dramsize = 0;
- }
-
- /* set SDRAM CS0 size according to the amount of RAM found */
- if (dramsize > 0) {
- *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 + __builtin_ffs(dramsize >> 20) - 1;
- } else {
- *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
- }
-
- /* let SDRAM CS1 start right after CS0 */
- *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;/* 2G */
-
- /* find RAM size using SDRAM CS1 only */
- if (!dramsize)
- sdram_start(0);
- test2 = test1 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
- if (!dramsize) {
- sdram_start(1);
- test2 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
- }
- if (test1 > test2) {
- sdram_start(0);
- dramsize2 = test1;
- } else {
- dramsize2 = test2;
- }
-
- /* memory smaller than 1MB is impossible */
- if (dramsize2 < (1 << 20)) {
- dramsize2 = 0;
- }
-
- /* set SDRAM CS1 size according to the amount of RAM found */
- if (dramsize2 > 0) {
- *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize
- | (0x13 + __builtin_ffs(dramsize2 >> 20) - 1);
- } else {
- *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
- }
-
-#else /* CONFIG_SYS_RAMBOOT */
-
- /* retrieve size of memory connected to SDRAM CS0 */
- dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
- if (dramsize >= 0x13) {
- dramsize = (1 << (dramsize - 0x13)) << 20;
- } else {
- dramsize = 0;
- }
-
- /* retrieve size of memory connected to SDRAM CS1 */
- dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF;
- if (dramsize2 >= 0x13) {
- dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
- } else {
- dramsize2 = 0;
- }
-
-#endif /* CONFIG_SYS_RAMBOOT */
-
- return dramsize + dramsize2;
-}
-
-int checkboard (void)
-{
- puts ("Board: MicroSys PM520 \n");
- return 0;
-}
-
-void flash_preinit(void)
-{
- /*
- * Now, when we are in RAM, enable flash write
- * access for detection process.
- * Note that CS_BOOT cannot be cleared when
- * executing in flash.
- */
- *(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
-}
-
-void flash_afterinit(ulong start, ulong size)
-{
-#if defined(CONFIG_BOOT_ROM)
- /* adjust mapping */
- *(vu_long *)MPC5XXX_CS1_START =
- START_REG(start);
- *(vu_long *)MPC5XXX_CS1_STOP =
- STOP_REG(start, size);
-#else
- /* adjust mapping */
- *(vu_long *)MPC5XXX_BOOTCS_START = *(vu_long *)MPC5XXX_CS0_START =
- START_REG(start);
- *(vu_long *)MPC5XXX_BOOTCS_STOP = *(vu_long *)MPC5XXX_CS0_STOP =
- STOP_REG(start, size);
-#endif
-}
-
-
-extern flash_info_t flash_info[]; /* info for FLASH chips */
-
-int misc_init_r (void)
-{
- /* adjust flash start */
- gd->bd->bi_flashstart = flash_info[0].start[0];
- return (0);
-}
-
-#ifdef CONFIG_PCI
-static struct pci_controller hose;
-
-extern void pci_mpc5xxx_init(struct pci_controller *);
-
-void pci_init_board(void)
-{
- pci_mpc5xxx_init(&hose);
-}
-#endif
-
-#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET)
-
-void init_ide_reset (void)
-{
- debug ("init_ide_reset\n");
-
-}
-
-void ide_set_reset (int idereset)
-{
- debug ("ide_reset(%d)\n", idereset);
-
-}
-#endif
-
-#if defined(CONFIG_CMD_DOC)
-void doc_init (void)
-{
- doc_probe (CONFIG_SYS_DOC_BASE);
-}
-#endif
-
-int board_eth_init(bd_t *bis)
-{
- cpu_eth_init(bis); /* Built in FEC comes first */
- return pci_eth_init(bis);
-}
diff --git a/configs/PM520_DDR_defconfig b/configs/PM520_DDR_defconfig
deleted file mode 100644
index 6d6a59d..0000000
--- a/configs/PM520_DDR_defconfig
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_SYS_EXTRA_OPTIONS="MPC5200_DDR"
-CONFIG_PPC=y
-CONFIG_MPC5xxx=y
-CONFIG_TARGET_PM520=y
diff --git a/configs/PM520_ROMBOOT_DDR_defconfig b/configs/PM520_ROMBOOT_DDR_defconfig
deleted file mode 100644
index f5a40d9..0000000
--- a/configs/PM520_ROMBOOT_DDR_defconfig
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_SYS_EXTRA_OPTIONS="MPC5200_DDR,BOOT_ROM"
-CONFIG_PPC=y
-CONFIG_MPC5xxx=y
-CONFIG_TARGET_PM520=y
diff --git a/configs/PM520_ROMBOOT_defconfig b/configs/PM520_ROMBOOT_defconfig
deleted file mode 100644
index d9f9ea0..0000000
--- a/configs/PM520_ROMBOOT_defconfig
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_SYS_EXTRA_OPTIONS="BOOT_ROM"
-CONFIG_PPC=y
-CONFIG_MPC5xxx=y
-CONFIG_TARGET_PM520=y
diff --git a/configs/PM520_defconfig b/configs/PM520_defconfig
deleted file mode 100644
index 2737a8c..0000000
--- a/configs/PM520_defconfig
+++ /dev/null
@@ -1,3 +0,0 @@
-CONFIG_PPC=y
-CONFIG_MPC5xxx=y
-CONFIG_TARGET_PM520=y
diff --git a/doc/README.scrapyard b/doc/README.scrapyard
index 0c4dbd0..a8eca4b 100644
--- a/doc/README.scrapyard
+++ b/doc/README.scrapyard
@@ -12,6 +12,7 @@ The list should be sorted in reverse chronological order.
Board Arch CPU Commit Removed Last known maintainer/contact
=================================================================================================
+PM520 powerpc mpc5xxx - - Josef Wagner <Wagner@Microsys.de>
Total5200 powerpc mpc5xxx - -
CATcenter powerpc ppc4xx - -
PPChameleonEVB powerpc ppc4xx - - Andrea "llandre" Marson <andrea.marson@dave-tech.it>
diff --git a/include/configs/PM520.h b/include/configs/PM520.h
deleted file mode 100644
index de46216..0000000
--- a/include/configs/PM520.h
+++ /dev/null
@@ -1,342 +0,0 @@
-/*
- * (C) Copyright 2003-2005
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_MPC5200
-#define CONFIG_PM520 1 /* PM520 board */
-
-#define CONFIG_SYS_TEXT_BASE 0xfff00000
-
-#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33MHz */
-
-#define CONFIG_MISC_INIT_R
-
-#define CONFIG_HIGH_BATS 1 /* High BATs supported */
-
-/*
- * Serial console configuration
- */
-#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
-#define CONFIG_BAUDRATE 9600 /* ... at 9600 bps */
-#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
-
-
-/*
- * PCI Mapping:
- * 0x40000000 - 0x4fffffff - PCI Memory
- * 0x50000000 - 0x50ffffff - PCI IO Space
- */
-#define CONFIG_PCI 1
-#define CONFIG_PCI_PNP 1
-#define CONFIG_PCI_SCAN_SHOW 1
-#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
-
-#define CONFIG_PCI_MEM_BUS 0x40000000
-#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
-#define CONFIG_PCI_MEM_SIZE 0x10000000
-
-#define CONFIG_PCI_IO_BUS 0x50000000
-#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
-#define CONFIG_PCI_IO_SIZE 0x01000000
-
-#define CONFIG_MII 1
-#define CONFIG_EEPRO100 1
-#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
-#undef CONFIG_NS8382X
-
-
-/* Partitions */
-#define CONFIG_DOS_PARTITION
-
-/* USB */
-#if 1
-#define CONFIG_USB_OHCI
-#define CONFIG_USB_STORAGE
-#endif
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_BEDBUG
-#define CONFIG_CMD_DATE
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_IDE
-#define CONFIG_CMD_NFS
-#define CONFIG_CMD_SNTP
-#define CONFIG_CMD_USB
-
-#define CONFIG_CMD_PCI
-
-
-/*
- * Autobooting
- */
-#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
-
-#define CONFIG_PREBOOT "echo;" \
- "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
- "echo"
-
-#undef CONFIG_BOOTARGS
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "netdev=eth0\0" \
- "hostname=pm520\0" \
- "nfsargs=setenv bootargs root=/dev/nfs rw " \
- "nfsroot=${serverip}:${rootpath}\0" \
- "ramargs=setenv bootargs root=/dev/ram rw\0" \
- "addip=setenv bootargs ${bootargs} " \
- "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
- ":${hostname}:${netdev}:off panic=1\0" \
- "flash_nfs=run nfsargs addip;" \
- "bootm ${kernel_addr}\0" \
- "flash_self=run ramargs addip;" \
- "bootm ${kernel_addr} ${ramdisk_addr}\0" \
- "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
- "rootpath=/opt/eldk30/ppc_82xx\0" \
- "bootfile=/tftpboot/PM520/uImage\0" \
- ""
-
-#define CONFIG_BOOTCOMMAND "run flash_self"
-
-/*
- * IPB Bus clocking configuration.
- */
-#undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
-/*
- * I2C configuration
- */
-#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
-#define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #1 or #2 */
-
-#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */
-#define CONFIG_SYS_I2C_SLAVE 0x7F
-
-/*
- * EEPROM configuration
- */
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x58
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
-
-/*
- * RTC configuration
- */
-#define CONFIG_RTC_PCF8563
-#define CONFIG_SYS_I2C_RTC_ADDR 0x51
-
-#define CONFIG_SYS_DOC_BASE 0xE0000000
-#define CONFIG_SYS_DOC_SIZE 0x00100000
-
-#if defined(CONFIG_BOOT_ROM)
-/*
- * Flash configuration (8,16 or 32 MB)
- * TEXT base always at 0xFFF00000
- * ENV_ADDR always at 0xFFF40000
- * FLASH_BASE at 0xFA000000 for 64 MB
- * 0xFC000000 for 32 MB
- * 0xFD000000 for 16 MB
- * 0xFD800000 for 8 MB
- */
-#define CONFIG_SYS_FLASH_BASE 0xFA000000
-#define CONFIG_SYS_FLASH_SIZE 0x04000000
-#define CONFIG_SYS_BOOTROM_BASE 0xFFF00000
-#define CONFIG_SYS_BOOTROM_SIZE 0x00080000
-#define CONFIG_ENV_ADDR (0xFDF00000 + 0x40000)
-#else
-/*
- * Flash configuration (8,16 or 32 MB)
- * TEXT base always at 0xFFF00000
- * ENV_ADDR always at 0xFFF40000
- * FLASH_BASE at 0xFC000000 for 64 MB
- * 0xFE000000 for 32 MB
- * 0xFF000000 for 16 MB
- * 0xFF800000 for 8 MB
- */
-#define CONFIG_SYS_FLASH_BASE 0xFC000000
-#define CONFIG_SYS_FLASH_SIZE 0x04000000
-#define CONFIG_ENV_ADDR (0xFFF00000 + 0x40000)
-#endif
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */
-
-#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max num of sects on one chip */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
-#define CONFIG_SYS_FLASH_LOCK_TOUT 5 /* Timeout for Flash Set Lock Bit (in ms) */
-#define CONFIG_SYS_FLASH_UNLOCK_TOUT 10000 /* Timeout for Flash Clear Lock Bits (in ms) */
-#define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
-
-#define PHYS_FLASH_SECT_SIZE 0x00040000 /* 256 KB sectors (x2) */
-
-#undef CONFIG_FLASH_16BIT /* Flash is 32-bit */
-
-
-/*
- * Environment settings
- */
-#define CONFIG_ENV_IS_IN_FLASH 1
-#define CONFIG_ENV_SIZE 0x10000
-#define CONFIG_ENV_SECT_SIZE 0x40000
-#define CONFIG_ENV_OVERWRITE 1
-
-/*
- * Memory map
- */
-#define CONFIG_SYS_MBAR 0xf0000000
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
-
-/* Use SRAM until RAM will be available */
-#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
-#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE /* Size of used area in DPRAM */
-
-
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
-#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
-# define CONFIG_SYS_RAMBOOT 1
-#endif
-
-#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
-#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-
-/*
- * Ethernet configuration
- */
-#define CONFIG_MPC5xxx_FEC 1
-#define CONFIG_MPC5xxx_FEC_MII100
-/*
- * Define CONFIG_MPC5xxx_FEC_MII10 to force FEC@10Mb
- */
-/* #define CONFIG_MPC5xxx_FEC_MII10 */
-#define CONFIG_PHY_ADDR 0x00
-
-/*
- * GPIO configuration
- */
-#define CONFIG_SYS_GPS_PORT_CONFIG 0x10000004
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
-
-#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
-
-#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
-#if defined(CONFIG_CMD_KGDB)
-# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
-#endif
-
-/*
- * Various low-level settings
- */
-#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
-#define CONFIG_SYS_HID0_FINAL HID0_ICE
-
-#if defined(CONFIG_BOOT_ROM)
-#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_BOOTROM_BASE
-#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_BOOTROM_SIZE
-#define CONFIG_SYS_BOOTCS_CFG 0x00047800
-#define CONFIG_SYS_CS0_START CONFIG_SYS_BOOTROM_BASE
-#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_BOOTROM_SIZE
-#define CONFIG_SYS_CS1_START CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_CS1_SIZE CONFIG_SYS_FLASH_SIZE
-#define CONFIG_SYS_CS1_CFG 0x0004FF00
-#else
-#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
-#define CONFIG_SYS_BOOTCS_CFG 0x0004FF00
-#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
-#define CONFIG_SYS_CS1_START CONFIG_SYS_DOC_BASE
-#define CONFIG_SYS_CS1_SIZE CONFIG_SYS_DOC_SIZE
-#define CONFIG_SYS_CS1_CFG 0x00047800
-#endif
-
-#define CONFIG_SYS_CS_BURST 0x00000000
-#define CONFIG_SYS_CS_DEADCYCLE 0x33333333
-
-#define CONFIG_SYS_RESET_ADDRESS 0xff000000
-
-/*-----------------------------------------------------------------------
- * USB stuff
- *-----------------------------------------------------------------------
- */
-#define CONFIG_USB_CLOCK 0x0001BBBB
-#define CONFIG_USB_CONFIG 0x00005000
-
-/*-----------------------------------------------------------------------
- * IDE/ATA stuff Supports IDE harddisk
- *-----------------------------------------------------------------------
- */
-
-#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
-
-#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
-#undef CONFIG_IDE_LED /* LED for ide not supported */
-
-#undef CONFIG_IDE_RESET /* reset for ide supported */
-#define CONFIG_IDE_PREINIT
-
-#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
-#define CONFIG_SYS_IDE_MAXDEVICE 2 /* max. 2 drive per IDE bus */
-
-#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
-
-#define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA
-
-/* Offset for data I/O */
-#define CONFIG_SYS_ATA_DATA_OFFSET (0x0060)
-
-/* Offset for normal register accesses */
-#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET)
-
-/* Offset for alternate registers */
-#define CONFIG_SYS_ATA_ALT_OFFSET (0x005C)
-
-/* Interval between registers */
-#define CONFIG_SYS_ATA_STRIDE 4
-
-#endif /* __CONFIG_H */
--
1.9.1
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [U-Boot] [PATCH 8/8] powerpc: remove icecube_5200, Lite5200, cpci5200, mecp5200, pf5200
2015-01-22 15:24 [U-Boot] [PATCH 0/8] powerpc: drop more non-generic boards Masahiro Yamada
` (6 preceding siblings ...)
2015-01-22 15:24 ` [U-Boot] [PATCH 7/8] powerpc: mpc5xxx: PM520 " Masahiro Yamada
@ 2015-01-22 15:24 ` Masahiro Yamada
2015-01-23 21:57 ` Tom Rini
7 siblings, 1 reply; 19+ messages in thread
From: Masahiro Yamada @ 2015-01-22 15:24 UTC (permalink / raw)
To: u-boot
These boards are still non-generic boards.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Reinhard Arlt <reinhard.arlt@esd-electronics.com>
---
arch/powerpc/cpu/mpc5xxx/Kconfig | 16 -
arch/powerpc/cpu/mpc5xxx/pci_mpc5200.c | 14 -
board/esd/cpci5200/Kconfig | 12 -
board/esd/cpci5200/MAINTAINERS | 6 -
board/esd/cpci5200/Makefile | 14 -
board/esd/cpci5200/cpci5200.c | 284 ----------
board/esd/cpci5200/mt46v16m16-75.h | 16 -
board/esd/cpci5200/strataflash.c | 786 ---------------------------
board/esd/mecp5200/Kconfig | 12 -
board/esd/mecp5200/MAINTAINERS | 6 -
board/esd/mecp5200/Makefile | 8 -
board/esd/mecp5200/mecp5200.c | 251 ---------
board/esd/mecp5200/mt46v16m16-75.h | 16 -
board/esd/pf5200/Kconfig | 12 -
board/esd/pf5200/MAINTAINERS | 6 -
board/esd/pf5200/Makefile | 14 -
board/esd/pf5200/flash.c | 445 ---------------
board/esd/pf5200/mt46v16m16-75.h | 16 -
board/esd/pf5200/pf5200.c | 357 ------------
board/icecube/Kconfig | 9 -
board/icecube/MAINTAINERS | 21 -
board/icecube/Makefile | 8 -
board/icecube/README | 13 -
board/icecube/README.Lite5200B_low_power | 22 -
board/icecube/flash.c | 477 ----------------
board/icecube/icecube.c | 326 -----------
board/icecube/mt46v16m16-75.h | 16 -
board/icecube/mt46v32m16.h | 16 -
board/icecube/mt48lc16m16a2-75.h | 14 -
configs/Lite5200_LOWBOOT08_defconfig | 4 -
configs/Lite5200_LOWBOOT_defconfig | 4 -
configs/Lite5200_defconfig | 3 -
configs/cpci5200_defconfig | 3 -
configs/icecube_5200_DDR_LOWBOOT08_defconfig | 4 -
configs/icecube_5200_DDR_LOWBOOT_defconfig | 4 -
configs/icecube_5200_DDR_defconfig | 4 -
configs/icecube_5200_LOWBOOT08_defconfig | 4 -
configs/icecube_5200_LOWBOOT_defconfig | 4 -
configs/icecube_5200_defconfig | 3 -
configs/lite5200b_LOWBOOT_defconfig | 4 -
configs/lite5200b_PM_defconfig | 4 -
configs/lite5200b_defconfig | 4 -
configs/mecp5200_defconfig | 3 -
configs/pf5200_defconfig | 3 -
doc/README.scrapyard | 5 +
include/configs/IceCube.h | 403 --------------
include/configs/cpci5200.h | 390 -------------
include/configs/mecp5200.h | 319 -----------
include/configs/pf5200.h | 372 -------------
49 files changed, 5 insertions(+), 4752 deletions(-)
delete mode 100644 board/esd/cpci5200/Kconfig
delete mode 100644 board/esd/cpci5200/MAINTAINERS
delete mode 100644 board/esd/cpci5200/Makefile
delete mode 100644 board/esd/cpci5200/cpci5200.c
delete mode 100644 board/esd/cpci5200/mt46v16m16-75.h
delete mode 100644 board/esd/cpci5200/strataflash.c
delete mode 100644 board/esd/mecp5200/Kconfig
delete mode 100644 board/esd/mecp5200/MAINTAINERS
delete mode 100644 board/esd/mecp5200/Makefile
delete mode 100644 board/esd/mecp5200/mecp5200.c
delete mode 100644 board/esd/mecp5200/mt46v16m16-75.h
delete mode 100644 board/esd/pf5200/Kconfig
delete mode 100644 board/esd/pf5200/MAINTAINERS
delete mode 100644 board/esd/pf5200/Makefile
delete mode 100644 board/esd/pf5200/flash.c
delete mode 100644 board/esd/pf5200/mt46v16m16-75.h
delete mode 100644 board/esd/pf5200/pf5200.c
delete mode 100644 board/icecube/Kconfig
delete mode 100644 board/icecube/MAINTAINERS
delete mode 100644 board/icecube/Makefile
delete mode 100644 board/icecube/README
delete mode 100644 board/icecube/README.Lite5200B_low_power
delete mode 100644 board/icecube/flash.c
delete mode 100644 board/icecube/icecube.c
delete mode 100644 board/icecube/mt46v16m16-75.h
delete mode 100644 board/icecube/mt46v32m16.h
delete mode 100644 board/icecube/mt48lc16m16a2-75.h
delete mode 100644 configs/Lite5200_LOWBOOT08_defconfig
delete mode 100644 configs/Lite5200_LOWBOOT_defconfig
delete mode 100644 configs/Lite5200_defconfig
delete mode 100644 configs/cpci5200_defconfig
delete mode 100644 configs/icecube_5200_DDR_LOWBOOT08_defconfig
delete mode 100644 configs/icecube_5200_DDR_LOWBOOT_defconfig
delete mode 100644 configs/icecube_5200_DDR_defconfig
delete mode 100644 configs/icecube_5200_LOWBOOT08_defconfig
delete mode 100644 configs/icecube_5200_LOWBOOT_defconfig
delete mode 100644 configs/icecube_5200_defconfig
delete mode 100644 configs/lite5200b_LOWBOOT_defconfig
delete mode 100644 configs/lite5200b_PM_defconfig
delete mode 100644 configs/lite5200b_defconfig
delete mode 100644 configs/mecp5200_defconfig
delete mode 100644 configs/pf5200_defconfig
delete mode 100644 include/configs/IceCube.h
delete mode 100644 include/configs/cpci5200.h
delete mode 100644 include/configs/mecp5200.h
delete mode 100644 include/configs/pf5200.h
diff --git a/arch/powerpc/cpu/mpc5xxx/Kconfig b/arch/powerpc/cpu/mpc5xxx/Kconfig
index 077225a..9da00da 100644
--- a/arch/powerpc/cpu/mpc5xxx/Kconfig
+++ b/arch/powerpc/cpu/mpc5xxx/Kconfig
@@ -26,9 +26,6 @@ config TARGET_CM5200
config TARGET_GALAXY5200
bool "Support galaxy5200"
-config TARGET_ICECUBE
- bool "Support IceCube"
-
config TARGET_INKA4X0
bool "Support inka4x0"
@@ -47,15 +44,6 @@ config TARGET_MUNICES
config TARGET_V38B
bool "Support v38b"
-config TARGET_CPCI5200
- bool "Support cpci5200"
-
-config TARGET_MECP5200
- bool "Support mecp5200"
-
-config TARGET_PF5200
- bool "Support pf5200"
-
config TARGET_O2D
bool "Support O2D"
@@ -99,11 +87,7 @@ source "board/a4m072/Kconfig"
source "board/bc3450/Kconfig"
source "board/canmb/Kconfig"
source "board/cm5200/Kconfig"
-source "board/esd/cpci5200/Kconfig"
-source "board/esd/mecp5200/Kconfig"
-source "board/esd/pf5200/Kconfig"
source "board/galaxy5200/Kconfig"
-source "board/icecube/Kconfig"
source "board/ifm/o2dnt2/Kconfig"
source "board/inka4x0/Kconfig"
source "board/intercontrol/digsy_mtc/Kconfig"
diff --git a/arch/powerpc/cpu/mpc5xxx/pci_mpc5200.c b/arch/powerpc/cpu/mpc5xxx/pci_mpc5200.c
index a89d5fd..70b7e6e 100644
--- a/arch/powerpc/cpu/mpc5xxx/pci_mpc5200.c
+++ b/arch/powerpc/cpu/mpc5xxx/pci_mpc5200.c
@@ -33,21 +33,7 @@ static int mpc5200_read_config_dword(struct pci_controller *hose,
*(volatile u32 *)MPC5XXX_PCI_CAR = (1 << 31) | dev | offset;
eieio();
udelay(10);
-#if (defined CONFIG_PF5200 || defined CONFIG_CPCI5200)
- if (dev & 0x00ff0000) {
- u32 val;
- val = in_le16((volatile u16 *)(CONFIG_PCI_IO_PHYS+2));
- udelay(10);
- val = val << 16;
- val |= in_le16((volatile u16 *)(CONFIG_PCI_IO_PHYS+0));
- *value = val;
- } else {
- *value = in_le32((volatile u32 *)CONFIG_PCI_IO_PHYS);
- }
- udelay(10);
-#else
*value = in_le32((volatile u32 *)CONFIG_PCI_IO_PHYS);
-#endif
eieio();
*(volatile u32 *)MPC5XXX_PCI_CAR = 0;
udelay(10);
diff --git a/board/esd/cpci5200/Kconfig b/board/esd/cpci5200/Kconfig
deleted file mode 100644
index ddd9418..0000000
--- a/board/esd/cpci5200/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_CPCI5200
-
-config SYS_BOARD
- default "cpci5200"
-
-config SYS_VENDOR
- default "esd"
-
-config SYS_CONFIG_NAME
- default "cpci5200"
-
-endif
diff --git a/board/esd/cpci5200/MAINTAINERS b/board/esd/cpci5200/MAINTAINERS
deleted file mode 100644
index 184d3cc..0000000
--- a/board/esd/cpci5200/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-CPCI5200 BOARD
-M: Reinhard Arlt <reinhard.arlt@esd-electronics.com>
-S: Maintained
-F: board/esd/cpci5200/
-F: include/configs/cpci5200.h
-F: configs/cpci5200_defconfig
diff --git a/board/esd/cpci5200/Makefile b/board/esd/cpci5200/Makefile
deleted file mode 100644
index 8421f54..0000000
--- a/board/esd/cpci5200/Makefile
+++ /dev/null
@@ -1,14 +0,0 @@
-#
-# (C) Copyright 2003-2006
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-# Objects for Xilinx JTAG programming (CPLD)
-# CPLD = ../common/xilinx_jtag/lenval.o \
-# ../common/xilinx_jtag/micro.o \
-# ../common/xilinx_jtag/ports.o
-
-# obj-y = cpci5200.o flash.o $(CPLD)
-obj-y = cpci5200.o strataflash.o
diff --git a/board/esd/cpci5200/cpci5200.c b/board/esd/cpci5200/cpci5200.c
deleted file mode 100644
index 8bded0b..0000000
--- a/board/esd/cpci5200/cpci5200.c
+++ /dev/null
@@ -1,284 +0,0 @@
-/*
- * (C) Copyright 2003
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- *
- * (C) Copyright 2004
- * Mark Jonas, Freescale Semiconductor, mark.jonas at motorola.com.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * cpci5200.c - main board support/init for the esd cpci5200.
- */
-
-#include <common.h>
-#include <mpc5xxx.h>
-#include <pci.h>
-#include <command.h>
-#include <netdev.h>
-
-#include "mt46v16m16-75.h"
-
-void init_ata_reset(void);
-
-static void sdram_start(int hi_addr)
-{
- long hi_addr_bit = hi_addr ? 0x01000000 : 0;
-
- /* unlock mode register */
- *(vu_long *) MPC5XXX_SDRAM_CTRL =
- SDRAM_CONTROL | 0x80000000 | hi_addr_bit;
- __asm__ volatile ("sync");
-
- /* precharge all banks */
- *(vu_long *) MPC5XXX_SDRAM_CTRL =
- SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
- __asm__ volatile ("sync");
-
- /* set mode register: extended mode */
- *(vu_long *) MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
- __asm__ volatile ("sync");
-
- /* set mode register: reset DLL */
- *(vu_long *) MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
- __asm__ volatile ("sync");
-
- /* precharge all banks */
- *(vu_long *) MPC5XXX_SDRAM_CTRL =
- SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
- __asm__ volatile ("sync");
-
- /* auto refresh */
- *(vu_long *) MPC5XXX_SDRAM_CTRL =
- SDRAM_CONTROL | 0x80000004 | hi_addr_bit;
- __asm__ volatile ("sync");
-
- /* set mode register */
- *(vu_long *) MPC5XXX_SDRAM_MODE = SDRAM_MODE;
- __asm__ volatile ("sync");
-
- /* normal operation */
- *(vu_long *) MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
- __asm__ volatile ("sync");
-}
-
-/*
- * ATTENTION: Although partially referenced initdram does NOT make real use
- * use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE
- * is something else than 0x00000000.
- */
-
-phys_size_t initdram(int board_type)
-{
- ulong dramsize = 0;
- ulong test1, test2;
-
- /* setup SDRAM chip selects */
- *(vu_long *) MPC5XXX_SDRAM_CS0CFG = 0x0000001e; /* 2G at 0x0 */
- *(vu_long *) MPC5XXX_SDRAM_CS1CFG = 0x80000000; /* disabled */
- __asm__ volatile ("sync");
-
- /* setup config registers */
- *(vu_long *) MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
- *(vu_long *) MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
- __asm__ volatile ("sync");
-
- /* set tap delay */
- *(vu_long *) MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
- __asm__ volatile ("sync");
-
- /* find RAM size using SDRAM CS0 only */
- sdram_start(0);
- test1 = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE, 0x80000000);
- sdram_start(1);
- test2 = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE, 0x80000000);
-
- if (test1 > test2) {
- sdram_start(0);
- dramsize = test1;
- } else {
- dramsize = test2;
- }
-
- /* memory smaller than 1MB is impossible */
- if (dramsize < (1 << 20)) {
- dramsize = 0;
- }
-
- /* set SDRAM CS0 size according to the amount of RAM found */
- if (dramsize > 0) {
- *(vu_long *) MPC5XXX_SDRAM_CS0CFG =
- 0x13 + __builtin_ffs(dramsize >> 20) - 1;
- /* let SDRAM CS1 start right after CS0 */
- *(vu_long *) MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e; /* 2G */
- } else {
-#if 0
- *(vu_long *) MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
- /* let SDRAM CS1 start right after CS0 */
- *(vu_long *) MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e; /* 2G */
-#else
- *(vu_long *) MPC5XXX_SDRAM_CS0CFG =
- 0x13 + __builtin_ffs(0x08000000 >> 20) - 1;
- /* let SDRAM CS1 start right after CS0 */
- *(vu_long *) MPC5XXX_SDRAM_CS1CFG = 0x08000000 + 0x0000001e; /* 2G */
-#endif
- }
-
-#if 0
- /* find RAM size using SDRAM CS1 only */
- sdram_start(0);
- get_ram_size((ulong *) (CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
- sdram_start(1);
- get_ram_size((ulong *) (CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
- sdram_start(0);
-#endif
- /* set SDRAM CS1 size according to the amount of RAM found */
-
- *(vu_long *) MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
-
- init_ata_reset();
- return (dramsize);
-}
-
-int checkboard(void)
-{
- puts("Board: esd CPCI5200 (cpci5200)\n");
- return 0;
-}
-
-void flash_preinit(void)
-{
- /*
- * Now, when we are in RAM, enable flash write
- * access for detection process.
- * Note that CS_BOOT cannot be cleared when
- * executing in flash.
- */
- *(vu_long *) MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
-}
-
-void flash_afterinit(ulong size)
-{
- if (size == 0x02000000) {
- /* adjust mapping */
- *(vu_long *) MPC5XXX_BOOTCS_START =
- *(vu_long *) MPC5XXX_CS0_START =
- START_REG(CONFIG_SYS_BOOTCS_START | size);
- *(vu_long *) MPC5XXX_BOOTCS_STOP =
- *(vu_long *) MPC5XXX_CS0_STOP =
- STOP_REG(CONFIG_SYS_BOOTCS_START | size, size);
- }
-}
-
-#ifdef CONFIG_PCI
-static struct pci_controller hose;
-
-extern void pci_mpc5xxx_init(struct pci_controller *);
-
-void pci_init_board(void) {
- pci_mpc5xxx_init(&hose);
-}
-#endif
-
-#if defined(CONFIG_CMD_IDE) && defined (CONFIG_IDE_RESET)
-
-void init_ide_reset(void)
-{
- debug("init_ide_reset\n");
-
- /* Configure PSC1_4 as GPIO output for ATA reset */
- *(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4;
- *(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC1_4;
-}
-
-void ide_set_reset(int idereset)
-{
- debug("ide_reset(%d)\n", idereset);
-
- if (idereset) {
- *(vu_long *) MPC5XXX_WU_GPIO_DATA_O &= ~GPIO_PSC1_4;
- } else {
- *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_PSC1_4;
- }
-}
-#endif
-
-#define MPC5XXX_SIMPLEIO_GPIO_ENABLE (MPC5XXX_GPIO + 0x0004)
-#define MPC5XXX_SIMPLEIO_GPIO_DIR (MPC5XXX_GPIO + 0x000C)
-#define MPC5XXX_SIMPLEIO_GPIO_DATA_OUTPUT (MPC5XXX_GPIO + 0x0010)
-#define MPC5XXX_SIMPLEIO_GPIO_DATA_INPUT (MPC5XXX_GPIO + 0x0014)
-
-#define MPC5XXX_INTERRUPT_GPIO_ENABLE (MPC5XXX_GPIO + 0x0020)
-#define MPC5XXX_INTERRUPT_GPIO_DIR (MPC5XXX_GPIO + 0x0028)
-#define MPC5XXX_INTERRUPT_GPIO_DATA_OUTPUT (MPC5XXX_GPIO + 0x002C)
-#define MPC5XXX_INTERRUPT_GPIO_STATUS (MPC5XXX_GPIO + 0x003C)
-
-#define GPIO_WU6 0x40000000UL
-#define GPIO_USB0 0x00010000UL
-#define GPIO_USB9 0x08000000UL
-#define GPIO_USB9S 0x00080000UL
-
-void init_ata_reset(void)
-{
- debug("init_ata_reset\n");
-
- /* Configure GPIO_WU6 as GPIO output for ATA reset */
- *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_WU6;
- *(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_WU6;
- *(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_WU6;
- __asm__ volatile ("sync");
-
- *(vu_long *) MPC5XXX_SIMPLEIO_GPIO_DATA_OUTPUT &= ~GPIO_USB0;
- *(vu_long *) MPC5XXX_SIMPLEIO_GPIO_ENABLE |= GPIO_USB0;
- *(vu_long *) MPC5XXX_SIMPLEIO_GPIO_DIR |= GPIO_USB0;
- __asm__ volatile ("sync");
-
- *(vu_long *) MPC5XXX_INTERRUPT_GPIO_DATA_OUTPUT &= ~GPIO_USB9;
- *(vu_long *) MPC5XXX_INTERRUPT_GPIO_ENABLE &= ~GPIO_USB9;
- __asm__ volatile ("sync");
-
- if ((*(vu_long *) MPC5XXX_INTERRUPT_GPIO_STATUS & GPIO_USB9S) == 0) {
- *(vu_long *) MPC5XXX_SIMPLEIO_GPIO_DATA_OUTPUT |= GPIO_USB0;
- __asm__ volatile ("sync");
- }
-}
-
-int board_eth_init(bd_t *bis)
-{
- return pci_eth_init(bis);
-}
-
-int do_writepci(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
-{
- unsigned int addr;
- unsigned int size;
- int i;
- volatile unsigned long *ptr;
-
- addr = simple_strtol(argv[1], NULL, 16);
- size = simple_strtol(argv[2], NULL, 16);
-
- printf("\nWriting at addr %08x, size %08x.\n", addr, size);
-
- while (1) {
- ptr = (volatile unsigned long *)addr;
- for (i = 0; i < (size >> 2); i++) {
- *ptr++ = i;
- }
-
- /* Abort if ctrl-c was pressed */
- if (ctrlc()) {
- puts("\nAbort\n");
- return 0;
- }
- putc('.');
- }
- return 0;
-}
-
-U_BOOT_CMD(writepci, 3, 1, do_writepci,
- "Write some data to pcibus",
- "<addr> <size>\n"
- ""
-);
diff --git a/board/esd/cpci5200/mt46v16m16-75.h b/board/esd/cpci5200/mt46v16m16-75.h
deleted file mode 100644
index 63a4032..0000000
--- a/board/esd/cpci5200/mt46v16m16-75.h
+++ /dev/null
@@ -1,16 +0,0 @@
-/*
- * (C) Copyright 2004
- * Mark Jonas, Freescale Semiconductor, mark.jonas at motorola.com.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#define SDRAM_DDR 1 /* is DDR */
-
-/* Settings for XLB = 132 MHz */
-#define SDRAM_MODE 0x018D0000
-#define SDRAM_EMODE 0x40090000
-#define SDRAM_CONTROL 0x705f0f00
-#define SDRAM_CONFIG1 0x73722930
-#define SDRAM_CONFIG2 0x47770000
-#define SDRAM_TAPDELAY 0x10000000
diff --git a/board/esd/cpci5200/strataflash.c b/board/esd/cpci5200/strataflash.c
deleted file mode 100644
index 7dc2e58..0000000
--- a/board/esd/cpci5200/strataflash.c
+++ /dev/null
@@ -1,786 +0,0 @@
-/*
- * (C) Copyright 2002
- * Brad Kemp, Seranoa Networks, Brad.Kemp at seranoa.com
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/processor.h>
-#include <asm/cache.h>
-
-#undef DEBUG_FLASH
-/*
- * This file implements a Common Flash Interface (CFI) driver for U-Boot.
- * The width of the port and the width of the chips are determined at initialization.
- * These widths are used to calculate the address for access CFI data structures.
- * It has been tested on an Intel Strataflash implementation.
- *
- * References
- * JEDEC Standard JESD68 - Common Flash Interface (CFI)
- * JEDEC Standard JEP137-A Common Flash Interface (CFI) ID Codes
- * Intel Application Note 646 Common Flash Interface (CFI) and Command Sets
- * Intel 290667-008 3 Volt Intel StrataFlash Memory datasheet
- *
- * TODO
- * Use Primary Extended Query table (PRI) and Alternate Algorithm Query Table (ALT) to determine if protection is available
- * Add support for other command sets Use the PRI and ALT to determine command set
- * Verify erase and program timeouts.
- */
-
-#define FLASH_CMD_CFI 0x98
-#define FLASH_CMD_READ_ID 0x90
-#define FLASH_CMD_RESET 0xff
-#define FLASH_CMD_BLOCK_ERASE 0x20
-#define FLASH_CMD_ERASE_CONFIRM 0xD0
-#define FLASH_CMD_WRITE 0x40
-#define FLASH_CMD_PROTECT 0x60
-#define FLASH_CMD_PROTECT_SET 0x01
-#define FLASH_CMD_PROTECT_CLEAR 0xD0
-#define FLASH_CMD_CLEAR_STATUS 0x50
-#define FLASH_CMD_WRITE_TO_BUFFER 0xE8
-#define FLASH_CMD_WRITE_BUFFER_CONFIRM 0xD0
-
-#define FLASH_STATUS_DONE 0x80
-#define FLASH_STATUS_ESS 0x40
-#define FLASH_STATUS_ECLBS 0x20
-#define FLASH_STATUS_PSLBS 0x10
-#define FLASH_STATUS_VPENS 0x08
-#define FLASH_STATUS_PSS 0x04
-#define FLASH_STATUS_DPS 0x02
-#define FLASH_STATUS_R 0x01
-#define FLASH_STATUS_PROTECT 0x01
-
-#define FLASH_OFFSET_CFI 0x55
-#define FLASH_OFFSET_CFI_RESP 0x10
-#define FLASH_OFFSET_WTOUT 0x1F
-#define FLASH_OFFSET_WBTOUT 0x20
-#define FLASH_OFFSET_ETOUT 0x21
-#define FLASH_OFFSET_CETOUT 0x22
-#define FLASH_OFFSET_WMAX_TOUT 0x23
-#define FLASH_OFFSET_WBMAX_TOUT 0x24
-#define FLASH_OFFSET_EMAX_TOUT 0x25
-#define FLASH_OFFSET_CEMAX_TOUT 0x26
-#define FLASH_OFFSET_SIZE 0x27
-#define FLASH_OFFSET_INTERFACE 0x28
-#define FLASH_OFFSET_BUFFER_SIZE 0x2A
-#define FLASH_OFFSET_NUM_ERASE_REGIONS 0x2C
-#define FLASH_OFFSET_ERASE_REGIONS 0x2D
-#define FLASH_OFFSET_PROTECT 0x02
-#define FLASH_OFFSET_USER_PROTECTION 0x85
-#define FLASH_OFFSET_INTEL_PROTECTION 0x81
-
-#define FLASH_MAN_CFI 0x01000000
-
-typedef union {
- unsigned char c;
- unsigned short w;
- unsigned long l;
-} cfiword_t;
-
-typedef union {
- unsigned char *cp;
- unsigned short *wp;
- unsigned long *lp;
-} cfiptr_t;
-
-#define NUM_ERASE_REGIONS 4
-
-flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
-
-/*-----------------------------------------------------------------------
- * Functions
- */
-
-static void flash_add_byte(flash_info_t * info, cfiword_t * cword, uchar c);
-static void flash_make_cmd(flash_info_t * info, uchar cmd, void *cmdbuf);
-static void flash_write_cmd(flash_info_t * info, int sect, uchar offset,
- uchar cmd);
-static int flash_isequal(flash_info_t * info, int sect, uchar offset,
- uchar cmd);
-static int flash_isset(flash_info_t * info, int sect, uchar offset, uchar cmd);
-static int flash_detect_cfi(flash_info_t * info);
-static ulong flash_get_size(ulong base, int banknum);
-static int flash_write_cfiword(flash_info_t * info, ulong dest,
- cfiword_t cword);
-static int flash_full_status_check(flash_info_t * info, ulong sector,
- ulong tout, char *prompt);
-#ifdef CONFIG_SYS_FLASH_USE_BUFFER_WRITE
-static int flash_write_cfibuffer(flash_info_t * info, ulong dest, uchar * cp,
- int len);
-#endif
-/*-----------------------------------------------------------------------
- * create an address based on the offset and the port width
- */
-inline uchar *flash_make_addr(flash_info_t * info, int sect, int offset)
-{
- return ((uchar *) (info->start[sect] + (offset * info->portwidth)));
-}
-
-/*-----------------------------------------------------------------------
- * read a character at a port width address
- */
-inline uchar flash_read_uchar(flash_info_t * info, uchar offset)
-{
- uchar *cp;
- cp = flash_make_addr(info, 0, offset);
- return (cp[info->portwidth - 1]);
-}
-
-/*-----------------------------------------------------------------------
- * read a short word by swapping for ppc format.
- */
-ushort flash_read_ushort(flash_info_t * info, int sect, uchar offset)
-{
- uchar *addr;
-
- addr = flash_make_addr(info, sect, offset);
- return ((addr[(2 * info->portwidth) - 1] << 8) |
- addr[info->portwidth - 1]);
-
-}
-
-/*-----------------------------------------------------------------------
- * read a long word by picking the least significant byte of each maiximum
- * port size word. Swap for ppc format.
- */
-ulong flash_read_long(flash_info_t * info, int sect, uchar offset)
-{
- uchar *addr;
-
- addr = flash_make_addr(info, sect, offset);
- return ((addr[(2 * info->portwidth) - 1] << 24) |
- (addr[(info->portwidth) - 1] << 16) |
- (addr[(4 * info->portwidth) - 1] << 8) |
- addr[(3 * info->portwidth) - 1]);
-
-}
-
-/*-----------------------------------------------------------------------
- */
-unsigned long flash_init(void)
-{
- unsigned long size;
- int i;
- unsigned long address;
-
- /* The flash is positioned back to back, with the demultiplexing of the chip
- * based on the A24 address line.
- *
- */
-
- address = CONFIG_SYS_FLASH_BASE;
- size = 0;
-
- /* Init: no FLASHes known */
- for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
- flash_info[i].flash_id = FLASH_UNKNOWN;
- size += flash_info[i].size = flash_get_size(address, i);
- address += CONFIG_SYS_FLASH_INCREMENT;
- if (flash_info[i].flash_id == FLASH_UNKNOWN) {
- printf
- ("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n",
- i, flash_info[0].size, flash_info[i].size << 20);
- }
- }
-
-#if 0 /* test-only */
- /* Monitor protection ON by default */
-#if (CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE)
- for (i = 0;
- flash_info[0].start[i] < CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1;
- i++)
- (void)flash_real_protect(&flash_info[0], i, 1);
-#endif
-#endif
-
- return (size);
-}
-
-/*-----------------------------------------------------------------------
- */
-int flash_erase(flash_info_t * info, int s_first, int s_last)
-{
- int rcode = 0;
- int prot;
- int sect;
-
- if (info->flash_id != FLASH_MAN_CFI) {
- printf("Can't erase unknown flash type - aborted\n");
- return 1;
- }
- if ((s_first < 0) || (s_first > s_last)) {
- printf("- no sectors to erase\n");
- return 1;
- }
-
- prot = 0;
- for (sect = s_first; sect <= s_last; ++sect) {
- if (info->protect[sect]) {
- prot++;
- }
- }
- if (prot) {
- printf("- Warning: %d protected sectors will not be erased!\n",
- prot);
- } else {
- printf("\n");
- }
-
- for (sect = s_first; sect <= s_last; sect++) {
- if (info->protect[sect] == 0) { /* not protected */
- flash_write_cmd(info, sect, 0, FLASH_CMD_CLEAR_STATUS);
- flash_write_cmd(info, sect, 0, FLASH_CMD_BLOCK_ERASE);
- flash_write_cmd(info, sect, 0, FLASH_CMD_ERASE_CONFIRM);
-
- if (flash_full_status_check
- (info, sect, info->erase_blk_tout, "erase")) {
- rcode = 1;
- } else
- printf(".");
- }
- }
- printf(" done\n");
- return rcode;
-}
-
-/*-----------------------------------------------------------------------
- */
-void flash_print_info(flash_info_t * info)
-{
- int i;
-
- if (info->flash_id != FLASH_MAN_CFI) {
- printf("missing or unknown FLASH type\n");
- return;
- }
-
- printf("CFI conformant FLASH (%d x %d)",
- (info->portwidth << 3), (info->chipwidth << 3));
- printf(" Size: %ld MB in %d Sectors\n",
- info->size >> 20, info->sector_count);
- printf
- (" Erase timeout %ld ms, write timeout %ld ms, buffer write timeout %ld ms, buffer size %d\n",
- info->erase_blk_tout, info->write_tout, info->buffer_write_tout,
- info->buffer_size);
-
- printf(" Sector Start Addresses:");
- for (i = 0; i < info->sector_count; ++i) {
- if ((i % 5) == 0)
- printf("\n");
- printf(" %08lX%5s",
- info->start[i], info->protect[i] ? " (RO)" : " ");
- }
- printf("\n");
- return;
-}
-
-/*-----------------------------------------------------------------------
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt)
-{
- ulong wp;
- ulong cp;
- int aln;
- cfiword_t cword;
- int i, rc;
-
- /* get lower aligned address */
- wp = (addr & ~(info->portwidth - 1));
-
- /* handle unaligned start */
- if ((aln = addr - wp) != 0) {
- cword.l = 0;
- cp = wp;
- for (i = 0; i < aln; ++i, ++cp)
- flash_add_byte(info, &cword, (*(uchar *) cp));
-
- for (; (i < info->portwidth) && (cnt > 0); i++) {
- flash_add_byte(info, &cword, *src++);
- cnt--;
- cp++;
- }
- for (; (cnt == 0) && (i < info->portwidth); ++i, ++cp)
- flash_add_byte(info, &cword, (*(uchar *) cp));
- if ((rc = flash_write_cfiword(info, wp, cword)) != 0)
- return rc;
- wp = cp;
- }
-#ifdef CONFIG_SYS_FLASH_USE_BUFFER_WRITE
- while (cnt >= info->portwidth) {
- i = info->buffer_size > cnt ? cnt : info->buffer_size;
- if ((rc = flash_write_cfibuffer(info, wp, src, i)) != ERR_OK)
- return rc;
- wp += i;
- src += i;
- cnt -= i;
- }
-#else
- /* handle the aligned part */
- while (cnt >= info->portwidth) {
- cword.l = 0;
- for (i = 0; i < info->portwidth; i++) {
- flash_add_byte(info, &cword, *src++);
- }
- if ((rc = flash_write_cfiword(info, wp, cword)) != 0)
- return rc;
- wp += info->portwidth;
- cnt -= info->portwidth;
- }
-#endif /* CONFIG_SYS_FLASH_USE_BUFFER_WRITE */
- if (cnt == 0) {
- return (0);
- }
-
- /*
- * handle unaligned tail bytes
- */
- cword.l = 0;
- for (i = 0, cp = wp; (i < info->portwidth) && (cnt > 0); ++i, ++cp) {
- flash_add_byte(info, &cword, *src++);
- --cnt;
- }
- for (; i < info->portwidth; ++i, ++cp) {
- flash_add_byte(info, &cword, (*(uchar *) cp));
- }
-
- return flash_write_cfiword(info, wp, cword);
-}
-
-/*-----------------------------------------------------------------------
- */
-int flash_real_protect(flash_info_t * info, long sector, int prot)
-{
- int retcode = 0;
-
- flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS);
- flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT);
- if (prot)
- flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT_SET);
- else
- flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT_CLEAR);
-
- if ((retcode =
- flash_full_status_check(info, sector, info->erase_blk_tout,
- prot ? "protect" : "unprotect")) == 0) {
-
- info->protect[sector] = prot;
- /* Intel's unprotect unprotects all locking */
- if (prot == 0) {
- int i;
- for (i = 0; i < info->sector_count; i++) {
- if (info->protect[i])
- flash_real_protect(info, i, 1);
- }
- }
- }
-
- return retcode;
-}
-
-/*-----------------------------------------------------------------------
- * wait for XSR.7 to be set. Time out with an error if it does not.
- * This routine does not set the flash to read-array mode.
- */
-static int flash_status_check(flash_info_t * info, ulong sector, ulong tout,
- char *prompt)
-{
- ulong start;
-
- /* Wait for command completion */
- start = get_timer(0);
- while (!flash_isset(info, sector, 0, FLASH_STATUS_DONE)) {
- if (get_timer(start) > info->erase_blk_tout) {
- printf("Flash %s timeout at address %lx\n", prompt,
- info->start[sector]);
- flash_write_cmd(info, sector, 0, FLASH_CMD_RESET);
- return ERR_TIMOUT;
- }
- }
- return ERR_OK;
-}
-
-/*-----------------------------------------------------------------------
- * Wait for XSR.7 to be set, if it times out print an error, otherwise do a full status check.
- * This routine sets the flash to read-array mode.
- */
-static int flash_full_status_check(flash_info_t * info, ulong sector,
- ulong tout, char *prompt)
-{
- int retcode;
- retcode = flash_status_check(info, sector, tout, prompt);
- if ((retcode == ERR_OK)
- && !flash_isequal(info, sector, 0, FLASH_STATUS_DONE)) {
- retcode = ERR_INVAL;
- printf("Flash %s error at address %lx\n", prompt,
- info->start[sector]);
- if (flash_isset
- (info, sector, 0,
- FLASH_STATUS_ECLBS | FLASH_STATUS_PSLBS)) {
- printf("Command Sequence Error.\n");
- } else if (flash_isset(info, sector, 0, FLASH_STATUS_ECLBS)) {
- printf("Block Erase Error.\n");
- retcode = ERR_NOT_ERASED;
- } else if (flash_isset(info, sector, 0, FLASH_STATUS_PSLBS)) {
- printf("Locking Error\n");
- }
- if (flash_isset(info, sector, 0, FLASH_STATUS_DPS)) {
- printf("Block locked.\n");
- retcode = ERR_PROTECTED;
- }
- if (flash_isset(info, sector, 0, FLASH_STATUS_VPENS))
- printf("Vpp Low Error.\n");
- }
- flash_write_cmd(info, sector, 0, FLASH_CMD_RESET);
- return retcode;
-}
-
-/*-----------------------------------------------------------------------
- */
-static void flash_add_byte(flash_info_t * info, cfiword_t * cword, uchar c)
-{
- switch (info->portwidth) {
- case FLASH_CFI_8BIT:
- cword->c = c;
- break;
- case FLASH_CFI_16BIT:
- cword->w = (cword->w << 8) | c;
- break;
- case FLASH_CFI_32BIT:
- cword->l = (cword->l << 8) | c;
- }
-}
-
-/*-----------------------------------------------------------------------
- * make a proper sized command based on the port and chip widths
- */
-static void flash_make_cmd(flash_info_t * info, uchar cmd, void *cmdbuf)
-{
- int i;
- uchar *cp = (uchar *) cmdbuf;
- for (i = 0; i < info->portwidth; i++)
- *cp++ = ((i + 1) % info->chipwidth) ? '\0' : cmd;
-}
-
-/*
- * Write a proper sized command to the correct address
- */
-static void flash_write_cmd(flash_info_t * info, int sect, uchar offset,
- uchar cmd)
-{
-
- volatile cfiptr_t addr;
- cfiword_t cword;
- addr.cp = flash_make_addr(info, sect, offset);
- flash_make_cmd(info, cmd, &cword);
- switch (info->portwidth) {
- case FLASH_CFI_8BIT:
- *addr.cp = cword.c;
- break;
- case FLASH_CFI_16BIT:
- *addr.wp = cword.w;
- break;
- case FLASH_CFI_32BIT:
- *addr.lp = cword.l;
- break;
- }
-}
-
-/*-----------------------------------------------------------------------
- */
-static int flash_isequal(flash_info_t * info, int sect, uchar offset, uchar cmd)
-{
- cfiptr_t cptr;
- cfiword_t cword;
- int retval;
- cptr.cp = flash_make_addr(info, sect, offset);
- flash_make_cmd(info, cmd, &cword);
- switch (info->portwidth) {
- case FLASH_CFI_8BIT:
- retval = (cptr.cp[0] == cword.c);
- break;
- case FLASH_CFI_16BIT:
- retval = (cptr.wp[0] == cword.w);
- break;
- case FLASH_CFI_32BIT:
- retval = (cptr.lp[0] == cword.l);
- break;
- default:
- retval = 0;
- break;
- }
- return retval;
-}
-
-/*-----------------------------------------------------------------------
- */
-static int flash_isset(flash_info_t * info, int sect, uchar offset, uchar cmd)
-{
- cfiptr_t cptr;
- cfiword_t cword;
- int retval;
- cptr.cp = flash_make_addr(info, sect, offset);
- flash_make_cmd(info, cmd, &cword);
- switch (info->portwidth) {
- case FLASH_CFI_8BIT:
- retval = ((cptr.cp[0] & cword.c) == cword.c);
- break;
- case FLASH_CFI_16BIT:
- retval = ((cptr.wp[0] & cword.w) == cword.w);
- break;
- case FLASH_CFI_32BIT:
- retval = ((cptr.lp[0] & cword.l) == cword.l);
- break;
- default:
- retval = 0;
- break;
- }
- return retval;
-}
-
-/*-----------------------------------------------------------------------
- * detect if flash is compatible with the Common Flash Interface (CFI)
- * http://www.jedec.org/download/search/jesd68.pdf
- *
- */
-static int flash_detect_cfi(flash_info_t * info)
-{
-
- for (info->portwidth = FLASH_CFI_8BIT;
- info->portwidth <= FLASH_CFI_32BIT; info->portwidth <<= 1) {
- for (info->chipwidth = FLASH_CFI_BY8;
- info->chipwidth <= info->portwidth;
- info->chipwidth <<= 1) {
- flash_write_cmd(info, 0, 0, FLASH_CMD_RESET);
- flash_write_cmd(info, 0, FLASH_OFFSET_CFI,
- FLASH_CMD_CFI);
- if (flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP, 'Q')
- && flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP + 1,
- 'R')
- && flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP + 2,
- 'Y'))
- return 1;
- }
- }
- return 0;
-}
-
-/*
- * The following code cannot be run from FLASH!
- *
- */
-static ulong flash_get_size(ulong base, int banknum)
-{
- flash_info_t *info = &flash_info[banknum];
- int i, j;
- int sect_cnt;
- unsigned long sector;
- unsigned long tmp;
- int size_ratio = 0;
- uchar num_erase_regions;
- int erase_region_size;
- int erase_region_count;
-
- info->start[0] = base;
-#if 0
- invalidate_dcache_range(base, base + 0x400);
-#endif
- if (flash_detect_cfi(info)) {
-
- size_ratio = info->portwidth / info->chipwidth;
- num_erase_regions =
- flash_read_uchar(info, FLASH_OFFSET_NUM_ERASE_REGIONS);
-
- sect_cnt = 0;
- sector = base;
- for (i = 0; i < num_erase_regions; i++) {
- if (i > NUM_ERASE_REGIONS) {
- printf("%d erase regions found, only %d used\n",
- num_erase_regions, NUM_ERASE_REGIONS);
- break;
- }
- tmp =
- flash_read_long(info, 0,
- FLASH_OFFSET_ERASE_REGIONS);
- erase_region_size =
- (tmp & 0xffff) ? ((tmp & 0xffff) * 256) : 128;
- tmp >>= 16;
- erase_region_count = (tmp & 0xffff) + 1;
- for (j = 0; j < erase_region_count; j++) {
- info->start[sect_cnt] = sector;
- sector += (erase_region_size * size_ratio);
- info->protect[sect_cnt] =
- flash_isset(info, sect_cnt,
- FLASH_OFFSET_PROTECT,
- FLASH_STATUS_PROTECT);
- sect_cnt++;
- }
- }
-
- info->sector_count = sect_cnt;
- /* multiply the size by the number of chips */
- info->size =
- (1 << flash_read_uchar(info, FLASH_OFFSET_SIZE)) *
- size_ratio;
- info->buffer_size =
- (1 << flash_read_ushort(info, 0, FLASH_OFFSET_BUFFER_SIZE));
- tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_ETOUT);
- info->erase_blk_tout =
- (tmp *
- (1 << flash_read_uchar(info, FLASH_OFFSET_EMAX_TOUT)));
- tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_WBTOUT);
- info->buffer_write_tout =
- (tmp *
- (1 << flash_read_uchar(info, FLASH_OFFSET_WBMAX_TOUT)));
- tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_WTOUT);
- info->write_tout =
- (tmp *
- (1 << flash_read_uchar(info, FLASH_OFFSET_WMAX_TOUT))) /
- 1000;
- info->flash_id = FLASH_MAN_CFI;
- }
-
- flash_write_cmd(info, 0, 0, FLASH_CMD_RESET);
-#ifdef DEBUG_FLASH
- printf("portwidth=%d chipwidth=%d\n", info->portwidth, info->chipwidth); /* test-only */
-#endif
-#ifdef DEBUG_FLASH
- printf("found %d erase regions\n", num_erase_regions);
-#endif
-#ifdef DEBUG_FLASH
- printf("size=%08x sectors=%08x \n", info->size, info->sector_count);
-#endif
- return (info->size);
-}
-
-/*-----------------------------------------------------------------------
- */
-static int flash_write_cfiword(flash_info_t * info, ulong dest, cfiword_t cword)
-{
-
- cfiptr_t cptr;
- int flag;
-
- cptr.cp = (uchar *)dest;
-
- /* Check if Flash is (sufficiently) erased */
- switch (info->portwidth) {
- case FLASH_CFI_8BIT:
- flag = ((cptr.cp[0] & cword.c) == cword.c);
- break;
- case FLASH_CFI_16BIT:
- flag = ((cptr.wp[0] & cword.w) == cword.w);
- break;
- case FLASH_CFI_32BIT:
- flag = ((cptr.lp[0] & cword.l) == cword.l);
- break;
- default:
- return 2;
- }
- if (!flag)
- return 2;
-
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts();
-
- flash_write_cmd(info, 0, 0, FLASH_CMD_CLEAR_STATUS);
- flash_write_cmd(info, 0, 0, FLASH_CMD_WRITE);
-
- switch (info->portwidth) {
- case FLASH_CFI_8BIT:
- cptr.cp[0] = cword.c;
- break;
- case FLASH_CFI_16BIT:
- cptr.wp[0] = cword.w;
- break;
- case FLASH_CFI_32BIT:
- cptr.lp[0] = cword.l;
- break;
- }
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts();
-
- return flash_full_status_check(info, 0, info->write_tout, "write");
-}
-
-#ifdef CONFIG_SYS_FLASH_USE_BUFFER_WRITE
-
-/* loop through the sectors from the highest address
- * when the passed address is greater or equal to the sector address
- * we have a match
- */
-static int find_sector(flash_info_t * info, ulong addr)
-{
- int sector;
- for (sector = info->sector_count - 1; sector >= 0; sector--) {
- if (addr >= info->start[sector])
- break;
- }
- return sector;
-}
-
-static int flash_write_cfibuffer(flash_info_t * info, ulong dest, uchar * cp,
- int len)
-{
-
- int sector;
- int cnt;
- int retcode;
- volatile cfiptr_t src;
- volatile cfiptr_t dst;
-
- src.cp = cp;
- dst.cp = (uchar *) dest;
- sector = find_sector(info, dest);
- flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS);
- flash_write_cmd(info, sector, 0, FLASH_CMD_WRITE_TO_BUFFER);
- if ((retcode = flash_status_check(info, sector, info->buffer_write_tout,
- "write to buffer")) == ERR_OK) {
- switch (info->portwidth) {
- case FLASH_CFI_8BIT:
- cnt = len;
- break;
- case FLASH_CFI_16BIT:
- cnt = len >> 1;
- break;
- case FLASH_CFI_32BIT:
- cnt = len >> 2;
- break;
- default:
- return ERR_INVAL;
- break;
- }
- flash_write_cmd(info, sector, 0, (uchar) cnt - 1);
- while (cnt-- > 0) {
- switch (info->portwidth) {
- case FLASH_CFI_8BIT:
- *dst.cp++ = *src.cp++;
- break;
- case FLASH_CFI_16BIT:
- *dst.wp++ = *src.wp++;
- break;
- case FLASH_CFI_32BIT:
- *dst.lp++ = *src.lp++;
- break;
- default:
- return ERR_INVAL;
- break;
- }
- }
- flash_write_cmd(info, sector, 0,
- FLASH_CMD_WRITE_BUFFER_CONFIRM);
- retcode =
- flash_full_status_check(info, sector,
- info->buffer_write_tout,
- "buffer write");
- }
- flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS);
- return retcode;
-}
-#endif /* CONFIG_SYS_USE_FLASH_BUFFER_WRITE */
diff --git a/board/esd/mecp5200/Kconfig b/board/esd/mecp5200/Kconfig
deleted file mode 100644
index cfd5307..0000000
--- a/board/esd/mecp5200/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_MECP5200
-
-config SYS_BOARD
- default "mecp5200"
-
-config SYS_VENDOR
- default "esd"
-
-config SYS_CONFIG_NAME
- default "mecp5200"
-
-endif
diff --git a/board/esd/mecp5200/MAINTAINERS b/board/esd/mecp5200/MAINTAINERS
deleted file mode 100644
index 05b7824..0000000
--- a/board/esd/mecp5200/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-MECP5200 BOARD
-M: Reinhard Arlt <reinhard.arlt@esd-electronics.com>
-S: Maintained
-F: board/esd/mecp5200/
-F: include/configs/mecp5200.h
-F: configs/mecp5200_defconfig
diff --git a/board/esd/mecp5200/Makefile b/board/esd/mecp5200/Makefile
deleted file mode 100644
index 3d66c9f..0000000
--- a/board/esd/mecp5200/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2003-2006
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y = mecp5200.o
diff --git a/board/esd/mecp5200/mecp5200.c b/board/esd/mecp5200/mecp5200.c
deleted file mode 100644
index 17a70a9..0000000
--- a/board/esd/mecp5200/mecp5200.c
+++ /dev/null
@@ -1,251 +0,0 @@
-/*
- * (C) Copyright 2003
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- *
- * (C) Copyright 2004
- * Mark Jonas, Freescale Semiconductor, mark.jonas at motorola.com.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * pf5200.c - main board support/init for the esd pf5200.
- */
-
-#include <common.h>
-#include <mpc5xxx.h>
-#include <pci.h>
-#include <command.h>
-#include <netdev.h>
-
-#include "mt46v16m16-75.h"
-
-void init_power_switch(void);
-
-static void sdram_start(int hi_addr)
-{
- long hi_addr_bit = hi_addr ? 0x01000000 : 0;
-
- /* unlock mode register */
- *(vu_long *) MPC5XXX_SDRAM_CTRL =
- SDRAM_CONTROL | 0x80000000 | hi_addr_bit;
- __asm__ volatile ("sync");
-
- /* precharge all banks */
- *(vu_long *) MPC5XXX_SDRAM_CTRL =
- SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
- __asm__ volatile ("sync");
-
- /* set mode register: extended mode */
- *(vu_long *) MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
- __asm__ volatile ("sync");
-
- /* set mode register: reset DLL */
- *(vu_long *) MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
- __asm__ volatile ("sync");
-
- /* precharge all banks */
- *(vu_long *) MPC5XXX_SDRAM_CTRL =
- SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
- __asm__ volatile ("sync");
-
- /* auto refresh */
- *(vu_long *) MPC5XXX_SDRAM_CTRL =
- SDRAM_CONTROL | 0x80000004 | hi_addr_bit;
- __asm__ volatile ("sync");
-
- /* set mode register */
- *(vu_long *) MPC5XXX_SDRAM_MODE = SDRAM_MODE;
- __asm__ volatile ("sync");
-
- /* normal operation */
- *(vu_long *) MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
- __asm__ volatile ("sync");
-}
-
-/*
- * ATTENTION: Although partially referenced initdram does NOT make real use
- * use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE
- * is something else than 0x00000000.
- */
-
-phys_size_t initdram(int board_type)
-{
- ulong dramsize = 0;
- ulong test1, test2;
-
- /* setup SDRAM chip selects */
- *(vu_long *) MPC5XXX_SDRAM_CS0CFG = 0x0000001e; /* 2G at 0x0 */
- *(vu_long *) MPC5XXX_SDRAM_CS1CFG = 0x80000000; /* disabled */
- __asm__ volatile ("sync");
-
- /* setup config registers */
- *(vu_long *) MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
- *(vu_long *) MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
- __asm__ volatile ("sync");
-
- /* set tap delay */
- *(vu_long *) MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
- __asm__ volatile ("sync");
-
- /* find RAM size using SDRAM CS0 only */
- sdram_start(0);
- test1 = get_ram_size(CONFIG_SYS_SDRAM_BASE, 0x80000000);
- sdram_start(1);
- test2 = get_ram_size(CONFIG_SYS_SDRAM_BASE, 0x80000000);
-
- if (test1 > test2) {
- sdram_start(0);
- dramsize = test1;
- } else {
- dramsize = test2;
- }
-
- /* memory smaller than 1MB is impossible */
- if (dramsize < (1 << 20))
- dramsize = 0;
-
- /* set SDRAM CS0 size according to the amount of RAM found */
- if (dramsize > 0) {
- *(vu_long *) MPC5XXX_SDRAM_CS0CFG =
- 0x13 + __builtin_ffs(dramsize >> 20) - 1;
- /* let SDRAM CS1 start right after CS0 */
- *(vu_long *) MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e; /* 2G */
- } else {
-#if 0
- *(vu_long *) MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
- /* let SDRAM CS1 start right after CS0 */
- *(vu_long *) MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e; /* 2G */
-#else
- *(vu_long *) MPC5XXX_SDRAM_CS0CFG =
- 0x13 + __builtin_ffs(0x08000000 >> 20) - 1;
- /* let SDRAM CS1 start right after CS0 */
- *(vu_long *) MPC5XXX_SDRAM_CS1CFG = 0x08000000 + 0x0000001e; /* 2G */
-#endif
- }
-
-#if 0
- /* find RAM size using SDRAM CS1 only */
- sdram_start(0);
- get_ram_size((ulong *) (CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
- sdram_start(1);
- get_ram_size((ulong *) (CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
- sdram_start(0);
-#endif
- /* set SDRAM CS1 size according to the amount of RAM found */
-
- *(vu_long *) MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
-
- init_power_switch();
- return (dramsize);
-}
-
-int checkboard(void)
-{
- puts("Board: esd CPX CPU5200 (mecp5200)\n");
- return 0;
-}
-
-void flash_preinit(void)
-{
- /*
- * Now, when we are in RAM, enable flash write
- * access for detection process.
- * Note that CS_BOOT cannot be cleared when
- * executing in flash.
- */
- *(vu_long *) MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
-}
-
-void flash_afterinit(ulong size)
-{
- if (size == CONFIG_SYS_FLASH_SIZE) {
- /* adjust mapping */
- *(vu_long *) MPC5XXX_BOOTCS_START =
- *(vu_long *) MPC5XXX_CS0_START =
- START_REG(CONFIG_SYS_BOOTCS_START | size);
- *(vu_long *) MPC5XXX_BOOTCS_STOP =
- *(vu_long *) MPC5XXX_CS0_STOP =
- STOP_REG(CONFIG_SYS_BOOTCS_START | size, size);
- }
-}
-
-#ifdef CONFIG_PCI
-static struct pci_controller hose;
-
-extern void pci_mpc5xxx_init(struct pci_controller *);
-
-void pci_init_board(void)
-{
- pci_mpc5xxx_init(&hose);
-}
-#endif
-
-#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET)
-
-#define GPIO_PSC1_4 0x01000000UL
-
-void init_ide_reset(void)
-{
- debug("init_ide_reset\n");
-
- /* Configure PSC1_4 as GPIO output for ATA reset */
- *(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4;
- *(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC1_4;
-}
-
-void ide_set_reset(int idereset)
-{
- debug("ide_reset(%d)\n", idereset);
-
- if (idereset)
- *(vu_long *) MPC5XXX_WU_GPIO_DATA_O &= ~GPIO_PSC1_4;
- else
- *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_PSC1_4;
-}
-#endif
-
-#define MPC5XXX_SIMPLEIO_GPIO_ENABLE (MPC5XXX_GPIO + 0x0004)
-#define MPC5XXX_SIMPLEIO_GPIO_DIR (MPC5XXX_GPIO + 0x000C)
-#define MPC5XXX_SIMPLEIO_GPIO_DATA_OUTPUT (MPC5XXX_GPIO + 0x0010)
-#define MPC5XXX_SIMPLEIO_GPIO_DATA_INPUT (MPC5XXX_GPIO + 0x0014)
-
-#define MPC5XXX_INTERRUPT_GPIO_ENABLE (MPC5XXX_GPIO + 0x0020)
-#define MPC5XXX_INTERRUPT_GPIO_DIR (MPC5XXX_GPIO + 0x0028)
-#define MPC5XXX_INTERRUPT_GPIO_DATA_OUTPUT (MPC5XXX_GPIO + 0x002C)
-#define MPC5XXX_INTERRUPT_GPIO_STATUS (MPC5XXX_GPIO + 0x003C)
-
-#define GPIO_WU6 0x40000000UL
-#define GPIO_USB0 0x00010000UL
-#define GPIO_USB9 0x08000000UL
-#define GPIO_USB9S 0x00080000UL
-
-void init_power_switch(void)
-{
- debug("init_power_switch\n");
-
- /* Configure GPIO_WU6 as GPIO output for ATA reset */
- *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_WU6;
- *(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_WU6;
- *(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_WU6;
- __asm__ volatile ("sync");
-
- *(vu_long *) MPC5XXX_SIMPLEIO_GPIO_DATA_OUTPUT &= ~GPIO_USB0;
- *(vu_long *) MPC5XXX_SIMPLEIO_GPIO_ENABLE |= GPIO_USB0;
- *(vu_long *) MPC5XXX_SIMPLEIO_GPIO_DIR |= GPIO_USB0;
- __asm__ volatile ("sync");
-
- *(vu_long *) MPC5XXX_INTERRUPT_GPIO_DATA_OUTPUT &= ~GPIO_USB9;
- *(vu_long *) MPC5XXX_INTERRUPT_GPIO_ENABLE &= ~GPIO_USB9;
- __asm__ volatile ("sync");
-
- if ((*(vu_long *) MPC5XXX_INTERRUPT_GPIO_STATUS & GPIO_USB9S) == 0) {
- *(vu_long *) MPC5XXX_SIMPLEIO_GPIO_DATA_OUTPUT |= GPIO_USB0;
- __asm__ volatile ("sync");
- }
-}
-
-int board_eth_init(bd_t *bis)
-{
- return pci_eth_init(bis);
-}
diff --git a/board/esd/mecp5200/mt46v16m16-75.h b/board/esd/mecp5200/mt46v16m16-75.h
deleted file mode 100644
index 63a4032..0000000
--- a/board/esd/mecp5200/mt46v16m16-75.h
+++ /dev/null
@@ -1,16 +0,0 @@
-/*
- * (C) Copyright 2004
- * Mark Jonas, Freescale Semiconductor, mark.jonas at motorola.com.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#define SDRAM_DDR 1 /* is DDR */
-
-/* Settings for XLB = 132 MHz */
-#define SDRAM_MODE 0x018D0000
-#define SDRAM_EMODE 0x40090000
-#define SDRAM_CONTROL 0x705f0f00
-#define SDRAM_CONFIG1 0x73722930
-#define SDRAM_CONFIG2 0x47770000
-#define SDRAM_TAPDELAY 0x10000000
diff --git a/board/esd/pf5200/Kconfig b/board/esd/pf5200/Kconfig
deleted file mode 100644
index c596e7a..0000000
--- a/board/esd/pf5200/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_PF5200
-
-config SYS_BOARD
- default "pf5200"
-
-config SYS_VENDOR
- default "esd"
-
-config SYS_CONFIG_NAME
- default "pf5200"
-
-endif
diff --git a/board/esd/pf5200/MAINTAINERS b/board/esd/pf5200/MAINTAINERS
deleted file mode 100644
index b6e624e..0000000
--- a/board/esd/pf5200/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-PF5200 BOARD
-M: Reinhard Arlt <reinhard.arlt@esd-electronics.com>
-S: Maintained
-F: board/esd/pf5200/
-F: include/configs/pf5200.h
-F: configs/pf5200_defconfig
diff --git a/board/esd/pf5200/Makefile b/board/esd/pf5200/Makefile
deleted file mode 100644
index a54289c..0000000
--- a/board/esd/pf5200/Makefile
+++ /dev/null
@@ -1,14 +0,0 @@
-#
-# (C) Copyright 2003-2006
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-# Objects for Xilinx JTAG programming (CPLD)
-# CPLD = ../common/xilinx_jtag/lenval.o \
-# ../common/xilinx_jtag/micro.o \
-# ../common/xilinx_jtag/ports.o
-
-# obj-y = pf5200.o flash.o $(CPLD)
-obj-y = pf5200.o flash.o
diff --git a/board/esd/pf5200/flash.c b/board/esd/pf5200/flash.c
deleted file mode 100644
index e1b13bf..0000000
--- a/board/esd/pf5200/flash.c
+++ /dev/null
@@ -1,445 +0,0 @@
-/*
- * (C) Copyright 2003
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-
-flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
-
-typedef unsigned short FLASH_PORT_WIDTH;
-typedef volatile unsigned short FLASH_PORT_WIDTHV;
-
-#define FLASH_ID_MASK 0x00FF
-
-#define FPW FLASH_PORT_WIDTH
-#define FPWV FLASH_PORT_WIDTHV
-
-#define FLASH_CYCLE1 0x0555
-#define FLASH_CYCLE2 0x0aaa
-#define FLASH_ID1 0x00
-#define FLASH_ID2 0x01
-#define FLASH_ID3 0x0E
-#define FLASH_ID4 0x0F
-
-/*-----------------------------------------------------------------------
- * Functions
- */
-static ulong flash_get_size(FPWV * addr, flash_info_t * info);
-static void flash_reset(flash_info_t * info);
-static int write_word_amd(flash_info_t * info, FPWV * dest, FPW data);
-static flash_info_t *flash_get_info(ulong base);
-
-/*-----------------------------------------------------------------------
- * flash_init()
- *
- * sets up flash_info and returns size of FLASH (bytes)
- */
-unsigned long flash_init(void)
-{
- unsigned long size = 0;
- int i = 0;
- extern void flash_preinit(void);
- extern void flash_afterinit(uint, ulong, ulong);
-
- ulong flashbase = CONFIG_SYS_FLASH_BASE;
-
- flash_preinit();
-
- /* There is only ONE FLASH device */
- memset(&flash_info[i], 0, sizeof(flash_info_t));
- flash_info[i].size = flash_get_size((FPW *) flashbase, &flash_info[i]);
- size += flash_info[i].size;
-
-#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
- /* monitor protection ON by default */
- flash_protect(FLAG_PROTECT_SET, CONFIG_SYS_MONITOR_BASE,
- CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1,
- flash_get_info(CONFIG_SYS_MONITOR_BASE));
-#endif
-
-#ifdef CONFIG_ENV_IS_IN_FLASH
- /* ENV protection ON by default */
- flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR,
- CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1,
- flash_get_info(CONFIG_ENV_ADDR));
-#endif
-
- flash_afterinit(i, flash_info[i].start[0], flash_info[i].size);
- return size ? size : 1;
-}
-
-/*-----------------------------------------------------------------------
- */
-static void flash_reset(flash_info_t * info) {
- FPWV *base = (FPWV *) (info->start[0]);
-
- /* Put FLASH back in read mode */
- if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
- *base = (FPW) 0x00FF00FF; /* Intel Read Mode */
- } else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD) {
- *base = (FPW) 0x00F000F0; /* AMD Read Mode */
- }
-}
-
-/*-----------------------------------------------------------------------
- */
-
-static flash_info_t *flash_get_info(ulong base) {
- int i;
- flash_info_t *info;
-
- for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
- info = &flash_info[i];
- if ((info->size) && (info->start[0] <= base)
- && (base <= info->start[0] + info->size - 1)) {
- break;
- }
- }
- return (i == CONFIG_SYS_MAX_FLASH_BANKS ? 0 : info);
-}
-
-/*-----------------------------------------------------------------------
- */
-
-void flash_print_info(flash_info_t * info) {
- int i;
- char *fmt;
-
- if (info->flash_id == FLASH_UNKNOWN) {
- printf("missing or unknown FLASH type\n");
- return;
- }
-
- switch (info->flash_id & FLASH_VENDMASK) {
- case FLASH_MAN_AMD:
- printf("AMD ");
- break;
- default:
- printf("Unknown Vendor ");
- break;
- }
-
- switch (info->flash_id & FLASH_TYPEMASK) {
- case FLASH_AMLV256U:
- fmt = "29LV256M (256 Mbit)\n";
- break;
- default:
- fmt = "Unknown Chip Type\n";
- break;
- }
-
- printf(fmt);
- printf(" Size: %ld MB in %d Sectors\n", info->size >> 20,
- info->sector_count);
- printf(" Sector Start Addresses:");
-
- for (i = 0; i < info->sector_count; ++i) {
- ulong size;
- int erased;
- ulong *flash = (unsigned long *)info->start[i];
-
- if ((i % 5) == 0) {
- printf("\n ");
- }
-
- /*
- * Check if whole sector is erased
- */
- size =
- (i !=
- (info->sector_count - 1)) ? (info->start[i + 1] -
- info->start[i]) >> 2 : (info->
- start
- [0] +
- info->
- size -
- info->
- start
- [i])
- >> 2;
-
- for (flash = (unsigned long *)info->start[i], erased = 1;
- (flash != (unsigned long *)info->start[i] + size)
- && erased; flash++) {
- erased = *flash == ~0x0UL;
- }
- printf(" %08lX %s %s", info->start[i], erased ? "E" : " ",
- info->protect[i] ? "(RO)" : " ");
- }
-
- printf("\n");
-}
-
-/*-----------------------------------------------------------------------
- */
-
-/*
- * The following code cannot be run from FLASH!
- */
-
-ulong flash_get_size(FPWV * addr, flash_info_t * info) {
- int i;
-
- /* Write auto select command: read Manufacturer ID */
- /* Write auto select command sequence and test FLASH answer */
- addr[FLASH_CYCLE1] = (FPW) 0x00AA00AA; /* for AMD, Intel ignores this */
- addr[FLASH_CYCLE2] = (FPW) 0x00550055; /* for AMD, Intel ignores this */
- addr[FLASH_CYCLE1] = (FPW) 0x00900090; /* selects Intel or AMD */
-
- /* The manufacturer codes are only 1 byte, so just use 1 byte. */
- /* This works for any bus width and any FLASH device width. */
- udelay(100);
- switch (addr[FLASH_ID1] & 0x00ff) {
- case (uchar) AMD_MANUFACT:
- info->flash_id = FLASH_MAN_AMD;
- break;
- default:
- printf("unknown vendor=%x ", addr[FLASH_ID1] & 0xff);
- info->flash_id = FLASH_UNKNOWN;
- info->sector_count = 0;
- info->size = 0;
- break;
- }
-
- /* Check 16 bits or 32 bits of ID so work on 32 or 16 bit bus. */
- if (info->flash_id != FLASH_UNKNOWN) {
- switch ((FPW) addr[FLASH_ID2]) {
- case (FPW) AMD_ID_MIRROR:
- /* MIRROR BIT FLASH, read more ID bytes */
- if ((FPW) addr[FLASH_ID3] == (FPW) AMD_ID_LV256U_2
- && (FPW) addr[FLASH_ID4] == (FPW) AMD_ID_LV256U_3) {
- /* attention: only the first 16 MB will be used in u-boot */
- info->flash_id += FLASH_AMLV256U;
- info->sector_count = 512;
- info->size = 0x02000000;
- for (i = 0; i < info->sector_count; i++) {
- info->start[i] =
- (ulong) addr + 0x10000 * i;
- }
- break;
- }
- /* fall thru to here ! */
- default:
- printf("unknown AMD device=%x %x %x",
- (FPW) addr[FLASH_ID2], (FPW) addr[FLASH_ID3],
- (FPW) addr[FLASH_ID4]);
- info->flash_id = FLASH_UNKNOWN;
- info->sector_count = 0;
- info->size = 0x800000;
- break;
- }
-
- /* Put FLASH back in read mode */
- flash_reset(info);
- }
- return (info->size);
-}
-
-/*-----------------------------------------------------------------------
- */
-
-int flash_erase(flash_info_t * info, int s_first, int s_last) {
- FPWV *addr;
- int flag, prot, sect;
- int intel = (info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL;
- ulong start, now, last;
- int rcode = 0;
-
- if ((s_first < 0) || (s_first > s_last)) {
- if (info->flash_id == FLASH_UNKNOWN) {
- printf("- missing\n");
- } else {
- printf("- no sectors to erase\n");
- }
- return 1;
- }
-
- switch (info->flash_id & FLASH_TYPEMASK) {
- case FLASH_AMLV256U:
- break;
- case FLASH_UNKNOWN:
- default:
- printf("Can't erase unknown flash type %08lx - aborted\n",
- info->flash_id);
- return 1;
- }
-
- prot = 0;
- for (sect = s_first; sect <= s_last; ++sect) {
- if (info->protect[sect]) {
- prot++;
- }
- }
-
- if (prot) {
- printf("- Warning: %d protected sectors will not be erased!\n",
- prot);
- } else {
- printf("\n");
- }
-
- last = get_timer(0);
-
- /* Start erase on unprotected sectors */
- for (sect = s_first; sect <= s_last && rcode == 0; sect++) {
- if (info->protect[sect] != 0) { /* protected, skip it */
- continue;
- }
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts();
-
- addr = (FPWV *) (info->start[sect]);
- if (intel) {
- *addr = (FPW) 0x00500050; /* clear status register */
- *addr = (FPW) 0x00200020; /* erase setup */
- *addr = (FPW) 0x00D000D0; /* erase confirm */
- } else {
- /* must be AMD style if not Intel */
- FPWV *base; /* first address in bank */
-
- base = (FPWV *) (info->start[0]);
- base[FLASH_CYCLE1] = (FPW) 0x00AA00AA; /* unlock */
- base[FLASH_CYCLE2] = (FPW) 0x00550055; /* unlock */
- base[FLASH_CYCLE1] = (FPW) 0x00800080; /* erase mode */
- base[FLASH_CYCLE1] = (FPW) 0x00AA00AA; /* unlock */
- base[FLASH_CYCLE2] = (FPW) 0x00550055; /* unlock */
- *addr = (FPW) 0x00300030; /* erase sector */
- }
-
- /* re-enable interrupts if necessary */
- if (flag) {
- enable_interrupts();
- }
- start = get_timer(0);
-
- /* wait at least 50us for AMD, 80us for Intel. */
- /* Let's wait 1 ms. */
- udelay(1000);
-
- while ((*addr & (FPW) 0x00800080) != (FPW) 0x00800080) {
- if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
- printf("Timeout\n");
- if (intel) {
- /* suspend erase */
- *addr = (FPW) 0x00B000B0;
- }
- flash_reset(info); /* reset to read mode */
- rcode = 1; /* failed */
- break;
- }
- /* show that we're waiting */
- if ((get_timer(last)) > CONFIG_SYS_HZ) {
- /* every second */
- putc('.');
- last = get_timer(0);
- }
- }
- /* show that we're waiting */
- if ((get_timer(last)) > CONFIG_SYS_HZ) {
- /* every second */
- putc('.');
- last = get_timer(0);
- }
- flash_reset(info); /* reset to read mode */
- }
- printf(" done\n");
- return (rcode);
-}
-
-/*-----------------------------------------------------------------------
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt)
-{
- FPW data = 0; /* 16 or 32 bit word, matches flash bus width on MPC8XX */
- int bytes; /* number of bytes to program in current word */
- int left; /* number of bytes left to program */
- int i, res;
-
- for (left = cnt, res = 0;
- left > 0 && res == 0;
- addr += sizeof(data), left -= sizeof(data) - bytes) {
-
- bytes = addr & (sizeof(data) - 1);
- addr &= ~(sizeof(data) - 1);
-
- /* combine source and destination data so can program
- * an entire word of 16 or 32 bits
- */
- for (i = 0; i < sizeof(data); i++) {
- data <<= 8;
- if (i < bytes || i - bytes >= left)
- data += *((uchar *) addr + i);
- else
- data += *src++;
- }
-
- /* write one word to the flash */
- switch (info->flash_id & FLASH_VENDMASK) {
- case FLASH_MAN_AMD:
- res = write_word_amd(info, (FPWV *) addr, data);
- break;
- default:
- /* unknown flash type, error! */
- printf("missing or unknown FLASH type\n");
- res = 1; /* not really a timeout, but gives error */
- break;
- }
- }
- return (res);
-}
-
-/*-----------------------------------------------------------------------
- * Write a word to Flash for AMD FLASH
- * A word is 16 or 32 bits, whichever the bus width of the flash bank
- * (not an individual chip) is.
- *
- * returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-static int write_word_amd(flash_info_t * info, FPWV * dest, FPW data) {
- ulong start;
- int flag;
- int res = 0; /* result, assume success */
- FPWV *base; /* first address in flash bank */
-
- /* Check if Flash is (sufficiently) erased */
- if ((*dest & data) != data) {
- return (2);
- }
-
- base = (FPWV *) (info->start[0]);
-
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts();
-
- base[FLASH_CYCLE1] = (FPW) 0x00AA00AA; /* unlock */
- base[FLASH_CYCLE2] = (FPW) 0x00550055; /* unlock */
- base[FLASH_CYCLE1] = (FPW) 0x00A000A0; /* selects program mode */
-
- *dest = data; /* start programming the data */
-
- /* re-enable interrupts if necessary */
- if (flag) {
- enable_interrupts();
- }
- start = get_timer(0);
-
- /* data polling for D7 */
- while (res == 0
- && (*dest & (FPW) 0x00800080) != (data & (FPW) 0x00800080)) {
- if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
- *dest = (FPW) 0x00F000F0; /* reset bank */
- res = 1;
- }
- }
- return (res);
-}
diff --git a/board/esd/pf5200/mt46v16m16-75.h b/board/esd/pf5200/mt46v16m16-75.h
deleted file mode 100644
index 63a4032..0000000
--- a/board/esd/pf5200/mt46v16m16-75.h
+++ /dev/null
@@ -1,16 +0,0 @@
-/*
- * (C) Copyright 2004
- * Mark Jonas, Freescale Semiconductor, mark.jonas at motorola.com.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#define SDRAM_DDR 1 /* is DDR */
-
-/* Settings for XLB = 132 MHz */
-#define SDRAM_MODE 0x018D0000
-#define SDRAM_EMODE 0x40090000
-#define SDRAM_CONTROL 0x705f0f00
-#define SDRAM_CONFIG1 0x73722930
-#define SDRAM_CONFIG2 0x47770000
-#define SDRAM_TAPDELAY 0x10000000
diff --git a/board/esd/pf5200/pf5200.c b/board/esd/pf5200/pf5200.c
deleted file mode 100644
index 7a9ed22..0000000
--- a/board/esd/pf5200/pf5200.c
+++ /dev/null
@@ -1,357 +0,0 @@
-/*
- * (C) Copyright 2003
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- *
- * (C) Copyright 2004
- * Mark Jonas, Freescale Semiconductor, mark.jonas at motorola.com.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * pf5200.c - main board support/init for the esd pf5200.
- */
-
-#include <common.h>
-#include <mpc5xxx.h>
-#include <pci.h>
-#include <command.h>
-#include <netdev.h>
-
-#include "mt46v16m16-75.h"
-
-void init_power_switch(void);
-
-static void sdram_start(int hi_addr)
-{
- long hi_addr_bit = hi_addr ? 0x01000000 : 0;
-
- /* unlock mode register */
- *(vu_long *) MPC5XXX_SDRAM_CTRL =
- SDRAM_CONTROL | 0x80000000 | hi_addr_bit;
- __asm__ volatile ("sync");
-
- /* precharge all banks */
- *(vu_long *) MPC5XXX_SDRAM_CTRL =
- SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
- __asm__ volatile ("sync");
-
- /* set mode register: extended mode */
- *(vu_long *) MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
- __asm__ volatile ("sync");
-
- /* set mode register: reset DLL */
- *(vu_long *) MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
- __asm__ volatile ("sync");
-
- /* precharge all banks */
- *(vu_long *) MPC5XXX_SDRAM_CTRL =
- SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
- __asm__ volatile ("sync");
-
- /* auto refresh */
- *(vu_long *) MPC5XXX_SDRAM_CTRL =
- SDRAM_CONTROL | 0x80000004 | hi_addr_bit;
- __asm__ volatile ("sync");
-
- /* set mode register */
- *(vu_long *) MPC5XXX_SDRAM_MODE = SDRAM_MODE;
- __asm__ volatile ("sync");
-
- /* normal operation */
- *(vu_long *) MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
- __asm__ volatile ("sync");
-}
-
-/*
- * ATTENTION: Although partially referenced initdram does NOT make real use
- * use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE
- * is something else than 0x00000000.
- */
-
-phys_size_t initdram(int board_type)
-{
- ulong dramsize = 0;
- ulong test1, test2;
-
- /* setup SDRAM chip selects */
- *(vu_long *) MPC5XXX_SDRAM_CS0CFG = 0x0000001e; /* 2G at 0x0 */
- *(vu_long *) MPC5XXX_SDRAM_CS1CFG = 0x80000000; /* disabled */
- __asm__ volatile ("sync");
-
- /* setup config registers */
- *(vu_long *) MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
- *(vu_long *) MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
- __asm__ volatile ("sync");
-
- /* set tap delay */
- *(vu_long *) MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
- __asm__ volatile ("sync");
-
- /* find RAM size using SDRAM CS0 only */
- sdram_start(0);
- test1 = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE, 0x80000000);
- sdram_start(1);
- test2 = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE, 0x80000000);
-
- if (test1 > test2) {
- sdram_start(0);
- dramsize = test1;
- } else {
- dramsize = test2;
- }
-
- /* memory smaller than 1MB is impossible */
- if (dramsize < (1 << 20)) {
- dramsize = 0;
- }
-
- /* set SDRAM CS0 size according to the amount of RAM found */
- if (dramsize > 0) {
- *(vu_long *) MPC5XXX_SDRAM_CS0CFG =
- 0x13 + __builtin_ffs(dramsize >> 20) - 1;
- /* let SDRAM CS1 start right after CS0 */
- *(vu_long *) MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e; /* 2G */
- } else {
-#if 0
- *(vu_long *) MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
- /* let SDRAM CS1 start right after CS0 */
- *(vu_long *) MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e; /* 2G */
-#else
- *(vu_long *) MPC5XXX_SDRAM_CS0CFG =
- 0x13 + __builtin_ffs(0x08000000 >> 20) - 1;
- /* let SDRAM CS1 start right after CS0 */
- *(vu_long *) MPC5XXX_SDRAM_CS1CFG = 0x08000000 + 0x0000001e; /* 2G */
-#endif
- }
-
-#if 0
- /* find RAM size using SDRAM CS1 only */
- sdram_start(0);
- get_ram_size((ulong *) (CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
- sdram_start(1);
- get_ram_size((ulong *) (CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
- sdram_start(0);
-#endif
- /* set SDRAM CS1 size according to the amount of RAM found */
-
- *(vu_long *) MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
-
- init_power_switch();
- return (dramsize);
-}
-
-int checkboard(void)
-{
- puts("Board: esd ParaFinder (pf5200)\n");
- return 0;
-}
-
-void flash_preinit(void)
-{
- /*
- * Now, when we are in RAM, enable flash write
- * access for detection process.
- * Note that CS_BOOT cannot be cleared when
- * executing in flash.
- */
- *(vu_long *) MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
-}
-
-void flash_afterinit(ulong size)
-{
- if (size == 0x02000000) {
- /* adjust mapping */
- *(vu_long *) MPC5XXX_BOOTCS_START =
- *(vu_long *) MPC5XXX_CS0_START =
- START_REG(CONFIG_SYS_BOOTCS_START | size);
- *(vu_long *) MPC5XXX_BOOTCS_STOP =
- *(vu_long *) MPC5XXX_CS0_STOP =
- STOP_REG(CONFIG_SYS_BOOTCS_START | size, size);
- }
-}
-
-#ifdef CONFIG_PCI
-static struct pci_controller hose;
-
-extern void pci_mpc5xxx_init(struct pci_controller *);
-
-void pci_init_board(void) {
- pci_mpc5xxx_init(&hose);
-}
-#endif
-
-#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET)
-
-void init_ide_reset(void)
-{
- debug("init_ide_reset\n");
-
- /* Configure PSC1_4 as GPIO output for ATA reset */
- *(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4;
- *(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC1_4;
-}
-
-void ide_set_reset(int idereset)
-{
- debug("ide_reset(%d)\n", idereset);
-
- if (idereset) {
- *(vu_long *) MPC5XXX_WU_GPIO_DATA_O &= ~GPIO_PSC1_4;
- } else {
- *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_PSC1_4;
- }
-}
-#endif
-
-#define MPC5XXX_SIMPLEIO_GPIO_ENABLE (MPC5XXX_GPIO + 0x0004)
-#define MPC5XXX_SIMPLEIO_GPIO_DIR (MPC5XXX_GPIO + 0x000C)
-#define MPC5XXX_SIMPLEIO_GPIO_DATA_OUTPUT (MPC5XXX_GPIO + 0x0010)
-#define MPC5XXX_SIMPLEIO_GPIO_DATA_INPUT (MPC5XXX_GPIO + 0x0014)
-
-#define MPC5XXX_INTERRUPT_GPIO_ENABLE (MPC5XXX_GPIO + 0x0020)
-#define MPC5XXX_INTERRUPT_GPIO_DIR (MPC5XXX_GPIO + 0x0028)
-#define MPC5XXX_INTERRUPT_GPIO_DATA_OUTPUT (MPC5XXX_GPIO + 0x002C)
-#define MPC5XXX_INTERRUPT_GPIO_STATUS (MPC5XXX_GPIO + 0x003C)
-
-#define GPIO_WU6 0x40000000UL
-#define GPIO_USB0 0x00010000UL
-#define GPIO_USB9 0x08000000UL
-#define GPIO_USB9S 0x00080000UL
-
-void init_power_switch(void)
-{
- debug("init_power_switch\n");
-
- /* Configure GPIO_WU6 as GPIO output for ATA reset */
- *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_WU6;
- *(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_WU6;
- *(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_WU6;
- __asm__ volatile ("sync");
-
- *(vu_long *) MPC5XXX_SIMPLEIO_GPIO_DATA_OUTPUT &= ~GPIO_USB0;
- *(vu_long *) MPC5XXX_SIMPLEIO_GPIO_ENABLE |= GPIO_USB0;
- *(vu_long *) MPC5XXX_SIMPLEIO_GPIO_DIR |= GPIO_USB0;
- __asm__ volatile ("sync");
-
- *(vu_long *) MPC5XXX_INTERRUPT_GPIO_DATA_OUTPUT &= ~GPIO_USB9;
- *(vu_long *) MPC5XXX_INTERRUPT_GPIO_ENABLE &= ~GPIO_USB9;
- __asm__ volatile ("sync");
-
- if ((*(vu_long *) MPC5XXX_INTERRUPT_GPIO_STATUS & GPIO_USB9S) == 0) {
- *(vu_long *) MPC5XXX_SIMPLEIO_GPIO_DATA_OUTPUT |= GPIO_USB0;
- __asm__ volatile ("sync");
- }
- *(vu_char *) CONFIG_SYS_CS1_START = 0x02; /* Red Power LED on */
- __asm__ volatile ("sync");
-
- *(vu_char *) (CONFIG_SYS_CS1_START + 1) = 0x02; /* Disable driver for KB11 */
- __asm__ volatile ("sync");
-}
-
-int board_eth_init(bd_t *bis)
-{
- return pci_eth_init(bis);
-}
-
-void power_set_reset(int power)
-{
- debug("ide_set_reset(%d)\n", power);
-
- if (power) {
- *(vu_long *) MPC5XXX_WU_GPIO_DATA_O &= ~GPIO_WU6;
- *(vu_long *) MPC5XXX_INTERRUPT_GPIO_DATA_OUTPUT &= ~GPIO_USB9;
- } else {
- *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_WU6;
- if ((*(vu_long *) MPC5XXX_INTERRUPT_GPIO_STATUS & GPIO_USB9S) ==
- 0) {
- *(vu_long *) MPC5XXX_SIMPLEIO_GPIO_DATA_OUTPUT |=
- GPIO_USB0;
- }
-
- }
-}
-
-int do_poweroff(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
-{
- power_set_reset(1);
- return (0);
-}
-
-U_BOOT_CMD(poweroff, 1, 1, do_poweroff, "Switch off power", "");
-
-int phypower(int flag)
-{
- u32 addr;
- vu_long *reg;
- int status;
- pci_dev_t dev;
-
- dev = PCI_BDF(0, 0x18, 0);
- status = pci_read_config_dword(dev, PCI_BASE_ADDRESS_1, &addr);
- if (status == 0) {
- reg = (vu_long *) (addr + 0x00000040);
- *reg |= 0x40000000;
- __asm__ volatile ("sync");
-
- reg = (vu_long *) (addr + 0x001000c);
- *reg |= 0x20000000;
- __asm__ volatile ("sync");
-
- reg = (vu_long *) (addr + 0x0010004);
- if (flag != 0) {
- *reg &= ~0x20000000;
- } else {
- *reg |= 0x20000000;
- }
- __asm__ volatile ("sync");
- }
- return (status);
-}
-
-int do_phypower(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
-{
- if (argv[1][0] == '0')
- (void)phypower(0);
- else
- (void)phypower(1);
-
- return (0);
-}
-
-U_BOOT_CMD(phypower, 2, 2, do_phypower,
- "Switch power of ethernet phy", "");
-
-int do_writepci(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
-{
- unsigned int addr;
- unsigned int size;
- int i;
- volatile unsigned long *ptr;
-
- addr = simple_strtol(argv[1], NULL, 16);
- size = simple_strtol(argv[2], NULL, 16);
-
- printf("\nWriting at addr %08x, size %08x.\n", addr, size);
-
- while (1) {
- ptr = (volatile unsigned long *)addr;
- for (i = 0; i < (size >> 2); i++) {
- *ptr++ = i;
- }
-
- /* Abort if ctrl-c was pressed */
- if (ctrlc()) {
- puts("\nAbort\n");
- return 0;
- }
- putc('.');
- }
- return 0;
-}
-
-U_BOOT_CMD(writepci, 3, 1, do_writepci,
- "Write some data to pcibus",
- "<addr> <size>\n"
- ""
-);
diff --git a/board/icecube/Kconfig b/board/icecube/Kconfig
deleted file mode 100644
index e5b2153..0000000
--- a/board/icecube/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_ICECUBE
-
-config SYS_BOARD
- default "icecube"
-
-config SYS_CONFIG_NAME
- default "IceCube"
-
-endif
diff --git a/board/icecube/MAINTAINERS b/board/icecube/MAINTAINERS
deleted file mode 100644
index 8a24eb4..0000000
--- a/board/icecube/MAINTAINERS
+++ /dev/null
@@ -1,21 +0,0 @@
-ICECUBE BOARD
-M: Wolfgang Denk <wd@denx.de>
-S: Maintained
-F: board/icecube/
-F: include/configs/IceCube.h
-F: configs/icecube_5200_defconfig
-
-ICECUBE_5200_DDR BOARD
-#M: -
-S: Maintained
-F: configs/icecube_5200_DDR_defconfig
-F: configs/icecube_5200_DDR_LOWBOOT_defconfig
-F: configs/icecube_5200_DDR_LOWBOOT08_defconfig
-F: configs/icecube_5200_LOWBOOT_defconfig
-F: configs/icecube_5200_LOWBOOT08_defconfig
-F: configs/Lite5200_defconfig
-F: configs/Lite5200_LOWBOOT_defconfig
-F: configs/Lite5200_LOWBOOT08_defconfig
-F: configs/lite5200b_defconfig
-F: configs/lite5200b_LOWBOOT_defconfig
-F: configs/lite5200b_PM_defconfig
diff --git a/board/icecube/Makefile b/board/icecube/Makefile
deleted file mode 100644
index c3c2cd1..0000000
--- a/board/icecube/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2003-2006
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := icecube.o flash.o
diff --git a/board/icecube/README b/board/icecube/README
deleted file mode 100644
index 5252bc9..0000000
--- a/board/icecube/README
+++ /dev/null
@@ -1,13 +0,0 @@
----------------------------------------------------------------------------
-Build target Flash address | BDI "go" command | Reset Vector
----------------------------------------------------------------------------
-Lite5200 0xFFF00000 | 0xFFF00100 | 0xFFF00100
-Lite5200_LOWBOOT 0xFF000000 | 0xFF000100 | 0x00000100
-Lite5200_LOWBOOT08 0xFF800000 | 0xFF800100 | 0x00000100
-icecube_5200 0xFFF00000 | 0xFFF00100 | 0xFFF00100
-icecube_5200_LOWBOOT 0xFF000000 | 0xFF000100 | 0x00000100
-icecube_5200_LOWBOOT08 0xFF800000 | 0xFF800100 | 0x00000100
-icecube_5200_DDR 0xFFF00000 | 0xFFF00100 | 0xFFF00100
-icecube_5200_DDR_LOWBOOT 0xFF800000 | 0xFF800100 | 0x00000100
-icecube_5200_DDR_LOWBOOT08 0xFF800000 | 0xFF800100 | 0x00000100
----------------------------------------------------------------------------
diff --git a/board/icecube/README.Lite5200B_low_power b/board/icecube/README.Lite5200B_low_power
deleted file mode 100644
index 5b04fbb..0000000
--- a/board/icecube/README.Lite5200B_low_power
+++ /dev/null
@@ -1,22 +0,0 @@
-Lite5200B wakeup from low-power mode (CONFIG_LITE5200B_PM)
-----------------------------------------------------------
-
-Low-power mode as described in Lite5200B User's Manual, means that
-with support of MC68HLC908QT1 microcontroller (refered to as QT),
-everything but the SDRAM can be powered down. This brings
-maximum power saving, while one can still restore previous state
-quickly.
-
-Quick overview where U-Boot comes into the picture:
-- OS saves device states
-- OS saves wakeup handler address to physical 0x0, puts SDRAM into
- self-refresh and signals to QT, it should power down the board
-- / board is sleeping here /
-- someone presses SW4 (connected to QT)
-- U-Boot checks PSC2_4 pin, if QT drives it down, then we woke up,
- so get SDRAM out of self-refresh and transfer control to OS
- wakeup handler
-- OS restores device states
-
-This was tested on Linux with USB and Ethernet in use. Adding
-support for other devices is an OS issue.
diff --git a/board/icecube/flash.c b/board/icecube/flash.c
deleted file mode 100644
index a044e8f..0000000
--- a/board/icecube/flash.c
+++ /dev/null
@@ -1,477 +0,0 @@
-/*
- * (C) Copyright 2003
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-
-#ifndef CONFIG_FLASH_CFI_DRIVER
-flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
-
-/* NOTE - CONFIG_FLASH_16BIT means the CPU interface is 16-bit, it
- * has nothing to do with the flash chip being 8-bit or 16-bit.
- */
-#ifdef CONFIG_FLASH_16BIT
-typedef unsigned short FLASH_PORT_WIDTH;
-typedef volatile unsigned short FLASH_PORT_WIDTHV;
-#define FLASH_ID_MASK 0xFFFF
-#else
-typedef unsigned char FLASH_PORT_WIDTH;
-typedef volatile unsigned char FLASH_PORT_WIDTHV;
-#define FLASH_ID_MASK 0xFF
-#endif
-
-#define FPW FLASH_PORT_WIDTH
-#define FPWV FLASH_PORT_WIDTHV
-
-#define ORMASK(size) ((-size) & OR_AM_MSK)
-
-#define FLASH_CYCLE1 0x0555
-#define FLASH_CYCLE2 0x02aa
-
-/*-----------------------------------------------------------------------
- * Functions
- */
-static ulong flash_get_size(FPWV *addr, flash_info_t *info);
-static void flash_reset(flash_info_t *info);
-static int write_word_amd(flash_info_t *info, FPWV *dest, FPW data);
-static flash_info_t *flash_get_info(ulong base);
-
-/*-----------------------------------------------------------------------
- * flash_init()
- *
- * sets up flash_info and returns size of FLASH (bytes)
- */
-unsigned long flash_init (void)
-{
- unsigned long size = 0;
- int i;
- extern void flash_preinit(void);
- extern void flash_afterinit(ulong);
- ulong flashbase = CONFIG_SYS_FLASH_BASE;
-
- flash_preinit();
-
- /* Init: no FLASHes known */
- for (i=0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
- memset(&flash_info[i], 0, sizeof(flash_info_t));
-
- flash_info[i].size =
- flash_get_size((FPW *)flashbase, &flash_info[i]);
-
- size += flash_info[i].size;
- flashbase += 0x800000;
- }
-#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
- /* monitor protection ON by default */
- flash_protect(FLAG_PROTECT_SET,
- CONFIG_SYS_MONITOR_BASE,
- CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
- flash_get_info(CONFIG_SYS_MONITOR_BASE));
-#endif
-
-#ifdef CONFIG_ENV_IS_IN_FLASH
- /* ENV protection ON by default */
- flash_protect(FLAG_PROTECT_SET,
- CONFIG_ENV_ADDR,
- CONFIG_ENV_ADDR+CONFIG_ENV_SIZE-1,
- flash_get_info(CONFIG_ENV_ADDR));
-#endif
-
-
- flash_afterinit(size);
- return size ? size : 1;
-}
-
-/*-----------------------------------------------------------------------
- */
-static void flash_reset(flash_info_t *info)
-{
- FPWV *base = (FPWV *)(info->start[0]);
-
- /* Put FLASH back in read mode */
- if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL)
- *base = (FPW)0x00FF00FF; /* Intel Read Mode */
- else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD)
- *base = (FPW)0x00F000F0; /* AMD Read Mode */
-}
-
-/*-----------------------------------------------------------------------
- */
-
-static flash_info_t *flash_get_info(ulong base)
-{
- int i;
- flash_info_t * info;
-
- for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i ++) {
- info = & flash_info[i];
- if (info->size &&
- info->start[0] <= base && base <= info->start[0] + info->size - 1)
- break;
- }
-
- return i == CONFIG_SYS_MAX_FLASH_BANKS ? 0 : info;
-}
-
-/*-----------------------------------------------------------------------
- */
-
-void flash_print_info (flash_info_t *info)
-{
- int i;
- uchar *boottype;
- uchar *bootletter;
- char *fmt;
- uchar botbootletter[] = "B";
- uchar topbootletter[] = "T";
- uchar botboottype[] = "bottom boot sector";
- uchar topboottype[] = "top boot sector";
-
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("missing or unknown FLASH type\n");
- return;
- }
-
- switch (info->flash_id & FLASH_VENDMASK) {
- case FLASH_MAN_AMD: printf ("AMD "); break;
- case FLASH_MAN_BM: printf ("BRIGHT MICRO "); break;
- case FLASH_MAN_FUJ: printf ("FUJITSU "); break;
- case FLASH_MAN_SST: printf ("SST "); break;
- case FLASH_MAN_STM: printf ("STM "); break;
- case FLASH_MAN_INTEL: printf ("INTEL "); break;
- default: printf ("Unknown Vendor "); break;
- }
-
- /* check for top or bottom boot, if it applies */
- if (info->flash_id & FLASH_BTYPE) {
- boottype = botboottype;
- bootletter = botbootletter;
- }
- else {
- boottype = topboottype;
- bootletter = topbootletter;
- }
-
- switch (info->flash_id & FLASH_TYPEMASK) {
- case FLASH_AMDLV065D:
- fmt = "29LV065 (64 Mbit, uniform sectors)\n";
- break;
- default:
- fmt = "Unknown Chip Type\n";
- break;
- }
-
- printf (fmt, bootletter, boottype);
-
- printf (" Size: %ld MB in %d Sectors\n",
- info->size >> 20,
- info->sector_count);
-
- printf (" Sector Start Addresses:");
-
- for (i=0; i<info->sector_count; ++i) {
- if ((i % 5) == 0) {
- printf ("\n ");
- }
-
- printf (" %08lX%s", info->start[i],
- info->protect[i] ? " (RO)" : " ");
- }
-
- printf ("\n");
-}
-
-/*-----------------------------------------------------------------------
- */
-
-/*
- * The following code cannot be run from FLASH!
- */
-
-ulong flash_get_size (FPWV *addr, flash_info_t *info)
-{
- int i;
- FPWV* addr2;
-
- /* Write auto select command: read Manufacturer ID */
- /* Write auto select command sequence and test FLASH answer */
- addr[FLASH_CYCLE1] = (FPW)0x00AA00AA; /* for AMD, Intel ignores this */
- addr[FLASH_CYCLE2] = (FPW)0x00550055; /* for AMD, Intel ignores this */
- addr[FLASH_CYCLE1] = (FPW)0x00900090; /* selects Intel or AMD */
-
- /* The manufacturer codes are only 1 byte, so just use 1 byte.
- * This works for any bus width and any FLASH device width.
- */
- udelay(100);
- switch (addr[0] & 0xff) {
-
- case (uchar)AMD_MANUFACT:
- info->flash_id = FLASH_MAN_AMD;
- break;
-
- case (uchar)INTEL_MANUFACT:
- info->flash_id = FLASH_MAN_INTEL;
- break;
-
- default:
- info->flash_id = FLASH_UNKNOWN;
- info->sector_count = 0;
- info->size = 0;
- break;
- }
-
- /* Check 16 bits or 32 bits of ID so work on 32 or 16 bit bus. */
- if (info->flash_id != FLASH_UNKNOWN) switch ((FPW)addr[1]) {
-
- case (FPW)AMD_ID_LV065D:
- info->flash_id += FLASH_AMDLV065D;
- info->sector_count = 128;
- info->size = 0x00800000;
- for( i = 0; i < info->sector_count; i++ )
- info->start[i] = (ulong)addr + (i * 0x10000);
- break; /* => 8 or 16 MB */
-
- default:
- info->flash_id = FLASH_UNKNOWN;
- info->sector_count = 0;
- info->size = 0;
- return (0); /* => no or unknown flash */
- }
-
- /* test for real flash at bank 1 */
- addr2 = (FPW *)((ulong)addr | 0x800000);
- if (addr2 != addr &&
- ((addr2[0] & 0xff) == (addr[0] & 0xff)) && ((FPW)addr2[1] == (FPW)addr[1])) {
- /* Seems 2 banks are the same space (8Mb chip is installed,
- * J24 in default position (CS0)). Disable this (first) bank.
- */
- info->flash_id = FLASH_UNKNOWN;
- info->sector_count = 0;
- info->size = 0;
- }
- /* Put FLASH back in read mode */
- flash_reset(info);
-
- return (info->size);
-}
-
-/*-----------------------------------------------------------------------
- */
-
-int flash_erase (flash_info_t *info, int s_first, int s_last)
-{
- FPWV *addr;
- int flag, prot, sect;
- int intel = (info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL;
- ulong start, now, last;
- int rcode = 0;
-
- if ((s_first < 0) || (s_first > s_last)) {
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("- missing\n");
- } else {
- printf ("- no sectors to erase\n");
- }
- return 1;
- }
-
- switch (info->flash_id & FLASH_TYPEMASK) {
- case FLASH_AMDLV065D:
- break;
- case FLASH_UNKNOWN:
- default:
- printf ("Can't erase unknown flash type %08lx - aborted\n",
- info->flash_id);
- return 1;
- }
-
- prot = 0;
- for (sect=s_first; sect<=s_last; ++sect) {
- if (info->protect[sect]) {
- prot++;
- }
- }
-
- if (prot) {
- printf ("- Warning: %d protected sectors will not be erased!\n",
- prot);
- } else {
- printf ("\n");
- }
-
- last = get_timer(0);
-
- /* Start erase on unprotected sectors */
- for (sect = s_first; sect<=s_last && rcode == 0; sect++) {
-
- if (info->protect[sect] != 0) /* protected, skip it */
- continue;
-
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts();
-
- addr = (FPWV *)(info->start[sect]);
- if (intel) {
- *addr = (FPW)0x00500050; /* clear status register */
- *addr = (FPW)0x00200020; /* erase setup */
- *addr = (FPW)0x00D000D0; /* erase confirm */
- }
- else {
- /* must be AMD style if not Intel */
- FPWV *base; /* first address in bank */
-
- base = (FPWV *)(info->start[0]);
- base[FLASH_CYCLE1] = (FPW)0x00AA00AA; /* unlock */
- base[FLASH_CYCLE2] = (FPW)0x00550055; /* unlock */
- base[FLASH_CYCLE1] = (FPW)0x00800080; /* erase mode */
- base[FLASH_CYCLE1] = (FPW)0x00AA00AA; /* unlock */
- base[FLASH_CYCLE2] = (FPW)0x00550055; /* unlock */
- *addr = (FPW)0x00300030; /* erase sector */
- }
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts();
-
- start = get_timer(0);
-
- /* wait at least 50us for AMD, 80us for Intel.
- * Let's wait 1 ms.
- */
- udelay (1000);
-
- while ((*addr & (FPW)0x00800080) != (FPW)0x00800080) {
- if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
- printf ("Timeout\n");
-
- if (intel) {
- /* suspend erase */
- *addr = (FPW)0x00B000B0;
- }
-
- flash_reset(info); /* reset to read mode */
- rcode = 1; /* failed */
- break;
- }
-
- /* show that we're waiting */
- if ((get_timer(last)) > CONFIG_SYS_HZ) {/* every second */
- putc ('.');
- last = get_timer(0);
- }
- }
-
- /* show that we're waiting */
- if ((get_timer(last)) > CONFIG_SYS_HZ) { /* every second */
- putc ('.');
- last = get_timer(0);
- }
-
- flash_reset(info); /* reset to read mode */
- }
-
- printf (" done\n");
- return rcode;
-}
-
-/*-----------------------------------------------------------------------
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
-{
- FPW data = 0; /* 16 or 32 bit word, matches flash bus width on MPC8XX */
- int bytes; /* number of bytes to program in current word */
- int left; /* number of bytes left to program */
- int i, res;
-
- for (left = cnt, res = 0;
- left > 0 && res == 0;
- addr += sizeof(data), left -= sizeof(data) - bytes) {
-
- bytes = addr & (sizeof(data) - 1);
- addr &= ~(sizeof(data) - 1);
-
- /* combine source and destination data so can program
- * an entire word of 16 or 32 bits
- */
- for (i = 0; i < sizeof(data); i++) {
- data <<= 8;
- if (i < bytes || i - bytes >= left )
- data += *((uchar *)addr + i);
- else
- data += *src++;
- }
-
- /* write one word to the flash */
- switch (info->flash_id & FLASH_VENDMASK) {
- case FLASH_MAN_AMD:
- res = write_word_amd(info, (FPWV *)addr, data);
- break;
- default:
- /* unknown flash type, error! */
- printf ("missing or unknown FLASH type\n");
- res = 1; /* not really a timeout, but gives error */
- break;
- }
- }
-
- return (res);
-}
-
-/*-----------------------------------------------------------------------
- * Write a word to Flash for AMD FLASH
- * A word is 16 or 32 bits, whichever the bus width of the flash bank
- * (not an individual chip) is.
- *
- * returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-static int write_word_amd (flash_info_t *info, FPWV *dest, FPW data)
-{
- ulong start;
- int flag;
- int res = 0; /* result, assume success */
- FPWV *base; /* first address in flash bank */
-
- /* Check if Flash is (sufficiently) erased */
- if ((*dest & data) != data) {
- return (2);
- }
-
-
- base = (FPWV *)(info->start[0]);
-
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts();
-
- base[FLASH_CYCLE1] = (FPW)0x00AA00AA; /* unlock */
- base[FLASH_CYCLE2] = (FPW)0x00550055; /* unlock */
- base[FLASH_CYCLE1] = (FPW)0x00A000A0; /* selects program mode */
-
- *dest = data; /* start programming the data */
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts();
-
- start = get_timer (0);
-
- /* data polling for D7 */
- while (res == 0 && (*dest & (FPW)0x00800080) != (data & (FPW)0x00800080)) {
- if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
- *dest = (FPW)0x00F000F0; /* reset bank */
- res = 1;
- }
- }
-
- return (res);
-}
-#endif /*CONFIG_FLASH_CFI_DRIVER*/
diff --git a/board/icecube/icecube.c b/board/icecube/icecube.c
deleted file mode 100644
index f0af24a..0000000
--- a/board/icecube/icecube.c
+++ /dev/null
@@ -1,326 +0,0 @@
-/*
- * (C) Copyright 2003
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- *
- * (C) Copyright 2004
- * Mark Jonas, Freescale Semiconductor, mark.jonas at motorola.com.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <mpc5xxx.h>
-#include <pci.h>
-#include <asm/processor.h>
-#include <libfdt.h>
-#include <netdev.h>
-
-#if defined(CONFIG_LITE5200B)
-#include "mt46v32m16.h"
-#else
-# if defined(CONFIG_MPC5200_DDR)
-# include "mt46v16m16-75.h"
-# else
-#include "mt48lc16m16a2-75.h"
-# endif
-#endif
-
-#ifdef CONFIG_LITE5200B_PM
-/* u-boot part of low-power mode implementation */
-#define SAVED_ADDR (*(void **)0x00000000)
-#define PSC2_4 0x02
-
-void lite5200b_wakeup(void)
-{
- unsigned char wakeup_pin;
- void (*linux_wakeup)(void);
-
- /* check PSC2_4, if it's down "QT" is signaling we have a wakeup
- * from low power mode */
- *(vu_char *)MPC5XXX_WU_GPIO_ENABLE = PSC2_4;
- __asm__ volatile ("sync");
-
- wakeup_pin = *(vu_char *)MPC5XXX_WU_GPIO_DATA_I;
- if (wakeup_pin & PSC2_4)
- return;
-
- /* acknowledge to "QT"
- * by holding pin at 1 for 10 uS */
- *(vu_char *)MPC5XXX_WU_GPIO_DIR = PSC2_4;
- __asm__ volatile ("sync");
- *(vu_char *)MPC5XXX_WU_GPIO_DATA_O = PSC2_4;
- __asm__ volatile ("sync");
- udelay(10);
-
- /* put ram out of self-refresh */
- *(vu_long *)MPC5XXX_SDRAM_CTRL |= 0x80000000; /* mode_en */
- __asm__ volatile ("sync");
- *(vu_long *)MPC5XXX_SDRAM_CTRL |= 0x50000000; /* cke ref_en */
- __asm__ volatile ("sync");
- *(vu_long *)MPC5XXX_SDRAM_CTRL &= ~0x80000000; /* !mode_en */
- __asm__ volatile ("sync");
- udelay(10); /* wait a bit */
-
- /* jump back to linux kernel code */
- linux_wakeup = SAVED_ADDR;
- printf("\n\nLooks like we just woke, transferring control to 0x%08lx\n",
- (unsigned long)linux_wakeup);
- linux_wakeup();
-}
-#else
-#define lite5200b_wakeup()
-#endif
-
-#ifndef CONFIG_SYS_RAMBOOT
-static void sdram_start (int hi_addr)
-{
- long hi_addr_bit = hi_addr ? 0x01000000 : 0;
-
- /* unlock mode register */
- *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | hi_addr_bit;
- __asm__ volatile ("sync");
-
- /* precharge all banks */
- *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
- __asm__ volatile ("sync");
-
-#if SDRAM_DDR
- /* set mode register: extended mode */
- *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
- __asm__ volatile ("sync");
-
- /* set mode register: reset DLL */
- *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
- __asm__ volatile ("sync");
-#endif
-
- /* precharge all banks */
- *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
- __asm__ volatile ("sync");
-
- /* auto refresh */
- *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | hi_addr_bit;
- __asm__ volatile ("sync");
-
- /* set mode register */
- *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE;
- __asm__ volatile ("sync");
-
- /* normal operation */
- *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
- __asm__ volatile ("sync");
-}
-#endif
-
-/*
- * ATTENTION: Although partially referenced initdram does NOT make real use
- * use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE
- * is something else than 0x00000000.
- */
-
-phys_size_t initdram (int board_type)
-{
- ulong dramsize = 0;
- ulong dramsize2 = 0;
- uint svr, pvr;
-
-#ifndef CONFIG_SYS_RAMBOOT
- ulong test1, test2;
-
- /* setup SDRAM chip selects */
- *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e;/* 2G at 0x0 */
- *(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x80000000;/* disabled */
- __asm__ volatile ("sync");
-
- /* setup config registers */
- *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
- *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
- __asm__ volatile ("sync");
-
-#if SDRAM_DDR
- /* set tap delay */
- *(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
- __asm__ volatile ("sync");
-#endif
-
- /* find RAM size using SDRAM CS0 only */
- sdram_start(0);
- test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
- sdram_start(1);
- test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
- if (test1 > test2) {
- sdram_start(0);
- dramsize = test1;
- } else {
- dramsize = test2;
- }
-
- /* memory smaller than 1MB is impossible */
- if (dramsize < (1 << 20)) {
- dramsize = 0;
- }
-
- /* set SDRAM CS0 size according to the amount of RAM found */
- if (dramsize > 0) {
- *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 + __builtin_ffs(dramsize >> 20) - 1;
- } else {
- *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
- }
-
- /* let SDRAM CS1 start right after CS0 */
- *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;/* 2G */
-
- /* find RAM size using SDRAM CS1 only */
- if (!dramsize)
- sdram_start(0);
- test2 = test1 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
- if (!dramsize) {
- sdram_start(1);
- test2 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
- }
- if (test1 > test2) {
- sdram_start(0);
- dramsize2 = test1;
- } else {
- dramsize2 = test2;
- }
-
- /* memory smaller than 1MB is impossible */
- if (dramsize2 < (1 << 20)) {
- dramsize2 = 0;
- }
-
- /* set SDRAM CS1 size according to the amount of RAM found */
- if (dramsize2 > 0) {
- *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize
- | (0x13 + __builtin_ffs(dramsize2 >> 20) - 1);
- } else {
- *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
- }
-
-#else /* CONFIG_SYS_RAMBOOT */
-
- /* retrieve size of memory connected to SDRAM CS0 */
- dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
- if (dramsize >= 0x13) {
- dramsize = (1 << (dramsize - 0x13)) << 20;
- } else {
- dramsize = 0;
- }
-
- /* retrieve size of memory connected to SDRAM CS1 */
- dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF;
- if (dramsize2 >= 0x13) {
- dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
- } else {
- dramsize2 = 0;
- }
-
-#endif /* CONFIG_SYS_RAMBOOT */
-
- /*
- * On MPC5200B we need to set the special configuration delay in the
- * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM
- * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190:
- *
- * "The SDelay should be written to a value of 0x00000004. It is
- * required to account for changes caused by normal wafer processing
- * parameters."
- */
- svr = get_svr();
- pvr = get_pvr();
- if ((SVR_MJREV(svr) >= 2) &&
- (PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4)) {
-
- *(vu_long *)MPC5XXX_SDRAM_SDELAY = 0x04;
- __asm__ volatile ("sync");
- }
-
- lite5200b_wakeup();
-
- return dramsize + dramsize2;
-}
-
-int checkboard (void)
-{
-#if defined (CONFIG_LITE5200B)
- puts ("Board: Freescale Lite5200B\n");
-#else
- puts ("Board: Motorola MPC5200 (IceCube)\n");
-#endif
- return 0;
-}
-
-void flash_preinit(void)
-{
- /*
- * Now, when we are in RAM, enable flash write
- * access for detection process.
- * Note that CS_BOOT cannot be cleared when
- * executing in flash.
- */
- *(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
-}
-
-void flash_afterinit(ulong size)
-{
- if (size == 0x800000) { /* adjust mapping */
- *(vu_long *)MPC5XXX_BOOTCS_START = *(vu_long *)MPC5XXX_CS0_START =
- START_REG(CONFIG_SYS_BOOTCS_START | size);
- *(vu_long *)MPC5XXX_BOOTCS_STOP = *(vu_long *)MPC5XXX_CS0_STOP =
- STOP_REG(CONFIG_SYS_BOOTCS_START | size, size);
- }
-}
-
-#ifdef CONFIG_PCI
-static struct pci_controller hose;
-
-extern void pci_mpc5xxx_init(struct pci_controller *);
-
-void pci_init_board(void)
-{
- pci_mpc5xxx_init(&hose);
-}
-#endif
-
-#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET)
-
-void init_ide_reset (void)
-{
- debug ("init_ide_reset\n");
-
- /* Configure PSC1_4 as GPIO output for ATA reset */
- *(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4;
- *(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC1_4;
- /* Deassert reset */
- *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_PSC1_4;
-}
-
-void ide_set_reset (int idereset)
-{
- debug ("ide_reset(%d)\n", idereset);
-
- if (idereset) {
- *(vu_long *) MPC5XXX_WU_GPIO_DATA_O &= ~GPIO_PSC1_4;
- /* Make a delay. MPC5200 spec says 25 usec min */
- udelay(500000);
- } else {
- *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_PSC1_4;
- }
-}
-#endif
-
-#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
-int ft_board_setup(void *blob, bd_t *bd)
-{
- ft_cpu_setup(blob, bd);
-
- return 0;
-}
-#endif
-
-int board_eth_init(bd_t *bis)
-{
- cpu_eth_init(bis); /* Built in FEC comes first */
- return pci_eth_init(bis);
-}
diff --git a/board/icecube/mt46v16m16-75.h b/board/icecube/mt46v16m16-75.h
deleted file mode 100644
index 919876f..0000000
--- a/board/icecube/mt46v16m16-75.h
+++ /dev/null
@@ -1,16 +0,0 @@
-/*
- * (C) Copyright 2004
- * Mark Jonas, Freescale Semiconductor, mark.jonas at motorola.com.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#define SDRAM_DDR 1 /* is DDR */
-
-/* Settings for XLB = 132 MHz */
-#define SDRAM_MODE 0x018D0000
-#define SDRAM_EMODE 0x40090000
-#define SDRAM_CONTROL 0x705f0f00
-#define SDRAM_CONFIG1 0x73722930
-#define SDRAM_CONFIG2 0x47770000
-#define SDRAM_TAPDELAY 0x10000000
diff --git a/board/icecube/mt46v32m16.h b/board/icecube/mt46v32m16.h
deleted file mode 100644
index a200bc7..0000000
--- a/board/icecube/mt46v32m16.h
+++ /dev/null
@@ -1,16 +0,0 @@
-/*
- * (C) Copyright 2004
- * Mark Jonas, Freescale Semiconductor, mark.jonas at motorola.com.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#define SDRAM_DDR 1 /* is DDR */
-
-/* Settings for XLB = 132 MHz */
-#define SDRAM_MODE 0x018D0000
-#define SDRAM_EMODE 0x40090000
-#define SDRAM_CONTROL 0x704f0f00
-#define SDRAM_CONFIG1 0x73722930
-#define SDRAM_CONFIG2 0x47770000
-#define SDRAM_TAPDELAY 0x10000000
diff --git a/board/icecube/mt48lc16m16a2-75.h b/board/icecube/mt48lc16m16a2-75.h
deleted file mode 100644
index 0133eaa..0000000
--- a/board/icecube/mt48lc16m16a2-75.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/*
- * (C) Copyright 2004
- * Mark Jonas, Freescale Semiconductor, mark.jonas at motorola.com.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#define SDRAM_DDR 0 /* is SDR */
-
-/* Settings for XLB = 132 MHz */
-#define SDRAM_MODE 0x00CD0000
-#define SDRAM_CONTROL 0x504F0000
-#define SDRAM_CONFIG1 0xD2322800
-#define SDRAM_CONFIG2 0x8AD70000
diff --git a/configs/Lite5200_LOWBOOT08_defconfig b/configs/Lite5200_LOWBOOT08_defconfig
deleted file mode 100644
index 9f0cbd8..0000000
--- a/configs/Lite5200_LOWBOOT08_defconfig
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0xFF800000"
-CONFIG_PPC=y
-CONFIG_MPC5xxx=y
-CONFIG_TARGET_ICECUBE=y
diff --git a/configs/Lite5200_LOWBOOT_defconfig b/configs/Lite5200_LOWBOOT_defconfig
deleted file mode 100644
index ff1552f..0000000
--- a/configs/Lite5200_LOWBOOT_defconfig
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0xFF000000"
-CONFIG_PPC=y
-CONFIG_MPC5xxx=y
-CONFIG_TARGET_ICECUBE=y
diff --git a/configs/Lite5200_defconfig b/configs/Lite5200_defconfig
deleted file mode 100644
index 49fdb3b..0000000
--- a/configs/Lite5200_defconfig
+++ /dev/null
@@ -1,3 +0,0 @@
-CONFIG_PPC=y
-CONFIG_MPC5xxx=y
-CONFIG_TARGET_ICECUBE=y
diff --git a/configs/cpci5200_defconfig b/configs/cpci5200_defconfig
deleted file mode 100644
index bdbf4fc..0000000
--- a/configs/cpci5200_defconfig
+++ /dev/null
@@ -1,3 +0,0 @@
-CONFIG_PPC=y
-CONFIG_MPC5xxx=y
-CONFIG_TARGET_CPCI5200=y
diff --git a/configs/icecube_5200_DDR_LOWBOOT08_defconfig b/configs/icecube_5200_DDR_LOWBOOT08_defconfig
deleted file mode 100644
index 79f8598..0000000
--- a/configs/icecube_5200_DDR_LOWBOOT08_defconfig
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0xFF800000,MPC5200_DDR"
-CONFIG_PPC=y
-CONFIG_MPC5xxx=y
-CONFIG_TARGET_ICECUBE=y
diff --git a/configs/icecube_5200_DDR_LOWBOOT_defconfig b/configs/icecube_5200_DDR_LOWBOOT_defconfig
deleted file mode 100644
index 79f8598..0000000
--- a/configs/icecube_5200_DDR_LOWBOOT_defconfig
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0xFF800000,MPC5200_DDR"
-CONFIG_PPC=y
-CONFIG_MPC5xxx=y
-CONFIG_TARGET_ICECUBE=y
diff --git a/configs/icecube_5200_DDR_defconfig b/configs/icecube_5200_DDR_defconfig
deleted file mode 100644
index 19d9637..0000000
--- a/configs/icecube_5200_DDR_defconfig
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_SYS_EXTRA_OPTIONS="MPC5200_DDR"
-CONFIG_PPC=y
-CONFIG_MPC5xxx=y
-CONFIG_TARGET_ICECUBE=y
diff --git a/configs/icecube_5200_LOWBOOT08_defconfig b/configs/icecube_5200_LOWBOOT08_defconfig
deleted file mode 100644
index 9f0cbd8..0000000
--- a/configs/icecube_5200_LOWBOOT08_defconfig
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0xFF800000"
-CONFIG_PPC=y
-CONFIG_MPC5xxx=y
-CONFIG_TARGET_ICECUBE=y
diff --git a/configs/icecube_5200_LOWBOOT_defconfig b/configs/icecube_5200_LOWBOOT_defconfig
deleted file mode 100644
index ff1552f..0000000
--- a/configs/icecube_5200_LOWBOOT_defconfig
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0xFF000000"
-CONFIG_PPC=y
-CONFIG_MPC5xxx=y
-CONFIG_TARGET_ICECUBE=y
diff --git a/configs/icecube_5200_defconfig b/configs/icecube_5200_defconfig
deleted file mode 100644
index 49fdb3b..0000000
--- a/configs/icecube_5200_defconfig
+++ /dev/null
@@ -1,3 +0,0 @@
-CONFIG_PPC=y
-CONFIG_MPC5xxx=y
-CONFIG_TARGET_ICECUBE=y
diff --git a/configs/lite5200b_LOWBOOT_defconfig b/configs/lite5200b_LOWBOOT_defconfig
deleted file mode 100644
index 9ceb834..0000000
--- a/configs/lite5200b_LOWBOOT_defconfig
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_SYS_EXTRA_OPTIONS="MPC5200_DDR,LITE5200B,SYS_TEXT_BASE=0xFF000000"
-CONFIG_PPC=y
-CONFIG_MPC5xxx=y
-CONFIG_TARGET_ICECUBE=y
diff --git a/configs/lite5200b_PM_defconfig b/configs/lite5200b_PM_defconfig
deleted file mode 100644
index 35b2aa3..0000000
--- a/configs/lite5200b_PM_defconfig
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_SYS_EXTRA_OPTIONS="MPC5200_DDR,LITE5200B,LITE5200B_PM"
-CONFIG_PPC=y
-CONFIG_MPC5xxx=y
-CONFIG_TARGET_ICECUBE=y
diff --git a/configs/lite5200b_defconfig b/configs/lite5200b_defconfig
deleted file mode 100644
index c7d4030..0000000
--- a/configs/lite5200b_defconfig
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_SYS_EXTRA_OPTIONS="MPC5200_DDR,LITE5200B"
-CONFIG_PPC=y
-CONFIG_MPC5xxx=y
-CONFIG_TARGET_ICECUBE=y
diff --git a/configs/mecp5200_defconfig b/configs/mecp5200_defconfig
deleted file mode 100644
index a30e224..0000000
--- a/configs/mecp5200_defconfig
+++ /dev/null
@@ -1,3 +0,0 @@
-CONFIG_PPC=y
-CONFIG_MPC5xxx=y
-CONFIG_TARGET_MECP5200=y
diff --git a/configs/pf5200_defconfig b/configs/pf5200_defconfig
deleted file mode 100644
index fe926a0..0000000
--- a/configs/pf5200_defconfig
+++ /dev/null
@@ -1,3 +0,0 @@
-CONFIG_PPC=y
-CONFIG_MPC5xxx=y
-CONFIG_TARGET_PF5200=y
diff --git a/doc/README.scrapyard b/doc/README.scrapyard
index a8eca4b..952ab87 100644
--- a/doc/README.scrapyard
+++ b/doc/README.scrapyard
@@ -12,6 +12,11 @@ The list should be sorted in reverse chronological order.
Board Arch CPU Commit Removed Last known maintainer/contact
=================================================================================================
+icecube_5200 powerpc mpc5xxx - - Wolfgang Denk <wd@denx.de>
+Lite5200 powerpc mpc5xxx - -
+cpci5200 powerpc mpc5xxx - - Reinhard Arlt <reinhard.arlt@esd-electronics.com>
+mecp5200 powerpc mpc5xxx - - Reinhard Arlt <reinhard.arlt@esd-electronics.com>
+pf5200 powerpc mpc5xxx - - Reinhard Arlt <reinhard.arlt@esd-electronics.com>
PM520 powerpc mpc5xxx - - Josef Wagner <Wagner@Microsys.de>
Total5200 powerpc mpc5xxx - -
CATcenter powerpc ppc4xx - -
diff --git a/include/configs/IceCube.h b/include/configs/IceCube.h
deleted file mode 100644
index 1861aa8..0000000
--- a/include/configs/IceCube.h
+++ /dev/null
@@ -1,403 +0,0 @@
-/*
- * (C) Copyright 2003-2005
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_MPC5200 1 /* This is a MPC5200 CPU */
-#define CONFIG_ICECUBE 1 /* ... on IceCube board */
-
-/*
- * Valid values for CONFIG_SYS_TEXT_BASE are:
- * 0xFFF00000 boot high (standard configuration)
- * 0xFF000000 boot low for 16 MiB boards
- * 0xFF800000 boot low for 8 MiB boards
- * 0x00100000 boot from RAM (for testing only)
- */
-#ifndef CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_TEXT_BASE 0xFFF00000
-#endif
-
-#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
-
-#define CONFIG_HIGH_BATS 1 /* High BATs supported */
-
-/*
- * Serial console configuration
- */
-#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
-#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
-#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
-
-
-/*
- * PCI Mapping:
- * 0x40000000 - 0x4fffffff - PCI Memory
- * 0x50000000 - 0x50ffffff - PCI IO Space
- */
-#define CONFIG_PCI
-
-#if defined(CONFIG_PCI)
-#define CONFIG_PCI_PNP 1
-#define CONFIG_PCI_SCAN_SHOW 1
-#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
-
-#define CONFIG_PCI_MEM_BUS 0x40000000
-#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
-#define CONFIG_PCI_MEM_SIZE 0x10000000
-
-#define CONFIG_PCI_IO_BUS 0x50000000
-#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
-#define CONFIG_PCI_IO_SIZE 0x01000000
-#endif
-
-#define CONFIG_SYS_XLB_PIPELINING 1
-
-#define CONFIG_MII 1
-#define CONFIG_EEPRO100 1
-#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
-#define CONFIG_NS8382X 1
-
-/* Partitions */
-#define CONFIG_MAC_PARTITION
-#define CONFIG_DOS_PARTITION
-#define CONFIG_ISO_PARTITION
-
-/* USB */
-#define CONFIG_USB_OHCI_NEW
-#define CONFIG_USB_STORAGE
-#define CONFIG_SYS_OHCI_BE_CONTROLLER
-#undef CONFIG_SYS_USB_OHCI_BOARD_INIT
-#define CONFIG_SYS_USB_OHCI_CPU_INIT 1
-#define CONFIG_SYS_USB_OHCI_REGS_BASE MPC5XXX_USB
-#define CONFIG_SYS_USB_OHCI_SLOT_NAME "mpc5200"
-#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
-
-#define CONFIG_TIMESTAMP /* Print image info with timestamp */
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_IDE
-#define CONFIG_CMD_NFS
-#define CONFIG_CMD_SNTP
-#define CONFIG_CMD_USB
-
-#if defined(CONFIG_PCI)
-#define CONFIG_CMD_PCI
-#endif
-
-
-#if (CONFIG_SYS_TEXT_BASE == 0xFF000000) /* Boot low with 16 MB Flash */
-# define CONFIG_SYS_LOWBOOT 1
-# define CONFIG_SYS_LOWBOOT16 1
-#endif
-#if (CONFIG_SYS_TEXT_BASE == 0xFF800000) /* Boot low with 8 MB Flash */
-#if defined(CONFIG_LITE5200B)
-# error CONFIG_SYS_LOWBOOT08 is incompatible with the Lite5200B
-#else
-# define CONFIG_SYS_LOWBOOT 1
-# define CONFIG_SYS_LOWBOOT08 1
-#endif
-#endif
-
-/*
- * Autobooting
- */
-#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
-
-#define CONFIG_PREBOOT "echo;" \
- "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
- "echo"
-
-#undef CONFIG_BOOTARGS
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "netdev=eth0\0" \
- "nfsargs=setenv bootargs root=/dev/nfs rw " \
- "nfsroot=${serverip}:${rootpath}\0" \
- "ramargs=setenv bootargs root=/dev/ram rw\0" \
- "addip=setenv bootargs ${bootargs} " \
- "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
- ":${hostname}:${netdev}:off panic=1\0" \
- "flash_nfs=run nfsargs addip;" \
- "bootm ${kernel_addr}\0" \
- "flash_self=run ramargs addip;" \
- "bootm ${kernel_addr} ${ramdisk_addr}\0" \
- "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
- "rootpath=/opt/eldk/ppc_82xx\0" \
- "bootfile=/tftpboot/MPC5200/uImage\0" \
- ""
-
-#define CONFIG_BOOTCOMMAND "run flash_self"
-
-/*
- * IPB Bus clocking configuration.
- */
-#if defined(CONFIG_LITE5200B)
-#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
-#else
-#undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
-#endif
-
-/* pass open firmware flat tree */
-#define CONFIG_OF_LIBFDT 1
-#define CONFIG_OF_BOARD_SETUP 1
-
-#define OF_CPU "PowerPC,5200 at 0"
-#define OF_SOC "soc5200 at f0000000"
-#define OF_TBCLK (bd->bi_busfreq / 4)
-#define OF_STDOUT_PATH "/soc5200 at f0000000/serial at 2000"
-
-/*
- * I2C configuration
- */
-#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
-#define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #1 or #2 */
-
-#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */
-#define CONFIG_SYS_I2C_SLAVE 0x7F
-
-/*
- * EEPROM configuration
- */
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 70
-
-/*
- * Flash configuration
- */
-#if defined(CONFIG_LITE5200B)
-#define CONFIG_SYS_FLASH_BASE 0xFE000000
-#define CONFIG_SYS_FLASH_SIZE 0x01000000
-#if !defined(CONFIG_SYS_LOWBOOT)
-#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x01760000 + 0x00800000)
-#else /* CONFIG_SYS_LOWBOOT */
-#if defined(CONFIG_SYS_LOWBOOT08)
-# error CONFIG_SYS_LOWBOOT08 is incompatible with the Lite5200B
-#endif
-#if defined(CONFIG_SYS_LOWBOOT16)
-#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x01060000)
-#endif
-#endif /* CONFIG_SYS_LOWBOOT */
-#else /* !CONFIG_LITE5200B (IceCube)*/
-#define CONFIG_SYS_FLASH_BASE 0xFF000000
-#define CONFIG_SYS_FLASH_SIZE 0x01000000
-#if !defined(CONFIG_SYS_LOWBOOT)
-#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00740000 + 0x00800000)
-#else /* CONFIG_SYS_LOWBOOT */
-#if defined(CONFIG_SYS_LOWBOOT08)
-#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00040000 + 0x00800000)
-#endif
-#if defined(CONFIG_SYS_LOWBOOT16)
-#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00040000)
-#endif
-#endif /* CONFIG_SYS_LOWBOOT */
-#endif /* CONFIG_LITE5200B */
-#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max num of memory banks */
-
-#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max num of sects on one chip */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
-
-#undef CONFIG_FLASH_16BIT /* Flash is 8-bit */
-
-#if defined(CONFIG_LITE5200B)
-#define CONFIG_FLASH_CFI_DRIVER
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_CS1_START,CONFIG_SYS_CS0_START}
-#endif
-
-
-/*
- * Environment settings
- */
-#define CONFIG_ENV_IS_IN_FLASH 1
-#define CONFIG_ENV_SIZE 0x10000
-#if defined(CONFIG_LITE5200B)
-#define CONFIG_ENV_SECT_SIZE 0x20000
-#else
-#define CONFIG_ENV_SECT_SIZE 0x10000
-#endif
-#define CONFIG_ENV_OVERWRITE 1
-
-/*
- * Memory map
- */
-#define CONFIG_SYS_MBAR 0xF0000000
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
-
-/* Use SRAM until RAM will be available */
-#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
-#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE /* Size of used area in DPRAM */
-
-
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
-#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
-# define CONFIG_SYS_RAMBOOT 1
-#endif
-
-#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
-#define CONFIG_SYS_MALLOC_LEN (512 << 10) /* Reserve 512 kB for malloc() */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-
-/*
- * Ethernet configuration
- */
-#define CONFIG_MPC5xxx_FEC 1
-#define CONFIG_MPC5xxx_FEC_MII100
-/*
- * Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb
- */
-/* #define CONFIG_MPC5xxx_FEC_MII10 */
-#define CONFIG_PHY_ADDR 0x00
-
-/*
- * GPIO configuration
- */
-#ifdef CONFIG_MPC5200_DDR
-#define CONFIG_SYS_GPS_PORT_CONFIG 0x90000004
-#else
-#define CONFIG_SYS_GPS_PORT_CONFIG 0x10000004
-#endif
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
-#define CONFIG_SYS_HUSH_PARSER 1 /* use "hush" command parser */
-
-#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
-
-#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
-
-#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
-#if defined(CONFIG_CMD_KGDB)
-# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
-#endif
-
-/*
- * Various low-level settings
- */
-#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
-#define CONFIG_SYS_HID0_FINAL HID0_ICE
-
-#if defined(CONFIG_LITE5200B)
-#define CONFIG_SYS_CS1_START CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_CS1_SIZE CONFIG_SYS_FLASH_SIZE
-#define CONFIG_SYS_CS1_CFG 0x00047800
-#define CONFIG_SYS_CS0_START (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE)
-#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
-#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_CS0_START
-#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
-#define CONFIG_SYS_BOOTCS_CFG 0x00047800
-#else /* IceCube aka Lite5200 */
-#ifdef CONFIG_MPC5200_DDR
-
-#define CONFIG_SYS_BOOTCS_START (CONFIG_SYS_CS1_START + CONFIG_SYS_CS1_SIZE)
-#define CONFIG_SYS_BOOTCS_SIZE 0x00800000
-#define CONFIG_SYS_BOOTCS_CFG 0x00047801
-#define CONFIG_SYS_CS1_START CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_CS1_SIZE 0x00800000
-#define CONFIG_SYS_CS1_CFG 0x00047800
-
-#else /* !CONFIG_MPC5200_DDR */
-
-#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
-#define CONFIG_SYS_BOOTCS_CFG 0x00047801
-#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
-
-#endif /* CONFIG_MPC5200_DDR */
-#endif /*CONFIG_LITE5200B */
-
-#define CONFIG_SYS_CS_BURST 0x00000000
-#define CONFIG_SYS_CS_DEADCYCLE 0x33333333
-
-#define CONFIG_SYS_RESET_ADDRESS 0xff000000
-
-/*-----------------------------------------------------------------------
- * USB stuff
- *-----------------------------------------------------------------------
- */
-#define CONFIG_USB_CLOCK 0x0001BBBB
-#define CONFIG_USB_CONFIG 0x00001000
-
-/*-----------------------------------------------------------------------
- * IDE/ATA stuff Supports IDE harddisk
- *-----------------------------------------------------------------------
- */
-
-#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
-
-#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
-#undef CONFIG_IDE_LED /* LED for ide not supported */
-
-#define CONFIG_IDE_RESET /* reset for ide supported */
-#define CONFIG_IDE_PREINIT
-
-#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
-#define CONFIG_SYS_IDE_MAXDEVICE 2 /* max. 1 drive per IDE bus */
-
-#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
-
-#define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA
-
-/* Offset for data I/O */
-#define CONFIG_SYS_ATA_DATA_OFFSET (0x0060)
-
-/* Offset for normal register accesses */
-#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET)
-
-/* Offset for alternate registers */
-#define CONFIG_SYS_ATA_ALT_OFFSET (0x005C)
-
-/* Interval between registers */
-#define CONFIG_SYS_ATA_STRIDE 4
-
-#define CONFIG_ATAPI 1
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/cpci5200.h b/include/configs/cpci5200.h
deleted file mode 100644
index ec926fd..0000000
--- a/include/configs/cpci5200.h
+++ /dev/null
@@ -1,390 +0,0 @@
-/*
- * (C) Copyright 2003-2004
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
-
- */
-
-/*************************************************************************
- * (c) 2005 esd gmbh Hannover
- *
- *
- * from IceCube.h file
- * by Reinhard Arlt reinhard.arlt at esd-electronics.com
- *
- *************************************************************************/
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */
-#define CONFIG_ICECUBE 1 /* ... on IceCube board */
-#define CONFIG_CPCI5200 1 /* ... on CPCI5200 board */
-#define CONFIG_MPC5200_DDR 1 /* ... use DDR RAM */
-
-#ifndef CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_TEXT_BASE 0xFFF00000 /* Standard: boot high */
-#endif
-
-#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
-
-#define CONFIG_HIGH_BATS 1 /* High BATs supported */
-
-/*
- * Serial console configuration
- */
-#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
-#define CONFIG_BAUDRATE 9600 /* ...@115200 bps */
-#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
-
-/*
- * PCI Mapping:
- * 0x40000000 - 0x4fffffff - PCI Memory
- * 0x50000000 - 0x50ffffff - PCI IO Space
- */
-#if 1
-#define CONFIG_PCI 1
-#if 1
-#define CONFIG_PCI_PNP 1
-#endif
-#define CONFIG_PCI_SCAN_SHOW 1
-#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
-
-#define CONFIG_PCI_MEM_BUS 0x40000000
-#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
-#define CONFIG_PCI_MEM_SIZE 0x10000000
-
-#define CONFIG_PCI_IO_BUS 0x50000000
-#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
-#define CONFIG_PCI_IO_SIZE 0x01000000
-#endif
-
-#define CONFIG_MII
-#if 0 /* test-only !!! */
-#define CONFIG_EEPRO100 1
-#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
-#define CONFIG_NS8382X 1
-#endif
-
-/* Partitions */
-#define CONFIG_MAC_PARTITION
-#define CONFIG_DOS_PARTITION
-
-/* USB */
-#if 0
-#define CONFIG_USB_OHCI
-#define CONFIG_USB_STORAGE
-#endif
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#if defined(CONFIG_PCI)
-#define CONFIG_CMD_PCI
-#endif
-
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_IDE
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_BSP
-#define CONFIG_CMD_ELF
-#define CONFIG_CMD_EXT2
-#define CONFIG_CMD_DATE
-
-#if (CONFIG_SYS_TEXT_BASE == 0xFF000000) /* Boot low with 16 MB Flash */
-# define CONFIG_SYS_LOWBOOT 1
-# define CONFIG_SYS_LOWBOOT16 1
-#endif
-#if (CONFIG_SYS_TEXT_BASE == 0xFF800000) /* Boot low with 8 MB Flash */
-# define CONFIG_SYS_LOWBOOT 1
-# define CONFIG_SYS_LOWBOOT08 1
-#endif
-
-/*
- * Autobooting
- */
-#define CONFIG_BOOTDELAY 3 /* autoboot after 5 seconds */
-
-#define CONFIG_PREBOOT "echo;" \
- "echo Welcome to esd CPU CPCI/5200;" \
- "echo"
-
-#undef CONFIG_BOOTARGS
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "netdev=eth0\0" \
- "flash_vxworks0=run ata_vxworks_args;setenv loadaddr ff000000;bootvx\0" \
- "flash_vxworks1=run ata_vxworks_args;setenv loadaddr ff200000:bootvx\0" \
- "net_vxworks=phypower 1;sleep 2;tftp ${loadaddr} ${image};run vxworks_args;bootvx\0" \
- "vxworks_args=setenv bootargs fec(0,0)${host}:${image} h=${serverip} e=${ipaddr} g=${gatewayip} u=${user} ${pass} tn=${target} s=${script}\0" \
- "ata_vxworks_args=setenv bootargs /ata0/vxWorks h=${serverip} e=${ipaddr} g=${gatewayip} u=${user} ${pass} tn=${target} s=${script} o=fec0 \0" \
- "loadaddr=01000000\0" \
- "serverip=192.168.2.99\0" \
- "gatewayip=10.0.0.79\0" \
- "user=mu\0" \
- "target=cpci5200.esd\0" \
- "script=cpci5200.bat\0" \
- "image=/tftpboot/vxWorks_cpci5200\0" \
- "ipaddr=10.0.13.196\0" \
- "netmask=255.255.0.0\0" \
- ""
-
-#define CONFIG_BOOTCOMMAND "run flash_vxworks0"
-
-#define CONFIG_RTC_M48T35A 1 /* ST Electronics M48 timekeeper */
-#define CONFIG_SYS_NVRAM_BASE_ADDR 0xfd010000
-#define CONFIG_SYS_NVRAM_SIZE 32*1024
-
-/*
- * IPB Bus clocking configuration.
- */
-#undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
-/*
- * I2C configuration
- */
-#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
-#define CONFIG_SYS_I2C_MODULE 1 /* Select I2C module #1 or #2 */
-
-#define CONFIG_SYS_I2C_SPEED 86000 /* 100 kHz */
-#define CONFIG_SYS_I2C_SLAVE 0x7F
-
-/*
- * EEPROM configuration
- */
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 20
-#define CONFIG_SYS_I2C_MULTI_EEPROMS 1
-/*
- * Flash configuration
- */
-
-#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
-#define CONFIG_SYS_FLASH_BASE 0xFE000000
-#define CONFIG_SYS_FLASH_SIZE 0x02000000
-#define CONFIG_SYS_FLASH_INCREMENT 0x01000000
-#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00000000)
-#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max num of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 128
-
-#define CONFIG_SYS_FLASH_PROTECTION 1 /* use hardware protection */
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
-
-/*
- * Environment settings
- */
-#if 1 /* test-only */
-#define CONFIG_ENV_IS_IN_FLASH 1
-#define CONFIG_ENV_SIZE 0x20000
-#define CONFIG_ENV_SECT_SIZE 0x20000
-#define CONFIG_ENV_OVERWRITE 1
-#else
-#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
-#define CONFIG_ENV_OFFSET 0x0000 /* environment starts at the beginning of the EEPROM */
-#define CONFIG_ENV_SIZE 0x0400 /* 8192 bytes may be used for env vars */
- /* total size of a CAT24WC32 is 8192 bytes */
-#define CONFIG_ENV_OVERWRITE 1
-#endif
-
-/*
- * Memory map
- */
-#define CONFIG_SYS_MBAR 0xF0000000
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
-
-/* Use SRAM until RAM will be available */
-#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
-#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE /* Size of used area in DPRAM */
-
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
-#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
-# define CONFIG_SYS_RAMBOOT 1
-#endif
-
-#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
-#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-
-/*
- * Ethernet configuration
- */
-#define CONFIG_MPC5xxx_FEC 1
-#define CONFIG_MPC5xxx_FEC_MII100
-/*
- * Define CONFIG_FEC_10MBIT to force FEC@10Mb
- */
-/* #define CONFIG_FEC_10MBIT 1 */
-#define CONFIG_PHY_ADDR 0x00
-#define CONFIG_UDP_CHECKSUM 1
-
-/*
- * GPIO configuration
- */
-#define CONFIG_SYS_GPS_PORT_CONFIG 0x01052444
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
-
-#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
-
-#define CONFIG_SYS_VXWORKS_MAC_PTR 0x00000000 /* Pass Ethernet MAC to VxWorks */
-
-#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
-#if defined(CONFIG_CMD_KGDB)
-# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
-#endif
-
-/*
- * Various low-level settings
- */
-#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
-#define CONFIG_SYS_HID0_FINAL HID0_ICE
-
-#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
-#define CONFIG_SYS_BOOTCS_CFG 0x0004DD00
-
-#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
-
-#define CONFIG_SYS_CS1_START 0xfd000000
-#define CONFIG_SYS_CS1_SIZE 0x00010000
-#define CONFIG_SYS_CS1_CFG 0x10101410
-
-#define CONFIG_SYS_CS3_START 0xfd010000
-#define CONFIG_SYS_CS3_SIZE 0x00010000
-#define CONFIG_SYS_CS3_CFG 0x10109410
-
-#define CONFIG_SYS_CS_BURST 0x00000000
-#define CONFIG_SYS_CS_DEADCYCLE 0x33333333
-
-#define CONFIG_SYS_RESET_ADDRESS 0xff000000
-
-/*-----------------------------------------------------------------------
- * USB stuff
- *-----------------------------------------------------------------------
- */
-#define CONFIG_USB_CLOCK 0x0001BBBB
-#define CONFIG_USB_CONFIG 0x00001000
-
-/*-----------------------------------------------------------------------
- * IDE/ATA stuff Supports IDE harddisk
- *-----------------------------------------------------------------------
- */
-
-#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
-
-#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
-#undef CONFIG_IDE_LED /* LED for ide not supported */
-
-#define CONFIG_IDE_RESET /* reset for ide supported */
-#define CONFIG_IDE_PREINIT
-
-#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
-#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
-
-#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
-
-#define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA
-
-/* Offset for data I/O */
-#define CONFIG_SYS_ATA_DATA_OFFSET (0x0060)
-
-/* Offset for normal register accesses */
-#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET)
-
-/* Offset for alternate registers */
-#define CONFIG_SYS_ATA_ALT_OFFSET (0x005C)
-
-/* Interval between registers */
-#define CONFIG_SYS_ATA_STRIDE 4
-
-/*-----------------------------------------------------------------------
- * CPLD stuff
- */
-#define CONFIG_SYS_FPGA_XC95XL 1 /* using Xilinx XC95XL CPLD */
-#define CONFIG_SYS_FPGA_MAX_SIZE 32*1024 /* 32kByte is enough for CPLD */
-
-/* CPLD program pin configuration */
-#define CONFIG_SYS_FPGA_PRG 0x20000000 /* JTAG TMS pin (ppc output) */
-#define CONFIG_SYS_FPGA_CLK 0x10000000 /* JTAG TCK pin (ppc output) */
-#define CONFIG_SYS_FPGA_DATA 0x20000000 /* JTAG TDO->TDI data pin (ppc output) */
-#define CONFIG_SYS_FPGA_DONE 0x10000000 /* JTAG TDI->TDO pin (ppc input) */
-
-#define JTAG_GPIO_ADDR_TMS (CONFIG_SYS_MBAR + 0xB10) /* JTAG TMS pin (GPS data out value reg.) */
-#define JTAG_GPIO_ADDR_TCK (CONFIG_SYS_MBAR + 0xC0C) /* JTAG TCK pin (GPW data out value reg.) */
-#define JTAG_GPIO_ADDR_TDI (CONFIG_SYS_MBAR + 0xC0C) /* JTAG TDO->TDI pin (GPW data out value reg.) */
-#define JTAG_GPIO_ADDR_TDO (CONFIG_SYS_MBAR + 0xB14) /* JTAG TDI->TDO pin (GPS data in value reg.) */
-
-#define JTAG_GPIO_ADDR_CFG (CONFIG_SYS_MBAR + 0xB00)
-#define JTAG_GPIO_CFG_SET 0x00000000
-#define JTAG_GPIO_CFG_RESET 0x00F00000
-
-#define JTAG_GPIO_ADDR_EN_TMS (CONFIG_SYS_MBAR + 0xB04)
-#define JTAG_GPIO_TMS_EN_SET 0x20000000 /* Enable for GPIO */
-#define JTAG_GPIO_TMS_EN_RESET 0x00000000
-#define JTAG_GPIO_ADDR_DDR_TMS (CONFIG_SYS_MBAR + 0xB0C)
-#define JTAG_GPIO_TMS_DDR_SET 0x20000000 /* Set as output */
-#define JTAG_GPIO_TMS_DDR_RESET 0x00000000
-
-#define JTAG_GPIO_ADDR_EN_TCK (CONFIG_SYS_MBAR + 0xC00)
-#define JTAG_GPIO_TCK_EN_SET 0x20000000 /* Enable for GPIO */
-#define JTAG_GPIO_TCK_EN_RESET 0x00000000
-#define JTAG_GPIO_ADDR_DDR_TCK (CONFIG_SYS_MBAR + 0xC08)
-#define JTAG_GPIO_TCK_DDR_SET 0x20000000 /* Set as output */
-#define JTAG_GPIO_TCK_DDR_RESET 0x00000000
-
-#define JTAG_GPIO_ADDR_EN_TDI (CONFIG_SYS_MBAR + 0xC00)
-#define JTAG_GPIO_TDI_EN_SET 0x10000000 /* Enable as GPIO */
-#define JTAG_GPIO_TDI_EN_RESET 0x00000000
-#define JTAG_GPIO_ADDR_DDR_TDI (CONFIG_SYS_MBAR + 0xC08)
-#define JTAG_GPIO_TDI_DDR_SET 0x10000000 /* Set as output */
-#define JTAG_GPIO_TDI_DDR_RESET 0x00000000
-
-#define JTAG_GPIO_ADDR_EN_TDO (CONFIG_SYS_MBAR + 0xB04)
-#define JTAG_GPIO_TDO_EN_SET 0x10000000 /* Enable as GPIO */
-#define JTAG_GPIO_TDO_EN_RESET 0x00000000
-#define JTAG_GPIO_ADDR_DDR_TDO (CONFIG_SYS_MBAR + 0xB0C)
-#define JTAG_GPIO_TDO_DDR_SET 0x00000000
-#define JTAG_GPIO_TDO_DDR_RESET 0x10000000 /* Set as input */
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/mecp5200.h b/include/configs/mecp5200.h
deleted file mode 100644
index b270429..0000000
--- a/include/configs/mecp5200.h
+++ /dev/null
@@ -1,319 +0,0 @@
-/*
- * (C) Copyright 2003-2004
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-
-/*************************************************************************
- * (c) 2005 esd gmbh Hannover
- *
- *
- * from IceCube.h file
- * by Reinhard Arlt reinhard.arlt at esd-electronics.com
- *
- *************************************************************************/
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */
-#define CONFIG_ICECUBE 1 /* ... on IceCube board */
-#define CONFIG_MECP5200 1 /* ... on MECP5200 board */
-#define CONFIG_MPC5200_DDR 1 /* ... use DDR RAM */
-
-#ifndef CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_TEXT_BASE 0xFFF00000
-#endif
-
-#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
-
-#define CONFIG_HIGH_BATS 1 /* High BATs supported */
-
-/*
- * Serial console configuration
- */
-#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
-#if 0 /* test-only */
-#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
-#else
-#define CONFIG_BAUDRATE 9600 /* ... at 115200 bps */
-#endif
-#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
-
-#define CONFIG_MII
-#if 0 /* test-only !!! */
-#define CONFIG_EEPRO100 1
-#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
-#define CONFIG_NS8382X 1
-#endif
-
-/* Partitions */
-#define CONFIG_MAC_PARTITION
-#define CONFIG_DOS_PARTITION
-
-/* USB */
-#if 0
-#define CONFIG_USB_OHCI
-#define CONFIG_USB_STORAGE
-#endif
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_EXT2
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_IDE
-#define CONFIG_CMD_BSP
-#define CONFIG_CMD_ELF
-
-
-#if (CONFIG_SYS_TEXT_BASE == 0xFF000000) /* Boot low with 16 MB Flash */
-# define CONFIG_SYS_LOWBOOT 1
-# define CONFIG_SYS_LOWBOOT16 1
-#endif
-#if (CONFIG_SYS_TEXT_BASE == 0xFF800000) /* Boot low with 8 MB Flash */
-# define CONFIG_SYS_LOWBOOT 1
-# define CONFIG_SYS_LOWBOOT08 1
-#endif
-
-/*
- * Autobooting
- */
-#define CONFIG_BOOTDELAY 3 /* autoboot after 5 seconds */
-
-#define CONFIG_PREBOOT "echo;" \
- "echo Welcome to CBX-CPU5200 (mecp5200);" \
- "echo"
-
-#undef CONFIG_BOOTARGS
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "netdev=eth0\0" \
- "flash_vxworks0=run ata_vxworks_args;setenv loadaddr ff000000;bootvx\0" \
- "flash_vxworks1=run ata_vxworks_args;setenv loadaddr ff200000:bootvx\0" \
- "net_vxworks=tftp $(loadaddr) $(image);run vxworks_args;bootvx\0" \
- "vxworks_args=setenv bootargs fec(0,0)$(host):$(image) h=$(serverip) e=$(ipaddr) g=$(gatewayip) u=$(user) $(pass) tn=$(target) s=$(script)\0" \
- "ata_vxworks_args=setenv bootargs /ata0/vxWorks h=$(serverip) e=$(ipaddr) g=$(gatewayip) u=$(user) $(pass) tn=$(target) s=$(script) o=fec0 \0" \
- "loadaddr=01000000\0" \
- "serverip=192.168.2.99\0" \
- "gatewayip=10.0.0.79\0" \
- "user=mu\0" \
- "target=mecp5200.esd\0" \
- "script=mecp5200.bat\0" \
- "image=/tftpboot/vxWorks_mecp5200\0" \
- "ipaddr=10.0.13.196\0" \
- "netmask=255.255.0.0\0" \
- ""
-
-#define CONFIG_BOOTCOMMAND "run flash_vxworks0"
-
-/*
- * IPB Bus clocking configuration.
- */
-#undef CONFIG_SYS_IPBSPEED_133 /* define for 133MHz speed */
-/*
- * I2C configuration
- */
-#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
-#define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #1 or #2 */
-
-#define CONFIG_SYS_I2C_SPEED 86000 /* 100 kHz */
-#define CONFIG_SYS_I2C_SLAVE 0x7F
-
-/*
- * EEPROM configuration
- */
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 20
-#define CONFIG_SYS_I2C_MULTI_EEPROMS 1
-/*
- * Flash configuration
- */
-#define CONFIG_SYS_FLASH_BASE 0xFFC00000
-#define CONFIG_SYS_FLASH_SIZE 0x00400000
-#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x003E0000)
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 512
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
-
-/*
- * Environment settings
- */
-#if 1 /* test-only */
-#define CONFIG_ENV_IS_IN_FLASH 1
-#define CONFIG_ENV_SIZE 0x10000
-#define CONFIG_ENV_SECT_SIZE 0x10000
-#define CONFIG_ENV_OVERWRITE 1
-#else
-#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
-#define CONFIG_ENV_OFFSET 0x0000 /* environment starts at the beginning of the EEPROM */
-#define CONFIG_ENV_SIZE 0x0400 /* 8192 bytes may be used for env vars*/
- /* total size of a CAT24WC32 is 8192 bytes */
-#define CONFIG_ENV_OVERWRITE 1
-#endif
-
-#define CONFIG_FLASH_CFI_DRIVER 1 /* Flash is CFI conformant */
-#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
-#define CONFIG_SYS_FLASH_PROTECTION 1 /* use hardware protection */
-#if 0
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
-#endif
-#define CONFIG_SYS_FLASH_INCREMENT 0x00400000 /* size of flash bank */
-#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
-#define CONFIG_SYS_FLASH_EMPTY_INFO 1 /* show if bank is empty */
-
-
-/*
- * Memory map
- */
-#define CONFIG_SYS_MBAR 0xF0000000
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
-
-/* Use SRAM until RAM will be available */
-#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
-#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE /* Size of used area in DPRAM */
-
-
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
-#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
-# define CONFIG_SYS_RAMBOOT 1
-#endif
-
-#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
-#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-
-/*
- * Ethernet configuration
- */
-#define CONFIG_MPC5xxx_FEC 1
-#define CONFIG_MPC5xxx_FEC_MII100
-/*
- * Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb
- */
-/* #define CONFIG_MPC5xxx_FEC_MII10 */
-#define CONFIG_PHY_ADDR 0x00
-#define CONFIG_UDP_CHECKSUM 1
-
-
-/*
- * GPIO configuration
- */
-#define CONFIG_SYS_GPS_PORT_CONFIG 0x01052444
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
-
-#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
-
-#define CONFIG_SYS_VXWORKS_MAC_PTR 0x00000000 /* Pass Ethernet MAC to VxWorks */
-
-#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
-#if defined(CONFIG_CMD_KGDB)
-# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
-#endif
-
-/*
- * Various low-level settings
- */
-#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
-#define CONFIG_SYS_HID0_FINAL HID0_ICE
-
-#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
-#define CONFIG_SYS_BOOTCS_CFG 0x00085d00
-
-#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
-
-#define CONFIG_SYS_CS1_START 0xfd000000
-#define CONFIG_SYS_CS1_SIZE 0x00010000
-#define CONFIG_SYS_CS1_CFG 0x10101410
-
-#define CONFIG_SYS_CS_BURST 0x00000000
-#define CONFIG_SYS_CS_DEADCYCLE 0x33333333
-
-#define CONFIG_SYS_RESET_ADDRESS 0xff000000
-
-/*-----------------------------------------------------------------------
- * USB stuff
- *-----------------------------------------------------------------------
- */
-#define CONFIG_USB_CLOCK 0x0001BBBB
-#define CONFIG_USB_CONFIG 0x00001000
-
-/*-----------------------------------------------------------------------
- * IDE/ATA stuff Supports IDE harddisk
- *-----------------------------------------------------------------------
- */
-
-#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
-
-#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
-#undef CONFIG_IDE_LED /* LED for ide not supported */
-
-#define CONFIG_IDE_RESET /* reset for ide supported */
-#define CONFIG_IDE_PREINIT
-
-#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
-#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
-
-#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
-
-#define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA
-
-/* Offset for data I/O */
-#define CONFIG_SYS_ATA_DATA_OFFSET (0x0060)
-
-/* Offset for normal register accesses */
-#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET)
-
-/* Offset for alternate registers */
-#define CONFIG_SYS_ATA_ALT_OFFSET (0x005C)
-
-/* Interval between registers */
-#define CONFIG_SYS_ATA_STRIDE 4
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/pf5200.h b/include/configs/pf5200.h
deleted file mode 100644
index be76478..0000000
--- a/include/configs/pf5200.h
+++ /dev/null
@@ -1,372 +0,0 @@
-/*
- * (C) Copyright 2003-2004
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*************************************************************************
- * (c) 2005 esd gmbh Hannover
- *
- *
- * from IceCube.h file
- * by Reinhard Arlt reinhard.arlt at esd-electronics.com
- *
- *************************************************************************/
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */
-#define CONFIG_ICECUBE 1 /* ... on IceCube board */
-#define CONFIG_PF5200 1 /* ... on PF5200 board */
-#define CONFIG_MPC5200_DDR 1 /* ... use DDR RAM */
-
-#ifndef CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_TEXT_BASE 0xFFF00000
-#endif
-
-#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
-
-#define CONFIG_HIGH_BATS 1 /* High BATs supported */
-/*
- * Serial console configuration
- */
-#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
-#if 0 /* test-only */
-#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
-#else
-#define CONFIG_BAUDRATE 9600 /* ...@115200 bps */
-#endif
-#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
-
-/*
- * PCI Mapping:
- * 0x40000000 - 0x4fffffff - PCI Memory
- * 0x50000000 - 0x50ffffff - PCI IO Space
- */
-#define CONFIG_PCI 1
-#define CONFIG_PCI_PNP 1
-#define CONFIG_PCI_SCAN_SHOW 1
-#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
-
-#define CONFIG_PCI_MEM_BUS 0x40000000
-#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
-#define CONFIG_PCI_MEM_SIZE 0x10000000
-
-#define CONFIG_PCI_IO_BUS 0x50000000
-#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
-#define CONFIG_PCI_IO_SIZE 0x01000000
-
-#define CONFIG_MII 1
-#if 0 /* test-only !!! */
-#define CONFIG_EEPRO100 1
-#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
-#define CONFIG_NS8382X 1
-#endif
-
-/* Partitions */
-#define CONFIG_MAC_PARTITION
-#define CONFIG_DOS_PARTITION
-
-/* USB */
-#if 0
-#define CONFIG_USB_OHCI
-#define CONFIG_USB_STORAGE
-#endif
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_BSP
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_ELF
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_IDE
-
-#define CONFIG_CMD_PCI
-
-
-#if (CONFIG_SYS_TEXT_BASE == 0xFF000000) /* Boot low with 16 MB Flash */
-# define CONFIG_SYS_LOWBOOT 1
-# define CONFIG_SYS_LOWBOOT16 1
-#endif
-#if (CONFIG_SYS_TEXT_BASE == 0xFF800000) /* Boot low with 8 MB Flash */
-# define CONFIG_SYS_LOWBOOT 1
-# define CONFIG_SYS_LOWBOOT08 1
-#endif
-
-/*
- * Autobooting
- */
-#define CONFIG_BOOTDELAY 3 /* autoboot after 5 seconds */
-
-#define CONFIG_PREBOOT "echo;" \
- "echo Welcome to ParaFinder pf5200;" \
- "echo"
-
-#undef CONFIG_BOOTARGS
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "netdev=eth0\0" \
- "flash_vxworks0=run ata_vxworks_args;setenv loadaddr ff000000;bootvx\0" \
- "flash_vxworks1=run ata_vxworks_args;setenv loadaddr ff200000:bootvx\0" \
- "net_vxworks=phypower 1;sleep 2;tftp ${loadaddr} ${image};run vxworks_args;bootvx\0" \
- "vxworks_args=setenv bootargs fec(0,0)${host}:${image} h=${serverip} e=${ipaddr} g=${gatewayip} u=${user} ${pass} tn=${target} s=${script}\0" \
- "ata_vxworks_args=setenv bootargs /ata0/vxWorks h=${serverip} e=${ipaddr} g=${gatewayip} u=${user} ${pass} tn=${target} s=${script} o=fec0 \0" \
- "loadaddr=01000000\0" \
- "serverip=192.168.2.99\0" \
- "gatewayip=10.0.0.79\0" \
- "user=mu\0" \
- "target=pf5200.esd\0" \
- "script=pf5200.bat\0" \
- "image=/tftpboot/vxWorks_pf5200\0" \
- "ipaddr=10.0.13.196\0" \
- "netmask=255.255.0.0\0" \
- ""
-
-#define CONFIG_BOOTCOMMAND "run flash_vxworks0"
-
-/*
- * IPB Bus clocking configuration.
- */
-#undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
-/*
- * I2C configuration
- */
-#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
-#define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #1 or #2 */
-
-#define CONFIG_SYS_I2C_SPEED 86000 /* 100 kHz */
-#define CONFIG_SYS_I2C_SLAVE 0x7F
-
-/*
- * EEPROM configuration
- */
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 20
-#define CONFIG_SYS_I2C_MULTI_EEPROMS 1
-/*
- * Flash configuration
- */
-#define CONFIG_SYS_FLASH_BASE 0xFE000000
-#define CONFIG_SYS_FLASH_SIZE 0x02000000
-#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00000000)
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 512
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
-
-/*
- * Environment settings
- */
-#if 1 /* test-only */
-#define CONFIG_ENV_IS_IN_FLASH
-#define CONFIG_ENV_SIZE 0x10000
-#define CONFIG_ENV_SECT_SIZE 0x10000
-#define CONFIG_ENV_OVERWRITE 1
-#else
-#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
-#define CONFIG_ENV_OFFSET 0x0000 /* environment starts at the beginning of the EEPROM */
-#define CONFIG_ENV_SIZE 0x0400 /* 8192 bytes may be used for env vars */
- /* total size of a CAT24WC32 is 8192 bytes */
-#define CONFIG_ENV_OVERWRITE 1
-#endif
-
-/*
- * Memory map
- */
-#define CONFIG_SYS_MBAR 0xF0000000
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
-
-/* Use SRAM until RAM will be available */
-#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
-#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE /* Size of used area in DPRAM */
-
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
-#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
-# define CONFIG_SYS_RAMBOOT 1
-#endif
-
-#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
-#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-
-/*
- * Ethernet configuration
- */
-#define CONFIG_MPC5xxx_FEC 1
-#define CONFIG_MPC5xxx_FEC_MII100
-/*
- * Define CONFIG_MPC5xxx_FEC_MII10 to force FEC@10Mb
- */
-/* #define CONFIG_MPC5xxx_FEC_MII10 */
-#define CONFIG_PHY_ADDR 0x00
-#define CONFIG_UDP_CHECKSUM 1
-
-/*
- * GPIO configuration
- */
-#define CONFIG_SYS_GPS_PORT_CONFIG 0x01052444
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
-
-#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
-
-#define CONFIG_SYS_VXWORKS_MAC_PTR 0x00000000 /* Pass Ethernet MAC to VxWorks */
-
-#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
-#if defined(CONFIG_CMD_KGDB)
-# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
-#endif
-
-/*
- * Various low-level settings
- */
-#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
-#define CONFIG_SYS_HID0_FINAL HID0_ICE
-
-#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
-#define CONFIG_SYS_BOOTCS_CFG 0x0004DD00
-
-#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
-
-#define CONFIG_SYS_CS1_START 0xfd000000
-#define CONFIG_SYS_CS1_SIZE 0x00010000
-#define CONFIG_SYS_CS1_CFG 0x10101410
-
-#define CONFIG_SYS_CS_BURST 0x00000000
-#define CONFIG_SYS_CS_DEADCYCLE 0x33333333
-
-#define CONFIG_SYS_RESET_ADDRESS 0xff000000
-
-/*-----------------------------------------------------------------------
- * USB stuff
- *-----------------------------------------------------------------------
- */
-#define CONFIG_USB_CLOCK 0x0001BBBB
-#define CONFIG_USB_CONFIG 0x00001000
-
-/*-----------------------------------------------------------------------
- * IDE/ATA stuff Supports IDE harddisk
- *-----------------------------------------------------------------------
- */
-
-#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
-
-#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
-#undef CONFIG_IDE_LED /* LED for ide not supported */
-
-#define CONFIG_IDE_RESET /* reset for ide supported */
-#define CONFIG_IDE_PREINIT
-
-#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
-#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
-
-#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
-
-#define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA
-
-/* Offset for data I/O */
-#define CONFIG_SYS_ATA_DATA_OFFSET (0x0060)
-
-/* Offset for normal register accesses */
-#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET)
-
-/* Offset for alternate registers */
-#define CONFIG_SYS_ATA_ALT_OFFSET (0x005C)
-
-/* Interval between registers */
-#define CONFIG_SYS_ATA_STRIDE 4
-
-/*-----------------------------------------------------------------------
- * CPLD stuff
- */
-#define CONFIG_SYS_FPGA_XC95XL 1 /* using Xilinx XC95XL CPLD */
-#define CONFIG_SYS_FPGA_MAX_SIZE 32*1024 /* 32kByte is enough for CPLD */
-
-/* CPLD program pin configuration */
-#define CONFIG_SYS_FPGA_PRG 0x20000000 /* JTAG TMS pin (ppc output) */
-#define CONFIG_SYS_FPGA_CLK 0x10000000 /* JTAG TCK pin (ppc output) */
-#define CONFIG_SYS_FPGA_DATA 0x20000000 /* JTAG TDO->TDI data pin (ppc output) */
-#define CONFIG_SYS_FPGA_DONE 0x10000000 /* JTAG TDI->TDO pin (ppc input) */
-
-#define JTAG_GPIO_ADDR_TMS (CONFIG_SYS_MBAR + 0xB10) /* JTAG TMS pin (GPS data out value reg.) */
-#define JTAG_GPIO_ADDR_TCK (CONFIG_SYS_MBAR + 0xC0C) /* JTAG TCK pin (GPW data out value reg.) */
-#define JTAG_GPIO_ADDR_TDI (CONFIG_SYS_MBAR + 0xC0C) /* JTAG TDO->TDI pin (GPW data out value reg.) */
-#define JTAG_GPIO_ADDR_TDO (CONFIG_SYS_MBAR + 0xB14) /* JTAG TDI->TDO pin (GPS data in value reg.) */
-
-#define JTAG_GPIO_ADDR_CFG (CONFIG_SYS_MBAR + 0xB00)
-#define JTAG_GPIO_CFG_SET 0x00000000
-#define JTAG_GPIO_CFG_RESET 0x00F00000
-
-#define JTAG_GPIO_ADDR_EN_TMS (CONFIG_SYS_MBAR + 0xB04)
-#define JTAG_GPIO_TMS_EN_SET 0x20000000 /* Enable for GPIO */
-#define JTAG_GPIO_TMS_EN_RESET 0x00000000
-#define JTAG_GPIO_ADDR_DDR_TMS (CONFIG_SYS_MBAR + 0xB0C)
-#define JTAG_GPIO_TMS_DDR_SET 0x20000000 /* Set as output */
-#define JTAG_GPIO_TMS_DDR_RESET 0x00000000
-
-#define JTAG_GPIO_ADDR_EN_TCK (CONFIG_SYS_MBAR + 0xC00)
-#define JTAG_GPIO_TCK_EN_SET 0x20000000 /* Enable for GPIO */
-#define JTAG_GPIO_TCK_EN_RESET 0x00000000
-#define JTAG_GPIO_ADDR_DDR_TCK (CONFIG_SYS_MBAR + 0xC08)
-#define JTAG_GPIO_TCK_DDR_SET 0x20000000 /* Set as output */
-#define JTAG_GPIO_TCK_DDR_RESET 0x00000000
-
-#define JTAG_GPIO_ADDR_EN_TDI (CONFIG_SYS_MBAR + 0xC00)
-#define JTAG_GPIO_TDI_EN_SET 0x10000000 /* Enable as GPIO */
-#define JTAG_GPIO_TDI_EN_RESET 0x00000000
-#define JTAG_GPIO_ADDR_DDR_TDI (CONFIG_SYS_MBAR + 0xC08)
-#define JTAG_GPIO_TDI_DDR_SET 0x10000000 /* Set as output */
-#define JTAG_GPIO_TDI_DDR_RESET 0x00000000
-
-#define JTAG_GPIO_ADDR_EN_TDO (CONFIG_SYS_MBAR + 0xB04)
-#define JTAG_GPIO_TDO_EN_SET 0x10000000 /* Enable as GPIO */
-#define JTAG_GPIO_TDO_EN_RESET 0x00000000
-#define JTAG_GPIO_ADDR_DDR_TDO (CONFIG_SYS_MBAR + 0xB0C)
-#define JTAG_GPIO_TDO_DDR_SET 0x00000000
-#define JTAG_GPIO_TDO_DDR_RESET 0x10000000 /* Set as input */
-
-#endif /* __CONFIG_H */
--
1.9.1
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [U-Boot] [PATCH 5/8] powerpc: ppc4xx: remove PPChameleonEVB, CATcenter boards
2015-01-22 15:24 ` [U-Boot] [PATCH 5/8] powerpc: ppc4xx: remove PPChameleonEVB, CATcenter boards Masahiro Yamada
@ 2015-01-22 15:41 ` Stefan Roese
2015-01-23 21:57 ` Tom Rini
1 sibling, 0 replies; 19+ messages in thread
From: Stefan Roese @ 2015-01-22 15:41 UTC (permalink / raw)
To: u-boot
On 22.01.2015 16:24, Masahiro Yamada wrote:
> These boards are still non-generic boards.
>
> It is a good thing that we can drop board-specific hack code
> from drivers/mtd/nand/nand_base.c
>
> Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
> Cc: Andrea "llandre" Marson <andrea.marson@dave-tech.it>
If nobody speaks up to maintain those 4xx board I'm fine to remove them. So:
Acked-by: Stefan Roese <sr@denx.de>
Thanks,
Stefan
^ permalink raw reply [flat|nested] 19+ messages in thread
* [U-Boot] [PATCH 3/8] powerpc: mpc85xx: remove P2020COME board support
2015-01-22 15:24 ` [U-Boot] [PATCH 3/8] powerpc: mpc85xx: remove P2020COME board support Masahiro Yamada
@ 2015-01-22 17:52 ` Ira Snyder
2015-01-23 21:57 ` Tom Rini
1 sibling, 0 replies; 19+ messages in thread
From: Ira Snyder @ 2015-01-22 17:52 UTC (permalink / raw)
To: u-boot
On Thu, Jan 22, 2015 at 7:24 AM, Masahiro Yamada
<yamada.m@jp.panasonic.com> wrote:
> This board is still a non-generic board.
>
Hi Masahiro,
This is fine by me. I no longer work for Caltech OVRO, and therefore
no longer have access to this hardware.
Freescale still has these boards for sale. Their team may want to
maintain the board.
Thanks,
Ira
> Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
> Cc: Ira W. Snyder <iws@ovro.caltech.edu>
> ---
>
> arch/powerpc/cpu/mpc85xx/Kconfig | 4 -
> board/freescale/p2020come/Kconfig | 12 -
> board/freescale/p2020come/MAINTAINERS | 7 -
> board/freescale/p2020come/Makefile | 10 -
> board/freescale/p2020come/ddr.c | 29 --
> board/freescale/p2020come/law.c | 23 --
> board/freescale/p2020come/p2020come.c | 275 -----------------
> board/freescale/p2020come/tlb.c | 83 ------
> configs/P2020COME_SDCARD_defconfig | 4 -
> configs/P2020COME_SPIFLASH_defconfig | 4 -
> doc/README.scrapyard | 1 +
> include/configs/P2020COME.h | 547 ----------------------------------
> 12 files changed, 1 insertion(+), 998 deletions(-)
> delete mode 100644 board/freescale/p2020come/Kconfig
> delete mode 100644 board/freescale/p2020come/MAINTAINERS
> delete mode 100644 board/freescale/p2020come/Makefile
> delete mode 100644 board/freescale/p2020come/ddr.c
> delete mode 100644 board/freescale/p2020come/law.c
> delete mode 100644 board/freescale/p2020come/p2020come.c
> delete mode 100644 board/freescale/p2020come/tlb.c
> delete mode 100644 configs/P2020COME_SDCARD_defconfig
> delete mode 100644 configs/P2020COME_SPIFLASH_defconfig
> delete mode 100644 include/configs/P2020COME.h
>
> diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig
> index 009d830..e643f91 100644
> --- a/arch/powerpc/cpu/mpc85xx/Kconfig
> +++ b/arch/powerpc/cpu/mpc85xx/Kconfig
> @@ -93,9 +93,6 @@ config TARGET_P1_P2_RDB_PC
> config TARGET_P1_TWR
> bool "Support p1_twr"
>
> -config TARGET_P2020COME
> - bool "Support P2020COME"
> -
> config TARGET_P2020DS
> bool "Support P2020DS"
>
> @@ -181,7 +178,6 @@ source "board/freescale/p1022ds/Kconfig"
> source "board/freescale/p1023rdb/Kconfig"
> source "board/freescale/p1_p2_rdb_pc/Kconfig"
> source "board/freescale/p1_twr/Kconfig"
> -source "board/freescale/p2020come/Kconfig"
> source "board/freescale/p2020ds/Kconfig"
> source "board/freescale/p2041rdb/Kconfig"
> source "board/freescale/qemu-ppce500/Kconfig"
> diff --git a/board/freescale/p2020come/Kconfig b/board/freescale/p2020come/Kconfig
> deleted file mode 100644
> index 8ce5cf1..0000000
> --- a/board/freescale/p2020come/Kconfig
> +++ /dev/null
> @@ -1,12 +0,0 @@
> -if TARGET_P2020COME
> -
> -config SYS_BOARD
> - default "p2020come"
> -
> -config SYS_VENDOR
> - default "freescale"
> -
> -config SYS_CONFIG_NAME
> - default "P2020COME"
> -
> -endif
> diff --git a/board/freescale/p2020come/MAINTAINERS b/board/freescale/p2020come/MAINTAINERS
> deleted file mode 100644
> index ab3ef94..0000000
> --- a/board/freescale/p2020come/MAINTAINERS
> +++ /dev/null
> @@ -1,7 +0,0 @@
> -P2020COME BOARD
> -M: Ira W. Snyder <iws@ovro.caltech.edu>
> -S: Maintained
> -F: board/freescale/p2020come/
> -F: include/configs/P2020COME.h
> -F: configs/P2020COME_SDCARD_defconfig
> -F: configs/P2020COME_SPIFLASH_defconfig
> diff --git a/board/freescale/p2020come/Makefile b/board/freescale/p2020come/Makefile
> deleted file mode 100644
> index 4857136..0000000
> --- a/board/freescale/p2020come/Makefile
> +++ /dev/null
> @@ -1,10 +0,0 @@
> -#
> -# Copyright 2009 Freescale Semiconductor, Inc.
> -#
> -# SPDX-License-Identifier: GPL-2.0+
> -#
> -
> -obj-y += p2020come.o
> -obj-y += ddr.o
> -obj-y += law.o
> -obj-y += tlb.o
> diff --git a/board/freescale/p2020come/ddr.c b/board/freescale/p2020come/ddr.c
> deleted file mode 100644
> index b642e12..0000000
> --- a/board/freescale/p2020come/ddr.c
> +++ /dev/null
> @@ -1,29 +0,0 @@
> -/*
> - * Copyright 2009, 2011 Freescale Semiconductor, Inc.
> - *
> - * SPDX-License-Identifier: GPL-2.0+
> - */
> -#include <common.h>
> -
> -#include <fsl_ddr_sdram.h>
> -#include <fsl_ddr_dimm_params.h>
> -
> -void fsl_ddr_board_options(memctl_options_t *popts,
> - dimm_params_t *pdimm,
> - unsigned int ctrl_num)
> -{
> - if (ctrl_num) {
> - printf("Wrong parameter for controller number %d", ctrl_num);
> - return;
> - }
> -
> - if (!pdimm->n_ranks)
> - return;
> -
> - /*
> - * Set DDR_SDRAM_CLK_CNTL = 0x02800000
> - *
> - * Clock is launched 5/8 applied cycle after address/command
> - */
> - popts->clk_adjust = 5;
> -}
> diff --git a/board/freescale/p2020come/law.c b/board/freescale/p2020come/law.c
> deleted file mode 100644
> index 7048a08..0000000
> --- a/board/freescale/p2020come/law.c
> +++ /dev/null
> @@ -1,23 +0,0 @@
> -/*
> - * Copyright 2009 Freescale Semiconductor, Inc.
> - *
> - * SPDX-License-Identifier: GPL-2.0+
> - */
> -
> -#include <common.h>
> -#include <asm/fsl_law.h>
> -#include <asm/mmu.h>
> -
> -/*
> - * Create a dummy LAW entry for the DDR SDRAM which will be replaced when
> - * the DDR SPD setup code runs.
> - *
> - * This table would be empty, except that it is used before the BSS section is
> - * initialized, and therefore must have at least one entry to push it into
> - * the DATA section.
> - */
> -struct law_entry law_table[] = {
> - SET_LAW(CONFIG_SYS_SDRAM_BASE, LAW_SIZE_4K, LAW_TRGT_IF_DDR),
> -};
> -
> -int num_law_entries = ARRAY_SIZE(law_table);
> diff --git a/board/freescale/p2020come/p2020come.c b/board/freescale/p2020come/p2020come.c
> deleted file mode 100644
> index 1db37e3..0000000
> --- a/board/freescale/p2020come/p2020come.c
> +++ /dev/null
> @@ -1,275 +0,0 @@
> -/*
> - * Copyright 2009,2012 Freescale Semiconductor, Inc.
> - *
> - * SPDX-License-Identifier: GPL-2.0+
> - */
> -
> -#include <common.h>
> -#include <hwconfig.h>
> -#include <command.h>
> -#include <asm/processor.h>
> -#include <asm/mmu.h>
> -#include <asm/cache.h>
> -#include <asm/immap_85xx.h>
> -#include <asm/mpc85xx_gpio.h>
> -#include <asm/fsl_serdes.h>
> -#include <asm/io.h>
> -#include <miiphy.h>
> -#include <libfdt.h>
> -#include <fdt_support.h>
> -#include <fsl_mdio.h>
> -#include <tsec.h>
> -#include <vsc7385.h>
> -#include <netdev.h>
> -#include <mmc.h>
> -#include <malloc.h>
> -#include <i2c.h>
> -
> -#if defined(CONFIG_PCI)
> -#include <asm/fsl_pci.h>
> -#include <pci.h>
> -#endif
> -
> -DECLARE_GLOBAL_DATA_PTR;
> -
> -#if defined(CONFIG_PCI)
> -void pci_init_board(void)
> -{
> - fsl_pcie_init_board(0);
> -}
> -
> -void ft_pci_board_setup(void *blob)
> -{
> - FT_FSL_PCI_SETUP;
> -}
> -#endif
> -
> -#define BOARD_PERI_RST_SET (VSC7385_RST_SET | SLIC_RST_SET | \
> - SGMII_PHY_RST_SET | PCIE_RST_SET | \
> - RGMII_PHY_RST_SET)
> -
> -#define SYSCLK_MASK 0x00200000
> -#define BOARDREV_MASK 0x10100000
> -#define BOARDREV_B 0x10100000
> -#define BOARDREV_C 0x00100000
> -#define BOARDREV_D 0x00000000
> -
> -#define SYSCLK_66 66666666
> -#define SYSCLK_50 50000000
> -#define SYSCLK_100 100000000
> -
> -unsigned long get_board_sys_clk(ulong dummy)
> -{
> - ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
> - u32 ddr_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO;
> -
> - ddr_ratio >>= MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
> - switch (ddr_ratio) {
> - case 0x0C:
> - return SYSCLK_66;
> - case 0x0A:
> - case 0x08:
> - return SYSCLK_100;
> - default:
> - puts("ERROR: unknown DDR ratio\n");
> - return SYSCLK_100;
> - }
> -}
> -
> -unsigned long get_board_ddr_clk(ulong dummy)
> -{
> - ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
> - u32 ddr_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO;
> -
> - ddr_ratio >>= MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
> - switch (ddr_ratio) {
> - case 0x0C:
> - case 0x0A:
> - return SYSCLK_66;
> - case 0x08:
> - return SYSCLK_100;
> - default:
> - puts("ERROR: unknown DDR ratio\n");
> - return SYSCLK_100;
> - }
> -}
> -
> -#ifdef CONFIG_MMC
> -int board_early_init_f(void)
> -{
> - ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
> -
> - setbits_be32(&gur->pmuxcr,
> - (MPC85xx_PMUXCR_SDHC_CD |
> - MPC85xx_PMUXCR_SDHC_WP));
> -
> - /* All the device are enable except for SRIO12 */
> - setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_SRIO);
> - return 0;
> -}
> -#endif
> -
> -#define GPIO_DIR 0x0f3a0000
> -#define GPIO_ODR 0x00000000
> -#define GPIO_DAT 0x001a0000
> -
> -int checkboard(void)
> -{
> - ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR + 0xC00);
> -
> - /*
> - * GPIO
> - * 0 - 3: CarryBoard Input;
> - * 4 - 7: CarryBoard Output;
> - * 8 : Mux as SDHC_CD (card detection)
> - * 9 : Mux as SDHC_WP
> - * 10 : Clear Watchdog timer
> - * 11 : LED Input
> - * 12 : Output to 1
> - * 13 : Open Drain
> - * 14 : LED Output
> - * 15 : Switch Input
> - *
> - * Set GPIOs 11, 12, 14 to 1.
> - */
> - out_be32(&pgpio->gpodr, GPIO_ODR);
> - mpc85xx_gpio_set(0xffffffff, GPIO_DIR, GPIO_DAT);
> -
> - puts("Board: Freescale COM Express P2020\n");
> - return 0;
> -}
> -
> -#define M41ST85W_I2C_BUS 1
> -#define M41ST85W_I2C_ADDR 0x68
> -#define M41ST85W_ERROR(fmt, args...) printf("ERROR: M41ST85W: " fmt, ##args)
> -
> -static void m41st85w_clear_bit(u8 reg, u8 mask, const char *name)
> -{
> - u8 data;
> -
> - if (i2c_read(M41ST85W_I2C_ADDR, reg, 1, &data, 1)) {
> - M41ST85W_ERROR("unable to read %s bit\n", name);
> - return;
> - }
> -
> - if (data & mask) {
> - data &= ~mask;
> - if (i2c_write(M41ST85W_I2C_ADDR, reg, 1, &data, 1)) {
> - M41ST85W_ERROR("unable to clear %s bit\n", name);
> - return;
> - }
> - }
> -}
> -
> -#define M41ST85W_REG_SEC2 0x01
> -#define M41ST85W_REG_SEC2_ST 0x80
> -
> -#define M41ST85W_REG_ALHOUR 0x0c
> -#define M41ST85W_REG_ALHOUR_HT 0x40
> -
> -/*
> - * The P2020COME board has a STMicro M41ST85W RTC/watchdog
> - * at i2c bus 1 address 0x68.
> - */
> -static void start_rtc(void)
> -{
> - unsigned int bus = i2c_get_bus_num();
> -
> - if (i2c_set_bus_num(M41ST85W_I2C_BUS)) {
> - M41ST85W_ERROR("unable to set i2c bus\n");
> - goto out;
> - }
> -
> - /* ensure ST (stop) and HT (halt update) bits are cleared */
> - m41st85w_clear_bit(M41ST85W_REG_SEC2, M41ST85W_REG_SEC2_ST, "ST");
> - m41st85w_clear_bit(M41ST85W_REG_ALHOUR, M41ST85W_REG_ALHOUR_HT, "HT");
> -
> -out:
> - /* reset the i2c bus */
> - i2c_set_bus_num(bus);
> -}
> -
> -int board_early_init_r(void)
> -{
> - start_rtc();
> - return 0;
> -}
> -
> -#define M41ST85W_REG_WATCHDOG 0x09
> -#define M41ST85W_REG_WATCHDOG_WDS 0x80
> -#define M41ST85W_REG_WATCHDOG_BMB0 0x04
> -
> -void board_reset(void)
> -{
> - u8 data = M41ST85W_REG_WATCHDOG_WDS | M41ST85W_REG_WATCHDOG_BMB0;
> -
> - /* set the hardware watchdog timeout to 1/16 second, then hang */
> - i2c_set_bus_num(M41ST85W_I2C_BUS);
> - i2c_write(M41ST85W_I2C_ADDR, M41ST85W_REG_WATCHDOG, 1, &data, 1);
> -
> - while (1)
> - /* hang */;
> -}
> -
> -#ifdef CONFIG_TSEC_ENET
> -int board_eth_init(bd_t *bis)
> -{
> - struct fsl_pq_mdio_info mdio_info;
> - struct tsec_info_struct tsec_info[4];
> - int num = 0;
> -
> -#ifdef CONFIG_TSEC1
> - SET_STD_TSEC_INFO(tsec_info[num], 1);
> - num++;
> -#endif
> -#ifdef CONFIG_TSEC2
> - SET_STD_TSEC_INFO(tsec_info[num], 2);
> - num++;
> -#endif
> -#ifdef CONFIG_TSEC3
> - SET_STD_TSEC_INFO(tsec_info[num], 3);
> - if (is_serdes_configured(SGMII_TSEC3)) {
> - puts("eTSEC3 is in sgmii mode.");
> - tsec_info[num].flags |= TSEC_SGMII;
> - }
> - num++;
> -#endif
> - if (!num) {
> - printf("No TSECs initialized\n");
> - return 0;
> - }
> -
> - mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
> - mdio_info.name = DEFAULT_MII_NAME;
> - fsl_pq_mdio_init(bis, &mdio_info);
> -
> - tsec_eth_init(bis, tsec_info, num);
> -
> - return pci_eth_init(bis);
> -}
> -#endif
> -
> -#if defined(CONFIG_OF_BOARD_SETUP)
> -int ft_board_setup(void *blob, bd_t *bd)
> -{
> - phys_addr_t base;
> - phys_size_t size;
> -
> - ft_cpu_setup(blob, bd);
> -
> - base = getenv_bootm_low();
> - size = getenv_bootm_size();
> -
> -#if defined(CONFIG_PCI)
> - ft_pci_board_setup(blob);
> -#endif
> -
> - fdt_fixup_memory(blob, (u64)base, (u64)size);
> -
> -#ifdef CONFIG_HAS_FSL_DR_USB
> - fdt_fixup_dr_usb(blob, bd);
> -#endif
> -
> - return 0;
> -}
> -#endif
> diff --git a/board/freescale/p2020come/tlb.c b/board/freescale/p2020come/tlb.c
> deleted file mode 100644
> index 08a1e34..0000000
> --- a/board/freescale/p2020come/tlb.c
> +++ /dev/null
> @@ -1,83 +0,0 @@
> -/*
> - * Copyright 2011 Freescale Semiconductor, Inc.
> - *
> - * SPDX-License-Identifier: GPL-2.0+
> - */
> -
> -#include <common.h>
> -#include <asm/mmu.h>
> -
> -struct fsl_e_tlb_entry tlb_table[] = {
> - /* TLB 0 - for temp stack in cache */
> - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
> - CONFIG_SYS_INIT_RAM_ADDR_PHYS,
> - MAS3_SW|MAS3_SR, 0,
> - 0, 0, BOOKE_PAGESZ_4K, 0),
> - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 ,
> - CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
> - MAS3_SW|MAS3_SR, 0,
> - 0, 0, BOOKE_PAGESZ_4K, 0),
> - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 ,
> - CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
> - MAS3_SW|MAS3_SR, 0,
> - 0, 0, BOOKE_PAGESZ_4K, 0),
> - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 ,
> - CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
> - MAS3_SW|MAS3_SR, 0,
> - 0, 0, BOOKE_PAGESZ_4K, 0),
> -
> - /* TLB 1 */
> - /* *I*** - Covers boot page */
> - SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
> - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
> - 0, 0, BOOKE_PAGESZ_4K, 1),
> -
> - /* *I*G* - CCSRBAR */
> - SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
> - MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
> - 0, 1, BOOKE_PAGESZ_1M, 1),
> -
> -#if defined(CONFIG_PCI)
> - /* *I*G* - PCI3 - PCI2 0x8000,0000 - 0xbfff,ffff, size = 1G */
> - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT, CONFIG_SYS_PCIE3_MEM_PHYS,
> - MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
> - 0, 2, BOOKE_PAGESZ_1G, 1),
> -
> - /* *I*G* - PCI1 0xC000,0000 - 0xcfff,ffff, size = 256M */
> - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_VIRT,
> - MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
> - 0, 3, BOOKE_PAGESZ_256M, 1),
> -
> - /* *I*G* - PCI1 0xD000,0000 - 0xDFFF,FFFF, size = 256M */
> - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x10000000,
> - CONFIG_SYS_PCIE1_MEM_PHYS + 0x10000000,
> - MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
> - 0, 4, BOOKE_PAGESZ_256M, 1),
> -
> - /*
> - * *I*G* - PCI I/O
> - *
> - * PCI3 => 0xFFC10000
> - * PCI2 => 0xFFC2,0000
> - * PCI1 => 0xFFC3,0000
> - */
> - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_IO_VIRT, CONFIG_SYS_PCIE3_IO_PHYS,
> - MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
> - 0, 5, BOOKE_PAGESZ_256K, 1),
> -#endif /* #if defined(CONFIG_PCI) */
> -
> -#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR)
> - /* *I*G - DDR3 2G Part 1: 0 - 0x3fff,ffff , size = 1G */
> - SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS,
> - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
> - 0, 6, BOOKE_PAGESZ_256K, 1),
> -
> - /* DDR3 2G Part 2: 0x4000,0000 - 0x7fff,ffff , size = 1G */
> - SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR + 0x40000,
> - CONFIG_SYS_INIT_L2_ADDR_PHYS + 0x40000,
> - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
> - 0, 7, BOOKE_PAGESZ_256K, 1),
> -#endif
> -};
> -
> -int num_tlb_entries = ARRAY_SIZE(tlb_table);
> diff --git a/configs/P2020COME_SDCARD_defconfig b/configs/P2020COME_SDCARD_defconfig
> deleted file mode 100644
> index c186fcb..0000000
> --- a/configs/P2020COME_SDCARD_defconfig
> +++ /dev/null
> @@ -1,4 +0,0 @@
> -CONFIG_SYS_EXTRA_OPTIONS="SDCARD"
> -CONFIG_PPC=y
> -CONFIG_MPC85xx=y
> -CONFIG_TARGET_P2020COME=y
> diff --git a/configs/P2020COME_SPIFLASH_defconfig b/configs/P2020COME_SPIFLASH_defconfig
> deleted file mode 100644
> index 17ce136..0000000
> --- a/configs/P2020COME_SPIFLASH_defconfig
> +++ /dev/null
> @@ -1,4 +0,0 @@
> -CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH"
> -CONFIG_PPC=y
> -CONFIG_MPC85xx=y
> -CONFIG_TARGET_P2020COME=y
> diff --git a/doc/README.scrapyard b/doc/README.scrapyard
> index f436a8e..5733c5a 100644
> --- a/doc/README.scrapyard
> +++ b/doc/README.scrapyard
> @@ -12,6 +12,7 @@ The list should be sorted in reverse chronological order.
>
> Board Arch CPU Commit Removed Last known maintainer/contact
> =================================================================================================
> +P2020COME powerpc mpc85xx - - Ira W. Snyder <iws@ovro.caltech.edu>
> P2020RDB powerpc mpc85xx - - Poonam Aggrwal <poonam.aggrwal@freescale.com>
> P2010RDB powerpc mpc85xx - -
> P1020RDB powerpc mpc85xx - -
> diff --git a/include/configs/P2020COME.h b/include/configs/P2020COME.h
> deleted file mode 100644
> index d414b84..0000000
> --- a/include/configs/P2020COME.h
> +++ /dev/null
> @@ -1,547 +0,0 @@
> -/*
> - * Copyright 2009-2010,2012 Freescale Semiconductor, Inc.
> - *
> - * SPDX-License-Identifier: GPL-2.0+
> - */
> -
> -#ifndef __CONFIG_H
> -#define __CONFIG_H
> -
> -/* The P2020COME board is only booted via the Freescale On-Chip ROM */
> -#define CONFIG_SYS_RAMBOOT
> -#define CONFIG_SYS_EXTRA_ENV_RELOC
> -
> -#define CONFIG_SYS_TEXT_BASE 0xf8f80000
> -#define CONFIG_RESET_VECTOR_ADDRESS 0xf8fffffc
> -
> -#ifdef CONFIG_SDCARD
> -#define CONFIG_RAMBOOT_SDCARD 1
> -#endif
> -
> -#ifdef CONFIG_SPIFLASH
> -#define CONFIG_RAMBOOT_SPIFLASH 1
> -#endif
> -
> -#ifndef CONFIG_SYS_MONITOR_BASE
> -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
> -#endif
> -
> -/* High Level Configuration Options */
> -#define CONFIG_BOOKE 1 /* BOOKE */
> -#define CONFIG_E500 1 /* BOOKE e500 family */
> -#define CONFIG_P2020 1
> -#define CONFIG_P2020COME 1
> -#define CONFIG_FSL_ELBC 1 /* Enable eLBC Support */
> -#define CONFIG_MP
> -
> -#define CONFIG_PCI 1 /* Enable PCI/PCIE */
> -#if defined(CONFIG_PCI)
> -#define CONFIG_PCIE1 1 /* PCIE controller 1 (slot 1) */
> -#define CONFIG_PCIE2 1 /* PCIE controller 2 (slot 2) */
> -#define CONFIG_PCIE3 1 /* PCIE controller 3 (slot 3) */
> -
> -#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
> -#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
> -#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
> -#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
> -#endif /* #if defined(CONFIG_PCI) */
> -#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
> -#define CONFIG_TSEC_ENET /* tsec ethernet support */
> -#define CONFIG_ENV_OVERWRITE
> -
> -#if defined(CONFIG_PCI)
> -#define CONFIG_E1000 1 /* E1000 pci Ethernet card */
> -#endif
> -
> -#ifndef __ASSEMBLY__
> -extern unsigned long get_board_ddr_clk(unsigned long dummy);
> -extern unsigned long get_board_sys_clk(unsigned long dummy);
> -#endif
> -
> -/*
> - * For P2020COME DDRCLK and SYSCLK are from the same oscillator
> - * For DA phase the SYSCLK is 66MHz
> - * For EA phase the SYSCLK is 100MHz
> - */
> -#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk(0)
> -#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0)
> -
> -#define CONFIG_HWCONFIG
> -
> -/*
> - * These can be toggled for performance analysis, otherwise use default.
> - */
> -#define CONFIG_L2_CACHE /* toggle L2 cache */
> -#define CONFIG_BTB /* toggle branch prediction */
> -
> -#define CONFIG_ADDR_STREAMING /* toggle addr streaming */
> -
> -#define CONFIG_ENABLE_36BIT_PHYS 1
> -
> -#ifdef CONFIG_PHYS_64BIT
> -#define CONFIG_ADDR_MAP 1
> -#define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
> -#endif
> -
> -#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */
> -#define CONFIG_SYS_MEMTEST_END 0x1fffffff
> -#define CONFIG_PANIC_HANG /* do not reset board on panic */
> -
> - /*
> - * Config the L2 Cache as L2 SRAM
> - */
> -#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
> -#ifdef CONFIG_PHYS_64BIT
> -#define CONFIG_SYS_INIT_L2_ADDR_PHYS 0xff8f80000ull
> -#else
> -#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
> -#endif
> -#define CONFIG_SYS_L2_SIZE (512 << 10)
> -#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR \
> - + CONFIG_SYS_L2_SIZE)
> -
> -#define CONFIG_SYS_CCSRBAR 0xffe00000
> -#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
> -
> -/* DDR Setup */
> -#define CONFIG_SYS_FSL_DDR3
> -#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
> -#define CONFIG_DDR_SPD
> -
> -#define CONFIG_DDR_ECC
> -#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
> -#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
> -
> -#define CONFIG_SYS_SDRAM_SIZE 2048ULL /* DDR size on P2020COME */
> -#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
> -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
> -
> -#define CONFIG_NUM_DDR_CONTROLLERS 1
> -#define CONFIG_DIMM_SLOTS_PER_CTLR 1
> -#define CONFIG_CHIP_SELECTS_PER_CTRL 2
> -
> -#define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d
> -#define CONFIG_SYS_DDR_ERR_DIS 0x00000000
> -#define CONFIG_SYS_DDR_SBE 0x00ff0000
> -
> -#define CONFIG_SYS_SPD_BUS_NUM 1
> -#define SPD_EEPROM_ADDRESS 0x53
> -
> -/*
> - * Memory map
> - *
> - * 0x0000_0000 0x7fff_ffff DDR3 2G Cacheable
> - * 0x8000_0000 0x9fff_ffff PCI Express 3 Mem 1G non-cacheable
> - * 0xa000_0000 0xbfff_ffff PCI Express 2 Mem 1G non-cacheable
> - * 0xc000_0000 0xdfff_ffff PCI Express 1 Mem 1G non-cacheable
> - * 0xffc1_0000 0xffc1_ffff PCI Express 3 IO 64K non-cacheable
> - * 0xffc2_0000 0xffc2_ffff PCI Express 2 IO 64K non-cacheable
> - * 0xffc3_0000 0xffc3_ffff PCI Express 1 IO 64K non-cacheable
> - *
> - * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0
> - * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
> - */
> -
> -/*
> - * Local Bus Definitions
> - */
> -
> -/* There is no NOR Flash on P2020COME */
> -#define CONFIG_SYS_NO_FLASH
> -
> -#define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
> -#define CONFIG_HWCONFIG
> -
> -#define CONFIG_SYS_INIT_RAM_LOCK 1
> -#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */
> -#ifdef CONFIG_PHYS_64BIT
> -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
> -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
> -/* the assembler doesn't like typecast */
> -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
> - ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
> - CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
> -#else
> -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR
> -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
> -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
> -#endif
> -#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
> -
> -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \
> - - GENERATED_GBL_DATA_SIZE)
> -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
> -
> -#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
> -#define CONFIG_SYS_MALLOC_LEN (1024 * 1024)
> -
> -/* Serial Port - controlled on board with jumper J8
> - * open - index 2
> - * shorted - index 1
> - */
> -#define CONFIG_CONS_INDEX 1
> -#define CONFIG_SYS_NS16550
> -#define CONFIG_SYS_NS16550_SERIAL
> -#define CONFIG_SYS_NS16550_REG_SIZE 1
> -#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
> -
> -#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */
> -
> -#define CONFIG_SYS_BAUDRATE_TABLE \
> - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
> -
> -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
> -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
> -
> -/* Use the HUSH parser */
> -#define CONFIG_SYS_HUSH_PARSER
> -
> -/*
> - * Pass open firmware flat tree
> - */
> -#define CONFIG_OF_LIBFDT 1
> -#define CONFIG_OF_BOARD_SETUP 1
> -#define CONFIG_OF_STDOUT_VIA_ALIAS 1
> -
> -/* new uImage format support */
> -#define CONFIG_FIT 1
> -#define CONFIG_FIT_VERBOSE 1
> -
> -/* I2C */
> -#define CONFIG_SYS_I2C
> -#define CONFIG_SYS_I2C_FSL
> -#define CONFIG_SYS_FSL_I2C_SPEED 400000
> -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
> -#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
> -#define CONFIG_SYS_FSL_I2C2_SPEED 400000
> -#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
> -#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
> -#define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} }
> -
> -/*
> - * I2C2 EEPROM
> - */
> -#define CONFIG_ID_EEPROM
> -#ifdef CONFIG_ID_EEPROM
> -#define CONFIG_SYS_I2C_EEPROM_NXID
> -#endif
> -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
> -#define CONFIG_SYS_I2C_EEPROM_ADDR2 0x18
> -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
> -#define CONFIG_SYS_EEPROM_BUS_NUM 0
> -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
> -
> -/*
> - * eSPI - Enhanced SPI
> - */
> -#define CONFIG_FSL_ESPI
> -#define CONFIG_SPI_FLASH
> -#define CONFIG_SPI_FLASH_STMICRO
> -#define CONFIG_CMD_SF
> -#define CONFIG_SF_DEFAULT_SPEED 10000000
> -#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
> -
> -/*
> - * General PCI
> - * Memory space is mapped 1-1, but I/O space must start from 0.
> - */
> -#if defined(CONFIG_PCI)
> -
> -/* controller 3, Slot 3, tgtid 3, Base address 8000 */
> -#define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000
> -#define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000
> -#define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000
> -#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
> -#define CONFIG_SYS_PCIE3_IO_VIRT 0xffc10000
> -#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
> -#define CONFIG_SYS_PCIE3_IO_PHYS 0xffc10000
> -#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
> -
> -/* controller 2, Slot 2, tgtid 2, Base address 9000 */
> -#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
> -#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
> -#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
> -#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
> -#define CONFIG_SYS_PCIE2_IO_VIRT 0xffc20000
> -#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
> -#define CONFIG_SYS_PCIE2_IO_PHYS 0xffc20000
> -#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
> -
> -/* controller 1, Slot 1, tgtid 1, Base address a000 */
> -#define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000
> -#define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000
> -#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000
> -#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
> -#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc30000
> -#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
> -#define CONFIG_SYS_PCIE1_IO_PHYS 0xffc30000
> -#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
> -
> -#define CONFIG_PCI_PNP /* do pci plug-and-play */
> -
> -#undef CONFIG_EEPRO100
> -#undef CONFIG_TULIP
> -#undef CONFIG_RTL8139
> -
> -#ifdef CONFIG_RTL8139
> -/* This macro is used by RTL8139 but not defined in PPC architecture */
> -#define KSEG1ADDR(x) (x)
> -#define _IO_BASE 0x00000000
> -#endif
> -
> -#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
> -#define CONFIG_DOS_PARTITION
> -
> -#endif /* CONFIG_PCI */
> -
> -#if defined(CONFIG_TSEC_ENET)
> -#define CONFIG_MII 1 /* MII PHY management */
> -#define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
> -#define CONFIG_TSEC1 1
> -#define CONFIG_TSEC1_NAME "eTSEC1"
> -#define CONFIG_TSEC2 1
> -#define CONFIG_TSEC2_NAME "eTSEC2"
> -#define CONFIG_TSEC3 1
> -#define CONFIG_TSEC3_NAME "eTSEC3"
> -
> -#define TSEC1_PHY_ADDR 0
> -#define TSEC2_PHY_ADDR 2
> -#define TSEC3_PHY_ADDR 1
> -
> -#undef CONFIG_VSC7385_ENET
> -
> -#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
> -#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
> -#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
> -
> -#define TSEC1_PHYIDX 0
> -#define TSEC2_PHYIDX 0
> -#define TSEC3_PHYIDX 0
> -
> -#define CONFIG_ETHPRIME "eTSEC1"
> -
> -#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
> -
> -#endif /* CONFIG_TSEC_ENET */
> -
> -/*
> - * Environment
> - */
> -#if defined(CONFIG_RAMBOOT_SDCARD)
> - #define CONFIG_ENV_IS_IN_MMC 1
> - #define CONFIG_FSL_FIXED_MMC_LOCATION
> - #define CONFIG_ENV_SIZE 0x2000
> - #define CONFIG_SYS_MMC_ENV_DEV 0
> -#elif defined(CONFIG_RAMBOOT_SPIFLASH)
> - #define CONFIG_ENV_IS_IN_SPI_FLASH
> - #define CONFIG_ENV_SPI_BUS 0
> - #define CONFIG_ENV_SPI_CS 0
> - #define CONFIG_ENV_SPI_MAX_HZ 10000000
> - #define CONFIG_ENV_SPI_MODE 0
> - #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
> - #define CONFIG_ENV_SECT_SIZE 0x10000
> - #define CONFIG_ENV_SIZE 0x2000
> -#endif
> -
> -#define CONFIG_LOADS_ECHO 1
> -#define CONFIG_SYS_LOADS_BAUD_CHANGE 1
> -
> -/*
> - * Command line configuration.
> - */
> -#include <config_cmd_default.h>
> -
> -#define CONFIG_CMD_ELF
> -#define CONFIG_CMD_I2C
> -#define CONFIG_CMD_IRQ
> -#define CONFIG_CMD_MII
> -#define CONFIG_CMD_PING
> -#define CONFIG_CMD_SETEXPR
> -#define CONFIG_CMD_REGINFO
> -
> -#if defined(CONFIG_PCI)
> -#define CONFIG_CMD_NET
> -#define CONFIG_CMD_PCI
> -#endif
> -
> -#undef CONFIG_WATCHDOG /* watchdog disabled */
> -
> -#define CONFIG_MMC 1
> -
> -#ifdef CONFIG_MMC
> -#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
> -#define CONFIG_CMD_MMC
> -#define CONFIG_DOS_PARTITION
> -#define CONFIG_FSL_ESDHC
> -#define CONFIG_GENERIC_MMC
> -#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
> -#define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
> -#endif /* CONFIG_MMC */
> -
> -#define CONFIG_HAS_FSL_DR_USB
> -#ifdef CONFIG_HAS_FSL_DR_USB
> -#define CONFIG_USB_EHCI
> -
> -#ifdef CONFIG_USB_EHCI
> -#define CONFIG_CMD_USB
> -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
> -#define CONFIG_USB_EHCI_FSL
> -#define CONFIG_USB_STORAGE
> -#endif
> -#endif
> -
> -#if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI)
> -#define CONFIG_CMD_EXT2
> -#define CONFIG_CMD_FAT
> -#define CONFIG_DOS_PARTITION
> -#endif
> -
> -/* Misc Extra Settings */
> -#define CONFIG_CMD_DHCP 1
> -
> -#define CONFIG_CMD_DATE 1
> -#define CONFIG_RTC_M41T62 1
> -#define CONFIG_SYS_RTC_BUS_NUM 1
> -#define CONFIG_SYS_I2C_RTC_ADDR 0x68
> -
> -/*
> - * Miscellaneous configurable options
> - */
> -#define CONFIG_SYS_LONGHELP /* undef to save memory */
> -#define CONFIG_CMDLINE_EDITING /* Command-line editing */
> -#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */
> -#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
> -#if defined(CONFIG_CMD_KGDB)
> -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
> -#else
> -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
> -#endif
> -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
> - /* Print Buffer Size */
> -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
> -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
> -
> -/*
> - * For booting Linux, the board info and command line data
> - * have to be in the first 64 MB of memory, since this is
> - * the maximum mapped by the Linux kernel during initialization.
> - */
> -#define CONFIG_SYS_BOOTMAPSZ (64 << 20)
> -#define CONFIG_SYS_BOOTM_LEN (64 << 20)
> -
> -#if defined(CONFIG_CMD_KGDB)
> -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
> -#endif
> -
> -/*
> - * Environment Configuration
> - */
> -
> -/* The mac addresses for all ethernet interface */
> -#if defined(CONFIG_TSEC_ENET)
> -#define CONFIG_HAS_ETH0
> -#define CONFIG_HAS_ETH1
> -#define CONFIG_HAS_ETH2
> -#define CONFIG_HAS_ETH3
> -#endif
> -
> -#define CONFIG_HOSTNAME unknown
> -#define CONFIG_ROOTPATH "/opt/nfsroot"
> -#define CONFIG_BOOTFILE "uImage"
> -#define CONFIG_UBOOTPATH u-boot.bin
> -
> -/* default location for tftp and bootm */
> -#define CONFIG_LOADADDR 1000000
> -
> -#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
> -#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
> -
> -#define CONFIG_BAUDRATE 115200
> -
> -#define CONFIG_EXTRA_ENV_SETTINGS \
> - "hwconfig=fsl_ddr:ecc=on\0" \
> - "bootcmd=run sdboot\0" \
> - "sdboot=setenv bootargs root=/dev/mmcblk0p2 rw " \
> - "rootdelay=$rootdelaysecond console=$consoledev,$baudrate "\
> - "$othbootargs; mmcinfo; " \
> - "ext2load mmc 0:2 $loadaddr /boot/$bootfile; " \
> - "ext2load mmc 0:2 $fdtaddr /boot/$fdtfile; " \
> - "bootm $loadaddr - $fdtaddr\0" \
> - "sdfatboot=setenv bootargs root=/dev/ram rw " \
> - "rootdelay=$rootdelaysecond console=$consoledev,$baudrate "\
> - "$othbootargs; mmcinfo; " \
> - "fatload mmc 0:1 $loadaddr $bootfile; " \
> - "fatload mmc 0:1 $fdtaddr $fdtfile; " \
> - "fatload mmc 0:1 $ramdiskaddr $ramdiskfile; " \
> - "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \
> - "usbboot=setenv bootargs root=/dev/sda1 rw " \
> - "rootdelay=$rootdelaysecond console=$consoledev,$baudrate "\
> - "$othbootargs; " \
> - "usb start; " \
> - "ext2load usb 0:1 $loadaddr /boot/$bootfile; " \
> - "ext2load usb 0:1 $fdtaddr /boot/$fdtfile; " \
> - "bootm $loadaddr - $fdtaddr\0" \
> - "usbfatboot=setenv bootargs root=/dev/ram rw " \
> - "console=$consoledev,$baudrate $othbootargs; " \
> - "usb start; " \
> - "fatload usb 0:2 $loadaddr $bootfile; " \
> - "fatload usb 0:2 $fdtaddr $fdtfile; " \
> - "fatload usb 0:2 $ramdiskaddr $ramdiskfile; " \
> - "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \
> - "usbext2boot=setenv bootargs root=/dev/ram rw " \
> - "console=$consoledev,$baudrate $othbootargs; " \
> - "usb start; " \
> - "ext2load usb 0:4 $loadaddr $bootfile; " \
> - "ext2load usb 0:4 $fdtaddr $fdtfile; " \
> - "ext2load usb 0:4 $ramdiskaddr $ramdiskfile; " \
> - "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \
> - "upgradespi=sf probe 0; " \
> - "setenv startaddr 0; " \
> - "setenv erasesize a0000; " \
> - "tftp 1000000 $tftppath/$uboot_spi; " \
> - "sf erase $startaddr $erasesize; " \
> - "sf write 1000000 $startaddr $filesize; " \
> - "sf erase 100000 120000\0" \
> - "clearspienv=sf probe 0;sf erase 100000 20000\0" \
> - "othbootargs=ramdisk_size=700000 cache-sram-size=0x10000\0" \
> - "netdev=eth0\0" \
> - "rootdelaysecond=15\0" \
> - "uboot_nor=u-boot-nor.bin\0" \
> - "uboot_spi=u-boot-p2020.spi\0" \
> - "uboot_sd=u-boot-p2020.bin\0" \
> - "consoledev=ttyS0\0" \
> - "ramdiskaddr=2000000\0" \
> - "ramdiskfile=rootfs-dev.ext2.img\0" \
> - "fdtaddr=c00000\0" \
> - "fdtfile=uImage-2.6.32-p2020.dtb\0" \
> - "tftppath=p2020\0"
> -
> -#define CONFIG_HDBOOT \
> - "setenv bootargs root=/dev/$bdev rw rootdelay=30 " \
> - "console=$consoledev,$baudrate $othbootargs;" \
> - "usb start;" \
> - "ext2load usb 0:1 $loadaddr /boot/$bootfile;" \
> - "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \
> - "bootm $loadaddr - $fdtaddr"
> -
> -#define CONFIG_NFSBOOTCOMMAND \
> - "setenv bootargs root=/dev/nfs rw " \
> - "nfsroot=$serverip:$rootpath " \
> - "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off "\
> - "console=$consoledev,$baudrate $othbootargs;" \
> - "tftp $loadaddr $tftppath/$bootfile;" \
> - "tftp $fdtaddr $tftppath/$fdtfile;" \
> - "bootm $loadaddr - $fdtaddr"
> -
> -
> -#define CONFIG_RAMBOOTCOMMAND \
> - "setenv bootargs root=/dev/ram rw " \
> - "console=$consoledev,$baudrate $othbootargs;" \
> - "tftp $ramdiskaddr $tftppath/$ramdiskfile;" \
> - "tftp $loadaddr $tftppath/$bootfile;" \
> - "tftp $fdtaddr $tftppath/$fdtfile;" \
> - "bootm $loadaddr $ramdiskaddr $fdtaddr"
> -
> -#define CONFIG_BOOTCOMMAND CONFIG_HDBOOT
> -
> -#endif /* __CONFIG_H */
> --
> 1.9.1
>
^ permalink raw reply [flat|nested] 19+ messages in thread
* [U-Boot] [PATCH 1/8] powerpc: mpc83xx: remove MPC8360ERDK, EMPC8360EMDS support
2015-01-22 15:24 ` [U-Boot] [PATCH 1/8] powerpc: mpc83xx: remove MPC8360ERDK, EMPC8360EMDS support Masahiro Yamada
@ 2015-01-23 21:57 ` Tom Rini
0 siblings, 0 replies; 19+ messages in thread
From: Tom Rini @ 2015-01-23 21:57 UTC (permalink / raw)
To: u-boot
On Fri, Jan 23, 2015 at 12:24:15AM +0900, Masahiro Yamada wrote:
> These boards are still non-generic boards.
>
> Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
> Cc: Dave Liu <daveliu@freescale.com>
> Cc: Anton Vorontsov <avorontsov@ru.mvista.com>
Applied to u-boot/master, thanks!
--
Tom
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* [U-Boot] [PATCH 2/8] powerpc: mpc85xx: remove P1_P2_RDB boards
2015-01-22 15:24 ` [U-Boot] [PATCH 2/8] powerpc: mpc85xx: remove P1_P2_RDB boards Masahiro Yamada
@ 2015-01-23 21:57 ` Tom Rini
0 siblings, 0 replies; 19+ messages in thread
From: Tom Rini @ 2015-01-23 21:57 UTC (permalink / raw)
To: u-boot
On Fri, Jan 23, 2015 at 12:24:16AM +0900, Masahiro Yamada wrote:
> These boards are still non-generic boards:
> P1011RDB, P1022RDB, P2010RDB, P2020RDB
>
> Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
> Cc: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Applied to u-boot/master, thanks!
--
Tom
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* [U-Boot] [PATCH 3/8] powerpc: mpc85xx: remove P2020COME board support
2015-01-22 15:24 ` [U-Boot] [PATCH 3/8] powerpc: mpc85xx: remove P2020COME board support Masahiro Yamada
2015-01-22 17:52 ` Ira Snyder
@ 2015-01-23 21:57 ` Tom Rini
1 sibling, 0 replies; 19+ messages in thread
From: Tom Rini @ 2015-01-23 21:57 UTC (permalink / raw)
To: u-boot
On Fri, Jan 23, 2015 at 12:24:17AM +0900, Masahiro Yamada wrote:
> This board is still a non-generic board.
>
> Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
> Cc: Ira W. Snyder <iws@ovro.caltech.edu>
Applied to u-boot/master, thanks!
--
Tom
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* [U-Boot] [PATCH 4/8] powerpc: mpc85xx: remove P2020DS board support
2015-01-22 15:24 ` [U-Boot] [PATCH 4/8] powerpc: mpc85xx: remove P2020DS " Masahiro Yamada
@ 2015-01-23 21:57 ` Tom Rini
0 siblings, 0 replies; 19+ messages in thread
From: Tom Rini @ 2015-01-23 21:57 UTC (permalink / raw)
To: u-boot
On Fri, Jan 23, 2015 at 12:24:18AM +0900, Masahiro Yamada wrote:
> This board is still a non-generic board.
>
> Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Applied to u-boot/master, thanks!
--
Tom
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* [U-Boot] [PATCH 5/8] powerpc: ppc4xx: remove PPChameleonEVB, CATcenter boards
2015-01-22 15:24 ` [U-Boot] [PATCH 5/8] powerpc: ppc4xx: remove PPChameleonEVB, CATcenter boards Masahiro Yamada
2015-01-22 15:41 ` Stefan Roese
@ 2015-01-23 21:57 ` Tom Rini
1 sibling, 0 replies; 19+ messages in thread
From: Tom Rini @ 2015-01-23 21:57 UTC (permalink / raw)
To: u-boot
On Fri, Jan 23, 2015 at 12:24:19AM +0900, Masahiro Yamada wrote:
> These boards are still non-generic boards.
>
> It is a good thing that we can drop board-specific hack code
> from drivers/mtd/nand/nand_base.c
>
> Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
> Cc: Andrea "llandre" Marson <andrea.marson@dave-tech.it>
Applied to u-boot/master, thanks!
--
Tom
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* [U-Boot] [PATCH 6/8] powerpc: mpc5xxx: remove Total5200 board support
2015-01-22 15:24 ` [U-Boot] [PATCH 6/8] powerpc: mpc5xxx: remove Total5200 board support Masahiro Yamada
@ 2015-01-23 21:57 ` Tom Rini
0 siblings, 0 replies; 19+ messages in thread
From: Tom Rini @ 2015-01-23 21:57 UTC (permalink / raw)
To: u-boot
On Fri, Jan 23, 2015 at 12:24:20AM +0900, Masahiro Yamada wrote:
> This board is still a non-generic board.
>
> Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Applied to u-boot/master, thanks!
--
Tom
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* [U-Boot] [PATCH 7/8] powerpc: mpc5xxx: PM520 board support
2015-01-22 15:24 ` [U-Boot] [PATCH 7/8] powerpc: mpc5xxx: PM520 " Masahiro Yamada
@ 2015-01-23 21:57 ` Tom Rini
0 siblings, 0 replies; 19+ messages in thread
From: Tom Rini @ 2015-01-23 21:57 UTC (permalink / raw)
To: u-boot
On Fri, Jan 23, 2015 at 12:24:21AM +0900, Masahiro Yamada wrote:
> This board is still a non-generic board.
>
> Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
> Cc: Josef Wagner <Wagner@Microsys.de>
Applied to u-boot/master, thanks!
--
Tom
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* [U-Boot] [PATCH 8/8] powerpc: remove icecube_5200, Lite5200, cpci5200, mecp5200, pf5200
2015-01-22 15:24 ` [U-Boot] [PATCH 8/8] powerpc: remove icecube_5200, Lite5200, cpci5200, mecp5200, pf5200 Masahiro Yamada
@ 2015-01-23 21:57 ` Tom Rini
0 siblings, 0 replies; 19+ messages in thread
From: Tom Rini @ 2015-01-23 21:57 UTC (permalink / raw)
To: u-boot
On Fri, Jan 23, 2015 at 12:24:22AM +0900, Masahiro Yamada wrote:
> These boards are still non-generic boards.
>
> Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
> Cc: Wolfgang Denk <wd@denx.de>
> Cc: Reinhard Arlt <reinhard.arlt@esd-electronics.com>
Applied to u-boot/master, thanks!
--
Tom
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end of thread, other threads:[~2015-01-23 21:57 UTC | newest]
Thread overview: 19+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2015-01-22 15:24 [U-Boot] [PATCH 0/8] powerpc: drop more non-generic boards Masahiro Yamada
2015-01-22 15:24 ` [U-Boot] [PATCH 1/8] powerpc: mpc83xx: remove MPC8360ERDK, EMPC8360EMDS support Masahiro Yamada
2015-01-23 21:57 ` Tom Rini
2015-01-22 15:24 ` [U-Boot] [PATCH 2/8] powerpc: mpc85xx: remove P1_P2_RDB boards Masahiro Yamada
2015-01-23 21:57 ` Tom Rini
2015-01-22 15:24 ` [U-Boot] [PATCH 3/8] powerpc: mpc85xx: remove P2020COME board support Masahiro Yamada
2015-01-22 17:52 ` Ira Snyder
2015-01-23 21:57 ` Tom Rini
2015-01-22 15:24 ` [U-Boot] [PATCH 4/8] powerpc: mpc85xx: remove P2020DS " Masahiro Yamada
2015-01-23 21:57 ` Tom Rini
2015-01-22 15:24 ` [U-Boot] [PATCH 5/8] powerpc: ppc4xx: remove PPChameleonEVB, CATcenter boards Masahiro Yamada
2015-01-22 15:41 ` Stefan Roese
2015-01-23 21:57 ` Tom Rini
2015-01-22 15:24 ` [U-Boot] [PATCH 6/8] powerpc: mpc5xxx: remove Total5200 board support Masahiro Yamada
2015-01-23 21:57 ` Tom Rini
2015-01-22 15:24 ` [U-Boot] [PATCH 7/8] powerpc: mpc5xxx: PM520 " Masahiro Yamada
2015-01-23 21:57 ` Tom Rini
2015-01-22 15:24 ` [U-Boot] [PATCH 8/8] powerpc: remove icecube_5200, Lite5200, cpci5200, mecp5200, pf5200 Masahiro Yamada
2015-01-23 21:57 ` Tom Rini
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