From: Atish Kumar Patra <atishp@rivosinc.com> To: Anup Patel <anup@brainfault.org> Cc: "Heiko Stübner" <heiko@sntech.de>, linux-riscv <linux-riscv@lists.infradead.org>, "linux-kernel@vger.kernel.org List" <linux-kernel@vger.kernel.org>, "Albert Ou" <aou@eecs.berkeley.edu>, "Atish Patra" <atishp@atishpatra.org>, "Damien Le Moal" <damien.lemoal@wdc.com>, DTML <devicetree@vger.kernel.org>, "Jisheng Zhang" <jszhang@kernel.org>, "Palmer Dabbelt" <palmer@dabbelt.com>, "Paul Walmsley" <paul.walmsley@sifive.com>, "Rob Herring" <robh+dt@kernel.org> Subject: Re: [PATCH 1/2] RISC-V: Fix counter restart during overflow for RV32 Date: Thu, 12 May 2022 10:21:56 -0700 [thread overview] Message-ID: <CAHBxVyF5T7r26nAp1Hep+DRkZErr2PH43k=HwLi6iuqMXWju6Q@mail.gmail.com> (raw) In-Reply-To: <CAAhSdy3t6cnfR02kfHvnKdCcDPvyX4jwccV7qkR_=-dV_m0aGQ@mail.gmail.com> On Thu, May 12, 2022 at 8:36 AM Anup Patel <anup@brainfault.org> wrote: > > On Thu, May 12, 2022 at 6:12 PM Heiko Stübner <heiko@sntech.de> wrote: > > > > Am Donnerstag, 12. Mai 2022, 06:44:12 CEST schrieb Anup Patel: > > > On Thu, May 12, 2022 at 1:41 AM Atish Patra <atishp@rivosinc.com> wrote: > > > > > > > > Pass the upper half of the initial value of the counter correctly > > > > for RV32. > > > > > > > > Fixes: 4905ec2fb7e6 ("RISC-V: Add sscofpmf extension support") > > > > > > > > Signed-off-by: Atish Patra <atishp@rivosinc.com> > > > > --- > > > > drivers/perf/riscv_pmu_sbi.c | 2 +- > > > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > > > > > diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_sbi.c > > > > index a1317a483512..24cea59612be 100644 > > > > --- a/drivers/perf/riscv_pmu_sbi.c > > > > +++ b/drivers/perf/riscv_pmu_sbi.c > > > > @@ -526,7 +526,7 @@ static inline void pmu_sbi_start_overflow_mask(struct riscv_pmu *pmu, > > > > max_period = riscv_pmu_ctr_get_width_mask(event); > > > > init_val = local64_read(&hwc->prev_count) & max_period; > > > > sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_START, idx, 1, > > > > - flag, init_val, 0, 0); > > > > + flag, init_val, init_val >> 32, 0); > > > > > > This should be under "#if __riscv_xlen == 32". > > > > What's the difference between using CONFIG_32BIT > > and checking the __riscv_xlen flag value? > > It's one and the same. > > > > > CONFIG_32BIT seems to be a bit the more kernel'ish > > way to do this, but it looks like most SBI parts check the > > __riscv_xlen instead. > Not only SBI parts, there are more users of __riscv_xlen compared CONFIG_32BIT in arch/riscv. > I agree with you. We should prefer "#ifdef CONFIG_32BIT" > in this case to match the kernel coding style. > Sure. I will change it to CONFIG_32BIT. > Currently, OpenSBI does not have CONFIG_xyz defines so > over there we use "#if __riscv_xlen == 32". > > Regards, > Anup > > > > > > > In any case, looking at the opensbi-side of the call, > > this fix is abviously correct, so > > > > Reviewed-by: Heiko Stuebner <heiko@sntech.de> > > > > > >
WARNING: multiple messages have this Message-ID (diff)
From: Atish Kumar Patra <atishp@rivosinc.com> To: Anup Patel <anup@brainfault.org> Cc: "Heiko Stübner" <heiko@sntech.de>, linux-riscv <linux-riscv@lists.infradead.org>, "linux-kernel@vger.kernel.org List" <linux-kernel@vger.kernel.org>, "Albert Ou" <aou@eecs.berkeley.edu>, "Atish Patra" <atishp@atishpatra.org>, "Damien Le Moal" <damien.lemoal@wdc.com>, DTML <devicetree@vger.kernel.org>, "Jisheng Zhang" <jszhang@kernel.org>, "Palmer Dabbelt" <palmer@dabbelt.com>, "Paul Walmsley" <paul.walmsley@sifive.com>, "Rob Herring" <robh+dt@kernel.org> Subject: Re: [PATCH 1/2] RISC-V: Fix counter restart during overflow for RV32 Date: Thu, 12 May 2022 10:21:56 -0700 [thread overview] Message-ID: <CAHBxVyF5T7r26nAp1Hep+DRkZErr2PH43k=HwLi6iuqMXWju6Q@mail.gmail.com> (raw) In-Reply-To: <CAAhSdy3t6cnfR02kfHvnKdCcDPvyX4jwccV7qkR_=-dV_m0aGQ@mail.gmail.com> On Thu, May 12, 2022 at 8:36 AM Anup Patel <anup@brainfault.org> wrote: > > On Thu, May 12, 2022 at 6:12 PM Heiko Stübner <heiko@sntech.de> wrote: > > > > Am Donnerstag, 12. Mai 2022, 06:44:12 CEST schrieb Anup Patel: > > > On Thu, May 12, 2022 at 1:41 AM Atish Patra <atishp@rivosinc.com> wrote: > > > > > > > > Pass the upper half of the initial value of the counter correctly > > > > for RV32. > > > > > > > > Fixes: 4905ec2fb7e6 ("RISC-V: Add sscofpmf extension support") > > > > > > > > Signed-off-by: Atish Patra <atishp@rivosinc.com> > > > > --- > > > > drivers/perf/riscv_pmu_sbi.c | 2 +- > > > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > > > > > diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_sbi.c > > > > index a1317a483512..24cea59612be 100644 > > > > --- a/drivers/perf/riscv_pmu_sbi.c > > > > +++ b/drivers/perf/riscv_pmu_sbi.c > > > > @@ -526,7 +526,7 @@ static inline void pmu_sbi_start_overflow_mask(struct riscv_pmu *pmu, > > > > max_period = riscv_pmu_ctr_get_width_mask(event); > > > > init_val = local64_read(&hwc->prev_count) & max_period; > > > > sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_START, idx, 1, > > > > - flag, init_val, 0, 0); > > > > + flag, init_val, init_val >> 32, 0); > > > > > > This should be under "#if __riscv_xlen == 32". > > > > What's the difference between using CONFIG_32BIT > > and checking the __riscv_xlen flag value? > > It's one and the same. > > > > > CONFIG_32BIT seems to be a bit the more kernel'ish > > way to do this, but it looks like most SBI parts check the > > __riscv_xlen instead. > Not only SBI parts, there are more users of __riscv_xlen compared CONFIG_32BIT in arch/riscv. > I agree with you. We should prefer "#ifdef CONFIG_32BIT" > in this case to match the kernel coding style. > Sure. I will change it to CONFIG_32BIT. > Currently, OpenSBI does not have CONFIG_xyz defines so > over there we use "#if __riscv_xlen == 32". > > Regards, > Anup > > > > > > > In any case, looking at the opensbi-side of the call, > > this fix is abviously correct, so > > > > Reviewed-by: Heiko Stuebner <heiko@sntech.de> > > > > > > _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2022-05-12 17:22 UTC|newest] Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top 2022-05-11 20:11 [PATCH 1/2] RISC-V: Fix counter restart during overflow for RV32 Atish Patra 2022-05-11 20:11 ` Atish Patra 2022-05-11 20:11 ` [PATCH 2/2] RISC-V: Update user page mapping only once during start Atish Patra 2022-05-11 20:11 ` Atish Patra 2022-05-12 4:45 ` Anup Patel 2022-05-12 4:45 ` Anup Patel 2022-05-12 4:44 ` [PATCH 1/2] RISC-V: Fix counter restart during overflow for RV32 Anup Patel 2022-05-12 4:44 ` Anup Patel 2022-05-12 12:42 ` Heiko Stübner 2022-05-12 12:42 ` Heiko Stübner 2022-05-12 15:36 ` Anup Patel 2022-05-12 15:36 ` Anup Patel 2022-05-12 17:21 ` Atish Kumar Patra [this message] 2022-05-12 17:21 ` Atish Kumar Patra
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