Re: [PATCH 1/3] arm: dts: imx8mm: Sync with Linux 6.3

[Adam Ford <aford173@gmail.com>]

On Thu, Apr 27, 2023 at 1:08 PM Fabio Estevam <festevam@gmail.com> wrote:
>
> From: Fabio Estevam <festevam@denx.de>
>
> Sync imx8mm.dtsi with Linux 6.3.
>
> The motivation for doing this sync was a bug when doing "ums 0 mmc 1"
> on imx8mm-evk. It worked well for the first time, but after doing
> a CTRL+C and launching the ums again, the command did not work.
>
> Adam Ford suggested to sync imx8mm.dtsi with the Linux dts, as there was
> a recent USB power domain reorganization there.
>
> After syncing the imx8mm.dtsi with Linux, the ums command works without
> problem after a CTRL+C.
>
> Suggested-by: Adam Ford <aford173@gmail.com>
> Signed-off-by: Fabio Estevam <festevam@denx.de>
Reviewed-by: Adam Ford <aford173@gmail.com>
> ---
>  arch/arm/dts/imx8mm.dtsi | 52 +++++++++++++++++++++++++++++-----------
>  1 file changed, 38 insertions(+), 14 deletions(-)
>
> diff --git a/arch/arm/dts/imx8mm.dtsi b/arch/arm/dts/imx8mm.dtsi
> index afb90f59c83c..31f4548f85cf 100644
> --- a/arch/arm/dts/imx8mm.dtsi
> +++ b/arch/arm/dts/imx8mm.dtsi
> @@ -139,6 +139,7 @@
>                 A53_L2: l2-cache0 {
>                         compatible = "cache";
>                         cache-level = <2>;
> +                       cache-unified;
>                         cache-size = <0x80000>;
>                         cache-line-size = <64>;
>                         cache-sets = <512>;
> @@ -276,6 +277,7 @@
>                 assigned-clocks = <&clk IMX8MM_CLK_USB_PHY_REF>;
>                 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_100M>;
>                 clock-names = "main_clk";
> +               power-domains = <&pgc_otg1>;
>         };
>
>         usbphynop2: usbphynop2 {
> @@ -285,6 +287,7 @@
>                 assigned-clocks = <&clk IMX8MM_CLK_USB_PHY_REF>;
>                 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_100M>;
>                 clock-names = "main_clk";
> +               power-domains = <&pgc_otg2>;
>         };
>
>         soc: soc@0 {
> @@ -493,6 +496,8 @@
>                                 compatible = "fsl,imx8mm-tmu";
>                                 reg = <0x30260000 0x10000>;
>                                 clocks = <&clk IMX8MM_CLK_TMU_ROOT>;
> +                               nvmem-cells = <&tmu_calib>;
> +                               nvmem-cell-names = "calib";
>                                 #thermal-sensor-cells = <0>;
>                         };
>
> @@ -547,8 +552,8 @@
>                                 reg = <0x30330000 0x10000>;
>                         };
>
> -                       gpr: iomuxc-gpr@30340000 {
> -                               compatible = "fsl,imx8mm-iomuxc-gpr", "fsl,imx6q-iomuxc-gpr", "syscon";
> +                       gpr: syscon@30340000 {
> +                               compatible = "fsl,imx8mm-iomuxc-gpr", "syscon";
>                                 reg = <0x30340000 0x10000>;
>                         };
>
> @@ -560,22 +565,40 @@
>                                 #address-cells = <1>;
>                                 #size-cells = <1>;
>
> -                               imx8mm_uid: unique-id@410 {
> +                               /*
> +                                * The register address below maps to the MX8M
> +                                * Fusemap Description Table entries this way.
> +                                * Assuming
> +                                *   reg = <ADDR SIZE>;
> +                                * then
> +                                *   Fuse Address = (ADDR * 4) + 0x400
> +                                * Note that if SIZE is greater than 4, then
> +                                * each subsequent fuse is located at offset
> +                                * +0x10 in Fusemap Description Table (e.g.
> +                                * reg = <0x4 0x8> describes fuses 0x410 and
> +                                * 0x420).
> +                                */
> +                               imx8mm_uid: unique-id@4 { /* 0x410-0x420 */
>                                         reg = <0x4 0x8>;
>                                 };
>
> -                               cpu_speed_grade: speed-grade@10 {
> +                               cpu_speed_grade: speed-grade@10 { /* 0x440 */
>                                         reg = <0x10 4>;
>                                 };
>
> -                               fec_mac_address: mac-address@90 {
> +                               tmu_calib: calib@3c { /* 0x4f0 */
> +                                       reg = <0x3c 4>;
> +                               };
> +
> +                               fec_mac_address: mac-address@90 { /* 0x640 */
>                                         reg = <0x90 6>;
>                                 };
>                         };
>
> -                       anatop: anatop@30360000 {
> -                               compatible = "fsl,imx8mm-anatop", "syscon";
> +                       anatop: clock-controller@30360000 {
> +                               compatible = "fsl,imx8mm-anatop";
>                                 reg = <0x30360000 0x10000>;
> +                               #clock-cells = <1>;
>                         };
>
>                         snvs: snvs@30370000 {
> @@ -674,13 +697,11 @@
>                                         pgc_otg1: power-domain@2 {
>                                                 #power-domain-cells = <0>;
>                                                 reg = <IMX8MM_POWER_DOMAIN_OTG1>;
> -                                               power-domains = <&pgc_hsiomix>;
>                                         };
>
>                                         pgc_otg2: power-domain@3 {
>                                                 #power-domain-cells = <0>;
>                                                 reg = <IMX8MM_POWER_DOMAIN_OTG2>;
> -                                               power-domains = <&pgc_hsiomix>;
>                                         };
>
>                                         pgc_gpumix: power-domain@4 {
> @@ -1186,7 +1207,7 @@
>                                 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>;
>                                 phys = <&usbphynop1>;
>                                 fsl,usbmisc = <&usbmisc1 0>;
> -                               power-domains = <&pgc_otg1>;
> +                               power-domains = <&pgc_hsiomix>;
>                                 status = "disabled";
>                         };
>
> @@ -1206,7 +1227,7 @@
>                                 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>;
>                                 phys = <&usbphynop2>;
>                                 fsl,usbmisc = <&usbmisc2 0>;
> -                               power-domains = <&pgc_otg2>;
> +                               power-domains = <&pgc_hsiomix>;
>                                 status = "disabled";
>                         };
>
> @@ -1238,16 +1259,15 @@
>                                      <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
>                                      <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
>                                      <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
> -                       interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
>                         #dma-cells = <1>;
>                         dma-channels = <4>;
>                         clocks = <&clk IMX8MM_CLK_NAND_USDHC_BUS_RAWNAND_CLK>;
>                 };
>
> -               gpmi: nand-controller@33002000{
> +               gpmi: nand-controller@33002000 {
>                         compatible = "fsl,imx8mm-gpmi-nand", "fsl,imx7d-gpmi-nand";
>                         #address-cells = <1>;
> -                       #size-cells = <1>;
> +                       #size-cells = <0>;
>                         reg = <0x33002000 0x2000>, <0x33004000 0x4000>;
>                         reg-names = "gpmi-nand", "bch";
>                         interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
> @@ -1282,6 +1302,10 @@
>                                         <0 0 0 4 &gic GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
>                         fsl,max-link-speed = <2>;
>                         linux,pci-domain = <0>;
> +                       clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>,
> +                                <&clk IMX8MM_CLK_PCIE1_PHY>,
> +                                <&clk IMX8MM_CLK_PCIE1_AUX>;
> +                       clock-names = "pcie", "pcie_bus", "pcie_aux";
>                         power-domains = <&pgc_pcie>;
>                         resets = <&src IMX8MQ_RESET_PCIE_CTRL_APPS_EN>,
>                                  <&src IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF>;
> --
> 2.34.1
>