From: Linus Torvalds <torvalds@linux-foundation.org>
To: Joerg Roedel <joro@8bytes.org>
Cc: Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
iommu <iommu@lists.linux-foundation.org>
Subject: Re: [git pull] IOMMU Fixes for Linux v5.7-rc4
Date: Sun, 10 May 2020 11:34:49 -0700 [thread overview]
Message-ID: <CAHk-=wht3yDtJ6zka=DNaB8Nymh-zmUMZhGaC8yFz29nuW-EsA@mail.gmail.com> (raw)
In-Reply-To: <20200510122634.GA32616@8bytes.org>
On Sun, May 10, 2020 at 5:26 AM Joerg Roedel <joro@8bytes.org> wrote:
>
> The first race condition was around
> the non-atomic update of the domain page-table root pointer
> and the variable containing the page-table depth (called
> mode). This is fixed now be merging page-table root and mode
> into one 64-bit field which is read/written atomically.
This seems a bit odd.
The pointer part is always page-aligned, and the "mode" is just three bits.
Why isn't it just encoded as one pointer with the low three bits being the mode?
The thing is, the 64-bit atomic reads/writes are very expensive on
32-bit x86. If it was just a native pointer, it would be much cheaper
than an "atomic64_t".
Linus
WARNING: multiple messages have this Message-ID (diff)
From: Linus Torvalds <torvalds@linux-foundation.org>
To: Joerg Roedel <joro@8bytes.org>
Cc: iommu <iommu@lists.linux-foundation.org>,
Linux Kernel Mailing List <linux-kernel@vger.kernel.org>
Subject: Re: [git pull] IOMMU Fixes for Linux v5.7-rc4
Date: Sun, 10 May 2020 11:34:49 -0700 [thread overview]
Message-ID: <CAHk-=wht3yDtJ6zka=DNaB8Nymh-zmUMZhGaC8yFz29nuW-EsA@mail.gmail.com> (raw)
In-Reply-To: <20200510122634.GA32616@8bytes.org>
On Sun, May 10, 2020 at 5:26 AM Joerg Roedel <joro@8bytes.org> wrote:
>
> The first race condition was around
> the non-atomic update of the domain page-table root pointer
> and the variable containing the page-table depth (called
> mode). This is fixed now be merging page-table root and mode
> into one 64-bit field which is read/written atomically.
This seems a bit odd.
The pointer part is always page-aligned, and the "mode" is just three bits.
Why isn't it just encoded as one pointer with the low three bits being the mode?
The thing is, the 64-bit atomic reads/writes are very expensive on
32-bit x86. If it was just a native pointer, it would be much cheaper
than an "atomic64_t".
Linus
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https://lists.linuxfoundation.org/mailman/listinfo/iommu
next prev parent reply other threads:[~2020-05-10 18:35 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-05-10 12:26 [git pull] IOMMU Fixes for Linux v5.7-rc4 Joerg Roedel
2020-05-10 12:26 ` Joerg Roedel
2020-05-10 18:34 ` Linus Torvalds [this message]
2020-05-10 18:34 ` Linus Torvalds
2020-05-10 22:25 ` Joerg Roedel
2020-05-10 22:25 ` Joerg Roedel
2020-05-10 19:45 ` pr-tracker-bot
2020-05-10 19:45 ` pr-tracker-bot
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