From: Linus Torvalds <torvalds@linux-foundation.org>
To: Al Viro <viro@zeniv.linux.org.uk>
Cc: Christophe Leroy <christophe.leroy@c-s.fr>,
Benjamin Herrenschmidt <benh@kernel.crashing.org>,
Paul Mackerras <paulus@samba.org>,
Michael Ellerman <mpe@ellerman.id.au>,
Dave Airlie <airlied@linux.ie>, Daniel Vetter <daniel@ffwll.ch>,
Andrew Morton <akpm@linux-foundation.org>,
Kees Cook <keescook@chromium.org>, Peter Anvin <hpa@zytor.com>,
Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
linuxppc-dev <linuxppc-dev@lists.ozlabs.org>,
Linux-MM <linux-mm@kvack.org>,
linux-arch <linux-arch@vger.kernel.org>,
intel-gfx@lists.freedesktop.org,
Russell King <linux@armlinux.org.uk>
Subject: Re: [PATCH v2 5/5] uaccess: Rename user_access_begin/end() to user_full_access_begin/end()
Date: Tue, 21 Apr 2020 11:34:04 -0700 [thread overview]
Message-ID: <CAHk-=wiuHxXwuPynLFh-fYjuUE3_HNPh79e_P6MFMbq4Ki+QCw@mail.gmail.com> (raw)
In-Reply-To: <20200421024919.GA23230@ZenIV.linux.org.uk>
On Mon, Apr 20, 2020 at 7:49 PM Al Viro <viro@zeniv.linux.org.uk> wrote:
>
> The only source I'd been able to find speaks of >= 60 cycles
> (and possibly much more) for non-pipelined coprocessor instructions;
> the list of such does contain loads and stores to a bunch of registers.
> However, the register in question (p15/c3) has only store mentioned there,
> so loads might be cheap; no obvious reasons for those to be slow.
> That's a question to arm folks, I'm afraid... rmk?
_If_ it turns out to be expensive, is there any reason we couldn't
just cache the value in general?
That's what x86 tends to do with expensive system registers. One
example would be "msr_misc_features_shadow".
But maybe that's something to worry about when/if it turns out to
actually be a problem?
Linus
WARNING: multiple messages have this Message-ID (diff)
From: Linus Torvalds <torvalds@linux-foundation.org>
To: Al Viro <viro@zeniv.linux.org.uk>
Cc: linux-arch <linux-arch@vger.kernel.org>,
Kees Cook <keescook@chromium.org>, Dave Airlie <airlied@linux.ie>,
intel-gfx@lists.freedesktop.org, Peter Anvin <hpa@zytor.com>,
Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
Russell King <linux@armlinux.org.uk>,
Linux-MM <linux-mm@kvack.org>, Paul Mackerras <paulus@samba.org>,
Daniel Vetter <daniel@ffwll.ch>,
Andrew Morton <akpm@linux-foundation.org>,
linuxppc-dev <linuxppc-dev@lists.ozlabs.org>
Subject: Re: [PATCH v2 5/5] uaccess: Rename user_access_begin/end() to user_full_access_begin/end()
Date: Tue, 21 Apr 2020 11:34:04 -0700 [thread overview]
Message-ID: <CAHk-=wiuHxXwuPynLFh-fYjuUE3_HNPh79e_P6MFMbq4Ki+QCw@mail.gmail.com> (raw)
In-Reply-To: <20200421024919.GA23230@ZenIV.linux.org.uk>
On Mon, Apr 20, 2020 at 7:49 PM Al Viro <viro@zeniv.linux.org.uk> wrote:
>
> The only source I'd been able to find speaks of >= 60 cycles
> (and possibly much more) for non-pipelined coprocessor instructions;
> the list of such does contain loads and stores to a bunch of registers.
> However, the register in question (p15/c3) has only store mentioned there,
> so loads might be cheap; no obvious reasons for those to be slow.
> That's a question to arm folks, I'm afraid... rmk?
_If_ it turns out to be expensive, is there any reason we couldn't
just cache the value in general?
That's what x86 tends to do with expensive system registers. One
example would be "msr_misc_features_shadow".
But maybe that's something to worry about when/if it turns out to
actually be a problem?
Linus
WARNING: multiple messages have this Message-ID (diff)
From: Linus Torvalds <torvalds@linux-foundation.org>
To: Al Viro <viro@zeniv.linux.org.uk>
Cc: Christophe Leroy <christophe.leroy@c-s.fr>,
linux-arch <linux-arch@vger.kernel.org>,
Kees Cook <keescook@chromium.org>, Dave Airlie <airlied@linux.ie>,
Benjamin Herrenschmidt <benh@kernel.crashing.org>,
intel-gfx@lists.freedesktop.org, Peter Anvin <hpa@zytor.com>,
Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
Russell King <linux@armlinux.org.uk>,
Linux-MM <linux-mm@kvack.org>, Paul Mackerras <paulus@samba.org>,
Michael Ellerman <mpe@ellerman.id.au>,
Andrew Morton <akpm@linux-foundation.org>,
linuxppc-dev <linuxppc-dev@lists.ozlabs.org>
Subject: Re: [Intel-gfx] [PATCH v2 5/5] uaccess: Rename user_access_begin/end() to user_full_access_begin/end()
Date: Tue, 21 Apr 2020 11:34:04 -0700 [thread overview]
Message-ID: <CAHk-=wiuHxXwuPynLFh-fYjuUE3_HNPh79e_P6MFMbq4Ki+QCw@mail.gmail.com> (raw)
In-Reply-To: <20200421024919.GA23230@ZenIV.linux.org.uk>
On Mon, Apr 20, 2020 at 7:49 PM Al Viro <viro@zeniv.linux.org.uk> wrote:
>
> The only source I'd been able to find speaks of >= 60 cycles
> (and possibly much more) for non-pipelined coprocessor instructions;
> the list of such does contain loads and stores to a bunch of registers.
> However, the register in question (p15/c3) has only store mentioned there,
> so loads might be cheap; no obvious reasons for those to be slow.
> That's a question to arm folks, I'm afraid... rmk?
_If_ it turns out to be expensive, is there any reason we couldn't
just cache the value in general?
That's what x86 tends to do with expensive system registers. One
example would be "msr_misc_features_shadow".
But maybe that's something to worry about when/if it turns out to
actually be a problem?
Linus
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
next prev parent reply other threads:[~2020-04-21 18:34 UTC|newest]
Thread overview: 53+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-04-03 7:20 [PATCH v2 1/5] uaccess: Add user_read_access_begin/end and user_write_access_begin/end Christophe Leroy
2020-04-03 7:20 ` [Intel-gfx] " Christophe Leroy
2020-04-03 7:20 ` Christophe Leroy
2020-04-03 7:20 ` [PATCH v2 2/5] uaccess: Selectively open read or write user access Christophe Leroy
2020-04-03 7:20 ` [Intel-gfx] " Christophe Leroy
2020-04-03 7:20 ` Christophe Leroy
2020-05-29 4:20 ` Michael Ellerman
2020-05-29 4:20 ` [Intel-gfx] " Michael Ellerman
2020-04-03 7:20 ` [PATCH v2 3/5] drm/i915/gem: Replace user_access_begin by user_write_access_begin Christophe Leroy
2020-04-03 7:20 ` [Intel-gfx] " Christophe Leroy
2020-04-03 7:20 ` Christophe Leroy
2020-05-29 4:20 ` Michael Ellerman
2020-05-29 4:20 ` [Intel-gfx] " Michael Ellerman
2020-04-03 7:20 ` [PATCH v2 4/5] powerpc/uaccess: Implement user_read_access_begin and user_write_access_begin Christophe Leroy
2020-04-03 7:20 ` [Intel-gfx] " Christophe Leroy
2020-04-03 7:20 ` Christophe Leroy
2020-05-29 4:24 ` Michael Ellerman
2020-05-29 4:24 ` [Intel-gfx] " Michael Ellerman
2020-04-03 7:20 ` [PATCH v2 5/5] uaccess: Rename user_access_begin/end() to user_full_access_begin/end() Christophe Leroy
2020-04-03 7:20 ` [Intel-gfx] " Christophe Leroy
2020-04-03 7:20 ` Christophe Leroy
2020-04-03 18:01 ` Linus Torvalds
2020-04-03 18:01 ` [Intel-gfx] " Linus Torvalds
2020-04-03 18:01 ` Linus Torvalds
2020-04-03 18:01 ` Linus Torvalds
2020-04-03 20:52 ` Al Viro
2020-04-03 20:52 ` [Intel-gfx] " Al Viro
2020-04-03 20:52 ` Al Viro
2020-04-21 2:49 ` Al Viro
2020-04-21 2:49 ` [Intel-gfx] " Al Viro
2020-04-21 2:49 ` Al Viro
2020-04-21 9:12 ` Russell King - ARM Linux admin
2020-04-21 9:12 ` [Intel-gfx] " Russell King - ARM Linux admin
2020-04-21 9:12 ` Russell King - ARM Linux admin
2020-04-21 18:34 ` Linus Torvalds [this message]
2020-04-21 18:34 ` [Intel-gfx] " Linus Torvalds
2020-04-21 18:34 ` Linus Torvalds
2020-04-21 18:34 ` Linus Torvalds
2020-04-05 18:47 ` Christophe Leroy
2020-04-05 18:47 ` [Intel-gfx] " Christophe Leroy
2020-04-05 18:47 ` Christophe Leroy
2020-04-04 6:20 ` kbuild test robot
2020-04-04 6:20 ` kbuild test robot
2020-04-04 6:20 ` [Intel-gfx] " kbuild test robot
2020-04-04 6:20 ` kbuild test robot
2020-04-04 7:17 ` kbuild test robot
2020-04-04 7:17 ` kbuild test robot
2020-04-04 7:17 ` [Intel-gfx] " kbuild test robot
2020-04-04 7:17 ` kbuild test robot
2020-04-04 7:17 ` kbuild test robot
2020-04-03 16:59 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for series starting with [v2,1/5] uaccess: Add user_read_access_begin/end and user_write_access_begin/end Patchwork
2020-05-29 4:20 ` [PATCH v2 1/5] " Michael Ellerman
2020-05-29 4:20 ` [Intel-gfx] " Michael Ellerman
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