[U-Boot] [PATCH] x86: tsc: Add support for APL soc

[U-Boot] [PATCH] x86: tsc: Add support for APL soc

[Bernhard Messerklinger]

Signed-off-by: Bernhard Messerklinger <bernhard.messerklinger@br-automation.com>
---

 drivers/timer/tsc_timer.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/timer/tsc_timer.c b/drivers/timer/tsc_timer.c
index da7c812908..b2a982812a 100644
--- a/drivers/timer/tsc_timer.c
+++ b/drivers/timer/tsc_timer.c
@@ -64,6 +64,8 @@ static struct freq_desc freq_desc_tables[] = {
 			80000, 93300, 90000, 88900, 87500 } },
 	/* Ivybridge */
 	{ 6, 0x3a, 2, { 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
+	/* Intel Atom processor E3900 series */
+	{ 6, 0x5c, 2, { 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
 };
 
 static int match_cpu(u8 family, u8 model)
-- 
2.19.1

[U-Boot] [PATCH] x86: tsc: Add support for APL soc

[Bin Meng]

Hi Bernhard,

On Thu, Oct 25, 2018 at 6:51 PM Bernhard Messerklinger
<bernhard.messerklinger@br-automation.com> wrote:
>

Missing commit message

APL means ApolloLake? Could you please spell it out?

> Signed-off-by: Bernhard Messerklinger <bernhard.messerklinger@br-automation.com>
> ---
>
>  drivers/timer/tsc_timer.c | 2 ++
>  1 file changed, 2 insertions(+)
>
> diff --git a/drivers/timer/tsc_timer.c b/drivers/timer/tsc_timer.c
> index da7c812908..b2a982812a 100644
> --- a/drivers/timer/tsc_timer.c
> +++ b/drivers/timer/tsc_timer.c
> @@ -64,6 +64,8 @@ static struct freq_desc freq_desc_tables[] = {
>                         80000, 93300, 90000, 88900, 87500 } },
>         /* Ivybridge */
>         { 6, 0x3a, 2, { 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
> +       /* Intel Atom processor E3900 series */
> +       { 6, 0x5c, 2, { 0, 0, 0, 0, 0, 0, 0, 0, 0 } },

Please avoid hardcoding TSC freq this way. Isn't calibrating from MSR
not working for ApolloLake?

>  };
>
>  static int match_cpu(u8 family, u8 model)
> --

Regards,
Bin

[U-Boot] Antwort: Re: [PATCH] x86: tsc: Add support for APL soc

[Bernhard Messerklinger]

Hi Bin,

> Missing commit message
I will fix this.
> 
> APL means ApolloLake? Could you please spell it out?
I will fix this.
> 
> > Signed-off-by: Bernhard Messerklinger <bernhard.messerklinger@br-
> automation.com>
> > ---
> >
> >  drivers/timer/tsc_timer.c | 2 ++
> >  1 file changed, 2 insertions(+)
> >
> > diff --git a/drivers/timer/tsc_timer.c b/drivers/timer/tsc_timer.c
> > index da7c812908..b2a982812a 100644
> > --- a/drivers/timer/tsc_timer.c
> > +++ b/drivers/timer/tsc_timer.c
> > @@ -64,6 +64,8 @@ static struct freq_desc freq_desc_tables[] = {
> >                         80000, 93300, 90000, 88900, 87500 } },
> >         /* Ivybridge */
> >         { 6, 0x3a, 2, { 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
> > +       /* Intel Atom processor E3900 series */
> > +       { 6, 0x5c, 2, { 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
> 
> Please avoid hardcoding TSC freq this way. Isn't calibrating from MSR
> not working for ApolloLake?
I found two ways to get the TSC freq.
1. Read the necessary parameters with cpuid(instruction 15) like it is 
done in 
the kernel.
The problem with this way is that for some reason my core crystal clock is 


always set to zero, so I would need to add the crystal frequency 
somewhere.
2. Read it from MSR.
That?s actually the way I do it in this patch. I only need to add my cpu 
family/model to avoid return with 0 at the begin of cpu_mhz_from_msr.

Please tell me if I overlook something.

Regards,
Bernhard

[U-Boot] [PATCH] x86: tsc: Add support for APL soc

[Bin Meng]

Hi Bernhard,

On Fri, Nov 23, 2018 at 5:13 PM Bernhard Messerklinger
<bernhard.messerklinger@br-automation.com> wrote:
>
> Hi Bin,
>
> > Missing commit message
> I will fix this.
> >
> > APL means ApolloLake? Could you please spell it out?
> I will fix this.
> >
> > > Signed-off-by: Bernhard Messerklinger <bernhard.messerklinger@br-
> > automation.com>
> > > ---
> > >
> > >  drivers/timer/tsc_timer.c | 2 ++
> > >  1 file changed, 2 insertions(+)
> > >
> > > diff --git a/drivers/timer/tsc_timer.c b/drivers/timer/tsc_timer.c
> > > index da7c812908..b2a982812a 100644
> > > --- a/drivers/timer/tsc_timer.c
> > > +++ b/drivers/timer/tsc_timer.c
> > > @@ -64,6 +64,8 @@ static struct freq_desc freq_desc_tables[] = {
> > >                         80000, 93300, 90000, 88900, 87500 } },
> > >         /* Ivybridge */
> > >         { 6, 0x3a, 2, { 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
> > > +       /* Intel Atom processor E3900 series */
> > > +       { 6, 0x5c, 2, { 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
> >
> > Please avoid hardcoding TSC freq this way. Isn't calibrating from MSR
> > not working for ApolloLake?
> I found two ways to get the TSC freq.
> 1. Read the necessary parameters with cpuid(instruction 15) like it is
> done in
> the kernel.
> The problem with this way is that for some reason my core crystal clock is
>
>
> always set to zero, so I would need to add the crystal frequency
> somewhere.

The TSC timer supports 3 ways of calibrating frequency:
cpu_mhz_from_cpuid(), cpu_mhz_from_msr() and quick_pit_calibrate().

Are you saying that if doing cpu_mhz_from_cpuid() you can't get
correct frequency? Can you investigate why your core crystal clock is
always zero?

> 2. Read it from MSR.
> That?s actually the way I do it in this patch. I only need to add my cpu
> family/model to avoid return with 0 at the begin of cpu_mhz_from_msr.
>
> Please tell me if I overlook something.
>

For the MSR, I meant to say the table below:

static struct freq_desc freq_desc_tables[] = {
/* PNW */
{ 6, 0x27, 0, { 0, 0, 0, 0, 0, 99840, 0, 83200, 0 } },
/* CLV+ */
{ 6, 0x35, 0, { 0, 133200, 0, 0, 0, 99840, 0, 83200, 0 } },
/* TNG - Intel Atom processor Z3400 series */
{ 6, 0x4a, 1, { 0, 100000, 133300, 0, 0, 0, 0, 0, 0 } },
/* VLV2 - Intel Atom processor E3000, Z3600, Z3700 series */
{ 6, 0x37, 1, { 83300, 100000, 133300, 116700, 80000, 0, 0, 0, 0 } },
/* ANN - Intel Atom processor Z3500 series */
{ 6, 0x5a, 1, { 83300, 100000, 133300, 100000, 0, 0, 0, 0, 0 } },
/* AMT - Intel Atom processor X7-Z8000 and X5-Z8000 series */
{ 6, 0x4c, 1, { 83300, 100000, 133300, 116700,
80000, 93300, 90000, 88900, 87500 } },
/* Ivybridge */
{ 6, 0x3a, 2, { 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
};

Can we do it something like VLV2?

Regards,
Bin

[U-Boot] [PATCH] x86: tsc: Add support for APL soc

[Christian Gmeiner]

Hi all.

Starting with Monday I have access to an APL system (where I need to get
coreboot running on). Maybe I can provide some additional information.

Am Sa., 24. Nov. 2018, 16:39 hat Bin Meng <bmeng.cn@gmail.com> geschrieben:

> Hi Bernhard,
>
> On Fri, Nov 23, 2018 at 5:13 PM Bernhard Messerklinger
> <bernhard.messerklinger@br-automation.com> wrote:
> >
> > Hi Bin,
> >
> > > Missing commit message
> > I will fix this.
> > >
> > > APL means ApolloLake? Could you please spell it out?
> > I will fix this.
> > >
> > > > Signed-off-by: Bernhard Messerklinger <bernhard.messerklinger@br-
> > > automation.com>
> > > > ---
> > > >
> > > >  drivers/timer/tsc_timer.c | 2 ++
> > > >  1 file changed, 2 insertions(+)
> > > >
> > > > diff --git a/drivers/timer/tsc_timer.c b/drivers/timer/tsc_timer.c
> > > > index da7c812908..b2a982812a 100644
> > > > --- a/drivers/timer/tsc_timer.c
> > > > +++ b/drivers/timer/tsc_timer.c
> > > > @@ -64,6 +64,8 @@ static struct freq_desc freq_desc_tables[] = {
> > > >                         80000, 93300, 90000, 88900, 87500 } },
> > > >         /* Ivybridge */
> > > >         { 6, 0x3a, 2, { 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
> > > > +       /* Intel Atom processor E3900 series */
> > > > +       { 6, 0x5c, 2, { 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
> > >
> > > Please avoid hardcoding TSC freq this way. Isn't calibrating from MSR
> > > not working for ApolloLake?
> > I found two ways to get the TSC freq.
> > 1. Read the necessary parameters with cpuid(instruction 15) like it is
> > done in
> > the kernel.
> > The problem with this way is that for some reason my core crystal clock
> is
> >
> >
> > always set to zero, so I would need to add the crystal frequency
> > somewhere.
>
> The TSC timer supports 3 ways of calibrating frequency:
> cpu_mhz_from_cpuid(), cpu_mhz_from_msr() and quick_pit_calibrate().
>
> Are you saying that if doing cpu_mhz_from_cpuid() you can't get
> correct frequency? Can you investigate why your core crystal clock is
> always zero?
>
> > 2. Read it from MSR.
> > That?s actually the way I do it in this patch. I only need to add my cpu
> > family/model to avoid return with 0 at the begin of cpu_mhz_from_msr.
> >
> > Please tell me if I overlook something.
> >
>
> For the MSR, I meant to say the table below:
>
> static struct freq_desc freq_desc_tables[] = {
> /* PNW */
> { 6, 0x27, 0, { 0, 0, 0, 0, 0, 99840, 0, 83200, 0 } },
> /* CLV+ */
> { 6, 0x35, 0, { 0, 133200, 0, 0, 0, 99840, 0, 83200, 0 } },
> /* TNG - Intel Atom processor Z3400 series */
> { 6, 0x4a, 1, { 0, 100000, 133300, 0, 0, 0, 0, 0, 0 } },
> /* VLV2 - Intel Atom processor E3000, Z3600, Z3700 series */
> { 6, 0x37, 1, { 83300, 100000, 133300, 116700, 80000, 0, 0, 0, 0 } },
> /* ANN - Intel Atom processor Z3500 series */
> { 6, 0x5a, 1, { 83300, 100000, 133300, 100000, 0, 0, 0, 0, 0 } },
> /* AMT - Intel Atom processor X7-Z8000 and X5-Z8000 series */
> { 6, 0x4c, 1, { 83300, 100000, 133300, 116700,
> 80000, 93300, 90000, 88900, 87500 } },
> /* Ivybridge */
> { 6, 0x3a, 2, { 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
> };
>
> Can we do it something like VLV2?
>
> Regards,
> Bin
>

Greets
--
Christian Gmeiner, MSc

https://christian-gmeiner.info

[U-Boot] [PATCH] x86: tsc: Add support for APL soc

[Andy Shevchenko]

On Sat, Nov 24, 2018 at 5:39 PM Bin Meng <bmeng.cn@gmail.com> wrote:
> On Fri, Nov 23, 2018 at 5:13 PM Bernhard Messerklinger
> <bernhard.messerklinger@br-automation.com> wrote:

> > > APL means ApolloLake? Could you please spell it out?
> > I will fix this.

> > > > --- a/drivers/timer/tsc_timer.c
> > > > +++ b/drivers/timer/tsc_timer.c
> > > > @@ -64,6 +64,8 @@ static struct freq_desc freq_desc_tables[] = {
> > > >                         80000, 93300, 90000, 88900, 87500 } },
> > > >         /* Ivybridge */
> > > >         { 6, 0x3a, 2, { 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
> > > > +       /* Intel Atom processor E3900 series */
> > > > +       { 6, 0x5c, 2, { 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
> > >
> > > Please avoid hardcoding TSC freq this way. Isn't calibrating from MSR
> > > not working for ApolloLake?

> > I found two ways to get the TSC freq.
> > 1. Read the necessary parameters with cpuid(instruction 15) like it is
> > done in
> > the kernel.
> > The problem with this way is that for some reason my core crystal clock is
> > always set to zero, so I would need to add the crystal frequency
> > somewhere.


> The TSC timer supports 3 ways of calibrating frequency:
> cpu_mhz_from_cpuid(), cpu_mhz_from_msr() and quick_pit_calibrate().
>
> Are you saying that if doing cpu_mhz_from_cpuid() you can't get
> correct frequency? Can you investigate why your core crystal clock is
> always zero?

Yes, this has to be investigated.

> Can we do it something like VLV2?

Please, don't. I see no evidence in the latest Linux kernel sources
that Apollo Lake has such issue as Intel MID family of Atom SoCs.

-- 
With Best Regards,
Andy Shevchenko

[U-Boot] [PATCH] x86: tsc: Add support for APL soc

[Andy Shevchenko]

On Sun, Nov 25, 2018 at 4:31 PM Andy Shevchenko
<andy.shevchenko@gmail.com> wrote:
> On Sat, Nov 24, 2018 at 5:39 PM Bin Meng <bmeng.cn@gmail.com> wrote:

> > Are you saying that if doing cpu_mhz_from_cpuid() you can't get
> > correct frequency? Can you investigate why your core crystal clock is
> > always zero?
>
> Yes, this has to be investigated.
>
> > Can we do it something like VLV2?
>
> Please, don't. I see no evidence in the latest Linux kernel sources
> that Apollo Lake has such issue as Intel MID family of Atom SoCs.

Sorry, I slipped one code in my consideration, i.e.

unsigned long native_calibrate_tsc(void)
{
...
if (crystal_khz == 0) {
switch (boot_cpu_data.x86_model) {
...
case INTEL_FAM6_ATOM_GOLDMONT:
crystal_khz = 19200; /* 19.2 MHz */
break;
}
...
if (boot_cpu_data.x86_model == INTEL_FAM6_ATOM_GOLDMONT)
setup_force_cpu_cap(X86_FEATURE_TSC_RELIABLE);
...
}

So, that's what we need to do in U-boot.

-- 
With Best Regards,
Andy Shevchenko

[U-Boot] [PATCH] x86: tsc: Add support for APL soc

[Bin Meng]

Hi Andy,

On Sun, Nov 25, 2018 at 10:43 PM Andy Shevchenko
<andy.shevchenko@gmail.com> wrote:
>
> On Sun, Nov 25, 2018 at 4:31 PM Andy Shevchenko
> <andy.shevchenko@gmail.com> wrote:
> > On Sat, Nov 24, 2018 at 5:39 PM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> > > Are you saying that if doing cpu_mhz_from_cpuid() you can't get
> > > correct frequency? Can you investigate why your core crystal clock is
> > > always zero?
> >
> > Yes, this has to be investigated.
> >
> > > Can we do it something like VLV2?
> >
> > Please, don't. I see no evidence in the latest Linux kernel sources
> > that Apollo Lake has such issue as Intel MID family of Atom SoCs.
>
> Sorry, I slipped one code in my consideration, i.e.
>
> unsigned long native_calibrate_tsc(void)
> {
> ...
> if (crystal_khz == 0) {
> switch (boot_cpu_data.x86_model) {
> ...
> case INTEL_FAM6_ATOM_GOLDMONT:
> crystal_khz = 19200; /* 19.2 MHz */
> break;
> }
> ...
> if (boot_cpu_data.x86_model == INTEL_FAM6_ATOM_GOLDMONT)
> setup_force_cpu_cap(X86_FEATURE_TSC_RELIABLE);
> ...
> }
>
> So, that's what we need to do in U-boot.
>

Thanks for the investigation. Could you please send a proper patch?

Regards,
Bin

[U-Boot] Antwort: Re: [PATCH] x86: tsc: Add support for APL soc

[Bernhard Messerklinger]

Hi Andy,

> Von: Bin Meng <bmeng.cn@gmail.com>
> An: Andy Shevchenko <andy.shevchenko@gmail.com>, 
> Kopie: Bernhard Messerklinger <bernhard.messerklinger@br-
> automation.com>, U-Boot Mailing List <u-boot@lists.denx.de>
> Datum: 25.11.2018 15:50
> Betreff: Re: [U-Boot] [PATCH] x86: tsc: Add support for APL soc
> 
> Hi Andy,
> 
> On Sun, Nov 25, 2018 at 10:43 PM Andy Shevchenko
> <andy.shevchenko@gmail.com> wrote:
> >
> > On Sun, Nov 25, 2018 at 4:31 PM Andy Shevchenko
> > <andy.shevchenko@gmail.com> wrote:
> > > On Sat, Nov 24, 2018 at 5:39 PM Bin Meng <bmeng.cn@gmail.com> wrote:
> >
> > > > Are you saying that if doing cpu_mhz_from_cpuid() you can't get
> > > > correct frequency? Can you investigate why your core crystal clock 
is
> > > > always zero?
> > >
> > > Yes, this has to be investigated.
> > >
> > > > Can we do it something like VLV2?
> > >
> > > Please, don't. I see no evidence in the latest Linux kernel sources
> > > that Apollo Lake has such issue as Intel MID family of Atom SoCs.
> >
> > Sorry, I slipped one code in my consideration, i.e.
> >
> > unsigned long native_calibrate_tsc(void)
> > {
> > ...
> > if (crystal_khz == 0) {
> > switch (boot_cpu_data.x86_model) {
> > ...
> > case INTEL_FAM6_ATOM_GOLDMONT:
> > crystal_khz = 19200; /* 19.2 MHz */
> > break;
> > }
> > ...
> > if (boot_cpu_data.x86_model == INTEL_FAM6_ATOM_GOLDMONT)
> > setup_force_cpu_cap(X86_FEATURE_TSC_RELIABLE);
> > ...
> > }
> >
> > So, that's what we need to do in U-boot.
> >
> 
> Thanks for the investigation. Could you please send a proper patch?
do you want to take charge of this?
Otherwise I will post patch V2.
> 
> Regards,
> Bin

Regards,
Bernhard

[U-Boot] [PATCH] x86: tsc: Add support for APL soc

[Andy Shevchenko]

On Mon, Nov 26, 2018 at 8:31 AM Bernhard Messerklinger
<bernhard.messerklinger@br-automation.com> wrote:

> > > > > Are you saying that if doing cpu_mhz_from_cpuid() you can't get
> > > > > correct frequency? Can you investigate why your core crystal clock
> is
> > > > > always zero?
> > > >
> > > > Yes, this has to be investigated.
> > > >
> > > > > Can we do it something like VLV2?
> > > >
> > > > Please, don't. I see no evidence in the latest Linux kernel sources
> > > > that Apollo Lake has such issue as Intel MID family of Atom SoCs.
> > >
> > > Sorry, I slipped one code in my consideration, i.e.
> > >
> > > unsigned long native_calibrate_tsc(void)
> > > {
> > > ...
> > > if (crystal_khz == 0) {
> > > switch (boot_cpu_data.x86_model) {
> > > ...
> > > case INTEL_FAM6_ATOM_GOLDMONT:
> > > crystal_khz = 19200; /* 19.2 MHz */
> > > break;
> > > }
> > > ...
> > > if (boot_cpu_data.x86_model == INTEL_FAM6_ATOM_GOLDMONT)
> > > setup_force_cpu_cap(X86_FEATURE_TSC_RELIABLE);
> > > ...
> > > }
> > >
> > > So, that's what we need to do in U-boot.
> > >
> >
> > Thanks for the investigation. Could you please send a proper patch?
> do you want to take charge of this?
> Otherwise I will post patch V2.

I'm busy with something else, so, if you don't mind, please, consider
v2 which takes into consideration my findings.

-- 
With Best Regards,
Andy Shevchenko

[U-Boot] Antwort: Re: Re: [PATCH] x86: tsc: Add support for APL soc

[Bernhard Messerklinger]

> > > > > > Are you saying that if doing cpu_mhz_from_cpuid() you can't 
get
> > > > > > correct frequency? Can you investigate why your core crystal 
clock
> > is
> > > > > > always zero?
> > > > >
> > > > > Yes, this has to be investigated.
> > > > >
> > > > > > Can we do it something like VLV2?
> > > > >
> > > > > Please, don't. I see no evidence in the latest Linux kernel 
sources
> > > > > that Apollo Lake has such issue as Intel MID family of Atom 
SoCs.
> > > >
> > > > Sorry, I slipped one code in my consideration, i.e.
> > > >
> > > > unsigned long native_calibrate_tsc(void)
> > > > {
> > > > ...
> > > > if (crystal_khz == 0) {
> > > > switch (boot_cpu_data.x86_model) {
> > > > ...
> > > > case INTEL_FAM6_ATOM_GOLDMONT:
> > > > crystal_khz = 19200; /* 19.2 MHz */
> > > > break;
> > > > }
> > > > ...
> > > > if (boot_cpu_data.x86_model == INTEL_FAM6_ATOM_GOLDMONT)
> > > > setup_force_cpu_cap(X86_FEATURE_TSC_RELIABLE);
> > > > ...
> > > > }
> > > >
> > > > So, that's what we need to do in U-boot.
> > > >
> > >
> > > Thanks for the investigation. Could you please send a proper patch?
> > do you want to take charge of this?
> > Otherwise I will post patch V2.
> 
> I'm busy with something else, so, if you don't mind, please, consider
> v2 which takes into consideration my findings.
Ok, as soon as I am done I will post v2.

--
Best Regards,
Bernhard 

[U-Boot] [PATCH v2] x86: tsc: Add support for native calibration of TSC freq

[Bernhard Messerklinger]

Add native tsc calibration function. Calibrate the tsc timer the same
way as linux does arch/x86/kernel/tsc.c.
Fixes booting for Apollo Lake processors.

Signed-off-by: Bernhard Messerklinger <bernhard.messerklinger@br-automation.com>
---
I hope this patch won't break other x86 board.
I only can test it with APL board.

Changes in v1:
- Update to linux way of dealing with TSC calibration

 drivers/timer/tsc_timer.c | 52 +++++++++++++++++++++++++++++++++++++++
 1 file changed, 52 insertions(+)

diff --git a/drivers/timer/tsc_timer.c b/drivers/timer/tsc_timer.c
index ba940ebf1c..ec7f05db17 100644
--- a/drivers/timer/tsc_timer.c
+++ b/drivers/timer/tsc_timer.c
@@ -19,8 +19,56 @@
 
 #define MAX_NUM_FREQS	9
 
+#define INTEL_FAM6_SKYLAKE_MOBILE	0x4E
+#define INTEL_FAM6_ATOM_GOLDMONT	0x5C /* Apollo Lake */
+#define INTEL_FAM6_SKYLAKE_DESKTOP	0x5E
+#define INTEL_FAM6_KABYLAKE_MOBILE	0x8E
+#define INTEL_FAM6_KABYLAKE_DESKTOP	0x9E
+#define INTEL_FAM6_ATOM_DENVERTON	0x5F /* Goldmont Microserver */
+
 DECLARE_GLOBAL_DATA_PTR;
 
+/*
+ * native_calibrate_tsc
+ * Determine TSC frequency via CPUID, else return 0.
+ */
+static unsigned long native_calibrate_tsc(void)
+{
+	struct cpuid_result tsc_info;
+	unsigned int crystal_freq;
+
+	if (gd->arch.x86_vendor != X86_VENDOR_INTEL)
+		return 0;
+
+	if (cpuid_eax(0) < 0x15)
+		return 0;
+
+	tsc_info = cpuid(0x15);
+
+	crystal_freq = tsc_info.ecx / 1000;
+
+	if (!crystal_freq) {
+		switch (gd->arch.x86_model) {
+		case INTEL_FAM6_SKYLAKE_MOBILE:
+		case INTEL_FAM6_SKYLAKE_DESKTOP:
+		case INTEL_FAM6_KABYLAKE_MOBILE:
+		case INTEL_FAM6_KABYLAKE_DESKTOP:
+			crystal_freq = 24000;	/* 24.0 MHz */
+			break;
+		case INTEL_FAM6_ATOM_DENVERTON:
+			crystal_freq = 25000;	/* 25.0 MHz */
+			break;
+		case INTEL_FAM6_ATOM_GOLDMONT:
+			crystal_freq = 19200;	/* 19.2 MHz */
+			break;
+		default:
+			return 0;
+		}
+	}
+
+	return (crystal_freq * tsc_info.ebx / tsc_info.eax) / 1000;
+}
+
 static unsigned long cpu_mhz_from_cpuid(void)
 {
 	if (gd->arch.x86_vendor != X86_VENDOR_INTEL)
@@ -350,6 +398,10 @@ static void tsc_timer_ensure_setup(bool early)
 	if (!gd->arch.clock_rate) {
 		unsigned long fast_calibrate;
 
+		fast_calibrate = native_calibrate_tsc();
+		if (fast_calibrate)
+			goto done;
+
 		fast_calibrate = cpu_mhz_from_cpuid();
 		if (fast_calibrate)
 			goto done;
-- 
2.20.1

[U-Boot] [PATCH v2] x86: tsc: Add support for native calibration of TSC freq

[Bin Meng]

Hi Bernhard,

On Fri, Dec 21, 2018 at 3:31 PM Bernhard Messerklinger
<bernhard.messerklinger@br-automation.com> wrote:
>
> Add native tsc calibration function. Calibrate the tsc timer the same
> way as linux does arch/x86/kernel/tsc.c.

nits: does in arch/x86/kernel/tsc.c

> Fixes booting for Apollo Lake processors.
>
> Signed-off-by: Bernhard Messerklinger <bernhard.messerklinger@br-automation.com>
> ---
> I hope this patch won't break other x86 board.
> I only can test it with APL board.
>
> Changes in v1:
> - Update to linux way of dealing with TSC calibration
>
>  drivers/timer/tsc_timer.c | 52 +++++++++++++++++++++++++++++++++++++++
>  1 file changed, 52 insertions(+)
>
> diff --git a/drivers/timer/tsc_timer.c b/drivers/timer/tsc_timer.c
> index ba940ebf1c..ec7f05db17 100644
> --- a/drivers/timer/tsc_timer.c
> +++ b/drivers/timer/tsc_timer.c
> @@ -19,8 +19,56 @@
>
>  #define MAX_NUM_FREQS  9
>
> +#define INTEL_FAM6_SKYLAKE_MOBILE      0x4E
> +#define INTEL_FAM6_ATOM_GOLDMONT       0x5C /* Apollo Lake */
> +#define INTEL_FAM6_SKYLAKE_DESKTOP     0x5E
> +#define INTEL_FAM6_KABYLAKE_MOBILE     0x8E
> +#define INTEL_FAM6_KABYLAKE_DESKTOP    0x9E
> +#define INTEL_FAM6_ATOM_DENVERTON      0x5F /* Goldmont Microserver */

Linux uses the macro name INTEL_FAM6_ATOM_GOLDMONT_X. Can we use
exactly the same name to keep in sync? Also please use the same
comments as Linux.

> +

nits: Can we sort the numbers here?

>  DECLARE_GLOBAL_DATA_PTR;
>
> +/*
> + * native_calibrate_tsc
> + * Determine TSC frequency via CPUID, else return 0.
> + */
> +static unsigned long native_calibrate_tsc(void)
> +{
> +       struct cpuid_result tsc_info;
> +       unsigned int crystal_freq;
> +
> +       if (gd->arch.x86_vendor != X86_VENDOR_INTEL)
> +               return 0;
> +
> +       if (cpuid_eax(0) < 0x15)
> +               return 0;
> +
> +       tsc_info = cpuid(0x15);
> +
> +       crystal_freq = tsc_info.ecx / 1000;
> +

Missing checking tsc_info.eax and tsc_info.ebx here, like what is done
in Linux codes.

> +       if (!crystal_freq) {
> +               switch (gd->arch.x86_model) {
> +               case INTEL_FAM6_SKYLAKE_MOBILE:
> +               case INTEL_FAM6_SKYLAKE_DESKTOP:
> +               case INTEL_FAM6_KABYLAKE_MOBILE:
> +               case INTEL_FAM6_KABYLAKE_DESKTOP:
> +                       crystal_freq = 24000;   /* 24.0 MHz */
> +                       break;
> +               case INTEL_FAM6_ATOM_DENVERTON:
> +                       crystal_freq = 25000;   /* 25.0 MHz */
> +                       break;
> +               case INTEL_FAM6_ATOM_GOLDMONT:
> +                       crystal_freq = 19200;   /* 19.2 MHz */
> +                       break;
> +               default:
> +                       return 0;
> +               }
> +       }
> +
> +       return (crystal_freq * tsc_info.ebx / tsc_info.eax) / 1000;
> +}
> +
>  static unsigned long cpu_mhz_from_cpuid(void)
>  {
>         if (gd->arch.x86_vendor != X86_VENDOR_INTEL)
> @@ -350,6 +398,10 @@ static void tsc_timer_ensure_setup(bool early)
>         if (!gd->arch.clock_rate) {
>                 unsigned long fast_calibrate;
>
> +               fast_calibrate = native_calibrate_tsc();
> +               if (fast_calibrate)
> +                       goto done;
> +
>                 fast_calibrate = cpu_mhz_from_cpuid();
>                 if (fast_calibrate)
>                         goto done;
> --

Regards,
Bin

[U-Boot] [PATCH v3] x86: tsc: Add support for native calibration of TSC freq

[Bernhard Messerklinger]

Add native tsc calibration function. Calibrate the tsc timer the same
way as linux does in arch/x86/kernel/tsc.c.
Fixes booting for Apollo Lake processors.

Signed-off-by: Bernhard Messerklinger <bernhard.messerklinger@br-automation.com>
---
I hope this patch won't break other x86 board.
I only can test it with APL board.

Changes in v4:
- Fix commit message
- Update macro names
- Order macro numbers
- Check cpuid eax and ebx return value

 drivers/timer/tsc_timer.c | 55 +++++++++++++++++++++++++++++++++++++++
 1 file changed, 55 insertions(+)

diff --git a/drivers/timer/tsc_timer.c b/drivers/timer/tsc_timer.c
index ba940ebf1c..919caba8a1 100644
--- a/drivers/timer/tsc_timer.c
+++ b/drivers/timer/tsc_timer.c
@@ -19,8 +19,59 @@
 
 #define MAX_NUM_FREQS	9
 
+#define INTEL_FAM6_SKYLAKE_MOBILE	0x4E
+#define INTEL_FAM6_ATOM_GOLDMONT	0x5C /* Apollo Lake */
+#define INTEL_FAM6_SKYLAKE_DESKTOP	0x5E
+#define INTEL_FAM6_ATOM_GOLDMONT_X	0x5F /* Denverton */
+#define INTEL_FAM6_KABYLAKE_MOBILE	0x8E
+#define INTEL_FAM6_KABYLAKE_DESKTOP	0x9E
+
 DECLARE_GLOBAL_DATA_PTR;
 
+/*
+ * native_calibrate_tsc
+ * Determine TSC frequency via CPUID, else return 0.
+ */
+static unsigned long native_calibrate_tsc(void)
+{
+	struct cpuid_result tsc_info;
+	unsigned int crystal_freq;
+
+	if (gd->arch.x86_vendor != X86_VENDOR_INTEL)
+		return 0;
+
+	if (cpuid_eax(0) < 0x15)
+		return 0;
+
+	tsc_info = cpuid(0x15);
+
+	if (tsc_info.ebx == 0 || tsc_info.eax == 0)
+		return 0;
+
+	crystal_freq = tsc_info.ecx / 1000;
+
+	if (!crystal_freq) {
+		switch (gd->arch.x86_model) {
+		case INTEL_FAM6_SKYLAKE_MOBILE:
+		case INTEL_FAM6_SKYLAKE_DESKTOP:
+		case INTEL_FAM6_KABYLAKE_MOBILE:
+		case INTEL_FAM6_KABYLAKE_DESKTOP:
+			crystal_freq = 24000;	/* 24.0 MHz */
+			break;
+		case INTEL_FAM6_ATOM_GOLDMONT_X:
+			crystal_freq = 25000;	/* 25.0 MHz */
+			break;
+		case INTEL_FAM6_ATOM_GOLDMONT:
+			crystal_freq = 19200;	/* 19.2 MHz */
+			break;
+		default:
+			return 0;
+		}
+	}
+
+	return (crystal_freq * tsc_info.ebx / tsc_info.eax) / 1000;
+}
+
 static unsigned long cpu_mhz_from_cpuid(void)
 {
 	if (gd->arch.x86_vendor != X86_VENDOR_INTEL)
@@ -350,6 +401,10 @@ static void tsc_timer_ensure_setup(bool early)
 	if (!gd->arch.clock_rate) {
 		unsigned long fast_calibrate;
 
+		fast_calibrate = native_calibrate_tsc();
+		if (fast_calibrate)
+			goto done;
+
 		fast_calibrate = cpu_mhz_from_cpuid();
 		if (fast_calibrate)
 			goto done;
-- 
2.20.1

[U-Boot] [PATCH v3] x86: tsc: Add support for native calibration of TSC freq

[Andy Shevchenko]

On Mon, Jan 7, 2019 at 1:14 PM Bernhard Messerklinger
<bernhard.messerklinger@br-automation.com> wrote:
>
> Add native tsc calibration function. Calibrate the tsc timer the same
> way as linux does in arch/x86/kernel/tsc.c.
> Fixes booting for Apollo Lake processors.
>

LGTM
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>

P.S. Though I didn't test it.

> Signed-off-by: Bernhard Messerklinger <bernhard.messerklinger@br-automation.com>
> ---
> I hope this patch won't break other x86 board.
> I only can test it with APL board.
>
> Changes in v4:
> - Fix commit message
> - Update macro names
> - Order macro numbers
> - Check cpuid eax and ebx return value
>
>  drivers/timer/tsc_timer.c | 55 +++++++++++++++++++++++++++++++++++++++
>  1 file changed, 55 insertions(+)
>
> diff --git a/drivers/timer/tsc_timer.c b/drivers/timer/tsc_timer.c
> index ba940ebf1c..919caba8a1 100644
> --- a/drivers/timer/tsc_timer.c
> +++ b/drivers/timer/tsc_timer.c
> @@ -19,8 +19,59 @@
>
>  #define MAX_NUM_FREQS  9
>
> +#define INTEL_FAM6_SKYLAKE_MOBILE      0x4E
> +#define INTEL_FAM6_ATOM_GOLDMONT       0x5C /* Apollo Lake */
> +#define INTEL_FAM6_SKYLAKE_DESKTOP     0x5E
> +#define INTEL_FAM6_ATOM_GOLDMONT_X     0x5F /* Denverton */
> +#define INTEL_FAM6_KABYLAKE_MOBILE     0x8E
> +#define INTEL_FAM6_KABYLAKE_DESKTOP    0x9E
> +
>  DECLARE_GLOBAL_DATA_PTR;
>
> +/*
> + * native_calibrate_tsc
> + * Determine TSC frequency via CPUID, else return 0.
> + */
> +static unsigned long native_calibrate_tsc(void)
> +{
> +       struct cpuid_result tsc_info;
> +       unsigned int crystal_freq;
> +
> +       if (gd->arch.x86_vendor != X86_VENDOR_INTEL)
> +               return 0;
> +
> +       if (cpuid_eax(0) < 0x15)
> +               return 0;
> +
> +       tsc_info = cpuid(0x15);
> +
> +       if (tsc_info.ebx == 0 || tsc_info.eax == 0)
> +               return 0;
> +
> +       crystal_freq = tsc_info.ecx / 1000;
> +
> +       if (!crystal_freq) {
> +               switch (gd->arch.x86_model) {
> +               case INTEL_FAM6_SKYLAKE_MOBILE:
> +               case INTEL_FAM6_SKYLAKE_DESKTOP:
> +               case INTEL_FAM6_KABYLAKE_MOBILE:
> +               case INTEL_FAM6_KABYLAKE_DESKTOP:
> +                       crystal_freq = 24000;   /* 24.0 MHz */
> +                       break;
> +               case INTEL_FAM6_ATOM_GOLDMONT_X:
> +                       crystal_freq = 25000;   /* 25.0 MHz */
> +                       break;
> +               case INTEL_FAM6_ATOM_GOLDMONT:
> +                       crystal_freq = 19200;   /* 19.2 MHz */
> +                       break;
> +               default:
> +                       return 0;
> +               }
> +       }
> +
> +       return (crystal_freq * tsc_info.ebx / tsc_info.eax) / 1000;
> +}
> +
>  static unsigned long cpu_mhz_from_cpuid(void)
>  {
>         if (gd->arch.x86_vendor != X86_VENDOR_INTEL)
> @@ -350,6 +401,10 @@ static void tsc_timer_ensure_setup(bool early)
>         if (!gd->arch.clock_rate) {
>                 unsigned long fast_calibrate;
>
> +               fast_calibrate = native_calibrate_tsc();
> +               if (fast_calibrate)
> +                       goto done;
> +
>                 fast_calibrate = cpu_mhz_from_cpuid();
>                 if (fast_calibrate)
>                         goto done;
> --
> 2.20.1
>
>


-- 
With Best Regards,
Andy Shevchenko

[U-Boot] [PATCH v2] x86: tsc: Add support for native calibration of TSC freq

[Bin Meng]

On Fri, Dec 21, 2018 at 3:31 PM Bernhard Messerklinger
<bernhard.messerklinger@br-automation.com> wrote:
>
> Add native tsc calibration function. Calibrate the tsc timer the same
> way as linux does arch/x86/kernel/tsc.c.
> Fixes booting for Apollo Lake processors.
>
> Signed-off-by: Bernhard Messerklinger <bernhard.messerklinger@br-automation.com>
> ---
> I hope this patch won't break other x86 board.
> I only can test it with APL board.
>
> Changes in v1:
> - Update to linux way of dealing with TSC calibration
>
>  drivers/timer/tsc_timer.c | 52 +++++++++++++++++++++++++++++++++++++++
>  1 file changed, 52 insertions(+)
>

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

[U-Boot] [PATCH v3] x86: tsc: Add support for native calibration of TSC freq

[Bin Meng]

On Mon, Jan 7, 2019 at 7:14 PM Bernhard Messerklinger
<bernhard.messerklinger@br-automation.com> wrote:
>
> Add native tsc calibration function. Calibrate the tsc timer the same
> way as linux does in arch/x86/kernel/tsc.c.
> Fixes booting for Apollo Lake processors.
>
> Signed-off-by: Bernhard Messerklinger <bernhard.messerklinger@br-automation.com>
> ---
> I hope this patch won't break other x86 board.
> I only can test it with APL board.
>
> Changes in v4:
> - Fix commit message
> - Update macro names
> - Order macro numbers
> - Check cpuid eax and ebx return value
>
>  drivers/timer/tsc_timer.c | 55 +++++++++++++++++++++++++++++++++++++++
>  1 file changed, 55 insertions(+)
>

applied to u-boot-x86, thanks!