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From: Andy Shevchenko <andy.shevchenko@gmail.com>
To: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Cc: "Linus Walleij" <linus.walleij@linaro.org>,
	"Rob Herring" <robh+dt@kernel.org>,
	"Andreas Färber" <afaerber@suse.de>, 刘炜 <liuwei@actions-semi.com>,
	mp-cs@actions-semi.com, 96boards@ucrobotics.com,
	devicetree <devicetree@vger.kernel.org>,
	"Daniel Thompson" <daniel.thompson@linaro.org>,
	amit.kucheria@linaro.org,
	"linux-arm Mailing List" <linux-arm-kernel@lists.infradead.org>,
	"open list:GPIO SUBSYSTEM" <linux-gpio@vger.kernel.org>,
	"Linux Kernel Mailing List" <linux-kernel@vger.kernel.org>,
	hzhang@ucrobotics.com, bdong@ucrobotics.com,
	manivannanece23@gmail.com
Subject: Re: [PATCH v3 04/10] pinctrl: actions: Add Actions S900 pinctrl driver
Date: Wed, 28 Feb 2018 20:36:53 +0200	[thread overview]
Message-ID: <CAHp75VchzV9SZb4g0fVP9aoKb7actsehXm8c4wsvVGASgkOc+w@mail.gmail.com> (raw)
In-Reply-To: <20180228181432.26847-5-manivannan.sadhasivam@linaro.org>

On Wed, Feb 28, 2018 at 8:14 PM, Manivannan Sadhasivam
<manivannan.sadhasivam@linaro.org> wrote:
> Add pinctrl driver for Actions Semi S900 SoC. The driver supports
> pinctrl, pinmux and pinconf functionalities through a range of registers
> common to both gpio driver and pinctrl driver.
>
> Pinmux functionality is available only for the pin groups while the
> pinconf functionality is available for both pin groups and individual
> pins.

> +static int owl_set_mux(struct pinctrl_dev *pctrldev,
> +                               unsigned int function,
> +                               unsigned int group)
> +{

> +       mfpval = readl(pctrl->base + g->mfpctl_reg);
> +       mfpval &= ~mask;
> +       mfpval |= val;
> +       writel(mfpval, pctrl->base + g->mfpctl_reg);

This is called owl_update_bits().

> +static int owl_pin_config_set(struct pinctrl_dev *pctrldev,
> +                               unsigned int pin,
> +                               unsigned long *configs,
> +                               unsigned int num_configs)
> +{

> +       int ret = 0;

Redundant assignment?

> +               mask = (1 << width) - 1;
> +               mask = mask << bit;
> +               tmp = readl(pctrl->base + reg);
> +               tmp &= ~mask;
> +               tmp |= arg << bit;
> +               writel(tmp, pctrl->base + reg);

This is called owl_update_bits().

> +}

> +static int owl_group_pinconf_val2arg(const struct owl_pingroup *g,
> +                               unsigned int param,
> +                               u32 *arg)
> +{

> +       case PIN_CONFIG_SLEW_RATE:
> +               if (*arg)
> +                       *arg = 1;
> +               else
> +                       *arg = 0;

Doesn't slew rate allow a non-binary value?

> +       return 0;
> +}
> +
> +static int owl_group_config_get(struct pinctrl_dev *pctrldev,
> +                               unsigned int group,
> +                               unsigned long *config)
> +{
> +       int ret = 0;

Redundant assignment.

> +}

> +static int owl_group_config_set(struct pinctrl_dev *pctrldev,
> +                               unsigned int group,
> +                               unsigned long *configs,
> +                               unsigned int num_configs)
> +{
> +       int ret = 0;

Redundant assignment, see below.

> +               mask = (1 << width) - 1;
> +               mask = mask << bit;
> +               tmp = readl(pctrl->base + reg);
> +               tmp &= ~mask;
> +               tmp |= arg << bit;
> +               writel(tmp, pctrl->base + reg);

This is called owl_update_bits().

> +       return ret;

return 0; ?

> +}

> +int owl_pinctrl_probe(struct platform_device *pdev,
> +                               struct owl_pinctrl_soc_data *soc_data)
> +{

> +       clk_prepare_enable(pctrl->clk);

This can fail.

> +}

> +static const struct of_device_id s900_pinctrl_of_match[] = {
> +       { .compatible = "actions,s900-pinctrl", },

> +       { },

No comma needed.

> +};

-- 
With Best Regards,
Andy Shevchenko

WARNING: multiple messages have this Message-ID (diff)
From: andy.shevchenko@gmail.com (Andy Shevchenko)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v3 04/10] pinctrl: actions: Add Actions S900 pinctrl driver
Date: Wed, 28 Feb 2018 20:36:53 +0200	[thread overview]
Message-ID: <CAHp75VchzV9SZb4g0fVP9aoKb7actsehXm8c4wsvVGASgkOc+w@mail.gmail.com> (raw)
In-Reply-To: <20180228181432.26847-5-manivannan.sadhasivam@linaro.org>

On Wed, Feb 28, 2018 at 8:14 PM, Manivannan Sadhasivam
<manivannan.sadhasivam@linaro.org> wrote:
> Add pinctrl driver for Actions Semi S900 SoC. The driver supports
> pinctrl, pinmux and pinconf functionalities through a range of registers
> common to both gpio driver and pinctrl driver.
>
> Pinmux functionality is available only for the pin groups while the
> pinconf functionality is available for both pin groups and individual
> pins.

> +static int owl_set_mux(struct pinctrl_dev *pctrldev,
> +                               unsigned int function,
> +                               unsigned int group)
> +{

> +       mfpval = readl(pctrl->base + g->mfpctl_reg);
> +       mfpval &= ~mask;
> +       mfpval |= val;
> +       writel(mfpval, pctrl->base + g->mfpctl_reg);

This is called owl_update_bits().

> +static int owl_pin_config_set(struct pinctrl_dev *pctrldev,
> +                               unsigned int pin,
> +                               unsigned long *configs,
> +                               unsigned int num_configs)
> +{

> +       int ret = 0;

Redundant assignment?

> +               mask = (1 << width) - 1;
> +               mask = mask << bit;
> +               tmp = readl(pctrl->base + reg);
> +               tmp &= ~mask;
> +               tmp |= arg << bit;
> +               writel(tmp, pctrl->base + reg);

This is called owl_update_bits().

> +}

> +static int owl_group_pinconf_val2arg(const struct owl_pingroup *g,
> +                               unsigned int param,
> +                               u32 *arg)
> +{

> +       case PIN_CONFIG_SLEW_RATE:
> +               if (*arg)
> +                       *arg = 1;
> +               else
> +                       *arg = 0;

Doesn't slew rate allow a non-binary value?

> +       return 0;
> +}
> +
> +static int owl_group_config_get(struct pinctrl_dev *pctrldev,
> +                               unsigned int group,
> +                               unsigned long *config)
> +{
> +       int ret = 0;

Redundant assignment.

> +}

> +static int owl_group_config_set(struct pinctrl_dev *pctrldev,
> +                               unsigned int group,
> +                               unsigned long *configs,
> +                               unsigned int num_configs)
> +{
> +       int ret = 0;

Redundant assignment, see below.

> +               mask = (1 << width) - 1;
> +               mask = mask << bit;
> +               tmp = readl(pctrl->base + reg);
> +               tmp &= ~mask;
> +               tmp |= arg << bit;
> +               writel(tmp, pctrl->base + reg);

This is called owl_update_bits().

> +       return ret;

return 0; ?

> +}

> +int owl_pinctrl_probe(struct platform_device *pdev,
> +                               struct owl_pinctrl_soc_data *soc_data)
> +{

> +       clk_prepare_enable(pctrl->clk);

This can fail.

> +}

> +static const struct of_device_id s900_pinctrl_of_match[] = {
> +       { .compatible = "actions,s900-pinctrl", },

> +       { },

No comma needed.

> +};

-- 
With Best Regards,
Andy Shevchenko

  reply	other threads:[~2018-02-28 18:36 UTC|newest]

Thread overview: 36+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-02-28 18:14 [PATCH v3 00/10] Add Actions Semi S900 pinctrl and gpio support Manivannan Sadhasivam
2018-02-28 18:14 ` Manivannan Sadhasivam
2018-02-28 18:14 ` [PATCH v3 01/10] dt-bindings: pinctrl: Add bindings for Actions S900 SoC Manivannan Sadhasivam
2018-02-28 18:14   ` Manivannan Sadhasivam
2018-03-01  9:20   ` Linus Walleij
2018-03-01  9:20     ` Linus Walleij
2018-03-01  9:25     ` Manivannan Sadhasivam
2018-03-01  9:25       ` Manivannan Sadhasivam
2018-03-01 10:23       ` Daniel Thompson
2018-03-01 10:23         ` Daniel Thompson
2018-03-01 10:33         ` Manivannan Sadhasivam
2018-03-01 10:33           ` Manivannan Sadhasivam
2018-02-28 18:14 ` [PATCH v3 02/10] arm64: dts: actions: Add pinctrl node for S900 Manivannan Sadhasivam
2018-02-28 18:14   ` Manivannan Sadhasivam
2018-02-28 18:14 ` [PATCH v3 03/10] arm64: actions: Enable PINCTRL in platforms Kconfig Manivannan Sadhasivam
2018-02-28 18:14   ` Manivannan Sadhasivam
2018-02-28 18:14 ` [PATCH v3 04/10] pinctrl: actions: Add Actions S900 pinctrl driver Manivannan Sadhasivam
2018-02-28 18:14   ` Manivannan Sadhasivam
2018-02-28 18:36   ` Andy Shevchenko [this message]
2018-02-28 18:36     ` Andy Shevchenko
2018-03-01 17:29     ` Manivannan Sadhasivam
2018-03-01 17:29       ` Manivannan Sadhasivam
2018-02-28 18:14 ` [PATCH v3 05/10] dt-bindings: gpio: Add gpio nodes for Actions S900 SoC Manivannan Sadhasivam
2018-02-28 18:14   ` Manivannan Sadhasivam
2018-02-28 18:14 ` [PATCH v3 06/10] arm64: dts: actions: Add S900 gpio nodes Manivannan Sadhasivam
2018-02-28 18:14   ` Manivannan Sadhasivam
2018-02-28 18:14 ` [PATCH v3 07/10] arm64: dts: actions: Add gpio line names to Bubblegum-96 board Manivannan Sadhasivam
2018-02-28 18:14   ` Manivannan Sadhasivam
2018-02-28 18:14 ` [PATCH v3 08/10] gpio: Add gpio driver for Actions OWL S900 SoC Manivannan Sadhasivam
2018-02-28 18:14   ` Manivannan Sadhasivam
2018-02-28 18:39   ` Andy Shevchenko
2018-02-28 18:39     ` Andy Shevchenko
2018-02-28 18:14 ` [PATCH v3 09/10] MAINTAINERS: Add reviewer for ACTIONS platforms Manivannan Sadhasivam
2018-02-28 18:14   ` Manivannan Sadhasivam
2018-02-28 18:14 ` [PATCH v3 10/10] MAINTAINERS: Add Actions Semi S900 pinctrl and gpio entries Manivannan Sadhasivam
2018-02-28 18:14   ` Manivannan Sadhasivam

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