* [PATCH 0/3] P2040/P2041 i2c recovery erratum
@ 2021-05-06 1:10 ` Chris Packham
0 siblings, 0 replies; 10+ messages in thread
From: Chris Packham @ 2021-05-06 1:10 UTC (permalink / raw)
To: wsa, andriy.shevchenko, andy.shevchenko, robh+dt, mpe
Cc: linux-i2c, devicetree, linuxppc-dev, linux-kernel, Chris Packham
The P2040/P2041 has an erratum where the i2c recovery scheme
documented in the reference manual (and currently implemented
in the i2c-mpc.c driver) does not work. The errata document
provides an alternative that does work. This series implements
that alternative and uses a property in the devicetree to
decide when the alternative mechanism is needed.
Chris Packham (3):
dt-bindings: i2c: mpc: Add fsl,i2c-erratum-a004447 flag
powerpc/fsl: set fsl,i2c-erratum-a004447 flag for P2041 i2c
controllers
i2c: mpc: implement erratum A-004447 workaround
.../devicetree/bindings/i2c/i2c-mpc.yaml | 7 ++
arch/powerpc/boot/dts/fsl/p2041si-post.dtsi | 16 ++++
drivers/i2c/busses/i2c-mpc.c | 88 ++++++++++++++++++-
3 files changed, 109 insertions(+), 2 deletions(-)
--
2.31.1
^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH 0/3] P2040/P2041 i2c recovery erratum
@ 2021-05-06 1:10 ` Chris Packham
0 siblings, 0 replies; 10+ messages in thread
From: Chris Packham @ 2021-05-06 1:10 UTC (permalink / raw)
To: wsa, andriy.shevchenko, andy.shevchenko, robh+dt, mpe
Cc: devicetree, Chris Packham, linuxppc-dev, linux-i2c, linux-kernel
The P2040/P2041 has an erratum where the i2c recovery scheme
documented in the reference manual (and currently implemented
in the i2c-mpc.c driver) does not work. The errata document
provides an alternative that does work. This series implements
that alternative and uses a property in the devicetree to
decide when the alternative mechanism is needed.
Chris Packham (3):
dt-bindings: i2c: mpc: Add fsl,i2c-erratum-a004447 flag
powerpc/fsl: set fsl,i2c-erratum-a004447 flag for P2041 i2c
controllers
i2c: mpc: implement erratum A-004447 workaround
.../devicetree/bindings/i2c/i2c-mpc.yaml | 7 ++
arch/powerpc/boot/dts/fsl/p2041si-post.dtsi | 16 ++++
drivers/i2c/busses/i2c-mpc.c | 88 ++++++++++++++++++-
3 files changed, 109 insertions(+), 2 deletions(-)
--
2.31.1
^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH 1/3] dt-bindings: i2c: mpc: Add fsl,i2c-erratum-a004447 flag
2021-05-06 1:10 ` Chris Packham
@ 2021-05-06 1:10 ` Chris Packham
-1 siblings, 0 replies; 10+ messages in thread
From: Chris Packham @ 2021-05-06 1:10 UTC (permalink / raw)
To: wsa, andriy.shevchenko, andy.shevchenko, robh+dt, mpe
Cc: linux-i2c, devicetree, linuxppc-dev, linux-kernel, Chris Packham
Document the fsl,i2c-erratum-a004447 flag which indicates the presence
of an i2c erratum on some QorIQ SoCs.
Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
---
Documentation/devicetree/bindings/i2c/i2c-mpc.yaml | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/Documentation/devicetree/bindings/i2c/i2c-mpc.yaml b/Documentation/devicetree/bindings/i2c/i2c-mpc.yaml
index 7b553d559c83..98c6fcf7bf26 100644
--- a/Documentation/devicetree/bindings/i2c/i2c-mpc.yaml
+++ b/Documentation/devicetree/bindings/i2c/i2c-mpc.yaml
@@ -46,6 +46,13 @@ properties:
description: |
I2C bus timeout in microseconds
+ fsl,i2c-erratum-a004447:
+ $ref: /schemas/types.yaml#/definitions/flag
+ description: |
+ Indicates the presence of QorIQ erratum A-004447, which
+ says that the standard i2c recovery scheme mechanism does
+ not work and an alternate implementation is needed.
+
required:
- compatible
- reg
--
2.31.1
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH 1/3] dt-bindings: i2c: mpc: Add fsl,i2c-erratum-a004447 flag
@ 2021-05-06 1:10 ` Chris Packham
0 siblings, 0 replies; 10+ messages in thread
From: Chris Packham @ 2021-05-06 1:10 UTC (permalink / raw)
To: wsa, andriy.shevchenko, andy.shevchenko, robh+dt, mpe
Cc: devicetree, Chris Packham, linuxppc-dev, linux-i2c, linux-kernel
Document the fsl,i2c-erratum-a004447 flag which indicates the presence
of an i2c erratum on some QorIQ SoCs.
Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
---
Documentation/devicetree/bindings/i2c/i2c-mpc.yaml | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/Documentation/devicetree/bindings/i2c/i2c-mpc.yaml b/Documentation/devicetree/bindings/i2c/i2c-mpc.yaml
index 7b553d559c83..98c6fcf7bf26 100644
--- a/Documentation/devicetree/bindings/i2c/i2c-mpc.yaml
+++ b/Documentation/devicetree/bindings/i2c/i2c-mpc.yaml
@@ -46,6 +46,13 @@ properties:
description: |
I2C bus timeout in microseconds
+ fsl,i2c-erratum-a004447:
+ $ref: /schemas/types.yaml#/definitions/flag
+ description: |
+ Indicates the presence of QorIQ erratum A-004447, which
+ says that the standard i2c recovery scheme mechanism does
+ not work and an alternate implementation is needed.
+
required:
- compatible
- reg
--
2.31.1
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH 2/3] powerpc/fsl: set fsl,i2c-erratum-a004447 flag for P2041 i2c controllers
2021-05-06 1:10 ` Chris Packham
@ 2021-05-06 1:10 ` Chris Packham
-1 siblings, 0 replies; 10+ messages in thread
From: Chris Packham @ 2021-05-06 1:10 UTC (permalink / raw)
To: wsa, andriy.shevchenko, andy.shevchenko, robh+dt, mpe
Cc: linux-i2c, devicetree, linuxppc-dev, linux-kernel, Chris Packham,
Benjamin Herrenschmidt, Paul Mackerras
The i2c controllers on the P2040/P2041 have an erratum where the
documented scheme for i2c bus recovery will not work (A-004447). A
different mechanism is needed which is documented in the P2040 Chip
Errata Rev Q (latest available at the time of writing).
Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
---
arch/powerpc/boot/dts/fsl/p2041si-post.dtsi | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/arch/powerpc/boot/dts/fsl/p2041si-post.dtsi b/arch/powerpc/boot/dts/fsl/p2041si-post.dtsi
index 872e4485dc3f..ddc018d42252 100644
--- a/arch/powerpc/boot/dts/fsl/p2041si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p2041si-post.dtsi
@@ -371,7 +371,23 @@ sdhc@114000 {
};
/include/ "qoriq-i2c-0.dtsi"
+ i2c@118000 {
+ fsl,i2c-erratum-a004447;
+ };
+
+ i2c@118100 {
+ fsl,i2c-erratum-a004447;
+ };
+
/include/ "qoriq-i2c-1.dtsi"
+ i2c@119000 {
+ fsl,i2c-erratum-a004447;
+ };
+
+ i2c@119100 {
+ fsl,i2c-erratum-a004447;
+ };
+
/include/ "qoriq-duart-0.dtsi"
/include/ "qoriq-duart-1.dtsi"
/include/ "qoriq-gpio-0.dtsi"
--
2.31.1
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH 2/3] powerpc/fsl: set fsl, i2c-erratum-a004447 flag for P2041 i2c controllers
@ 2021-05-06 1:10 ` Chris Packham
0 siblings, 0 replies; 10+ messages in thread
From: Chris Packham @ 2021-05-06 1:10 UTC (permalink / raw)
To: wsa, andriy.shevchenko, andy.shevchenko, robh+dt, mpe
Cc: devicetree, linux-kernel, Chris Packham, Paul Mackerras,
linux-i2c, linuxppc-dev
The i2c controllers on the P2040/P2041 have an erratum where the
documented scheme for i2c bus recovery will not work (A-004447). A
different mechanism is needed which is documented in the P2040 Chip
Errata Rev Q (latest available at the time of writing).
Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
---
arch/powerpc/boot/dts/fsl/p2041si-post.dtsi | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/arch/powerpc/boot/dts/fsl/p2041si-post.dtsi b/arch/powerpc/boot/dts/fsl/p2041si-post.dtsi
index 872e4485dc3f..ddc018d42252 100644
--- a/arch/powerpc/boot/dts/fsl/p2041si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p2041si-post.dtsi
@@ -371,7 +371,23 @@ sdhc@114000 {
};
/include/ "qoriq-i2c-0.dtsi"
+ i2c@118000 {
+ fsl,i2c-erratum-a004447;
+ };
+
+ i2c@118100 {
+ fsl,i2c-erratum-a004447;
+ };
+
/include/ "qoriq-i2c-1.dtsi"
+ i2c@119000 {
+ fsl,i2c-erratum-a004447;
+ };
+
+ i2c@119100 {
+ fsl,i2c-erratum-a004447;
+ };
+
/include/ "qoriq-duart-0.dtsi"
/include/ "qoriq-duart-1.dtsi"
/include/ "qoriq-gpio-0.dtsi"
--
2.31.1
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH 3/3] i2c: mpc: implement erratum A-004447 workaround
2021-05-06 1:10 ` Chris Packham
@ 2021-05-06 1:10 ` Chris Packham
-1 siblings, 0 replies; 10+ messages in thread
From: Chris Packham @ 2021-05-06 1:10 UTC (permalink / raw)
To: wsa, andriy.shevchenko, andy.shevchenko, robh+dt, mpe
Cc: linux-i2c, devicetree, linuxppc-dev, linux-kernel, Chris Packham
The P2040/P2041 has an erratum where the normal i2c recovery mechanism
does not work. Implement the alternative recovery mechanism documented
in the P2040 Chip Errata Rev Q.
Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
---
drivers/i2c/busses/i2c-mpc.c | 88 +++++++++++++++++++++++++++++++++++-
1 file changed, 86 insertions(+), 2 deletions(-)
diff --git a/drivers/i2c/busses/i2c-mpc.c b/drivers/i2c/busses/i2c-mpc.c
index 30d9e89a3db2..052e37718771 100644
--- a/drivers/i2c/busses/i2c-mpc.c
+++ b/drivers/i2c/busses/i2c-mpc.c
@@ -45,6 +45,7 @@
#define CCR_MTX 0x10
#define CCR_TXAK 0x08
#define CCR_RSTA 0x04
+#define CCR_RSVD 0x02
#define CSR_MCF 0x80
#define CSR_MAAS 0x40
@@ -97,7 +98,7 @@ struct mpc_i2c {
u32 block;
int rc;
int expect_rxack;
-
+ bool has_errata_A004447;
};
struct mpc_i2c_divider {
@@ -136,6 +137,83 @@ static void mpc_i2c_fixup(struct mpc_i2c *i2c)
}
}
+static int i2c_mpc_wait_sr(struct mpc_i2c *i2c, int mask)
+{
+ unsigned long timeout = jiffies + usecs_to_jiffies(100);
+ int ret = 0;
+
+ while ((readb(i2c->base + MPC_I2C_SR) & mask) == 0) {
+ if (time_after(jiffies, timeout)) {
+ ret = -ETIMEDOUT;
+ break;
+ }
+ cond_resched();
+ }
+
+ return ret;
+}
+
+/*
+ * Workaround for Erratum A004447. From the P2040CE Rev Q
+ *
+ * 1. Set up the frequency divider and sampling rate.
+ * 2. I2CCR - a0h
+ * 3. Poll for I2CSR[MBB] to get set.
+ * 4. If I2CSR[MAL] is set (an indication that SDA is stuck low), then go to
+ * step 5. If MAL is not set, then go to step 13.
+ * 5. I2CCR - 00h
+ * 6. I2CCR - 22h
+ * 7. I2CCR - a2h
+ * 8. Poll for I2CSR[MBB] to get set.
+ * 9. Issue read to I2CDR.
+ * 10. Poll for I2CSR[MIF] to be set.
+ * 11. I2CCR - 82h
+ * 12. Workaround complete. Skip the next steps.
+ * 13. Issue read to I2CDR.
+ * 14. Poll for I2CSR[MIF] to be set.
+ * 15. I2CCR - 80h
+ */
+static void mpc_i2c_fixup_A004447(struct mpc_i2c *i2c)
+{
+ int ret;
+ u32 val;
+
+ writeccr(i2c, CCR_MEN | CCR_MSTA);
+ ret = i2c_mpc_wait_sr(i2c, CSR_MBB);
+ if (ret) {
+ dev_err(i2c->dev, "timeout waiting for CSR_MBB\n");
+ return;
+ }
+
+ val = readb(i2c->base + MPC_I2C_SR);
+
+ if (val & CSR_MAL) {
+ writeccr(i2c, 0x00);
+ writeccr(i2c, CCR_MSTA | CCR_RSVD);
+ writeccr(i2c, CCR_MEN | CCR_MSTA | CCR_RSVD);
+ ret = i2c_mpc_wait_sr(i2c, CSR_MBB);
+ if (ret) {
+ dev_err(i2c->dev, "timeout waiting for CSR_MBB\n");
+ return;
+ }
+ val = readb(i2c->base + MPC_I2C_DR);
+ ret = i2c_mpc_wait_sr(i2c, CSR_MIF);
+ if (ret) {
+ dev_err(i2c->dev, "timeout waiting for CSR_MIF\n");
+ return;
+ }
+ writeccr(i2c, CCR_MEN | CCR_RSVD);
+ } else {
+ val = readb(i2c->base + MPC_I2C_DR);
+ ret = i2c_mpc_wait_sr(i2c, CSR_MIF);
+ if (ret) {
+ dev_err(i2c->dev, "timeout waiting for CSR_MIF\n");
+ return;
+ }
+ writeccr(i2c, CCR_MEN);
+ }
+}
+
#if defined(CONFIG_PPC_MPC52xx) || defined(CONFIG_PPC_MPC512x)
static const struct mpc_i2c_divider mpc_i2c_dividers_52xx[] = {
{20, 0x20}, {22, 0x21}, {24, 0x22}, {26, 0x23},
@@ -670,7 +748,10 @@ static int fsl_i2c_bus_recovery(struct i2c_adapter *adap)
{
struct mpc_i2c *i2c = i2c_get_adapdata(adap);
- mpc_i2c_fixup(i2c);
+ if (i2c->has_errata_A004447)
+ mpc_i2c_fixup_A004447(i2c);
+ else
+ mpc_i2c_fixup(i2c);
return 0;
}
@@ -767,6 +848,9 @@ static int fsl_i2c_probe(struct platform_device *op)
}
dev_info(i2c->dev, "timeout %u us\n", mpc_ops.timeout * 1000000 / HZ);
+ if (of_property_read_bool(op->dev.of_node, "fsl,i2c-erratum-a004447"))
+ i2c->has_errata_A004447 = true;
+
i2c->adap = mpc_ops;
scnprintf(i2c->adap.name, sizeof(i2c->adap.name),
"MPC adapter (%s)", of_node_full_name(op->dev.of_node));
--
2.31.1
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH 3/3] i2c: mpc: implement erratum A-004447 workaround
@ 2021-05-06 1:10 ` Chris Packham
0 siblings, 0 replies; 10+ messages in thread
From: Chris Packham @ 2021-05-06 1:10 UTC (permalink / raw)
To: wsa, andriy.shevchenko, andy.shevchenko, robh+dt, mpe
Cc: devicetree, Chris Packham, linuxppc-dev, linux-i2c, linux-kernel
The P2040/P2041 has an erratum where the normal i2c recovery mechanism
does not work. Implement the alternative recovery mechanism documented
in the P2040 Chip Errata Rev Q.
Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
---
drivers/i2c/busses/i2c-mpc.c | 88 +++++++++++++++++++++++++++++++++++-
1 file changed, 86 insertions(+), 2 deletions(-)
diff --git a/drivers/i2c/busses/i2c-mpc.c b/drivers/i2c/busses/i2c-mpc.c
index 30d9e89a3db2..052e37718771 100644
--- a/drivers/i2c/busses/i2c-mpc.c
+++ b/drivers/i2c/busses/i2c-mpc.c
@@ -45,6 +45,7 @@
#define CCR_MTX 0x10
#define CCR_TXAK 0x08
#define CCR_RSTA 0x04
+#define CCR_RSVD 0x02
#define CSR_MCF 0x80
#define CSR_MAAS 0x40
@@ -97,7 +98,7 @@ struct mpc_i2c {
u32 block;
int rc;
int expect_rxack;
-
+ bool has_errata_A004447;
};
struct mpc_i2c_divider {
@@ -136,6 +137,83 @@ static void mpc_i2c_fixup(struct mpc_i2c *i2c)
}
}
+static int i2c_mpc_wait_sr(struct mpc_i2c *i2c, int mask)
+{
+ unsigned long timeout = jiffies + usecs_to_jiffies(100);
+ int ret = 0;
+
+ while ((readb(i2c->base + MPC_I2C_SR) & mask) == 0) {
+ if (time_after(jiffies, timeout)) {
+ ret = -ETIMEDOUT;
+ break;
+ }
+ cond_resched();
+ }
+
+ return ret;
+}
+
+/*
+ * Workaround for Erratum A004447. From the P2040CE Rev Q
+ *
+ * 1. Set up the frequency divider and sampling rate.
+ * 2. I2CCR - a0h
+ * 3. Poll for I2CSR[MBB] to get set.
+ * 4. If I2CSR[MAL] is set (an indication that SDA is stuck low), then go to
+ * step 5. If MAL is not set, then go to step 13.
+ * 5. I2CCR - 00h
+ * 6. I2CCR - 22h
+ * 7. I2CCR - a2h
+ * 8. Poll for I2CSR[MBB] to get set.
+ * 9. Issue read to I2CDR.
+ * 10. Poll for I2CSR[MIF] to be set.
+ * 11. I2CCR - 82h
+ * 12. Workaround complete. Skip the next steps.
+ * 13. Issue read to I2CDR.
+ * 14. Poll for I2CSR[MIF] to be set.
+ * 15. I2CCR - 80h
+ */
+static void mpc_i2c_fixup_A004447(struct mpc_i2c *i2c)
+{
+ int ret;
+ u32 val;
+
+ writeccr(i2c, CCR_MEN | CCR_MSTA);
+ ret = i2c_mpc_wait_sr(i2c, CSR_MBB);
+ if (ret) {
+ dev_err(i2c->dev, "timeout waiting for CSR_MBB\n");
+ return;
+ }
+
+ val = readb(i2c->base + MPC_I2C_SR);
+
+ if (val & CSR_MAL) {
+ writeccr(i2c, 0x00);
+ writeccr(i2c, CCR_MSTA | CCR_RSVD);
+ writeccr(i2c, CCR_MEN | CCR_MSTA | CCR_RSVD);
+ ret = i2c_mpc_wait_sr(i2c, CSR_MBB);
+ if (ret) {
+ dev_err(i2c->dev, "timeout waiting for CSR_MBB\n");
+ return;
+ }
+ val = readb(i2c->base + MPC_I2C_DR);
+ ret = i2c_mpc_wait_sr(i2c, CSR_MIF);
+ if (ret) {
+ dev_err(i2c->dev, "timeout waiting for CSR_MIF\n");
+ return;
+ }
+ writeccr(i2c, CCR_MEN | CCR_RSVD);
+ } else {
+ val = readb(i2c->base + MPC_I2C_DR);
+ ret = i2c_mpc_wait_sr(i2c, CSR_MIF);
+ if (ret) {
+ dev_err(i2c->dev, "timeout waiting for CSR_MIF\n");
+ return;
+ }
+ writeccr(i2c, CCR_MEN);
+ }
+}
+
#if defined(CONFIG_PPC_MPC52xx) || defined(CONFIG_PPC_MPC512x)
static const struct mpc_i2c_divider mpc_i2c_dividers_52xx[] = {
{20, 0x20}, {22, 0x21}, {24, 0x22}, {26, 0x23},
@@ -670,7 +748,10 @@ static int fsl_i2c_bus_recovery(struct i2c_adapter *adap)
{
struct mpc_i2c *i2c = i2c_get_adapdata(adap);
- mpc_i2c_fixup(i2c);
+ if (i2c->has_errata_A004447)
+ mpc_i2c_fixup_A004447(i2c);
+ else
+ mpc_i2c_fixup(i2c);
return 0;
}
@@ -767,6 +848,9 @@ static int fsl_i2c_probe(struct platform_device *op)
}
dev_info(i2c->dev, "timeout %u us\n", mpc_ops.timeout * 1000000 / HZ);
+ if (of_property_read_bool(op->dev.of_node, "fsl,i2c-erratum-a004447"))
+ i2c->has_errata_A004447 = true;
+
i2c->adap = mpc_ops;
scnprintf(i2c->adap.name, sizeof(i2c->adap.name),
"MPC adapter (%s)", of_node_full_name(op->dev.of_node));
--
2.31.1
^ permalink raw reply related [flat|nested] 10+ messages in thread
* Re: [PATCH 3/3] i2c: mpc: implement erratum A-004447 workaround
2021-05-06 1:10 ` Chris Packham
(?)
@ 2021-05-06 8:03 ` Andy Shevchenko
2021-05-06 20:45 ` Chris Packham
-1 siblings, 1 reply; 10+ messages in thread
From: Andy Shevchenko @ 2021-05-06 8:03 UTC (permalink / raw)
To: Chris Packham
Cc: devicetree, linux-kernel, wsa, robh+dt, linux-i2c,
andriy.shevchenko, linuxppc-dev
[-- Attachment #1: Type: text/plain, Size: 4798 bytes --]
On Thursday, May 6, 2021, Chris Packham <chris.packham@alliedtelesis.co.nz>
wrote:
> The P2040/P2041 has an erratum where the normal i2c recovery mechanism
> does not work. Implement the alternative recovery mechanism documented
> in the P2040 Chip Errata Rev Q.
>
> Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
> ---
> drivers/i2c/busses/i2c-mpc.c | 88 +++++++++++++++++++++++++++++++++++-
> 1 file changed, 86 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/i2c/busses/i2c-mpc.c b/drivers/i2c/busses/i2c-mpc.c
> index 30d9e89a3db2..052e37718771 100644
> --- a/drivers/i2c/busses/i2c-mpc.c
> +++ b/drivers/i2c/busses/i2c-mpc.c
> @@ -45,6 +45,7 @@
> #define CCR_MTX 0x10
> #define CCR_TXAK 0x08
> #define CCR_RSTA 0x04
> +#define CCR_RSVD 0x02
>
> #define CSR_MCF 0x80
> #define CSR_MAAS 0x40
> @@ -97,7 +98,7 @@ struct mpc_i2c {
> u32 block;
> int rc;
> int expect_rxack;
> -
> + bool has_errata_A004447;
> };
>
> struct mpc_i2c_divider {
> @@ -136,6 +137,83 @@ static void mpc_i2c_fixup(struct mpc_i2c *i2c)
> }
> }
>
> +static int i2c_mpc_wait_sr(struct mpc_i2c *i2c, int mask)
> +{
> + unsigned long timeout = jiffies + usecs_to_jiffies(100);
> + int ret = 0;
> +
> + while ((readb(i2c->base + MPC_I2C_SR) & mask) == 0) {
> + if (time_after(jiffies, timeout)) {
> + ret = -ETIMEDOUT;
> + break;
> + }
> + cond_resched();
> + }
> +
> + return ret;
> +}
readb_poll_timeout()
> +
> +/*
> + * Workaround for Erratum A004447. From the P2040CE Rev Q
> + *
> + * 1. Set up the frequency divider and sampling rate.
> + * 2. I2CCR - a0h
> + * 3. Poll for I2CSR[MBB] to get set.
> + * 4. If I2CSR[MAL] is set (an indication that SDA is stuck low), then
> go to
> + * step 5. If MAL is not set, then go to step 13.
> + * 5. I2CCR - 00h
> + * 6. I2CCR - 22h
> + * 7. I2CCR - a2h
> + * 8. Poll for I2CSR[MBB] to get set.
> + * 9. Issue read to I2CDR.
> + * 10. Poll for I2CSR[MIF] to be set.
> + * 11. I2CCR - 82h
> + * 12. Workaround complete. Skip the next steps.
> + * 13. Issue read to I2CDR.
> + * 14. Poll for I2CSR[MIF] to be set.
> + * 15. I2CCR - 80h
> + */
> +static void mpc_i2c_fixup_A004447(struct mpc_i2c *i2c)
> +{
> + int ret;
> + u32 val;
> +
> + writeccr(i2c, CCR_MEN | CCR_MSTA);
> + ret = i2c_mpc_wait_sr(i2c, CSR_MBB);
> + if (ret) {
> + dev_err(i2c->dev, "timeout waiting for CSR_MBB\n");
> + return;
> + }
> +
> + val = readb(i2c->base + MPC_I2C_SR);
> +
> + if (val & CSR_MAL) {
> + writeccr(i2c, 0x00);
> + writeccr(i2c, CCR_MSTA | CCR_RSVD);
> + writeccr(i2c, CCR_MEN | CCR_MSTA | CCR_RSVD);
> + ret = i2c_mpc_wait_sr(i2c, CSR_MBB);
> + if (ret) {
> + dev_err(i2c->dev, "timeout waiting for CSR_MBB\n");
> + return;
> + }
> + val = readb(i2c->base + MPC_I2C_DR);
> + ret = i2c_mpc_wait_sr(i2c, CSR_MIF);
> + if (ret) {
> + dev_err(i2c->dev, "timeout waiting for CSR_MIF\n");
> + return;
> + }
> + writeccr(i2c, CCR_MEN | CCR_RSVD);
> + } else {
> + val = readb(i2c->base + MPC_I2C_DR);
> + ret = i2c_mpc_wait_sr(i2c, CSR_MIF);
> + if (ret) {
> + dev_err(i2c->dev, "timeout waiting for CSR_MIF\n");
> + return;
> + }
> + writeccr(i2c, CCR_MEN);
> + }
> +}
> +
> #if defined(CONFIG_PPC_MPC52xx) || defined(CONFIG_PPC_MPC512x)
> static const struct mpc_i2c_divider mpc_i2c_dividers_52xx[] = {
> {20, 0x20}, {22, 0x21}, {24, 0x22}, {26, 0x23},
> @@ -670,7 +748,10 @@ static int fsl_i2c_bus_recovery(struct i2c_adapter
> *adap)
> {
> struct mpc_i2c *i2c = i2c_get_adapdata(adap);
>
> - mpc_i2c_fixup(i2c);
> + if (i2c->has_errata_A004447)
> + mpc_i2c_fixup_A004447(i2c);
> + else
> + mpc_i2c_fixup(i2c);
>
> return 0;
> }
> @@ -767,6 +848,9 @@ static int fsl_i2c_probe(struct platform_device *op)
> }
> dev_info(i2c->dev, "timeout %u us\n", mpc_ops.timeout * 1000000 /
> HZ);
>
> + if (of_property_read_bool(op->dev.of_node,
> "fsl,i2c-erratum-a004447"))
> + i2c->has_errata_A004447 = true;
> +
> i2c->adap = mpc_ops;
> scnprintf(i2c->adap.name, sizeof(i2c->adap.name),
> "MPC adapter (%s)", of_node_full_name(op->dev.of_node));
> --
> 2.31.1
>
>
--
With Best Regards,
Andy Shevchenko
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^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH 3/3] i2c: mpc: implement erratum A-004447 workaround
2021-05-06 8:03 ` Andy Shevchenko
@ 2021-05-06 20:45 ` Chris Packham
0 siblings, 0 replies; 10+ messages in thread
From: Chris Packham @ 2021-05-06 20:45 UTC (permalink / raw)
To: Andy Shevchenko
Cc: devicetree, linux-kernel, wsa, robh+dt, linux-i2c,
andriy.shevchenko, linuxppc-dev
[-- Attachment #1: Type: text/plain, Size: 4981 bytes --]
On 6/05/21 8:03 pm, Andy Shevchenko wrote:
On Thursday, May 6, 2021, Chris Packham <chris.packham@alliedtelesis.co.nz<mailto:chris.packham@alliedtelesis.co.nz>> wrote:
The P2040/P2041 has an erratum where the normal i2c recovery mechanism
does not work. Implement the alternative recovery mechanism documented
in the P2040 Chip Errata Rev Q.
Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz<mailto:chris.packham@alliedtelesis.co.nz>>
---
drivers/i2c/busses/i2c-mpc.c | 88 +++++++++++++++++++++++++++++++++++-
1 file changed, 86 insertions(+), 2 deletions(-)
diff --git a/drivers/i2c/busses/i2c-mpc.c b/drivers/i2c/busses/i2c-mpc.c
index 30d9e89a3db2..052e37718771 100644
--- a/drivers/i2c/busses/i2c-mpc.c
+++ b/drivers/i2c/busses/i2c-mpc.c
@@ -45,6 +45,7 @@
#define CCR_MTX 0x10
#define CCR_TXAK 0x08
#define CCR_RSTA 0x04
+#define CCR_RSVD 0x02
#define CSR_MCF 0x80
#define CSR_MAAS 0x40
@@ -97,7 +98,7 @@ struct mpc_i2c {
u32 block;
int rc;
int expect_rxack;
-
+ bool has_errata_A004447;
};
struct mpc_i2c_divider {
@@ -136,6 +137,83 @@ static void mpc_i2c_fixup(struct mpc_i2c *i2c)
}
}
+static int i2c_mpc_wait_sr(struct mpc_i2c *i2c, int mask)
+{
+ unsigned long timeout = jiffies + usecs_to_jiffies(100);
+ int ret = 0;
+
+ while ((readb(i2c->base + MPC_I2C_SR) & mask) == 0) {
+ if (time_after(jiffies, timeout)) {
+ ret = -ETIMEDOUT;
+ break;
+ }
+ cond_resched();
+ }
+
+ return ret;
+}
readb_poll_timeout()
Thanks. I figured this existed I was just grepping for wait_.* and didn't find it. I'll prepare a v2 and get it out by the end of my day.
+
+/*
+ * Workaround for Erratum A004447. From the P2040CE Rev Q
+ *
+ * 1. Set up the frequency divider and sampling rate.
+ * 2. I2CCR - a0h
+ * 3. Poll for I2CSR[MBB] to get set.
+ * 4. If I2CSR[MAL] is set (an indication that SDA is stuck low), then go to
+ * step 5. If MAL is not set, then go to step 13.
+ * 5. I2CCR - 00h
+ * 6. I2CCR - 22h
+ * 7. I2CCR - a2h
+ * 8. Poll for I2CSR[MBB] to get set.
+ * 9. Issue read to I2CDR.
+ * 10. Poll for I2CSR[MIF] to be set.
+ * 11. I2CCR - 82h
+ * 12. Workaround complete. Skip the next steps.
+ * 13. Issue read to I2CDR.
+ * 14. Poll for I2CSR[MIF] to be set.
+ * 15. I2CCR - 80h
+ */
+static void mpc_i2c_fixup_A004447(struct mpc_i2c *i2c)
+{
+ int ret;
+ u32 val;
+
+ writeccr(i2c, CCR_MEN | CCR_MSTA);
+ ret = i2c_mpc_wait_sr(i2c, CSR_MBB);
+ if (ret) {
+ dev_err(i2c->dev, "timeout waiting for CSR_MBB\n");
+ return;
+ }
+
+ val = readb(i2c->base + MPC_I2C_SR);
+
+ if (val & CSR_MAL) {
+ writeccr(i2c, 0x00);
+ writeccr(i2c, CCR_MSTA | CCR_RSVD);
+ writeccr(i2c, CCR_MEN | CCR_MSTA | CCR_RSVD);
+ ret = i2c_mpc_wait_sr(i2c, CSR_MBB);
+ if (ret) {
+ dev_err(i2c->dev, "timeout waiting for CSR_MBB\n");
+ return;
+ }
+ val = readb(i2c->base + MPC_I2C_DR);
+ ret = i2c_mpc_wait_sr(i2c, CSR_MIF);
+ if (ret) {
+ dev_err(i2c->dev, "timeout waiting for CSR_MIF\n");
+ return;
+ }
+ writeccr(i2c, CCR_MEN | CCR_RSVD);
+ } else {
+ val = readb(i2c->base + MPC_I2C_DR);
+ ret = i2c_mpc_wait_sr(i2c, CSR_MIF);
+ if (ret) {
+ dev_err(i2c->dev, "timeout waiting for CSR_MIF\n");
+ return;
+ }
+ writeccr(i2c, CCR_MEN);
+ }
+}
+
#if defined(CONFIG_PPC_MPC52xx) || defined(CONFIG_PPC_MPC512x)
static const struct mpc_i2c_divider mpc_i2c_dividers_52xx[] = {
{20, 0x20}, {22, 0x21}, {24, 0x22}, {26, 0x23},
@@ -670,7 +748,10 @@ static int fsl_i2c_bus_recovery(struct i2c_adapter *adap)
{
struct mpc_i2c *i2c = i2c_get_adapdata(adap);
- mpc_i2c_fixup(i2c);
+ if (i2c->has_errata_A004447)
+ mpc_i2c_fixup_A004447(i2c);
+ else
+ mpc_i2c_fixup(i2c);
return 0;
}
@@ -767,6 +848,9 @@ static int fsl_i2c_probe(struct platform_device *op)
}
dev_info(i2c->dev, "timeout %u us\n", mpc_ops.timeout * 1000000 / HZ);
+ if (of_property_read_bool(op->dev.of_node, "fsl,i2c-erratum-a004447"))
+ i2c->has_errata_A004447 = true;
+
i2c->adap = mpc_ops;
scnprintf(i2c->adap.name<http://adap.name>, sizeof(i2c->adap.name<http://adap.name>),
"MPC adapter (%s)", of_node_full_name(op->dev.of_node));
--
2.31.1
--
With Best Regards,
Andy Shevchenko
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^ permalink raw reply related [flat|nested] 10+ messages in thread
end of thread, other threads:[~2021-05-06 21:54 UTC | newest]
Thread overview: 10+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-05-06 1:10 [PATCH 0/3] P2040/P2041 i2c recovery erratum Chris Packham
2021-05-06 1:10 ` Chris Packham
2021-05-06 1:10 ` [PATCH 1/3] dt-bindings: i2c: mpc: Add fsl,i2c-erratum-a004447 flag Chris Packham
2021-05-06 1:10 ` Chris Packham
2021-05-06 1:10 ` [PATCH 2/3] powerpc/fsl: set fsl,i2c-erratum-a004447 flag for P2041 i2c controllers Chris Packham
2021-05-06 1:10 ` [PATCH 2/3] powerpc/fsl: set fsl, i2c-erratum-a004447 " Chris Packham
2021-05-06 1:10 ` [PATCH 3/3] i2c: mpc: implement erratum A-004447 workaround Chris Packham
2021-05-06 1:10 ` Chris Packham
2021-05-06 8:03 ` Andy Shevchenko
2021-05-06 20:45 ` Chris Packham
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