* [U-Boot] [PATCH v3] serial: Add serial driver for Intel MID
@ 2017-02-28 12:04 Andy Shevchenko
2017-03-03 4:53 ` Simon Glass
2017-03-03 10:31 ` Kever Yang
0 siblings, 2 replies; 7+ messages in thread
From: Andy Shevchenko @ 2017-02-28 12:04 UTC (permalink / raw)
To: u-boot
Add a specific serial driver for Intel MID platforms.
It has special fractional divider which can be programmed via UART_PS,
UART_MUL, and UART_DIV registers.
The UART clock is calculated as
UART clock = XTAL * UART_MUL / UART_DIV
The baudrate is calculated as
baud rate = UART clock / UART_PS / DLAB
Initialize fractional divider correctly for Intel Edison platform.
For backward compatibility we have to set initial DLAB value to 16
and speed to 115200 baud, where initial frequency is 29491200Hz, and
XTAL frequency is 38.4MHz.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
---
drivers/serial/Kconfig | 9 +++++
drivers/serial/Makefile | 1 +
drivers/serial/serial_intel_mid.c | 69 +++++++++++++++++++++++++++++++++++++++
3 files changed, 79 insertions(+)
create mode 100644 drivers/serial/serial_intel_mid.c
diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
index b11f3ff89e..99dcdeb00d 100644
--- a/drivers/serial/Kconfig
+++ b/drivers/serial/Kconfig
@@ -347,6 +347,15 @@ config SYS_NS16550
be used. It can be a constant or a function to get clock, eg,
get_serial_clock().
+config INTEL_MID_SERIAL
+ bool "Intel MID platform UART support"
+ depends on DM_SERIAL && OF_CONTROL
+ depends on INTEL_MID
+ select SYS_NS16550
+ help
+ Select this to enable a UART for Intel MID platforms.
+ This uses the ns16550 driver as a library.
+
config ROCKCHIP_SERIAL
bool "Rockchip on-chip UART support"
depends on DM_SERIAL && SPL_OF_PLATDATA
diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile
index 8430668bf9..abd9dea4dc 100644
--- a/drivers/serial/Makefile
+++ b/drivers/serial/Makefile
@@ -28,6 +28,7 @@ obj-$(CONFIG_S5P) += serial_s5p.o
obj-$(CONFIG_MXC_UART) += serial_mxc.o
obj-$(CONFIG_PXA_SERIAL) += serial_pxa.o
obj-$(CONFIG_MESON_SERIAL) += serial_meson.o
+obj-$(CONFIG_INTEL_MID_SERIAL) += serial_intel_mid.o
ifdef CONFIG_SPL_BUILD
obj-$(CONFIG_ROCKCHIP_SERIAL) += serial_rockchip.o
endif
diff --git a/drivers/serial/serial_intel_mid.c b/drivers/serial/serial_intel_mid.c
new file mode 100644
index 0000000000..777c09d6d2
--- /dev/null
+++ b/drivers/serial/serial_intel_mid.c
@@ -0,0 +1,69 @@
+/*
+ * Copyright (c) 2017 Intel Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <ns16550.h>
+#include <serial.h>
+
+/*
+ * The UART clock is calculated as
+ *
+ * UART clock = XTAL * UART_MUL / UART_DIV
+ *
+ * The baudrate is calculated as
+ *
+ * baud rate = UART clock / UART_PS / DLAB
+ */
+#define UART_PS 0x30
+#define UART_MUL 0x34
+#define UART_DIV 0x38
+
+static void mid_writel(struct ns16550_platdata *plat, int offset, int value)
+{
+ unsigned char *addr;
+
+ offset *= 1 << plat->reg_shift;
+ addr = (unsigned char *)plat->base + offset;
+
+ writel(value, addr + plat->reg_offset);
+}
+
+static int mid_serial_probe(struct udevice *dev)
+{
+ struct ns16550_platdata *plat = dev_get_platdata(dev);
+
+ /*
+ * Initialize fractional divider correctly for Intel Edison
+ * platform.
+ *
+ * For backward compatibility we have to set initial DLAB value
+ * to 16 and speed to 115200 baud, where initial frequency is
+ * 29491200Hz, and XTAL frequency is 38.4MHz.
+ */
+ mid_writel(plat, UART_MUL, 96);
+ mid_writel(plat, UART_DIV, 125);
+ mid_writel(plat, UART_PS, 16);
+
+ return ns16550_serial_probe(dev);
+}
+
+static const struct udevice_id mid_serial_ids[] = {
+ { .compatible = "intel,mid-uart" },
+ {}
+};
+
+U_BOOT_DRIVER(serial_intel_mid) = {
+ .name = "serial_intel_mid",
+ .id = UCLASS_SERIAL,
+ .of_match = mid_serial_ids,
+ .ofdata_to_platdata = ns16550_serial_ofdata_to_platdata,
+ .platdata_auto_alloc_size = sizeof(struct ns16550_platdata),
+ .priv_auto_alloc_size = sizeof(struct NS16550),
+ .probe = mid_serial_probe,
+ .ops = &ns16550_serial_ops,
+ .flags = DM_FLAG_PRE_RELOC,
+};
--
2.11.0
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [U-Boot] [PATCH v3] serial: Add serial driver for Intel MID
2017-02-28 12:04 [U-Boot] [PATCH v3] serial: Add serial driver for Intel MID Andy Shevchenko
@ 2017-03-03 4:53 ` Simon Glass
2017-03-03 10:31 ` Kever Yang
1 sibling, 0 replies; 7+ messages in thread
From: Simon Glass @ 2017-03-03 4:53 UTC (permalink / raw)
To: u-boot
On 28 February 2017 at 05:04, Andy Shevchenko
<andriy.shevchenko@linux.intel.com> wrote:
> Add a specific serial driver for Intel MID platforms.
>
> It has special fractional divider which can be programmed via UART_PS,
> UART_MUL, and UART_DIV registers.
>
> The UART clock is calculated as
>
> UART clock = XTAL * UART_MUL / UART_DIV
>
> The baudrate is calculated as
>
> baud rate = UART clock / UART_PS / DLAB
>
> Initialize fractional divider correctly for Intel Edison platform.
>
> For backward compatibility we have to set initial DLAB value to 16
> and speed to 115200 baud, where initial frequency is 29491200Hz, and
> XTAL frequency is 38.4MHz.
>
> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
> ---
> drivers/serial/Kconfig | 9 +++++
> drivers/serial/Makefile | 1 +
> drivers/serial/serial_intel_mid.c | 69 +++++++++++++++++++++++++++++++++++++++
> 3 files changed, 79 insertions(+)
> create mode 100644 drivers/serial/serial_intel_mid.c
Reviewed-by: Simon Glass <sjg@chromium.org>
^ permalink raw reply [flat|nested] 7+ messages in thread
* [U-Boot] [PATCH v3] serial: Add serial driver for Intel MID
2017-02-28 12:04 [U-Boot] [PATCH v3] serial: Add serial driver for Intel MID Andy Shevchenko
2017-03-03 4:53 ` Simon Glass
@ 2017-03-03 10:31 ` Kever Yang
2017-03-13 14:09 ` Andy Shevchenko
1 sibling, 1 reply; 7+ messages in thread
From: Kever Yang @ 2017-03-03 10:31 UTC (permalink / raw)
To: u-boot
Hi Andy,
On 02/28/2017 08:04 PM, Andy Shevchenko wrote:
> Add a specific serial driver for Intel MID platforms.
>
> It has special fractional divider which can be programmed via UART_PS,
> UART_MUL, and UART_DIV registers.
>
> The UART clock is calculated as
>
> UART clock = XTAL * UART_MUL / UART_DIV
>
> The baudrate is calculated as
>
> baud rate = UART clock / UART_PS / DLAB
>
> Initialize fractional divider correctly for Intel Edison platform.
>
> For backward compatibility we have to set initial DLAB value to 16
> and speed to 115200 baud, where initial frequency is 29491200Hz, and
> XTAL frequency is 38.4MHz.
>
> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
> ---
> drivers/serial/Kconfig | 9 +++++
> drivers/serial/Makefile | 1 +
> drivers/serial/serial_intel_mid.c | 69 +++++++++++++++++++++++++++++++++++++++
> 3 files changed, 79 insertions(+)
> create mode 100644 drivers/serial/serial_intel_mid.c
>
> diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
> index b11f3ff89e..99dcdeb00d 100644
> --- a/drivers/serial/Kconfig
> +++ b/drivers/serial/Kconfig
> @@ -347,6 +347,15 @@ config SYS_NS16550
> be used. It can be a constant or a function to get clock, eg,
> get_serial_clock().
>
> +config INTEL_MID_SERIAL
> + bool "Intel MID platform UART support"
> + depends on DM_SERIAL && OF_CONTROL
> + depends on INTEL_MID
> + select SYS_NS16550
> + help
> + Select this to enable a UART for Intel MID platforms.
> + This uses the ns16550 driver as a library.
> +
> config ROCKCHIP_SERIAL
> bool "Rockchip on-chip UART support"
> depends on DM_SERIAL && SPL_OF_PLATDATA
> diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile
> index 8430668bf9..abd9dea4dc 100644
> --- a/drivers/serial/Makefile
> +++ b/drivers/serial/Makefile
> @@ -28,6 +28,7 @@ obj-$(CONFIG_S5P) += serial_s5p.o
> obj-$(CONFIG_MXC_UART) += serial_mxc.o
> obj-$(CONFIG_PXA_SERIAL) += serial_pxa.o
> obj-$(CONFIG_MESON_SERIAL) += serial_meson.o
> +obj-$(CONFIG_INTEL_MID_SERIAL) += serial_intel_mid.o
> ifdef CONFIG_SPL_BUILD
> obj-$(CONFIG_ROCKCHIP_SERIAL) += serial_rockchip.o
> endif
> diff --git a/drivers/serial/serial_intel_mid.c b/drivers/serial/serial_intel_mid.c
> new file mode 100644
> index 0000000000..777c09d6d2
> --- /dev/null
> +++ b/drivers/serial/serial_intel_mid.c
> @@ -0,0 +1,69 @@
> +/*
> + * Copyright (c) 2017 Intel Corporation
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + */
> +
> +#include <common.h>
> +#include <dm.h>
> +#include <ns16550.h>
> +#include <serial.h>
> +
> +/*
> + * The UART clock is calculated as
> + *
> + * UART clock = XTAL * UART_MUL / UART_DIV
> + *
> + * The baudrate is calculated as
> + *
> + * baud rate = UART clock / UART_PS / DLAB
> + */
> +#define UART_PS 0x30
> +#define UART_MUL 0x34
> +#define UART_DIV 0x38
> +
> +static void mid_writel(struct ns16550_platdata *plat, int offset, int value)
> +{
> + unsigned char *addr;
> +
> + offset *= 1 << plat->reg_shift;
> + addr = (unsigned char *)plat->base + offset;
> +
> + writel(value, addr + plat->reg_offset);
> +}
> +
> +static int mid_serial_probe(struct udevice *dev)
> +{
> + struct ns16550_platdata *plat = dev_get_platdata(dev);
> +
> + /*
> + * Initialize fractional divider correctly for Intel Edison
> + * platform.
> + *
> + * For backward compatibility we have to set initial DLAB value
> + * to 16 and speed to 115200 baud, where initial frequency is
> + * 29491200Hz, and XTAL frequency is 38.4MHz.
> + */
> + mid_writel(plat, UART_MUL, 96);
> + mid_writel(plat, UART_DIV, 125);
> + mid_writel(plat, UART_PS, 16);
> +
> + return ns16550_serial_probe(dev);
> +}
> +
> +static const struct udevice_id mid_serial_ids[] = {
> + { .compatible = "intel,mid-uart" },
> + {}
> +};
> +
> +U_BOOT_DRIVER(serial_intel_mid) = {
> + .name = "serial_intel_mid",
> + .id = UCLASS_SERIAL,
> + .of_match = mid_serial_ids,
> + .ofdata_to_platdata = ns16550_serial_ofdata_to_platdata,
> + .platdata_auto_alloc_size = sizeof(struct ns16550_platdata),
> + .priv_auto_alloc_size = sizeof(struct NS16550),
> + .probe = mid_serial_probe,
> + .ops = &ns16550_serial_ops,
> + .flags = DM_FLAG_PRE_RELOC,
> +};
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Thanks,
- Kever
^ permalink raw reply [flat|nested] 7+ messages in thread
* [U-Boot] [PATCH v3] serial: Add serial driver for Intel MID
2017-03-03 10:31 ` Kever Yang
@ 2017-03-13 14:09 ` Andy Shevchenko
2017-03-26 11:48 ` Andy Shevchenko
0 siblings, 1 reply; 7+ messages in thread
From: Andy Shevchenko @ 2017-03-13 14:09 UTC (permalink / raw)
To: u-boot
On Fri, Mar 3, 2017 at 12:31 PM, Kever Yang <kever.yang@rock-chips.com> wrote:
> On 02/28/2017 08:04 PM, Andy Shevchenko wrote:
>>
>> Add a specific serial driver for Intel MID platforms.
>>
>> It has special fractional divider which can be programmed via UART_PS,
>> UART_MUL, and UART_DIV registers.
>>
>> The UART clock is calculated as
>>
>> UART clock = XTAL * UART_MUL / UART_DIV
>>
>> The baudrate is calculated as
>>
>> baud rate = UART clock / UART_PS / DLAB
>>
>> Initialize fractional divider correctly for Intel Edison platform.
>>
>> For backward compatibility we have to set initial DLAB value to 16
>> and speed to 115200 baud, where initial frequency is 29491200Hz, and
>> XTAL frequency is 38.4MHz.
> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Thanks!
Tom et all, is it forgotten?
--
With Best Regards,
Andy Shevchenko
^ permalink raw reply [flat|nested] 7+ messages in thread
* [U-Boot] [PATCH v3] serial: Add serial driver for Intel MID
2017-03-13 14:09 ` Andy Shevchenko
@ 2017-03-26 11:48 ` Andy Shevchenko
2017-04-01 4:22 ` Simon Glass
0 siblings, 1 reply; 7+ messages in thread
From: Andy Shevchenko @ 2017-03-26 11:48 UTC (permalink / raw)
To: u-boot
On Mon, 2017-03-13 at 16:09 +0200, Andy Shevchenko wrote:
> On Fri, Mar 3, 2017 at 12:31 PM, Kever Yang <kever.yang@rock-chips.com
> > wrote:
> > On 02/28/2017 08:04 PM, Andy Shevchenko wrote:
> > >
> > > Add a specific serial driver for Intel MID platforms.
> > >
> > > It has special fractional divider which can be programmed via
> > > UART_PS,
> > > UART_MUL, and UART_DIV registers.
> > >
> > > The UART clock is calculated as
> > >
> > > UART clock = XTAL * UART_MUL / UART_DIV
> > >
> > > The baudrate is calculated as
> > >
> > > baud rate = UART clock / UART_PS / DLAB
> > >
> > > Initialize fractional divider correctly for Intel Edison platform.
> > >
> > > For backward compatibility we have to set initial DLAB value to 16
> > > and speed to 115200 baud, where initial frequency is 29491200Hz,
> > > and
> > > XTAL frequency is 38.4MHz.
> > Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
>
> Thanks!
>
> Tom et all, is it forgotten?
Any update on this? Should I do something about?
--
Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Intel Finland Oy
^ permalink raw reply [flat|nested] 7+ messages in thread
* [U-Boot] [PATCH v3] serial: Add serial driver for Intel MID
2017-03-26 11:48 ` Andy Shevchenko
@ 2017-04-01 4:22 ` Simon Glass
2017-04-10 2:01 ` Bin Meng
0 siblings, 1 reply; 7+ messages in thread
From: Simon Glass @ 2017-04-01 4:22 UTC (permalink / raw)
To: u-boot
+Bin
Hi,
On 26 March 2017 at 05:48, Andy Shevchenko
<andriy.shevchenko@linux.intel.com> wrote:
> On Mon, 2017-03-13 at 16:09 +0200, Andy Shevchenko wrote:
>> On Fri, Mar 3, 2017 at 12:31 PM, Kever Yang <kever.yang@rock-chips.com
>> > wrote:
>> > On 02/28/2017 08:04 PM, Andy Shevchenko wrote:
>> > >
>> > > Add a specific serial driver for Intel MID platforms.
>> > >
>> > > It has special fractional divider which can be programmed via
>> > > UART_PS,
>> > > UART_MUL, and UART_DIV registers.
>> > >
>> > > The UART clock is calculated as
>> > >
>> > > UART clock = XTAL * UART_MUL / UART_DIV
>> > >
>> > > The baudrate is calculated as
>> > >
>> > > baud rate = UART clock / UART_PS / DLAB
>> > >
>> > > Initialize fractional divider correctly for Intel Edison platform.
>> > >
>> > > For backward compatibility we have to set initial DLAB value to 16
>> > > and speed to 115200 baud, where initial frequency is 29491200Hz,
>> > > and
>> > > XTAL frequency is 38.4MHz.
>> > Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
>>
>> Thanks!
>>
>> Tom et all, is it forgotten?
>
> Any update on this? Should I do something about?
Probably Bin can apply it - it's a good idea to cc him on x86 stuff.
If not let me know and I can pull it in via DM.
Regards,
Simon
^ permalink raw reply [flat|nested] 7+ messages in thread
* [U-Boot] [PATCH v3] serial: Add serial driver for Intel MID
2017-04-01 4:22 ` Simon Glass
@ 2017-04-10 2:01 ` Bin Meng
0 siblings, 0 replies; 7+ messages in thread
From: Bin Meng @ 2017-04-10 2:01 UTC (permalink / raw)
To: u-boot
On Sat, Apr 1, 2017 at 12:22 PM, Simon Glass <sjg@chromium.org> wrote:
> +Bin
>
> Hi,
>
> On 26 March 2017 at 05:48, Andy Shevchenko
> <andriy.shevchenko@linux.intel.com> wrote:
>> On Mon, 2017-03-13 at 16:09 +0200, Andy Shevchenko wrote:
>>> On Fri, Mar 3, 2017 at 12:31 PM, Kever Yang <kever.yang@rock-chips.com
>>> > wrote:
>>> > On 02/28/2017 08:04 PM, Andy Shevchenko wrote:
>>> > >
>>> > > Add a specific serial driver for Intel MID platforms.
>>> > >
>>> > > It has special fractional divider which can be programmed via
>>> > > UART_PS,
>>> > > UART_MUL, and UART_DIV registers.
>>> > >
>>> > > The UART clock is calculated as
>>> > >
>>> > > UART clock = XTAL * UART_MUL / UART_DIV
>>> > >
>>> > > The baudrate is calculated as
>>> > >
>>> > > baud rate = UART clock / UART_PS / DLAB
>>> > >
>>> > > Initialize fractional divider correctly for Intel Edison platform.
>>> > >
>>> > > For backward compatibility we have to set initial DLAB value to 16
>>> > > and speed to 115200 baud, where initial frequency is 29491200Hz,
>>> > > and
>>> > > XTAL frequency is 38.4MHz.
>>> > Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
>>>
>>> Thanks!
>>>
>>> Tom et all, is it forgotten?
>>
>> Any update on this? Should I do something about?
>
> Probably Bin can apply it - it's a good idea to cc him on x86 stuff.
> If not let me know and I can pull it in via DM.
>
applied to u-boot-x86, thanks!
^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2017-04-10 2:01 UTC | newest]
Thread overview: 7+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2017-02-28 12:04 [U-Boot] [PATCH v3] serial: Add serial driver for Intel MID Andy Shevchenko
2017-03-03 4:53 ` Simon Glass
2017-03-03 10:31 ` Kever Yang
2017-03-13 14:09 ` Andy Shevchenko
2017-03-26 11:48 ` Andy Shevchenko
2017-04-01 4:22 ` Simon Glass
2017-04-10 2:01 ` Bin Meng
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