From: Zhi Li <lznuaa@gmail.com> To: David Laight <David.Laight@aculab.com> Cc: "fugang.duan@freescale.com" <fugang.duan@freescale.com>, "Frank.Li@freescale.com" <Frank.Li@freescale.com>, "davem@davemloft.net" <davem@davemloft.net>, "netdev@vger.kernel.org" <netdev@vger.kernel.org>, "shawn.guo@linaro.org" <shawn.guo@linaro.org>, "linux-arm-kernel@lists.infradead.org" <linux-arm-kernel@lists.infradead.org>, "devicetree@vger.kernel.org" <devicetree@vger.kernel.org> Subject: Re: [Patch net-next 08/11] net:fec: change FEC alignment to 64 bytes for ARM platform Date: Thu, 4 Sep 2014 09:17:20 -0500 [thread overview] Message-ID: <CAHrpEqQYUTL8ux9dwnzogihdVXhDs=W25nZthpjBAVzcEEzXUw@mail.gmail.com> (raw) In-Reply-To: <063D6719AE5E284EB5DD2968C1650D6D174872BE@AcuExch.aculab.com> On Thu, Sep 4, 2014 at 4:18 AM, David Laight <David.Laight@aculab.com> wrote: > From: fugang.duan@freescale.com >> >From: Frank Li >> >> From: Fugang Duan <B38611@freescale.com> >> >> >> >> Since enet-avb has 64 bytes alignment limitation for rx DMA transfer. >> >> The previous enet IP for ARM platform has 16 bytes alignment for tx >> >> DMA transfer. >> > >> >Do you mean rx or tx here? or both?? >> > >> >And can we beat up the hardware designers to stop these restrictions on rx >> >(in particular) ethernet buffer alignments? >> >A device isn't suitable for ethernet unless is can write the destination >> >mac address to a 4n+2 boundary. >> > >> > David >> > >> Hi, David, >> >> For previous enet IP there has 16 bytes data buffer alignment limitation for tx & rx DMA transfer. >> For imx6sx enet-avb IP, there has 64 bytes data buffer alignment limitation for rx DMA transfer, byte >> alignment for tx data >> Buffer for DMA transfer. >> >> I think rx data buffer alignment limitation don't introduce performance drop, is not complex for sw >> implemention. Anyway, >> We can request IC designer to remove the limitation for future chips. > > The 'problem' is that you need the IP header to be 32bit aligned. > If the dma buffer has to be aligned then the code either has to do an expensive > misaligned copy of the entire frame (at some point the entire frame is almost > certainly all copied into an aligned buffer), or take the hit of misaligned > memory accesses (which might have to be emulated with byte transfers). > > The rx buffer can be aligned provided the hardware skips (or writes junk to) > the first two bytes. ENET IP have feature to add additional 2 byte when save data to memory. RX FIFO Shift-16 When this field is set, the actual frame data starts at bit 16 of the first word read from the RX FIFO aligning the Ethernet payload on a 32-bit boundary. NOTE: This function only affects the FIFO storage and has no influence on the statistics, which use the actual length of the frame received. 0 Disabled. 1 Instructs the MAC to write two additional bytes in front of each frame received into the RX FIFO. i.MX6SX, Remove TX alignment requirement. But RX and DMA BD address is 64byte aligment. best regards Frank Li > > David > > >
WARNING: multiple messages have this Message-ID (diff)
From: lznuaa@gmail.com (Zhi Li) To: linux-arm-kernel@lists.infradead.org Subject: [Patch net-next 08/11] net:fec: change FEC alignment to 64 bytes for ARM platform Date: Thu, 4 Sep 2014 09:17:20 -0500 [thread overview] Message-ID: <CAHrpEqQYUTL8ux9dwnzogihdVXhDs=W25nZthpjBAVzcEEzXUw@mail.gmail.com> (raw) In-Reply-To: <063D6719AE5E284EB5DD2968C1650D6D174872BE@AcuExch.aculab.com> On Thu, Sep 4, 2014 at 4:18 AM, David Laight <David.Laight@aculab.com> wrote: > From: fugang.duan at freescale.com >> >From: Frank Li >> >> From: Fugang Duan <B38611@freescale.com> >> >> >> >> Since enet-avb has 64 bytes alignment limitation for rx DMA transfer. >> >> The previous enet IP for ARM platform has 16 bytes alignment for tx >> >> DMA transfer. >> > >> >Do you mean rx or tx here? or both?? >> > >> >And can we beat up the hardware designers to stop these restrictions on rx >> >(in particular) ethernet buffer alignments? >> >A device isn't suitable for ethernet unless is can write the destination >> >mac address to a 4n+2 boundary. >> > >> > David >> > >> Hi, David, >> >> For previous enet IP there has 16 bytes data buffer alignment limitation for tx & rx DMA transfer. >> For imx6sx enet-avb IP, there has 64 bytes data buffer alignment limitation for rx DMA transfer, byte >> alignment for tx data >> Buffer for DMA transfer. >> >> I think rx data buffer alignment limitation don't introduce performance drop, is not complex for sw >> implemention. Anyway, >> We can request IC designer to remove the limitation for future chips. > > The 'problem' is that you need the IP header to be 32bit aligned. > If the dma buffer has to be aligned then the code either has to do an expensive > misaligned copy of the entire frame (at some point the entire frame is almost > certainly all copied into an aligned buffer), or take the hit of misaligned > memory accesses (which might have to be emulated with byte transfers). > > The rx buffer can be aligned provided the hardware skips (or writes junk to) > the first two bytes. ENET IP have feature to add additional 2 byte when save data to memory. RX FIFO Shift-16 When this field is set, the actual frame data starts at bit 16 of the first word read from the RX FIFO aligning the Ethernet payload on a 32-bit boundary. NOTE: This function only affects the FIFO storage and has no influence on the statistics, which use the actual length of the frame received. 0 Disabled. 1 Instructs the MAC to write two additional bytes in front of each frame received into the RX FIFO. i.MX6SX, Remove TX alignment requirement. But RX and DMA BD address is 64byte aligment. best regards Frank Li > > David > > >
next prev parent reply other threads:[~2014-09-04 14:17 UTC|newest] Thread overview: 43+ messages / expand[flat|nested] mbox.gz Atom feed top 2014-09-03 20:38 [Patch net-next 00/11] net: fec: imx6sx multiqueue support Frank Li 2014-09-03 20:38 ` Frank Li 2014-09-03 20:38 ` [Patch net-next 03/11] net:fec: use multiqueue interface to allocate Ethernet device Frank Li 2014-09-03 20:38 ` Frank Li 2014-09-03 21:20 ` Florian Fainelli 2014-09-03 21:20 ` Florian Fainelli [not found] ` <1409776697-1536-1-git-send-email-Frank.Li-KZfg59tc24xl57MIdRCFDg@public.gmane.org> 2014-09-03 20:38 ` [Patch net-next 01/11] net:fec: add enet refrence clock for i.MX 6SX chip Frank Li 2014-09-03 20:38 ` Frank Li 2014-09-03 20:38 ` [Patch net-next 02/11] net:fec: add enet AVB feature macro define for imx6sx Frank Li 2014-09-03 20:38 ` Frank Li 2014-09-03 20:38 ` [Patch net-next 04/11] net:fec: add multiqueue support Frank Li 2014-09-03 20:38 ` Frank Li 2014-09-03 21:27 ` Florian Fainelli 2014-09-03 21:27 ` Florian Fainelli [not found] ` <540787B9.8090504-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> 2014-09-04 3:41 ` Zhi Li 2014-09-04 3:41 ` Zhi Li 2014-09-04 4:09 ` Florian Fainelli 2014-09-04 4:09 ` Florian Fainelli 2014-09-04 14:02 ` Zhi Li 2014-09-04 14:02 ` Zhi Li 2014-09-03 20:38 ` [Patch net-next 08/11] net:fec: change FEC alignment to 64 bytes for ARM platform Frank Li 2014-09-03 20:38 ` Frank Li 2014-09-04 8:50 ` David Laight 2014-09-04 9:11 ` fugang.duan at freescale.com 2014-09-04 9:18 ` David Laight 2014-09-04 14:17 ` Zhi Li [this message] 2014-09-04 14:17 ` Zhi Li 2014-09-03 20:38 ` [Patch net-next 09/11] net:fec: remove unnessary memory copy for address alignment in .xmit() Frank Li 2014-09-03 20:38 ` Frank Li 2014-09-03 20:38 ` [Patch net-next 10/11] ARM: Documentation: Update fec dts binding doc Frank Li 2014-09-03 20:38 ` Frank Li 2014-09-03 20:38 ` [Patch net-next 05/11] net:fec: Disable enet-avb MAC instead of reset MAC Frank Li 2014-09-03 20:38 ` Frank Li 2014-09-03 20:38 ` [Patch net-next 06/11] net:fec: add enet-avb IP support Frank Li 2014-09-03 20:38 ` Frank Li 2014-09-03 20:38 ` [Patch net-next 07/11] net:fec: Add fsl,imx6sx-fec compatible strings Frank Li 2014-09-03 20:38 ` Frank Li 2014-09-03 20:38 ` [Patch net-next 11/11] ARM: dts: imx6sx: add multi-queue support enet Frank Li 2014-09-03 20:38 ` Frank Li [not found] <1409776486-1403-1-git-send-email-y> 2014-09-03 20:34 ` [Patch net-next 08/11] net:fec: change FEC alignment to 64 bytes for ARM platform y 2014-09-03 20:34 ` y 2014-09-03 20:34 ` y 2014-09-03 20:34 ` y
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