* [PATCH 0/5] ARM: EXYNOS4: Add support new EXYNOS4212 SoC
@ 2011-08-24 13:25 ` Kukjin Kim
0 siblings, 0 replies; 20+ messages in thread
From: Kukjin Kim @ 2011-08-24 13:25 UTC (permalink / raw)
To: linux-arm-kernel, linux-samsung-soc; +Cc: ben-linux
This patch adds support new EXYNOS4212 SoC and SMDK4212 Board.
[PATCH 1/5] ARM: EXYNOS4: Add support new EXYNOS4212 SoC
[PATCH 2/5] ARM: EXYNOS4: Add support clock for EXYNOS4212
[PATCH 3/5] ARM: EXYNOS4: Add support PM for EXYNOS4212
[PATCH 4/5] ARM: EXYNOS4: Add support SMDK4212 Board
[PATCH 5/5] tty: Add support serial for EXYNOS4212 SoC
arch/arm/mach-exynos4/Kconfig | 30 ++
arch/arm/mach-exynos4/Makefile | 8 +-
arch/arm/mach-exynos4/clock-exynos4210.c | 139 ++++++++++
arch/arm/mach-exynos4/clock-exynos4212.c | 118 ++++++++
arch/arm/mach-exynos4/clock.c | 218 ++++++++++-----
arch/arm/mach-exynos4/cpu.c | 12 +-
arch/arm/mach-exynos4/include/mach/exynos4-clock.h | 43 +++
arch/arm/mach-exynos4/include/mach/regs-clock.h | 54 +++--
arch/arm/mach-exynos4/mach-smdk4212.c | 292 ++++++++++++++++++++
arch/arm/mach-exynos4/pm.c | 79 +-----
arch/arm/plat-s5p/cpu.c | 9 +
arch/arm/plat-s5p/include/plat/exynos4.h | 5 +-
arch/arm/plat-s5p/include/plat/pll.h | 55 ++++-
arch/arm/plat-samsung/include/plat/cpu.h | 8 +
drivers/tty/serial/Kconfig | 4 +-
15 files changed, 903 insertions(+), 171 deletions(-)
^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH 0/5] ARM: EXYNOS4: Add support new EXYNOS4212 SoC
@ 2011-08-24 13:25 ` Kukjin Kim
0 siblings, 0 replies; 20+ messages in thread
From: Kukjin Kim @ 2011-08-24 13:25 UTC (permalink / raw)
To: linux-arm-kernel
This patch adds support new EXYNOS4212 SoC and SMDK4212 Board.
[PATCH 1/5] ARM: EXYNOS4: Add support new EXYNOS4212 SoC
[PATCH 2/5] ARM: EXYNOS4: Add support clock for EXYNOS4212
[PATCH 3/5] ARM: EXYNOS4: Add support PM for EXYNOS4212
[PATCH 4/5] ARM: EXYNOS4: Add support SMDK4212 Board
[PATCH 5/5] tty: Add support serial for EXYNOS4212 SoC
arch/arm/mach-exynos4/Kconfig | 30 ++
arch/arm/mach-exynos4/Makefile | 8 +-
arch/arm/mach-exynos4/clock-exynos4210.c | 139 ++++++++++
arch/arm/mach-exynos4/clock-exynos4212.c | 118 ++++++++
arch/arm/mach-exynos4/clock.c | 218 ++++++++++-----
arch/arm/mach-exynos4/cpu.c | 12 +-
arch/arm/mach-exynos4/include/mach/exynos4-clock.h | 43 +++
arch/arm/mach-exynos4/include/mach/regs-clock.h | 54 +++--
arch/arm/mach-exynos4/mach-smdk4212.c | 292 ++++++++++++++++++++
arch/arm/mach-exynos4/pm.c | 79 +-----
arch/arm/plat-s5p/cpu.c | 9 +
arch/arm/plat-s5p/include/plat/exynos4.h | 5 +-
arch/arm/plat-s5p/include/plat/pll.h | 55 ++++-
arch/arm/plat-samsung/include/plat/cpu.h | 8 +
drivers/tty/serial/Kconfig | 4 +-
15 files changed, 903 insertions(+), 171 deletions(-)
^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH 1/5] ARM: EXYNOS4: Add support new EXYNOS4212 SoC
2011-08-24 13:25 ` Kukjin Kim
@ 2011-08-24 13:25 ` Kukjin Kim
-1 siblings, 0 replies; 20+ messages in thread
From: Kukjin Kim @ 2011-08-24 13:25 UTC (permalink / raw)
To: linux-arm-kernel, linux-samsung-soc; +Cc: ben-linux, Kukjin Kim
This patch adds Samsung EXYNOS4212 SoC support.
The EXYNOS4212 integrates a ARM Cortex A9 multi-core.
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
---
arch/arm/mach-exynos4/Kconfig | 5 +++++
arch/arm/mach-exynos4/Makefile | 6 ++++--
arch/arm/mach-exynos4/cpu.c | 6 +++++-
arch/arm/plat-s5p/cpu.c | 9 +++++++++
arch/arm/plat-s5p/include/plat/exynos4.h | 3 +--
arch/arm/plat-samsung/include/plat/cpu.h | 8 ++++++++
6 files changed, 32 insertions(+), 5 deletions(-)
diff --git a/arch/arm/mach-exynos4/Kconfig b/arch/arm/mach-exynos4/Kconfig
index bee8f77..0b40289 100644
--- a/arch/arm/mach-exynos4/Kconfig
+++ b/arch/arm/mach-exynos4/Kconfig
@@ -15,6 +15,11 @@ config CPU_EXYNOS4210
help
Enable EXYNOS4210 CPU support
+config SOC_EXYNOS4212
+ bool
+ help
+ Enable EXYNOS4212 SoC support
+
config EXYNOS4_MCT
bool
default y
diff --git a/arch/arm/mach-exynos4/Makefile b/arch/arm/mach-exynos4/Makefile
index e3e93ea..4624457 100644
--- a/arch/arm/mach-exynos4/Makefile
+++ b/arch/arm/mach-exynos4/Makefile
@@ -12,8 +12,10 @@ obj- :=
# Core support for EXYNOS4 system
-obj-$(CONFIG_CPU_EXYNOS4210) += cpu.o init.o clock.o irq-combiner.o
-obj-$(CONFIG_CPU_EXYNOS4210) += setup-i2c0.o irq-eint.o dma.o pmu.o
+obj-$(CONFIG_ARCH_EXYNOS4) += cpu.o init.o clock.o irq-combiner.o
+obj-$(CONFIG_ARCH_EXYNOS4) += setup-i2c0.o irq-eint.o dma.o pmu.o
+obj-$(CONFIG_CPU_EXYNOS4210) += clock-exynos4210.o
+obj-$(CONFIG_SOC_EXYNOS4212) += clock-exynos4212.o
obj-$(CONFIG_PM) += pm.o sleep.o
obj-$(CONFIG_CPU_IDLE) += cpuidle.o
diff --git a/arch/arm/mach-exynos4/cpu.c b/arch/arm/mach-exynos4/cpu.c
index 0d281bb..1e1a7a9 100644
--- a/arch/arm/mach-exynos4/cpu.c
+++ b/arch/arm/mach-exynos4/cpu.c
@@ -241,7 +241,11 @@ static int __init exynos4_l2x0_cache_init(void)
{
/* TAG, Data Latency Control: 2cycle */
__raw_writel(0x110, S5P_VA_L2CC + L2X0_TAG_LATENCY_CTRL);
- __raw_writel(0x110, S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL);
+
+ if (soc_is_exynos4210())
+ __raw_writel(0x110, S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL);
+ else if (soc_is_exynos4212())
+ __raw_writel(0x120, S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL);
/* L2X0 Prefetch Control */
__raw_writel(0x30000007, S5P_VA_L2CC + L2X0_PREFETCH_CTRL);
diff --git a/arch/arm/plat-s5p/cpu.c b/arch/arm/plat-s5p/cpu.c
index 04392c7..909507b 100644
--- a/arch/arm/plat-s5p/cpu.c
+++ b/arch/arm/plat-s5p/cpu.c
@@ -33,6 +33,7 @@ static const char name_s5p6450[] = "S5P6450";
static const char name_s5pc100[] = "S5PC100";
static const char name_s5pv210[] = "S5PV210/S5PC110";
static const char name_exynos4210[] = "EXYNOS4210";
+static const char name_exynos4212[] = "EXYNOS4212";
static struct cpu_table cpu_ids[] __initdata = {
{
@@ -75,6 +76,14 @@ static struct cpu_table cpu_ids[] __initdata = {
.init_uarts = exynos4_init_uarts,
.init = exynos4_init,
.name = name_exynos4210,
+ }, {
+ .idcode = EXYNOS4212_CPU_ID,
+ .idmask = EXYNOS4_CPU_MASK,
+ .map_io = exynos4_map_io,
+ .init_clocks = exynos4_init_clocks,
+ .init_uarts = exynos4_init_uarts,
+ .init = exynos4_init,
+ .name = name_exynos4212,
},
};
diff --git a/arch/arm/plat-s5p/include/plat/exynos4.h b/arch/arm/plat-s5p/include/plat/exynos4.h
index 907caab..4aed130 100644
--- a/arch/arm/plat-s5p/include/plat/exynos4.h
+++ b/arch/arm/plat-s5p/include/plat/exynos4.h
@@ -16,8 +16,7 @@ extern void exynos4_common_init_uarts(struct s3c2410_uartcfg *cfg, int no);
extern void exynos4_register_clocks(void);
extern void exynos4_setup_clocks(void);
-#ifdef CONFIG_CPU_EXYNOS4210
-
+#ifdef CONFIG_ARCH_EXYNOS4
extern int exynos4_init(void);
extern void exynos4_init_irq(void);
extern void exynos4_map_io(void);
diff --git a/arch/arm/plat-samsung/include/plat/cpu.h b/arch/arm/plat-samsung/include/plat/cpu.h
index 6fdd5ef..aa1f69b 100644
--- a/arch/arm/plat-samsung/include/plat/cpu.h
+++ b/arch/arm/plat-samsung/include/plat/cpu.h
@@ -39,6 +39,7 @@ extern unsigned long samsung_cpu_id;
#define S5PV210_CPU_MASK 0xFFFFF000
#define EXYNOS4210_CPU_ID 0x43210000
+#define EXYNOS4212_CPU_ID 0x43220000
#define EXYNOS4_CPU_MASK 0xFFFE0000
#define IS_SAMSUNG_CPU(name, id, mask) \
@@ -54,6 +55,7 @@ IS_SAMSUNG_CPU(s5p6450, S5P6450_CPU_ID, S5P64XX_CPU_MASK)
IS_SAMSUNG_CPU(s5pc100, S5PC100_CPU_ID, S5PC100_CPU_MASK)
IS_SAMSUNG_CPU(s5pv210, S5PV210_CPU_ID, S5PV210_CPU_MASK)
IS_SAMSUNG_CPU(exynos4210, EXYNOS4210_CPU_ID, EXYNOS4_CPU_MASK)
+IS_SAMSUNG_CPU(exynos4212, EXYNOS4212_CPU_ID, EXYNOS4_CPU_MASK)
#if defined(CONFIG_CPU_S3C2410) || defined(CONFIG_CPU_S3C2412) || \
defined(CONFIG_CPU_S3C2416) || defined(CONFIG_CPU_S3C2440) || \
@@ -100,6 +102,12 @@ IS_SAMSUNG_CPU(exynos4210, EXYNOS4210_CPU_ID, EXYNOS4_CPU_MASK)
# define soc_is_exynos4210() 0
#endif
+#if defined(CONFIG_SOC_EXYNOS4212)
+# define soc_is_exynos4212() is_samsung_exynos4212()
+#else
+# define soc_is_exynos4212() 0
+#endif
+
#define EXYNOS4210_REV_0 (0x0)
#define EXYNOS4210_REV_1_0 (0x10)
#define EXYNOS4210_REV_1_1 (0x11)
--
1.7.1
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH 1/5] ARM: EXYNOS4: Add support new EXYNOS4212 SoC
@ 2011-08-24 13:25 ` Kukjin Kim
0 siblings, 0 replies; 20+ messages in thread
From: Kukjin Kim @ 2011-08-24 13:25 UTC (permalink / raw)
To: linux-arm-kernel
This patch adds Samsung EXYNOS4212 SoC support.
The EXYNOS4212 integrates a ARM Cortex A9 multi-core.
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
---
arch/arm/mach-exynos4/Kconfig | 5 +++++
arch/arm/mach-exynos4/Makefile | 6 ++++--
arch/arm/mach-exynos4/cpu.c | 6 +++++-
arch/arm/plat-s5p/cpu.c | 9 +++++++++
arch/arm/plat-s5p/include/plat/exynos4.h | 3 +--
arch/arm/plat-samsung/include/plat/cpu.h | 8 ++++++++
6 files changed, 32 insertions(+), 5 deletions(-)
diff --git a/arch/arm/mach-exynos4/Kconfig b/arch/arm/mach-exynos4/Kconfig
index bee8f77..0b40289 100644
--- a/arch/arm/mach-exynos4/Kconfig
+++ b/arch/arm/mach-exynos4/Kconfig
@@ -15,6 +15,11 @@ config CPU_EXYNOS4210
help
Enable EXYNOS4210 CPU support
+config SOC_EXYNOS4212
+ bool
+ help
+ Enable EXYNOS4212 SoC support
+
config EXYNOS4_MCT
bool
default y
diff --git a/arch/arm/mach-exynos4/Makefile b/arch/arm/mach-exynos4/Makefile
index e3e93ea..4624457 100644
--- a/arch/arm/mach-exynos4/Makefile
+++ b/arch/arm/mach-exynos4/Makefile
@@ -12,8 +12,10 @@ obj- :=
# Core support for EXYNOS4 system
-obj-$(CONFIG_CPU_EXYNOS4210) += cpu.o init.o clock.o irq-combiner.o
-obj-$(CONFIG_CPU_EXYNOS4210) += setup-i2c0.o irq-eint.o dma.o pmu.o
+obj-$(CONFIG_ARCH_EXYNOS4) += cpu.o init.o clock.o irq-combiner.o
+obj-$(CONFIG_ARCH_EXYNOS4) += setup-i2c0.o irq-eint.o dma.o pmu.o
+obj-$(CONFIG_CPU_EXYNOS4210) += clock-exynos4210.o
+obj-$(CONFIG_SOC_EXYNOS4212) += clock-exynos4212.o
obj-$(CONFIG_PM) += pm.o sleep.o
obj-$(CONFIG_CPU_IDLE) += cpuidle.o
diff --git a/arch/arm/mach-exynos4/cpu.c b/arch/arm/mach-exynos4/cpu.c
index 0d281bb..1e1a7a9 100644
--- a/arch/arm/mach-exynos4/cpu.c
+++ b/arch/arm/mach-exynos4/cpu.c
@@ -241,7 +241,11 @@ static int __init exynos4_l2x0_cache_init(void)
{
/* TAG, Data Latency Control: 2cycle */
__raw_writel(0x110, S5P_VA_L2CC + L2X0_TAG_LATENCY_CTRL);
- __raw_writel(0x110, S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL);
+
+ if (soc_is_exynos4210())
+ __raw_writel(0x110, S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL);
+ else if (soc_is_exynos4212())
+ __raw_writel(0x120, S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL);
/* L2X0 Prefetch Control */
__raw_writel(0x30000007, S5P_VA_L2CC + L2X0_PREFETCH_CTRL);
diff --git a/arch/arm/plat-s5p/cpu.c b/arch/arm/plat-s5p/cpu.c
index 04392c7..909507b 100644
--- a/arch/arm/plat-s5p/cpu.c
+++ b/arch/arm/plat-s5p/cpu.c
@@ -33,6 +33,7 @@ static const char name_s5p6450[] = "S5P6450";
static const char name_s5pc100[] = "S5PC100";
static const char name_s5pv210[] = "S5PV210/S5PC110";
static const char name_exynos4210[] = "EXYNOS4210";
+static const char name_exynos4212[] = "EXYNOS4212";
static struct cpu_table cpu_ids[] __initdata = {
{
@@ -75,6 +76,14 @@ static struct cpu_table cpu_ids[] __initdata = {
.init_uarts = exynos4_init_uarts,
.init = exynos4_init,
.name = name_exynos4210,
+ }, {
+ .idcode = EXYNOS4212_CPU_ID,
+ .idmask = EXYNOS4_CPU_MASK,
+ .map_io = exynos4_map_io,
+ .init_clocks = exynos4_init_clocks,
+ .init_uarts = exynos4_init_uarts,
+ .init = exynos4_init,
+ .name = name_exynos4212,
},
};
diff --git a/arch/arm/plat-s5p/include/plat/exynos4.h b/arch/arm/plat-s5p/include/plat/exynos4.h
index 907caab..4aed130 100644
--- a/arch/arm/plat-s5p/include/plat/exynos4.h
+++ b/arch/arm/plat-s5p/include/plat/exynos4.h
@@ -16,8 +16,7 @@ extern void exynos4_common_init_uarts(struct s3c2410_uartcfg *cfg, int no);
extern void exynos4_register_clocks(void);
extern void exynos4_setup_clocks(void);
-#ifdef CONFIG_CPU_EXYNOS4210
-
+#ifdef CONFIG_ARCH_EXYNOS4
extern int exynos4_init(void);
extern void exynos4_init_irq(void);
extern void exynos4_map_io(void);
diff --git a/arch/arm/plat-samsung/include/plat/cpu.h b/arch/arm/plat-samsung/include/plat/cpu.h
index 6fdd5ef..aa1f69b 100644
--- a/arch/arm/plat-samsung/include/plat/cpu.h
+++ b/arch/arm/plat-samsung/include/plat/cpu.h
@@ -39,6 +39,7 @@ extern unsigned long samsung_cpu_id;
#define S5PV210_CPU_MASK 0xFFFFF000
#define EXYNOS4210_CPU_ID 0x43210000
+#define EXYNOS4212_CPU_ID 0x43220000
#define EXYNOS4_CPU_MASK 0xFFFE0000
#define IS_SAMSUNG_CPU(name, id, mask) \
@@ -54,6 +55,7 @@ IS_SAMSUNG_CPU(s5p6450, S5P6450_CPU_ID, S5P64XX_CPU_MASK)
IS_SAMSUNG_CPU(s5pc100, S5PC100_CPU_ID, S5PC100_CPU_MASK)
IS_SAMSUNG_CPU(s5pv210, S5PV210_CPU_ID, S5PV210_CPU_MASK)
IS_SAMSUNG_CPU(exynos4210, EXYNOS4210_CPU_ID, EXYNOS4_CPU_MASK)
+IS_SAMSUNG_CPU(exynos4212, EXYNOS4212_CPU_ID, EXYNOS4_CPU_MASK)
#if defined(CONFIG_CPU_S3C2410) || defined(CONFIG_CPU_S3C2412) || \
defined(CONFIG_CPU_S3C2416) || defined(CONFIG_CPU_S3C2440) || \
@@ -100,6 +102,12 @@ IS_SAMSUNG_CPU(exynos4210, EXYNOS4210_CPU_ID, EXYNOS4_CPU_MASK)
# define soc_is_exynos4210() 0
#endif
+#if defined(CONFIG_SOC_EXYNOS4212)
+# define soc_is_exynos4212() is_samsung_exynos4212()
+#else
+# define soc_is_exynos4212() 0
+#endif
+
#define EXYNOS4210_REV_0 (0x0)
#define EXYNOS4210_REV_1_0 (0x10)
#define EXYNOS4210_REV_1_1 (0x11)
--
1.7.1
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH 2/5] ARM: EXYNOS4: Add support clock for EXYNOS4212
2011-08-24 13:25 ` Kukjin Kim
@ 2011-08-24 13:25 ` Kukjin Kim
-1 siblings, 0 replies; 20+ messages in thread
From: Kukjin Kim @ 2011-08-24 13:25 UTC (permalink / raw)
To: linux-arm-kernel, linux-samsung-soc; +Cc: ben-linux, Kukjin Kim
This patch splits EXYNOS4 clock code to EXYNOS4 common,
EXYNOS4210 and EXYNOS4212 for supporting new EXYNOS4212
SoC with one kernel image. Of course, this patch adds
some clock codes for EXYNOS4212 SoC.
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
---
arch/arm/mach-exynos4/clock-exynos4210.c | 101 ++++++++++++++++
arch/arm/mach-exynos4/clock-exynos4212.c | 84 +++++++++++++
arch/arm/mach-exynos4/clock.c | 127 +++++++++-----------
arch/arm/mach-exynos4/cpu.c | 6 +
arch/arm/mach-exynos4/include/mach/exynos4-clock.h | 43 +++++++
arch/arm/mach-exynos4/include/mach/regs-clock.h | 50 +++++---
arch/arm/plat-s5p/include/plat/exynos4.h | 2 +
arch/arm/plat-s5p/include/plat/pll.h | 55 ++++++++-
8 files changed, 377 insertions(+), 91 deletions(-)
create mode 100644 arch/arm/mach-exynos4/clock-exynos4210.c
create mode 100644 arch/arm/mach-exynos4/clock-exynos4212.c
create mode 100644 arch/arm/mach-exynos4/include/mach/exynos4-clock.h
diff --git a/arch/arm/mach-exynos4/clock-exynos4210.c b/arch/arm/mach-exynos4/clock-exynos4210.c
new file mode 100644
index 0000000..fe74b91
--- /dev/null
+++ b/arch/arm/mach-exynos4/clock-exynos4210.c
@@ -0,0 +1,101 @@
+/*
+ * linux/arch/arm/mach-exynos4/clock-exynos4210.c
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * EXYNOS4210 - Clock support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/kernel.h>
+#include <linux/err.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+
+#include <plat/cpu-freq.h>
+#include <plat/clock.h>
+#include <plat/cpu.h>
+#include <plat/pll.h>
+#include <plat/s5p-clock.h>
+#include <plat/clock-clksrc.h>
+#include <plat/exynos4.h>
+
+#include <mach/hardware.h>
+#include <mach/map.h>
+#include <mach/regs-clock.h>
+#include <mach/exynos4-clock.h>
+
+static struct clksrc_clk *sysclks[] = {
+ /* nothing here yet */
+};
+
+static int exynos4_clksrc_mask_lcd1_ctrl(struct clk *clk, int enable)
+{
+ return s5p_gatectrl(S5P_CLKSRC_MASK_LCD1, clk, enable);
+}
+
+static struct clksrc_clk clksrcs[] = {
+ {
+ .clk = {
+ .name = "sclk_sata",
+ .id = -1,
+ .enable = exynos4_clksrc_mask_fsys_ctrl,
+ .ctrlbit = (1 << 24),
+ },
+ .sources = &clkset_mout_corebus,
+ .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 24, .size = 1 },
+ .reg_div = { .reg = S5P_CLKDIV_FSYS0, .shift = 20, .size = 4 },
+ }, {
+ .clk = {
+ .name = "sclk_fimd",
+ .devname = "exynos4-fb.1",
+ .enable = exynos4_clksrc_mask_lcd1_ctrl,
+ .ctrlbit = (1 << 0),
+ },
+ .sources = &clkset_group,
+ .reg_src = { .reg = S5P_CLKSRC_LCD1, .shift = 0, .size = 4 },
+ .reg_div = { .reg = S5P_CLKDIV_LCD1, .shift = 0, .size = 4 },
+ },
+};
+
+static struct clk init_clocks_off[] = {
+ {
+ .name = "sataphy",
+ .id = -1,
+ .parent = &clk_aclk_133.clk,
+ .enable = exynos4_clk_ip_fsys_ctrl,
+ .ctrlbit = (1 << 3),
+ }, {
+ .name = "sata",
+ .id = -1,
+ .parent = &clk_aclk_133.clk,
+ .enable = exynos4_clk_ip_fsys_ctrl,
+ .ctrlbit = (1 << 10),
+ }, {
+ .name = "fimd",
+ .devname = "exynos4-fb.1",
+ .enable = exynos4_clk_ip_lcd1_ctrl,
+ .ctrlbit = (1 << 0),
+ },
+};
+
+void __init exynos4210_register_clocks(void)
+{
+ int ptr;
+
+ clk_mout_mpll.reg_src.reg = S5P_CLKSRC_CPU;
+ clk_mout_mpll.reg_src.shift = 8;
+ clk_mout_mpll.reg_src.size = 1;
+
+ for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
+ s3c_register_clksrc(sysclks[ptr], 1);
+
+ s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
+
+ s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
+ s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
+}
diff --git a/arch/arm/mach-exynos4/clock-exynos4212.c b/arch/arm/mach-exynos4/clock-exynos4212.c
new file mode 100644
index 0000000..5a47a3f
--- /dev/null
+++ b/arch/arm/mach-exynos4/clock-exynos4212.c
@@ -0,0 +1,84 @@
+/*
+ * linux/arch/arm/mach-exynos4/clock-exynos4212.c
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * EXYNOS4212 - Clock support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/kernel.h>
+#include <linux/err.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+
+#include <plat/cpu-freq.h>
+#include <plat/clock.h>
+#include <plat/cpu.h>
+#include <plat/pll.h>
+#include <plat/s5p-clock.h>
+#include <plat/clock-clksrc.h>
+#include <plat/exynos4.h>
+
+#include <mach/hardware.h>
+#include <mach/map.h>
+#include <mach/regs-clock.h>
+#include <mach/exynos4-clock.h>
+
+static struct clk *clk_src_mpll_user_list[] = {
+ [0] = &clk_fin_mpll,
+ [1] = &clk_mout_mpll.clk,
+};
+
+static struct clksrc_sources clk_src_mpll_user = {
+ .sources = clk_src_mpll_user_list,
+ .nr_sources = ARRAY_SIZE(clk_src_mpll_user_list),
+};
+
+static struct clksrc_clk clk_mout_mpll_user = {
+ .clk = {
+ .name = "mout_mpll_user",
+ },
+ .sources = &clk_src_mpll_user,
+ .reg_src = { .reg = S5P_CLKSRC_CPU, .shift = 24, .size = 1 },
+};
+
+static struct clksrc_clk *sysclks[] = {
+ &clk_mout_mpll_user,
+};
+
+static struct clksrc_clk clksrcs[] = {
+ /* nothing here yet */
+};
+
+static struct clk init_clocks_off[] = {
+ /* nothing here yet */
+};
+
+void __init exynos4212_register_clocks(void)
+{
+ int ptr;
+
+ /* usbphy1 is removed */
+ clkset_group_list[4] = NULL;
+
+ /* mout_mpll_user is used */
+ clkset_group_list[6] = &clk_mout_mpll_user.clk;
+ clkset_aclk_top_list[0] = &clk_mout_mpll_user.clk;
+
+ clk_mout_mpll.reg_src.reg = S5P_CLKSRC_DMC;
+ clk_mout_mpll.reg_src.shift = 12;
+ clk_mout_mpll.reg_src.size = 1;
+
+ for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
+ s3c_register_clksrc(sysclks[ptr], 1);
+
+ s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
+
+ s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
+ s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
+}
diff --git a/arch/arm/mach-exynos4/clock.c b/arch/arm/mach-exynos4/clock.c
index 79d6cd0..eb99467 100644
--- a/arch/arm/mach-exynos4/clock.c
+++ b/arch/arm/mach-exynos4/clock.c
@@ -20,26 +20,28 @@
#include <plat/pll.h>
#include <plat/s5p-clock.h>
#include <plat/clock-clksrc.h>
+#include <plat/exynos4.h>
#include <mach/map.h>
#include <mach/regs-clock.h>
#include <mach/sysmmu.h>
+#include <mach/exynos4-clock.h>
-static struct clk clk_sclk_hdmi27m = {
+struct clk clk_sclk_hdmi27m = {
.name = "sclk_hdmi27m",
.rate = 27000000,
};
-static struct clk clk_sclk_hdmiphy = {
+struct clk clk_sclk_hdmiphy = {
.name = "sclk_hdmiphy",
};
-static struct clk clk_sclk_usbphy0 = {
+struct clk clk_sclk_usbphy0 = {
.name = "sclk_usbphy0",
.rate = 27000000,
};
-static struct clk clk_sclk_usbphy1 = {
+struct clk clk_sclk_usbphy1 = {
.name = "sclk_usbphy1",
};
@@ -58,12 +60,7 @@ static int exynos4_clksrc_mask_lcd0_ctrl(struct clk *clk, int enable)
return s5p_gatectrl(S5P_CLKSRC_MASK_LCD0, clk, enable);
}
-static int exynos4_clksrc_mask_lcd1_ctrl(struct clk *clk, int enable)
-{
- return s5p_gatectrl(S5P_CLKSRC_MASK_LCD1, clk, enable);
-}
-
-static int exynos4_clksrc_mask_fsys_ctrl(struct clk *clk, int enable)
+int exynos4_clksrc_mask_fsys_ctrl(struct clk *clk, int enable)
{
return s5p_gatectrl(S5P_CLKSRC_MASK_FSYS, clk, enable);
}
@@ -103,12 +100,12 @@ static int exynos4_clk_ip_lcd0_ctrl(struct clk *clk, int enable)
return s5p_gatectrl(S5P_CLKGATE_IP_LCD0, clk, enable);
}
-static int exynos4_clk_ip_lcd1_ctrl(struct clk *clk, int enable)
+int exynos4_clk_ip_lcd1_ctrl(struct clk *clk, int enable)
{
return s5p_gatectrl(S5P_CLKGATE_IP_LCD1, clk, enable);
}
-static int exynos4_clk_ip_fsys_ctrl(struct clk *clk, int enable)
+int exynos4_clk_ip_fsys_ctrl(struct clk *clk, int enable)
{
return s5p_gatectrl(S5P_CLKGATE_IP_FSYS, clk, enable);
}
@@ -133,7 +130,7 @@ static struct clksrc_clk clk_mout_apll = {
.reg_src = { .reg = S5P_CLKSRC_CPU, .shift = 0, .size = 1 },
};
-static struct clksrc_clk clk_sclk_apll = {
+struct clksrc_clk clk_sclk_apll = {
.clk = {
.name = "sclk_apll",
.parent = &clk_mout_apll.clk,
@@ -141,7 +138,7 @@ static struct clksrc_clk clk_sclk_apll = {
.reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 24, .size = 3 },
};
-static struct clksrc_clk clk_mout_epll = {
+struct clksrc_clk clk_mout_epll = {
.clk = {
.name = "mout_epll",
},
@@ -149,12 +146,13 @@ static struct clksrc_clk clk_mout_epll = {
.reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 4, .size = 1 },
};
-static struct clksrc_clk clk_mout_mpll = {
+struct clksrc_clk clk_mout_mpll = {
.clk = {
.name = "mout_mpll",
},
.sources = &clk_src_mpll,
- .reg_src = { .reg = S5P_CLKSRC_CPU, .shift = 8, .size = 1 },
+
+ /* reg_src will be added in each SoCs' clock */
};
static struct clk *clkset_moutcore_list[] = {
@@ -224,12 +222,12 @@ static struct clksrc_clk clk_periphclk = {
/* Core list of CMU_CORE side */
-static struct clk *clkset_corebus_list[] = {
+struct clk *clkset_corebus_list[] = {
[0] = &clk_mout_mpll.clk,
[1] = &clk_sclk_apll.clk,
};
-static struct clksrc_sources clkset_mout_corebus = {
+struct clksrc_sources clkset_mout_corebus = {
.sources = clkset_corebus_list,
.nr_sources = ARRAY_SIZE(clkset_corebus_list),
};
@@ -284,12 +282,12 @@ static struct clksrc_clk clk_pclk_acp = {
/* Core list of CMU_TOP side */
-static struct clk *clkset_aclk_top_list[] = {
+struct clk *clkset_aclk_top_list[] = {
[0] = &clk_mout_mpll.clk,
[1] = &clk_sclk_apll.clk,
};
-static struct clksrc_sources clkset_aclk = {
+struct clksrc_sources clkset_aclk = {
.sources = clkset_aclk_top_list,
.nr_sources = ARRAY_SIZE(clkset_aclk_top_list),
};
@@ -321,7 +319,7 @@ static struct clksrc_clk clk_aclk_160 = {
.reg_div = { .reg = S5P_CLKDIV_TOP, .shift = 8, .size = 3 },
};
-static struct clksrc_clk clk_aclk_133 = {
+struct clksrc_clk clk_aclk_133 = {
.clk = {
.name = "aclk_133",
},
@@ -360,7 +358,7 @@ static struct clksrc_sources clkset_sclk_vpll = {
.nr_sources = ARRAY_SIZE(clkset_sclk_vpll_list),
};
-static struct clksrc_clk clk_sclk_vpll = {
+struct clksrc_clk clk_sclk_vpll = {
.clk = {
.name = "sclk_vpll",
},
@@ -410,16 +408,6 @@ static struct clk init_clocks_off[] = {
.enable = exynos4_clk_ip_lcd0_ctrl,
.ctrlbit = (1 << 0),
}, {
- .name = "fimd",
- .devname = "exynos4-fb.1",
- .enable = exynos4_clk_ip_lcd1_ctrl,
- .ctrlbit = (1 << 0),
- }, {
- .name = "sataphy",
- .parent = &clk_aclk_133.clk,
- .enable = exynos4_clk_ip_fsys_ctrl,
- .ctrlbit = (1 << 3),
- }, {
.name = "hsmmc",
.devname = "s3c-sdhci.0",
.parent = &clk_aclk_133.clk,
@@ -449,11 +437,6 @@ static struct clk init_clocks_off[] = {
.enable = exynos4_clk_ip_fsys_ctrl,
.ctrlbit = (1 << 9),
}, {
- .name = "sata",
- .parent = &clk_aclk_133.clk,
- .enable = exynos4_clk_ip_fsys_ctrl,
- .ctrlbit = (1 << 10),
- }, {
.name = "pdma",
.devname = "s3c-pl330.0",
.enable = exynos4_clk_ip_fsys_ctrl,
@@ -673,7 +656,7 @@ static struct clk init_clocks[] = {
}
};
-static struct clk *clkset_group_list[] = {
+struct clk *clkset_group_list[] = {
[0] = &clk_ext_xtal_mux,
[1] = &clk_xusbxti,
[2] = &clk_sclk_hdmi27m,
@@ -685,7 +668,7 @@ static struct clk *clkset_group_list[] = {
[8] = &clk_sclk_vpll.clk,
};
-static struct clksrc_sources clkset_group = {
+struct clksrc_sources clkset_group = {
.sources = clkset_group_list,
.nr_sources = ARRAY_SIZE(clkset_group_list),
};
@@ -969,25 +952,6 @@ static struct clksrc_clk clksrcs[] = {
.reg_div = { .reg = S5P_CLKDIV_LCD0, .shift = 0, .size = 4 },
}, {
.clk = {
- .name = "sclk_fimd",
- .devname = "exynos4-fb.1",
- .enable = exynos4_clksrc_mask_lcd1_ctrl,
- .ctrlbit = (1 << 0),
- },
- .sources = &clkset_group,
- .reg_src = { .reg = S5P_CLKSRC_LCD1, .shift = 0, .size = 4 },
- .reg_div = { .reg = S5P_CLKDIV_LCD1, .shift = 0, .size = 4 },
- }, {
- .clk = {
- .name = "sclk_sata",
- .enable = exynos4_clksrc_mask_fsys_ctrl,
- .ctrlbit = (1 << 24),
- },
- .sources = &clkset_mout_corebus,
- .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 24, .size = 1 },
- .reg_div = { .reg = S5P_CLKDIV_FSYS0, .shift = 20, .size = 4 },
- }, {
- .clk = {
.name = "sclk_spi",
.devname = "s3c64xx-spi.0",
.enable = exynos4_clksrc_mask_peril1_ctrl,
@@ -1116,7 +1080,13 @@ static int xtal_rate;
static unsigned long exynos4_fout_apll_get_rate(struct clk *clk)
{
- return s5p_get_pll45xx(xtal_rate, __raw_readl(S5P_APLL_CON0), pll_4508);
+ if (soc_is_exynos4210())
+ return s5p_get_pll45xx(xtal_rate, __raw_readl(S5P_APLL_CON0),
+ pll_4508);
+ else if (soc_is_exynos4212())
+ return s5p_get_pll35xx(xtal_rate, __raw_readl(S5P_APLL_CON0));
+ else
+ return 0;
}
static struct clk_ops exynos4_fout_apll_ops = {
@@ -1126,10 +1096,10 @@ static struct clk_ops exynos4_fout_apll_ops = {
void __init_or_cpufreq exynos4_setup_clocks(void)
{
struct clk *xtal_clk;
- unsigned long apll;
- unsigned long mpll;
- unsigned long epll;
- unsigned long vpll;
+ unsigned long apll = 0;
+ unsigned long mpll = 0;
+ unsigned long epll = 0;
+ unsigned long vpll = 0;
unsigned long vpllsrc;
unsigned long xtal;
unsigned long armclk;
@@ -1153,14 +1123,29 @@ void __init_or_cpufreq exynos4_setup_clocks(void)
printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
- apll = s5p_get_pll45xx(xtal, __raw_readl(S5P_APLL_CON0), pll_4508);
- mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P_MPLL_CON0), pll_4508);
- epll = s5p_get_pll46xx(xtal, __raw_readl(S5P_EPLL_CON0),
- __raw_readl(S5P_EPLL_CON1), pll_4600);
-
- vpllsrc = clk_get_rate(&clk_vpllsrc.clk);
- vpll = s5p_get_pll46xx(vpllsrc, __raw_readl(S5P_VPLL_CON0),
- __raw_readl(S5P_VPLL_CON1), pll_4650c);
+ if (soc_is_exynos4210()) {
+ apll = s5p_get_pll45xx(xtal, __raw_readl(S5P_APLL_CON0),
+ pll_4508);
+ mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P_MPLL_CON0),
+ pll_4508);
+ epll = s5p_get_pll46xx(xtal, __raw_readl(S5P_EPLL_CON0),
+ __raw_readl(S5P_EPLL_CON1), pll_4600);
+
+ vpllsrc = clk_get_rate(&clk_vpllsrc.clk);
+ vpll = s5p_get_pll46xx(vpllsrc, __raw_readl(S5P_VPLL_CON0),
+ __raw_readl(S5P_VPLL_CON1), pll_4650c);
+ } else if (soc_is_exynos4212()) {
+ apll = s5p_get_pll35xx(xtal, __raw_readl(S5P_APLL_CON0));
+ mpll = s5p_get_pll35xx(xtal, __raw_readl(S5P_MPLL_CON0));
+ epll = s5p_get_pll36xx(xtal, __raw_readl(S5P_EPLL_CON0),
+ __raw_readl(S5P_EPLL_CON1));
+
+ vpllsrc = clk_get_rate(&clk_vpllsrc.clk);
+ vpll = s5p_get_pll36xx(vpllsrc, __raw_readl(S5P_VPLL_CON0),
+ __raw_readl(S5P_VPLL_CON1));
+ } else {
+ /* nothing */
+ }
clk_fout_apll.ops = &exynos4_fout_apll_ops;
clk_fout_mpll.rate = mpll;
diff --git a/arch/arm/mach-exynos4/cpu.c b/arch/arm/mach-exynos4/cpu.c
index 1e1a7a9..02ec52a 100644
--- a/arch/arm/mach-exynos4/cpu.c
+++ b/arch/arm/mach-exynos4/cpu.c
@@ -188,6 +188,12 @@ void __init exynos4_init_clocks(int xtal)
s3c24xx_register_baseclocks(xtal);
s5p_register_clocks(xtal);
+
+ if (soc_is_exynos4210())
+ exynos4210_register_clocks();
+ else if (soc_is_exynos4212())
+ exynos4212_register_clocks();
+
exynos4_register_clocks();
exynos4_setup_clocks();
}
diff --git a/arch/arm/mach-exynos4/include/mach/exynos4-clock.h b/arch/arm/mach-exynos4/include/mach/exynos4-clock.h
new file mode 100644
index 0000000..a07fcbf
--- /dev/null
+++ b/arch/arm/mach-exynos4/include/mach/exynos4-clock.h
@@ -0,0 +1,43 @@
+/*
+ * linux/arch/arm/mach-exynos4/include/mach/exynos4-clock.h
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * Header file for exynos4 clock support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_CLOCK_H
+#define __ASM_ARCH_CLOCK_H __FILE__
+
+#include <linux/clk.h>
+
+extern struct clk clk_sclk_hdmi27m;
+extern struct clk clk_sclk_usbphy0;
+extern struct clk clk_sclk_usbphy1;
+extern struct clk clk_sclk_hdmiphy;
+
+extern struct clksrc_clk clk_sclk_apll;
+extern struct clksrc_clk clk_mout_mpll;
+extern struct clksrc_clk clk_aclk_133;
+extern struct clksrc_clk clk_mout_epll;
+extern struct clksrc_clk clk_sclk_vpll;
+
+extern struct clk *clkset_corebus_list[];
+extern struct clksrc_sources clkset_mout_corebus;
+
+extern struct clk *clkset_aclk_top_list[];
+extern struct clksrc_sources clkset_aclk;
+
+extern struct clk *clkset_group_list[];
+extern struct clksrc_sources clkset_group;
+
+extern int exynos4_clksrc_mask_fsys_ctrl(struct clk *clk, int enable);
+extern int exynos4_clk_ip_fsys_ctrl(struct clk *clk, int enable);
+extern int exynos4_clk_ip_lcd1_ctrl(struct clk *clk, int enable);
+
+#endif /* __ASM_ARCH_CLOCK_H */
diff --git a/arch/arm/mach-exynos4/include/mach/regs-clock.h b/arch/arm/mach-exynos4/include/mach/regs-clock.h
index d493fdb..e75d0f8 100644
--- a/arch/arm/mach-exynos4/include/mach/regs-clock.h
+++ b/arch/arm/mach-exynos4/include/mach/regs-clock.h
@@ -13,6 +13,7 @@
#ifndef __ASM_ARCH_REGS_CLOCK_H
#define __ASM_ARCH_REGS_CLOCK_H __FILE__
+#include <plat/cpu.h>
#include <mach/map.h>
#define S5P_CLKREG(x) (S5P_VA_CMU + (x))
@@ -41,12 +42,20 @@
#define S5P_CLKSRC_G3D S5P_CLKREG(0x0C22C)
#define S5P_CLKSRC_IMAGE S5P_CLKREG(0x0C230)
#define S5P_CLKSRC_LCD0 S5P_CLKREG(0x0C234)
-#define S5P_CLKSRC_LCD1 S5P_CLKREG(0x0C238)
#define S5P_CLKSRC_MAUDIO S5P_CLKREG(0x0C23C)
#define S5P_CLKSRC_FSYS S5P_CLKREG(0x0C240)
#define S5P_CLKSRC_PERIL0 S5P_CLKREG(0x0C250)
#define S5P_CLKSRC_PERIL1 S5P_CLKREG(0x0C254)
+#define S5P_CLKSRC_MASK_TOP S5P_CLKREG(0x0C310)
+#define S5P_CLKSRC_MASK_CAM S5P_CLKREG(0x0C320)
+#define S5P_CLKSRC_MASK_TV S5P_CLKREG(0x0C324)
+#define S5P_CLKSRC_MASK_LCD0 S5P_CLKREG(0x0C334)
+#define S5P_CLKSRC_MASK_MAUDIO S5P_CLKREG(0x0C33C)
+#define S5P_CLKSRC_MASK_FSYS S5P_CLKREG(0x0C340)
+#define S5P_CLKSRC_MASK_PERIL0 S5P_CLKREG(0x0C350)
+#define S5P_CLKSRC_MASK_PERIL1 S5P_CLKREG(0x0C354)
+
#define S5P_CLKDIV_TOP S5P_CLKREG(0x0C510)
#define S5P_CLKDIV_CAM S5P_CLKREG(0x0C520)
#define S5P_CLKDIV_TV S5P_CLKREG(0x0C524)
@@ -54,7 +63,6 @@
#define S5P_CLKDIV_G3D S5P_CLKREG(0x0C52C)
#define S5P_CLKDIV_IMAGE S5P_CLKREG(0x0C530)
#define S5P_CLKDIV_LCD0 S5P_CLKREG(0x0C534)
-#define S5P_CLKDIV_LCD1 S5P_CLKREG(0x0C538)
#define S5P_CLKDIV_MAUDIO S5P_CLKREG(0x0C53C)
#define S5P_CLKDIV_FSYS0 S5P_CLKREG(0x0C540)
#define S5P_CLKDIV_FSYS1 S5P_CLKREG(0x0C544)
@@ -68,16 +76,6 @@
#define S5P_CLKDIV_PERIL5 S5P_CLKREG(0x0C564)
#define S5P_CLKDIV2_RATIO S5P_CLKREG(0x0C580)
-#define S5P_CLKSRC_MASK_TOP S5P_CLKREG(0x0C310)
-#define S5P_CLKSRC_MASK_CAM S5P_CLKREG(0x0C320)
-#define S5P_CLKSRC_MASK_TV S5P_CLKREG(0x0C324)
-#define S5P_CLKSRC_MASK_LCD0 S5P_CLKREG(0x0C334)
-#define S5P_CLKSRC_MASK_LCD1 S5P_CLKREG(0x0C338)
-#define S5P_CLKSRC_MASK_MAUDIO S5P_CLKREG(0x0C33C)
-#define S5P_CLKSRC_MASK_FSYS S5P_CLKREG(0x0C340)
-#define S5P_CLKSRC_MASK_PERIL0 S5P_CLKREG(0x0C350)
-#define S5P_CLKSRC_MASK_PERIL1 S5P_CLKREG(0x0C354)
-
#define S5P_CLKDIV_STAT_TOP S5P_CLKREG(0x0C610)
#define S5P_CLKGATE_SCLKCAM S5P_CLKREG(0x0C820)
@@ -85,13 +83,16 @@
#define S5P_CLKGATE_IP_TV S5P_CLKREG(0x0C924)
#define S5P_CLKGATE_IP_MFC S5P_CLKREG(0x0C928)
#define S5P_CLKGATE_IP_G3D S5P_CLKREG(0x0C92C)
-#define S5P_CLKGATE_IP_IMAGE S5P_CLKREG(0x0C930)
+#define S5P_CLKGATE_IP_IMAGE (soc_is_exynos4210() ? \
+ S5P_CLKREG(0x0C930) : \
+ S5P_CLKREG(0x04930))
#define S5P_CLKGATE_IP_LCD0 S5P_CLKREG(0x0C934)
-#define S5P_CLKGATE_IP_LCD1 S5P_CLKREG(0x0C938)
#define S5P_CLKGATE_IP_FSYS S5P_CLKREG(0x0C940)
#define S5P_CLKGATE_IP_GPS S5P_CLKREG(0x0C94C)
#define S5P_CLKGATE_IP_PERIL S5P_CLKREG(0x0C950)
-#define S5P_CLKGATE_IP_PERIR S5P_CLKREG(0x0C960)
+#define S5P_CLKGATE_IP_PERIR (soc_is_exynos4210() ? \
+ S5P_CLKREG(0x0C960) : \
+ S5P_CLKREG(0x08960))
#define S5P_CLKGATE_BLOCK S5P_CLKREG(0x0C970)
#define S5P_CLKSRC_MASK_DMC S5P_CLKREG(0x10300)
@@ -102,11 +103,17 @@
#define S5P_CLKGATE_IP_DMC S5P_CLKREG(0x10900)
#define S5P_APLL_LOCK S5P_CLKREG(0x14000)
-#define S5P_MPLL_LOCK S5P_CLKREG(0x14004)
+#define S5P_MPLL_LOCK (soc_is_exynos4210() ? \
+ S5P_CLKREG(0x14004) : \
+ S5P_CLKREG(0x10008))
#define S5P_APLL_CON0 S5P_CLKREG(0x14100)
#define S5P_APLL_CON1 S5P_CLKREG(0x14104)
-#define S5P_MPLL_CON0 S5P_CLKREG(0x14108)
-#define S5P_MPLL_CON1 S5P_CLKREG(0x1410C)
+#define S5P_MPLL_CON0 (soc_is_exynos4210() ? \
+ S5P_CLKREG(0x14108) : \
+ S5P_CLKREG(0x10108))
+#define S5P_MPLL_CON1 (soc_is_exynos4210() ? \
+ S5P_CLKREG(0x1410C) : \
+ S5P_CLKREG(0x1010C))
#define S5P_CLKSRC_CPU S5P_CLKREG(0x14200)
#define S5P_CLKMUX_STATCPU S5P_CLKREG(0x14400)
@@ -183,6 +190,13 @@
#define S5P_CLKDIV_BUS_GPLR_SHIFT (4)
#define S5P_CLKDIV_BUS_GPLR_MASK (0x7 << S5P_CLKDIV_BUS_GPLR_SHIFT)
+/* Only for EXYNOS4210 */
+
+#define S5P_CLKSRC_LCD1 S5P_CLKREG(0x0C238)
+#define S5P_CLKSRC_MASK_LCD1 S5P_CLKREG(0x0C338)
+#define S5P_CLKDIV_LCD1 S5P_CLKREG(0x0C538)
+#define S5P_CLKGATE_IP_LCD1 S5P_CLKREG(0x0C938)
+
/* Compatibility defines and inclusion */
#include <mach/regs-pmu.h>
diff --git a/arch/arm/plat-s5p/include/plat/exynos4.h b/arch/arm/plat-s5p/include/plat/exynos4.h
index 4aed130..f680a14 100644
--- a/arch/arm/plat-s5p/include/plat/exynos4.h
+++ b/arch/arm/plat-s5p/include/plat/exynos4.h
@@ -14,6 +14,8 @@
extern void exynos4_common_init_uarts(struct s3c2410_uartcfg *cfg, int no);
extern void exynos4_register_clocks(void);
+extern void exynos4210_register_clocks(void);
+extern void exynos4212_register_clocks(void);
extern void exynos4_setup_clocks(void);
#ifdef CONFIG_ARCH_EXYNOS4
diff --git a/arch/arm/plat-s5p/include/plat/pll.h b/arch/arm/plat-s5p/include/plat/pll.h
index bf28fad..1bfd61a 100644
--- a/arch/arm/plat-s5p/include/plat/pll.h
+++ b/arch/arm/plat-s5p/include/plat/pll.h
@@ -12,6 +12,59 @@
* published by the Free Software Foundation.
*/
+#include <asm/div64.h>
+
+#define PLL35XX_MDIV_MASK (0x3FF)
+#define PLL35XX_PDIV_MASK (0x3F)
+#define PLL35XX_SDIV_MASK (0x7)
+#define PLL35XX_MDIV_SHIFT (16)
+#define PLL35XX_PDIV_SHIFT (8)
+#define PLL35XX_SDIV_SHIFT (0)
+
+static inline unsigned long s5p_get_pll35xx(unsigned long baseclk, u32 pll_con)
+{
+ u32 mdiv, pdiv, sdiv;
+ u64 fvco = baseclk;
+
+ mdiv = (pll_con >> PLL35XX_MDIV_SHIFT) & PLL35XX_MDIV_MASK;
+ pdiv = (pll_con >> PLL35XX_PDIV_SHIFT) & PLL35XX_PDIV_MASK;
+ sdiv = (pll_con >> PLL35XX_SDIV_SHIFT) & PLL35XX_SDIV_MASK;
+
+ fvco *= mdiv;
+ do_div(fvco, (pdiv << sdiv));
+
+ return (unsigned long)fvco;
+}
+
+#define PLL36XX_KDIV_MASK (0xFFFF)
+#define PLL36XX_MDIV_MASK (0x1FF)
+#define PLL36XX_PDIV_MASK (0x3F)
+#define PLL36XX_SDIV_MASK (0x7)
+#define PLL36XX_MDIV_SHIFT (16)
+#define PLL36XX_PDIV_SHIFT (8)
+#define PLL36XX_SDIV_SHIFT (0)
+
+static inline unsigned long s5p_get_pll36xx(unsigned long baseclk,
+ u32 pll_con0, u32 pll_con1)
+{
+ unsigned long result;
+ u32 mdiv, pdiv, sdiv, kdiv;
+ u64 tmp;
+
+ mdiv = (pll_con0 >> PLL36XX_MDIV_SHIFT) & PLL36XX_MDIV_MASK;
+ pdiv = (pll_con0 >> PLL36XX_PDIV_SHIFT) & PLL36XX_PDIV_MASK;
+ sdiv = (pll_con0 >> PLL36XX_SDIV_SHIFT) & PLL36XX_SDIV_MASK;
+ kdiv = pll_con1 & PLL36XX_KDIV_MASK;
+
+ tmp = baseclk;
+
+ tmp *= (mdiv << 16) + kdiv;
+ do_div(tmp, (pdiv << sdiv));
+ result = tmp >> 16;
+
+ return result;
+}
+
#define PLL45XX_MDIV_MASK (0x3FF)
#define PLL45XX_PDIV_MASK (0x3F)
#define PLL45XX_SDIV_MASK (0x7)
@@ -19,8 +72,6 @@
#define PLL45XX_PDIV_SHIFT (8)
#define PLL45XX_SDIV_SHIFT (0)
-#include <asm/div64.h>
-
enum pll45xx_type_t {
pll_4500,
pll_4502,
--
1.7.1
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH 2/5] ARM: EXYNOS4: Add support clock for EXYNOS4212
@ 2011-08-24 13:25 ` Kukjin Kim
0 siblings, 0 replies; 20+ messages in thread
From: Kukjin Kim @ 2011-08-24 13:25 UTC (permalink / raw)
To: linux-arm-kernel
This patch splits EXYNOS4 clock code to EXYNOS4 common,
EXYNOS4210 and EXYNOS4212 for supporting new EXYNOS4212
SoC with one kernel image. Of course, this patch adds
some clock codes for EXYNOS4212 SoC.
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
---
arch/arm/mach-exynos4/clock-exynos4210.c | 101 ++++++++++++++++
arch/arm/mach-exynos4/clock-exynos4212.c | 84 +++++++++++++
arch/arm/mach-exynos4/clock.c | 127 +++++++++-----------
arch/arm/mach-exynos4/cpu.c | 6 +
arch/arm/mach-exynos4/include/mach/exynos4-clock.h | 43 +++++++
arch/arm/mach-exynos4/include/mach/regs-clock.h | 50 +++++---
arch/arm/plat-s5p/include/plat/exynos4.h | 2 +
arch/arm/plat-s5p/include/plat/pll.h | 55 ++++++++-
8 files changed, 377 insertions(+), 91 deletions(-)
create mode 100644 arch/arm/mach-exynos4/clock-exynos4210.c
create mode 100644 arch/arm/mach-exynos4/clock-exynos4212.c
create mode 100644 arch/arm/mach-exynos4/include/mach/exynos4-clock.h
diff --git a/arch/arm/mach-exynos4/clock-exynos4210.c b/arch/arm/mach-exynos4/clock-exynos4210.c
new file mode 100644
index 0000000..fe74b91
--- /dev/null
+++ b/arch/arm/mach-exynos4/clock-exynos4210.c
@@ -0,0 +1,101 @@
+/*
+ * linux/arch/arm/mach-exynos4/clock-exynos4210.c
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * EXYNOS4210 - Clock support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/kernel.h>
+#include <linux/err.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+
+#include <plat/cpu-freq.h>
+#include <plat/clock.h>
+#include <plat/cpu.h>
+#include <plat/pll.h>
+#include <plat/s5p-clock.h>
+#include <plat/clock-clksrc.h>
+#include <plat/exynos4.h>
+
+#include <mach/hardware.h>
+#include <mach/map.h>
+#include <mach/regs-clock.h>
+#include <mach/exynos4-clock.h>
+
+static struct clksrc_clk *sysclks[] = {
+ /* nothing here yet */
+};
+
+static int exynos4_clksrc_mask_lcd1_ctrl(struct clk *clk, int enable)
+{
+ return s5p_gatectrl(S5P_CLKSRC_MASK_LCD1, clk, enable);
+}
+
+static struct clksrc_clk clksrcs[] = {
+ {
+ .clk = {
+ .name = "sclk_sata",
+ .id = -1,
+ .enable = exynos4_clksrc_mask_fsys_ctrl,
+ .ctrlbit = (1 << 24),
+ },
+ .sources = &clkset_mout_corebus,
+ .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 24, .size = 1 },
+ .reg_div = { .reg = S5P_CLKDIV_FSYS0, .shift = 20, .size = 4 },
+ }, {
+ .clk = {
+ .name = "sclk_fimd",
+ .devname = "exynos4-fb.1",
+ .enable = exynos4_clksrc_mask_lcd1_ctrl,
+ .ctrlbit = (1 << 0),
+ },
+ .sources = &clkset_group,
+ .reg_src = { .reg = S5P_CLKSRC_LCD1, .shift = 0, .size = 4 },
+ .reg_div = { .reg = S5P_CLKDIV_LCD1, .shift = 0, .size = 4 },
+ },
+};
+
+static struct clk init_clocks_off[] = {
+ {
+ .name = "sataphy",
+ .id = -1,
+ .parent = &clk_aclk_133.clk,
+ .enable = exynos4_clk_ip_fsys_ctrl,
+ .ctrlbit = (1 << 3),
+ }, {
+ .name = "sata",
+ .id = -1,
+ .parent = &clk_aclk_133.clk,
+ .enable = exynos4_clk_ip_fsys_ctrl,
+ .ctrlbit = (1 << 10),
+ }, {
+ .name = "fimd",
+ .devname = "exynos4-fb.1",
+ .enable = exynos4_clk_ip_lcd1_ctrl,
+ .ctrlbit = (1 << 0),
+ },
+};
+
+void __init exynos4210_register_clocks(void)
+{
+ int ptr;
+
+ clk_mout_mpll.reg_src.reg = S5P_CLKSRC_CPU;
+ clk_mout_mpll.reg_src.shift = 8;
+ clk_mout_mpll.reg_src.size = 1;
+
+ for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
+ s3c_register_clksrc(sysclks[ptr], 1);
+
+ s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
+
+ s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
+ s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
+}
diff --git a/arch/arm/mach-exynos4/clock-exynos4212.c b/arch/arm/mach-exynos4/clock-exynos4212.c
new file mode 100644
index 0000000..5a47a3f
--- /dev/null
+++ b/arch/arm/mach-exynos4/clock-exynos4212.c
@@ -0,0 +1,84 @@
+/*
+ * linux/arch/arm/mach-exynos4/clock-exynos4212.c
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * EXYNOS4212 - Clock support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/kernel.h>
+#include <linux/err.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+
+#include <plat/cpu-freq.h>
+#include <plat/clock.h>
+#include <plat/cpu.h>
+#include <plat/pll.h>
+#include <plat/s5p-clock.h>
+#include <plat/clock-clksrc.h>
+#include <plat/exynos4.h>
+
+#include <mach/hardware.h>
+#include <mach/map.h>
+#include <mach/regs-clock.h>
+#include <mach/exynos4-clock.h>
+
+static struct clk *clk_src_mpll_user_list[] = {
+ [0] = &clk_fin_mpll,
+ [1] = &clk_mout_mpll.clk,
+};
+
+static struct clksrc_sources clk_src_mpll_user = {
+ .sources = clk_src_mpll_user_list,
+ .nr_sources = ARRAY_SIZE(clk_src_mpll_user_list),
+};
+
+static struct clksrc_clk clk_mout_mpll_user = {
+ .clk = {
+ .name = "mout_mpll_user",
+ },
+ .sources = &clk_src_mpll_user,
+ .reg_src = { .reg = S5P_CLKSRC_CPU, .shift = 24, .size = 1 },
+};
+
+static struct clksrc_clk *sysclks[] = {
+ &clk_mout_mpll_user,
+};
+
+static struct clksrc_clk clksrcs[] = {
+ /* nothing here yet */
+};
+
+static struct clk init_clocks_off[] = {
+ /* nothing here yet */
+};
+
+void __init exynos4212_register_clocks(void)
+{
+ int ptr;
+
+ /* usbphy1 is removed */
+ clkset_group_list[4] = NULL;
+
+ /* mout_mpll_user is used */
+ clkset_group_list[6] = &clk_mout_mpll_user.clk;
+ clkset_aclk_top_list[0] = &clk_mout_mpll_user.clk;
+
+ clk_mout_mpll.reg_src.reg = S5P_CLKSRC_DMC;
+ clk_mout_mpll.reg_src.shift = 12;
+ clk_mout_mpll.reg_src.size = 1;
+
+ for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
+ s3c_register_clksrc(sysclks[ptr], 1);
+
+ s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
+
+ s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
+ s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
+}
diff --git a/arch/arm/mach-exynos4/clock.c b/arch/arm/mach-exynos4/clock.c
index 79d6cd0..eb99467 100644
--- a/arch/arm/mach-exynos4/clock.c
+++ b/arch/arm/mach-exynos4/clock.c
@@ -20,26 +20,28 @@
#include <plat/pll.h>
#include <plat/s5p-clock.h>
#include <plat/clock-clksrc.h>
+#include <plat/exynos4.h>
#include <mach/map.h>
#include <mach/regs-clock.h>
#include <mach/sysmmu.h>
+#include <mach/exynos4-clock.h>
-static struct clk clk_sclk_hdmi27m = {
+struct clk clk_sclk_hdmi27m = {
.name = "sclk_hdmi27m",
.rate = 27000000,
};
-static struct clk clk_sclk_hdmiphy = {
+struct clk clk_sclk_hdmiphy = {
.name = "sclk_hdmiphy",
};
-static struct clk clk_sclk_usbphy0 = {
+struct clk clk_sclk_usbphy0 = {
.name = "sclk_usbphy0",
.rate = 27000000,
};
-static struct clk clk_sclk_usbphy1 = {
+struct clk clk_sclk_usbphy1 = {
.name = "sclk_usbphy1",
};
@@ -58,12 +60,7 @@ static int exynos4_clksrc_mask_lcd0_ctrl(struct clk *clk, int enable)
return s5p_gatectrl(S5P_CLKSRC_MASK_LCD0, clk, enable);
}
-static int exynos4_clksrc_mask_lcd1_ctrl(struct clk *clk, int enable)
-{
- return s5p_gatectrl(S5P_CLKSRC_MASK_LCD1, clk, enable);
-}
-
-static int exynos4_clksrc_mask_fsys_ctrl(struct clk *clk, int enable)
+int exynos4_clksrc_mask_fsys_ctrl(struct clk *clk, int enable)
{
return s5p_gatectrl(S5P_CLKSRC_MASK_FSYS, clk, enable);
}
@@ -103,12 +100,12 @@ static int exynos4_clk_ip_lcd0_ctrl(struct clk *clk, int enable)
return s5p_gatectrl(S5P_CLKGATE_IP_LCD0, clk, enable);
}
-static int exynos4_clk_ip_lcd1_ctrl(struct clk *clk, int enable)
+int exynos4_clk_ip_lcd1_ctrl(struct clk *clk, int enable)
{
return s5p_gatectrl(S5P_CLKGATE_IP_LCD1, clk, enable);
}
-static int exynos4_clk_ip_fsys_ctrl(struct clk *clk, int enable)
+int exynos4_clk_ip_fsys_ctrl(struct clk *clk, int enable)
{
return s5p_gatectrl(S5P_CLKGATE_IP_FSYS, clk, enable);
}
@@ -133,7 +130,7 @@ static struct clksrc_clk clk_mout_apll = {
.reg_src = { .reg = S5P_CLKSRC_CPU, .shift = 0, .size = 1 },
};
-static struct clksrc_clk clk_sclk_apll = {
+struct clksrc_clk clk_sclk_apll = {
.clk = {
.name = "sclk_apll",
.parent = &clk_mout_apll.clk,
@@ -141,7 +138,7 @@ static struct clksrc_clk clk_sclk_apll = {
.reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 24, .size = 3 },
};
-static struct clksrc_clk clk_mout_epll = {
+struct clksrc_clk clk_mout_epll = {
.clk = {
.name = "mout_epll",
},
@@ -149,12 +146,13 @@ static struct clksrc_clk clk_mout_epll = {
.reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 4, .size = 1 },
};
-static struct clksrc_clk clk_mout_mpll = {
+struct clksrc_clk clk_mout_mpll = {
.clk = {
.name = "mout_mpll",
},
.sources = &clk_src_mpll,
- .reg_src = { .reg = S5P_CLKSRC_CPU, .shift = 8, .size = 1 },
+
+ /* reg_src will be added in each SoCs' clock */
};
static struct clk *clkset_moutcore_list[] = {
@@ -224,12 +222,12 @@ static struct clksrc_clk clk_periphclk = {
/* Core list of CMU_CORE side */
-static struct clk *clkset_corebus_list[] = {
+struct clk *clkset_corebus_list[] = {
[0] = &clk_mout_mpll.clk,
[1] = &clk_sclk_apll.clk,
};
-static struct clksrc_sources clkset_mout_corebus = {
+struct clksrc_sources clkset_mout_corebus = {
.sources = clkset_corebus_list,
.nr_sources = ARRAY_SIZE(clkset_corebus_list),
};
@@ -284,12 +282,12 @@ static struct clksrc_clk clk_pclk_acp = {
/* Core list of CMU_TOP side */
-static struct clk *clkset_aclk_top_list[] = {
+struct clk *clkset_aclk_top_list[] = {
[0] = &clk_mout_mpll.clk,
[1] = &clk_sclk_apll.clk,
};
-static struct clksrc_sources clkset_aclk = {
+struct clksrc_sources clkset_aclk = {
.sources = clkset_aclk_top_list,
.nr_sources = ARRAY_SIZE(clkset_aclk_top_list),
};
@@ -321,7 +319,7 @@ static struct clksrc_clk clk_aclk_160 = {
.reg_div = { .reg = S5P_CLKDIV_TOP, .shift = 8, .size = 3 },
};
-static struct clksrc_clk clk_aclk_133 = {
+struct clksrc_clk clk_aclk_133 = {
.clk = {
.name = "aclk_133",
},
@@ -360,7 +358,7 @@ static struct clksrc_sources clkset_sclk_vpll = {
.nr_sources = ARRAY_SIZE(clkset_sclk_vpll_list),
};
-static struct clksrc_clk clk_sclk_vpll = {
+struct clksrc_clk clk_sclk_vpll = {
.clk = {
.name = "sclk_vpll",
},
@@ -410,16 +408,6 @@ static struct clk init_clocks_off[] = {
.enable = exynos4_clk_ip_lcd0_ctrl,
.ctrlbit = (1 << 0),
}, {
- .name = "fimd",
- .devname = "exynos4-fb.1",
- .enable = exynos4_clk_ip_lcd1_ctrl,
- .ctrlbit = (1 << 0),
- }, {
- .name = "sataphy",
- .parent = &clk_aclk_133.clk,
- .enable = exynos4_clk_ip_fsys_ctrl,
- .ctrlbit = (1 << 3),
- }, {
.name = "hsmmc",
.devname = "s3c-sdhci.0",
.parent = &clk_aclk_133.clk,
@@ -449,11 +437,6 @@ static struct clk init_clocks_off[] = {
.enable = exynos4_clk_ip_fsys_ctrl,
.ctrlbit = (1 << 9),
}, {
- .name = "sata",
- .parent = &clk_aclk_133.clk,
- .enable = exynos4_clk_ip_fsys_ctrl,
- .ctrlbit = (1 << 10),
- }, {
.name = "pdma",
.devname = "s3c-pl330.0",
.enable = exynos4_clk_ip_fsys_ctrl,
@@ -673,7 +656,7 @@ static struct clk init_clocks[] = {
}
};
-static struct clk *clkset_group_list[] = {
+struct clk *clkset_group_list[] = {
[0] = &clk_ext_xtal_mux,
[1] = &clk_xusbxti,
[2] = &clk_sclk_hdmi27m,
@@ -685,7 +668,7 @@ static struct clk *clkset_group_list[] = {
[8] = &clk_sclk_vpll.clk,
};
-static struct clksrc_sources clkset_group = {
+struct clksrc_sources clkset_group = {
.sources = clkset_group_list,
.nr_sources = ARRAY_SIZE(clkset_group_list),
};
@@ -969,25 +952,6 @@ static struct clksrc_clk clksrcs[] = {
.reg_div = { .reg = S5P_CLKDIV_LCD0, .shift = 0, .size = 4 },
}, {
.clk = {
- .name = "sclk_fimd",
- .devname = "exynos4-fb.1",
- .enable = exynos4_clksrc_mask_lcd1_ctrl,
- .ctrlbit = (1 << 0),
- },
- .sources = &clkset_group,
- .reg_src = { .reg = S5P_CLKSRC_LCD1, .shift = 0, .size = 4 },
- .reg_div = { .reg = S5P_CLKDIV_LCD1, .shift = 0, .size = 4 },
- }, {
- .clk = {
- .name = "sclk_sata",
- .enable = exynos4_clksrc_mask_fsys_ctrl,
- .ctrlbit = (1 << 24),
- },
- .sources = &clkset_mout_corebus,
- .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 24, .size = 1 },
- .reg_div = { .reg = S5P_CLKDIV_FSYS0, .shift = 20, .size = 4 },
- }, {
- .clk = {
.name = "sclk_spi",
.devname = "s3c64xx-spi.0",
.enable = exynos4_clksrc_mask_peril1_ctrl,
@@ -1116,7 +1080,13 @@ static int xtal_rate;
static unsigned long exynos4_fout_apll_get_rate(struct clk *clk)
{
- return s5p_get_pll45xx(xtal_rate, __raw_readl(S5P_APLL_CON0), pll_4508);
+ if (soc_is_exynos4210())
+ return s5p_get_pll45xx(xtal_rate, __raw_readl(S5P_APLL_CON0),
+ pll_4508);
+ else if (soc_is_exynos4212())
+ return s5p_get_pll35xx(xtal_rate, __raw_readl(S5P_APLL_CON0));
+ else
+ return 0;
}
static struct clk_ops exynos4_fout_apll_ops = {
@@ -1126,10 +1096,10 @@ static struct clk_ops exynos4_fout_apll_ops = {
void __init_or_cpufreq exynos4_setup_clocks(void)
{
struct clk *xtal_clk;
- unsigned long apll;
- unsigned long mpll;
- unsigned long epll;
- unsigned long vpll;
+ unsigned long apll = 0;
+ unsigned long mpll = 0;
+ unsigned long epll = 0;
+ unsigned long vpll = 0;
unsigned long vpllsrc;
unsigned long xtal;
unsigned long armclk;
@@ -1153,14 +1123,29 @@ void __init_or_cpufreq exynos4_setup_clocks(void)
printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
- apll = s5p_get_pll45xx(xtal, __raw_readl(S5P_APLL_CON0), pll_4508);
- mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P_MPLL_CON0), pll_4508);
- epll = s5p_get_pll46xx(xtal, __raw_readl(S5P_EPLL_CON0),
- __raw_readl(S5P_EPLL_CON1), pll_4600);
-
- vpllsrc = clk_get_rate(&clk_vpllsrc.clk);
- vpll = s5p_get_pll46xx(vpllsrc, __raw_readl(S5P_VPLL_CON0),
- __raw_readl(S5P_VPLL_CON1), pll_4650c);
+ if (soc_is_exynos4210()) {
+ apll = s5p_get_pll45xx(xtal, __raw_readl(S5P_APLL_CON0),
+ pll_4508);
+ mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P_MPLL_CON0),
+ pll_4508);
+ epll = s5p_get_pll46xx(xtal, __raw_readl(S5P_EPLL_CON0),
+ __raw_readl(S5P_EPLL_CON1), pll_4600);
+
+ vpllsrc = clk_get_rate(&clk_vpllsrc.clk);
+ vpll = s5p_get_pll46xx(vpllsrc, __raw_readl(S5P_VPLL_CON0),
+ __raw_readl(S5P_VPLL_CON1), pll_4650c);
+ } else if (soc_is_exynos4212()) {
+ apll = s5p_get_pll35xx(xtal, __raw_readl(S5P_APLL_CON0));
+ mpll = s5p_get_pll35xx(xtal, __raw_readl(S5P_MPLL_CON0));
+ epll = s5p_get_pll36xx(xtal, __raw_readl(S5P_EPLL_CON0),
+ __raw_readl(S5P_EPLL_CON1));
+
+ vpllsrc = clk_get_rate(&clk_vpllsrc.clk);
+ vpll = s5p_get_pll36xx(vpllsrc, __raw_readl(S5P_VPLL_CON0),
+ __raw_readl(S5P_VPLL_CON1));
+ } else {
+ /* nothing */
+ }
clk_fout_apll.ops = &exynos4_fout_apll_ops;
clk_fout_mpll.rate = mpll;
diff --git a/arch/arm/mach-exynos4/cpu.c b/arch/arm/mach-exynos4/cpu.c
index 1e1a7a9..02ec52a 100644
--- a/arch/arm/mach-exynos4/cpu.c
+++ b/arch/arm/mach-exynos4/cpu.c
@@ -188,6 +188,12 @@ void __init exynos4_init_clocks(int xtal)
s3c24xx_register_baseclocks(xtal);
s5p_register_clocks(xtal);
+
+ if (soc_is_exynos4210())
+ exynos4210_register_clocks();
+ else if (soc_is_exynos4212())
+ exynos4212_register_clocks();
+
exynos4_register_clocks();
exynos4_setup_clocks();
}
diff --git a/arch/arm/mach-exynos4/include/mach/exynos4-clock.h b/arch/arm/mach-exynos4/include/mach/exynos4-clock.h
new file mode 100644
index 0000000..a07fcbf
--- /dev/null
+++ b/arch/arm/mach-exynos4/include/mach/exynos4-clock.h
@@ -0,0 +1,43 @@
+/*
+ * linux/arch/arm/mach-exynos4/include/mach/exynos4-clock.h
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * Header file for exynos4 clock support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_CLOCK_H
+#define __ASM_ARCH_CLOCK_H __FILE__
+
+#include <linux/clk.h>
+
+extern struct clk clk_sclk_hdmi27m;
+extern struct clk clk_sclk_usbphy0;
+extern struct clk clk_sclk_usbphy1;
+extern struct clk clk_sclk_hdmiphy;
+
+extern struct clksrc_clk clk_sclk_apll;
+extern struct clksrc_clk clk_mout_mpll;
+extern struct clksrc_clk clk_aclk_133;
+extern struct clksrc_clk clk_mout_epll;
+extern struct clksrc_clk clk_sclk_vpll;
+
+extern struct clk *clkset_corebus_list[];
+extern struct clksrc_sources clkset_mout_corebus;
+
+extern struct clk *clkset_aclk_top_list[];
+extern struct clksrc_sources clkset_aclk;
+
+extern struct clk *clkset_group_list[];
+extern struct clksrc_sources clkset_group;
+
+extern int exynos4_clksrc_mask_fsys_ctrl(struct clk *clk, int enable);
+extern int exynos4_clk_ip_fsys_ctrl(struct clk *clk, int enable);
+extern int exynos4_clk_ip_lcd1_ctrl(struct clk *clk, int enable);
+
+#endif /* __ASM_ARCH_CLOCK_H */
diff --git a/arch/arm/mach-exynos4/include/mach/regs-clock.h b/arch/arm/mach-exynos4/include/mach/regs-clock.h
index d493fdb..e75d0f8 100644
--- a/arch/arm/mach-exynos4/include/mach/regs-clock.h
+++ b/arch/arm/mach-exynos4/include/mach/regs-clock.h
@@ -13,6 +13,7 @@
#ifndef __ASM_ARCH_REGS_CLOCK_H
#define __ASM_ARCH_REGS_CLOCK_H __FILE__
+#include <plat/cpu.h>
#include <mach/map.h>
#define S5P_CLKREG(x) (S5P_VA_CMU + (x))
@@ -41,12 +42,20 @@
#define S5P_CLKSRC_G3D S5P_CLKREG(0x0C22C)
#define S5P_CLKSRC_IMAGE S5P_CLKREG(0x0C230)
#define S5P_CLKSRC_LCD0 S5P_CLKREG(0x0C234)
-#define S5P_CLKSRC_LCD1 S5P_CLKREG(0x0C238)
#define S5P_CLKSRC_MAUDIO S5P_CLKREG(0x0C23C)
#define S5P_CLKSRC_FSYS S5P_CLKREG(0x0C240)
#define S5P_CLKSRC_PERIL0 S5P_CLKREG(0x0C250)
#define S5P_CLKSRC_PERIL1 S5P_CLKREG(0x0C254)
+#define S5P_CLKSRC_MASK_TOP S5P_CLKREG(0x0C310)
+#define S5P_CLKSRC_MASK_CAM S5P_CLKREG(0x0C320)
+#define S5P_CLKSRC_MASK_TV S5P_CLKREG(0x0C324)
+#define S5P_CLKSRC_MASK_LCD0 S5P_CLKREG(0x0C334)
+#define S5P_CLKSRC_MASK_MAUDIO S5P_CLKREG(0x0C33C)
+#define S5P_CLKSRC_MASK_FSYS S5P_CLKREG(0x0C340)
+#define S5P_CLKSRC_MASK_PERIL0 S5P_CLKREG(0x0C350)
+#define S5P_CLKSRC_MASK_PERIL1 S5P_CLKREG(0x0C354)
+
#define S5P_CLKDIV_TOP S5P_CLKREG(0x0C510)
#define S5P_CLKDIV_CAM S5P_CLKREG(0x0C520)
#define S5P_CLKDIV_TV S5P_CLKREG(0x0C524)
@@ -54,7 +63,6 @@
#define S5P_CLKDIV_G3D S5P_CLKREG(0x0C52C)
#define S5P_CLKDIV_IMAGE S5P_CLKREG(0x0C530)
#define S5P_CLKDIV_LCD0 S5P_CLKREG(0x0C534)
-#define S5P_CLKDIV_LCD1 S5P_CLKREG(0x0C538)
#define S5P_CLKDIV_MAUDIO S5P_CLKREG(0x0C53C)
#define S5P_CLKDIV_FSYS0 S5P_CLKREG(0x0C540)
#define S5P_CLKDIV_FSYS1 S5P_CLKREG(0x0C544)
@@ -68,16 +76,6 @@
#define S5P_CLKDIV_PERIL5 S5P_CLKREG(0x0C564)
#define S5P_CLKDIV2_RATIO S5P_CLKREG(0x0C580)
-#define S5P_CLKSRC_MASK_TOP S5P_CLKREG(0x0C310)
-#define S5P_CLKSRC_MASK_CAM S5P_CLKREG(0x0C320)
-#define S5P_CLKSRC_MASK_TV S5P_CLKREG(0x0C324)
-#define S5P_CLKSRC_MASK_LCD0 S5P_CLKREG(0x0C334)
-#define S5P_CLKSRC_MASK_LCD1 S5P_CLKREG(0x0C338)
-#define S5P_CLKSRC_MASK_MAUDIO S5P_CLKREG(0x0C33C)
-#define S5P_CLKSRC_MASK_FSYS S5P_CLKREG(0x0C340)
-#define S5P_CLKSRC_MASK_PERIL0 S5P_CLKREG(0x0C350)
-#define S5P_CLKSRC_MASK_PERIL1 S5P_CLKREG(0x0C354)
-
#define S5P_CLKDIV_STAT_TOP S5P_CLKREG(0x0C610)
#define S5P_CLKGATE_SCLKCAM S5P_CLKREG(0x0C820)
@@ -85,13 +83,16 @@
#define S5P_CLKGATE_IP_TV S5P_CLKREG(0x0C924)
#define S5P_CLKGATE_IP_MFC S5P_CLKREG(0x0C928)
#define S5P_CLKGATE_IP_G3D S5P_CLKREG(0x0C92C)
-#define S5P_CLKGATE_IP_IMAGE S5P_CLKREG(0x0C930)
+#define S5P_CLKGATE_IP_IMAGE (soc_is_exynos4210() ? \
+ S5P_CLKREG(0x0C930) : \
+ S5P_CLKREG(0x04930))
#define S5P_CLKGATE_IP_LCD0 S5P_CLKREG(0x0C934)
-#define S5P_CLKGATE_IP_LCD1 S5P_CLKREG(0x0C938)
#define S5P_CLKGATE_IP_FSYS S5P_CLKREG(0x0C940)
#define S5P_CLKGATE_IP_GPS S5P_CLKREG(0x0C94C)
#define S5P_CLKGATE_IP_PERIL S5P_CLKREG(0x0C950)
-#define S5P_CLKGATE_IP_PERIR S5P_CLKREG(0x0C960)
+#define S5P_CLKGATE_IP_PERIR (soc_is_exynos4210() ? \
+ S5P_CLKREG(0x0C960) : \
+ S5P_CLKREG(0x08960))
#define S5P_CLKGATE_BLOCK S5P_CLKREG(0x0C970)
#define S5P_CLKSRC_MASK_DMC S5P_CLKREG(0x10300)
@@ -102,11 +103,17 @@
#define S5P_CLKGATE_IP_DMC S5P_CLKREG(0x10900)
#define S5P_APLL_LOCK S5P_CLKREG(0x14000)
-#define S5P_MPLL_LOCK S5P_CLKREG(0x14004)
+#define S5P_MPLL_LOCK (soc_is_exynos4210() ? \
+ S5P_CLKREG(0x14004) : \
+ S5P_CLKREG(0x10008))
#define S5P_APLL_CON0 S5P_CLKREG(0x14100)
#define S5P_APLL_CON1 S5P_CLKREG(0x14104)
-#define S5P_MPLL_CON0 S5P_CLKREG(0x14108)
-#define S5P_MPLL_CON1 S5P_CLKREG(0x1410C)
+#define S5P_MPLL_CON0 (soc_is_exynos4210() ? \
+ S5P_CLKREG(0x14108) : \
+ S5P_CLKREG(0x10108))
+#define S5P_MPLL_CON1 (soc_is_exynos4210() ? \
+ S5P_CLKREG(0x1410C) : \
+ S5P_CLKREG(0x1010C))
#define S5P_CLKSRC_CPU S5P_CLKREG(0x14200)
#define S5P_CLKMUX_STATCPU S5P_CLKREG(0x14400)
@@ -183,6 +190,13 @@
#define S5P_CLKDIV_BUS_GPLR_SHIFT (4)
#define S5P_CLKDIV_BUS_GPLR_MASK (0x7 << S5P_CLKDIV_BUS_GPLR_SHIFT)
+/* Only for EXYNOS4210 */
+
+#define S5P_CLKSRC_LCD1 S5P_CLKREG(0x0C238)
+#define S5P_CLKSRC_MASK_LCD1 S5P_CLKREG(0x0C338)
+#define S5P_CLKDIV_LCD1 S5P_CLKREG(0x0C538)
+#define S5P_CLKGATE_IP_LCD1 S5P_CLKREG(0x0C938)
+
/* Compatibility defines and inclusion */
#include <mach/regs-pmu.h>
diff --git a/arch/arm/plat-s5p/include/plat/exynos4.h b/arch/arm/plat-s5p/include/plat/exynos4.h
index 4aed130..f680a14 100644
--- a/arch/arm/plat-s5p/include/plat/exynos4.h
+++ b/arch/arm/plat-s5p/include/plat/exynos4.h
@@ -14,6 +14,8 @@
extern void exynos4_common_init_uarts(struct s3c2410_uartcfg *cfg, int no);
extern void exynos4_register_clocks(void);
+extern void exynos4210_register_clocks(void);
+extern void exynos4212_register_clocks(void);
extern void exynos4_setup_clocks(void);
#ifdef CONFIG_ARCH_EXYNOS4
diff --git a/arch/arm/plat-s5p/include/plat/pll.h b/arch/arm/plat-s5p/include/plat/pll.h
index bf28fad..1bfd61a 100644
--- a/arch/arm/plat-s5p/include/plat/pll.h
+++ b/arch/arm/plat-s5p/include/plat/pll.h
@@ -12,6 +12,59 @@
* published by the Free Software Foundation.
*/
+#include <asm/div64.h>
+
+#define PLL35XX_MDIV_MASK (0x3FF)
+#define PLL35XX_PDIV_MASK (0x3F)
+#define PLL35XX_SDIV_MASK (0x7)
+#define PLL35XX_MDIV_SHIFT (16)
+#define PLL35XX_PDIV_SHIFT (8)
+#define PLL35XX_SDIV_SHIFT (0)
+
+static inline unsigned long s5p_get_pll35xx(unsigned long baseclk, u32 pll_con)
+{
+ u32 mdiv, pdiv, sdiv;
+ u64 fvco = baseclk;
+
+ mdiv = (pll_con >> PLL35XX_MDIV_SHIFT) & PLL35XX_MDIV_MASK;
+ pdiv = (pll_con >> PLL35XX_PDIV_SHIFT) & PLL35XX_PDIV_MASK;
+ sdiv = (pll_con >> PLL35XX_SDIV_SHIFT) & PLL35XX_SDIV_MASK;
+
+ fvco *= mdiv;
+ do_div(fvco, (pdiv << sdiv));
+
+ return (unsigned long)fvco;
+}
+
+#define PLL36XX_KDIV_MASK (0xFFFF)
+#define PLL36XX_MDIV_MASK (0x1FF)
+#define PLL36XX_PDIV_MASK (0x3F)
+#define PLL36XX_SDIV_MASK (0x7)
+#define PLL36XX_MDIV_SHIFT (16)
+#define PLL36XX_PDIV_SHIFT (8)
+#define PLL36XX_SDIV_SHIFT (0)
+
+static inline unsigned long s5p_get_pll36xx(unsigned long baseclk,
+ u32 pll_con0, u32 pll_con1)
+{
+ unsigned long result;
+ u32 mdiv, pdiv, sdiv, kdiv;
+ u64 tmp;
+
+ mdiv = (pll_con0 >> PLL36XX_MDIV_SHIFT) & PLL36XX_MDIV_MASK;
+ pdiv = (pll_con0 >> PLL36XX_PDIV_SHIFT) & PLL36XX_PDIV_MASK;
+ sdiv = (pll_con0 >> PLL36XX_SDIV_SHIFT) & PLL36XX_SDIV_MASK;
+ kdiv = pll_con1 & PLL36XX_KDIV_MASK;
+
+ tmp = baseclk;
+
+ tmp *= (mdiv << 16) + kdiv;
+ do_div(tmp, (pdiv << sdiv));
+ result = tmp >> 16;
+
+ return result;
+}
+
#define PLL45XX_MDIV_MASK (0x3FF)
#define PLL45XX_PDIV_MASK (0x3F)
#define PLL45XX_SDIV_MASK (0x7)
@@ -19,8 +72,6 @@
#define PLL45XX_PDIV_SHIFT (8)
#define PLL45XX_SDIV_SHIFT (0)
-#include <asm/div64.h>
-
enum pll45xx_type_t {
pll_4500,
pll_4502,
--
1.7.1
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH 3/5] ARM: EXYNOS4: Add support PM for EXYNOS4212
2011-08-24 13:25 ` Kukjin Kim
@ 2011-08-24 13:25 ` Kukjin Kim
-1 siblings, 0 replies; 20+ messages in thread
From: Kukjin Kim @ 2011-08-24 13:25 UTC (permalink / raw)
To: linux-arm-kernel, linux-samsung-soc; +Cc: ben-linux, Jonghwan Choi, Kukjin Kim
From: Jonghwan Choi <jhbird.choi@samsung.com>
This patch moves regarding clock stuff of PM into clock
file to support PM on EXYNOS4210 and EXYNOS4212 with one
single kernel image. Because some clock registers are
different on each SoCs.
Signed-off-by: Jonghwan Choi <jhbird.choi@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
---
arch/arm/mach-exynos4/clock-exynos4210.c | 38 ++++++++++
arch/arm/mach-exynos4/clock-exynos4212.c | 34 +++++++++
arch/arm/mach-exynos4/clock.c | 89 +++++++++++++++++++++++
arch/arm/mach-exynos4/include/mach/regs-clock.h | 4 +
arch/arm/mach-exynos4/pm.c | 79 ++------------------
5 files changed, 172 insertions(+), 72 deletions(-)
diff --git a/arch/arm/mach-exynos4/clock-exynos4210.c b/arch/arm/mach-exynos4/clock-exynos4210.c
index fe74b91..a4b00b7 100644
--- a/arch/arm/mach-exynos4/clock-exynos4210.c
+++ b/arch/arm/mach-exynos4/clock-exynos4210.c
@@ -15,6 +15,7 @@
#include <linux/err.h>
#include <linux/clk.h>
#include <linux/io.h>
+#include <linux/syscore_ops.h>
#include <plat/cpu-freq.h>
#include <plat/clock.h>
@@ -23,12 +24,24 @@
#include <plat/s5p-clock.h>
#include <plat/clock-clksrc.h>
#include <plat/exynos4.h>
+#include <plat/pm.h>
#include <mach/hardware.h>
#include <mach/map.h>
#include <mach/regs-clock.h>
#include <mach/exynos4-clock.h>
+static struct sleep_save exynos4210_clock_save[] = {
+ SAVE_ITEM(S5P_CLKSRC_IMAGE),
+ SAVE_ITEM(S5P_CLKSRC_LCD1),
+ SAVE_ITEM(S5P_CLKDIV_IMAGE),
+ SAVE_ITEM(S5P_CLKDIV_LCD1),
+ SAVE_ITEM(S5P_CLKSRC_MASK_LCD1),
+ SAVE_ITEM(S5P_CLKGATE_IP_IMAGE_4210),
+ SAVE_ITEM(S5P_CLKGATE_IP_LCD1),
+ SAVE_ITEM(S5P_CLKGATE_IP_PERIR_4210),
+};
+
static struct clksrc_clk *sysclks[] = {
/* nothing here yet */
};
@@ -83,6 +96,29 @@ static struct clk init_clocks_off[] = {
},
};
+#ifdef CONFIG_PM
+static int exynos4210_clock_suspend(void)
+{
+ s3c_pm_do_save(exynos4210_clock_save, ARRAY_SIZE(exynos4210_clock_save));
+
+ return 0;
+}
+
+static void exynos4210_clock_resume(void)
+{
+ s3c_pm_do_restore_core(exynos4210_clock_save, ARRAY_SIZE(exynos4210_clock_save));
+}
+
+#else
+#define exynos4210_clock_suspend NULL
+#define exynos4210_clock_resume NULL
+#endif
+
+struct syscore_ops exynos4210_clock_syscore_ops = {
+ .suspend = exynos4210_clock_suspend,
+ .resume = exynos4210_clock_resume,
+};
+
void __init exynos4210_register_clocks(void)
{
int ptr;
@@ -98,4 +134,6 @@ void __init exynos4210_register_clocks(void)
s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
+
+ register_syscore_ops(&exynos4210_clock_syscore_ops);
}
diff --git a/arch/arm/mach-exynos4/clock-exynos4212.c b/arch/arm/mach-exynos4/clock-exynos4212.c
index 5a47a3f..4638a21 100644
--- a/arch/arm/mach-exynos4/clock-exynos4212.c
+++ b/arch/arm/mach-exynos4/clock-exynos4212.c
@@ -15,6 +15,7 @@
#include <linux/err.h>
#include <linux/clk.h>
#include <linux/io.h>
+#include <linux/syscore_ops.h>
#include <plat/cpu-freq.h>
#include <plat/clock.h>
@@ -23,12 +24,20 @@
#include <plat/s5p-clock.h>
#include <plat/clock-clksrc.h>
#include <plat/exynos4.h>
+#include <plat/pm.h>
#include <mach/hardware.h>
#include <mach/map.h>
#include <mach/regs-clock.h>
#include <mach/exynos4-clock.h>
+static struct sleep_save exynos4212_clock_save[] = {
+ SAVE_ITEM(S5P_CLKSRC_IMAGE),
+ SAVE_ITEM(S5P_CLKDIV_IMAGE),
+ SAVE_ITEM(S5P_CLKGATE_IP_IMAGE_4212),
+ SAVE_ITEM(S5P_CLKGATE_IP_PERIR_4212),
+};
+
static struct clk *clk_src_mpll_user_list[] = {
[0] = &clk_fin_mpll,
[1] = &clk_mout_mpll.clk,
@@ -59,6 +68,29 @@ static struct clk init_clocks_off[] = {
/* nothing here yet */
};
+#ifdef CONFIG_PM
+static int exynos4212_clock_suspend(void)
+{
+ s3c_pm_do_save(exynos4212_clock_save, ARRAY_SIZE(exynos4212_clock_save));
+
+ return 0;
+}
+
+static void exynos4212_clock_resume(void)
+{
+ s3c_pm_do_restore_core(exynos4212_clock_save, ARRAY_SIZE(exynos4212_clock_save));
+}
+
+#else
+#define exynos4212_clock_suspend NULL
+#define exynos4212_clock_resume NULL
+#endif
+
+struct syscore_ops exynos4212_clock_syscore_ops = {
+ .suspend = exynos4212_clock_suspend,
+ .resume = exynos4212_clock_resume,
+};
+
void __init exynos4212_register_clocks(void)
{
int ptr;
@@ -81,4 +113,6 @@ void __init exynos4212_register_clocks(void)
s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
+
+ register_syscore_ops(&exynos4212_clock_syscore_ops);
}
diff --git a/arch/arm/mach-exynos4/clock.c b/arch/arm/mach-exynos4/clock.c
index eb99467..99c2a1f 100644
--- a/arch/arm/mach-exynos4/clock.c
+++ b/arch/arm/mach-exynos4/clock.c
@@ -13,6 +13,7 @@
#include <linux/kernel.h>
#include <linux/err.h>
#include <linux/io.h>
+#include <linux/syscore_ops.h>
#include <plat/cpu-freq.h>
#include <plat/clock.h>
@@ -21,12 +22,77 @@
#include <plat/s5p-clock.h>
#include <plat/clock-clksrc.h>
#include <plat/exynos4.h>
+#include <plat/pm.h>
#include <mach/map.h>
#include <mach/regs-clock.h>
#include <mach/sysmmu.h>
#include <mach/exynos4-clock.h>
+static struct sleep_save exynos4_clock_save[] = {
+ SAVE_ITEM(S5P_CLKDIV_LEFTBUS),
+ SAVE_ITEM(S5P_CLKGATE_IP_LEFTBUS),
+ SAVE_ITEM(S5P_CLKDIV_RIGHTBUS),
+ SAVE_ITEM(S5P_CLKGATE_IP_RIGHTBUS),
+ SAVE_ITEM(S5P_CLKSRC_TOP0),
+ SAVE_ITEM(S5P_CLKSRC_TOP1),
+ SAVE_ITEM(S5P_CLKSRC_CAM),
+ SAVE_ITEM(S5P_CLKSRC_TV),
+ SAVE_ITEM(S5P_CLKSRC_MFC),
+ SAVE_ITEM(S5P_CLKSRC_G3D),
+ SAVE_ITEM(S5P_CLKSRC_LCD0),
+ SAVE_ITEM(S5P_CLKSRC_MAUDIO),
+ SAVE_ITEM(S5P_CLKSRC_FSYS),
+ SAVE_ITEM(S5P_CLKSRC_PERIL0),
+ SAVE_ITEM(S5P_CLKSRC_PERIL1),
+ SAVE_ITEM(S5P_CLKDIV_CAM),
+ SAVE_ITEM(S5P_CLKDIV_TV),
+ SAVE_ITEM(S5P_CLKDIV_MFC),
+ SAVE_ITEM(S5P_CLKDIV_G3D),
+ SAVE_ITEM(S5P_CLKDIV_LCD0),
+ SAVE_ITEM(S5P_CLKDIV_MAUDIO),
+ SAVE_ITEM(S5P_CLKDIV_FSYS0),
+ SAVE_ITEM(S5P_CLKDIV_FSYS1),
+ SAVE_ITEM(S5P_CLKDIV_FSYS2),
+ SAVE_ITEM(S5P_CLKDIV_FSYS3),
+ SAVE_ITEM(S5P_CLKDIV_PERIL0),
+ SAVE_ITEM(S5P_CLKDIV_PERIL1),
+ SAVE_ITEM(S5P_CLKDIV_PERIL2),
+ SAVE_ITEM(S5P_CLKDIV_PERIL3),
+ SAVE_ITEM(S5P_CLKDIV_PERIL4),
+ SAVE_ITEM(S5P_CLKDIV_PERIL5),
+ SAVE_ITEM(S5P_CLKDIV_TOP),
+ SAVE_ITEM(S5P_CLKSRC_MASK_TOP),
+ SAVE_ITEM(S5P_CLKSRC_MASK_CAM),
+ SAVE_ITEM(S5P_CLKSRC_MASK_TV),
+ SAVE_ITEM(S5P_CLKSRC_MASK_LCD0),
+ SAVE_ITEM(S5P_CLKSRC_MASK_MAUDIO),
+ SAVE_ITEM(S5P_CLKSRC_MASK_FSYS),
+ SAVE_ITEM(S5P_CLKSRC_MASK_PERIL0),
+ SAVE_ITEM(S5P_CLKSRC_MASK_PERIL1),
+ SAVE_ITEM(S5P_CLKDIV2_RATIO),
+ SAVE_ITEM(S5P_CLKGATE_SCLKCAM),
+ SAVE_ITEM(S5P_CLKGATE_IP_CAM),
+ SAVE_ITEM(S5P_CLKGATE_IP_TV),
+ SAVE_ITEM(S5P_CLKGATE_IP_MFC),
+ SAVE_ITEM(S5P_CLKGATE_IP_G3D),
+ SAVE_ITEM(S5P_CLKGATE_IP_LCD0),
+ SAVE_ITEM(S5P_CLKGATE_IP_FSYS),
+ SAVE_ITEM(S5P_CLKGATE_IP_GPS),
+ SAVE_ITEM(S5P_CLKGATE_IP_PERIL),
+ SAVE_ITEM(S5P_CLKGATE_BLOCK),
+ SAVE_ITEM(S5P_CLKSRC_MASK_DMC),
+ SAVE_ITEM(S5P_CLKSRC_DMC),
+ SAVE_ITEM(S5P_CLKDIV_DMC0),
+ SAVE_ITEM(S5P_CLKDIV_DMC1),
+ SAVE_ITEM(S5P_CLKGATE_IP_DMC),
+ SAVE_ITEM(S5P_CLKSRC_CPU),
+ SAVE_ITEM(S5P_CLKDIV_CPU),
+ SAVE_ITEM(S5P_CLKDIV_CPU + 0x4),
+ SAVE_ITEM(S5P_CLKGATE_SCLKCPU),
+ SAVE_ITEM(S5P_CLKGATE_IP_CPU),
+};
+
struct clk clk_sclk_hdmi27m = {
.name = "sclk_hdmi27m",
.rate = 27000000,
@@ -1180,6 +1246,28 @@ static struct clk *clks[] __initdata = {
/* Nothing here yet */
};
+#ifdef CONFIG_PM
+static int exynos4_clock_suspend(void)
+{
+ s3c_pm_do_save(exynos4_clock_save, ARRAY_SIZE(exynos4_clock_save));
+ return 0;
+}
+
+static void exynos4_clock_resume(void)
+{
+ s3c_pm_do_restore_core(exynos4_clock_save, ARRAY_SIZE(exynos4_clock_save));
+}
+
+#else
+#define exynos4_clock_suspend NULL
+#define exynos4_clock_resume NULL
+#endif
+
+struct syscore_ops exynos4_clock_syscore_ops = {
+ .suspend = exynos4_clock_suspend,
+ .resume = exynos4_clock_resume,
+};
+
void __init exynos4_register_clocks(void)
{
int ptr;
@@ -1195,5 +1283,6 @@ void __init exynos4_register_clocks(void)
s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
+ register_syscore_ops(&exynos4_clock_syscore_ops);
s3c_pwmclk_init();
}
diff --git a/arch/arm/mach-exynos4/include/mach/regs-clock.h b/arch/arm/mach-exynos4/include/mach/regs-clock.h
index e75d0f8..6c37ebe 100644
--- a/arch/arm/mach-exynos4/include/mach/regs-clock.h
+++ b/arch/arm/mach-exynos4/include/mach/regs-clock.h
@@ -86,6 +86,8 @@
#define S5P_CLKGATE_IP_IMAGE (soc_is_exynos4210() ? \
S5P_CLKREG(0x0C930) : \
S5P_CLKREG(0x04930))
+#define S5P_CLKGATE_IP_IMAGE_4210 S5P_CLKREG(0x0C930)
+#define S5P_CLKGATE_IP_IMAGE_4212 S5P_CLKREG(0x04930)
#define S5P_CLKGATE_IP_LCD0 S5P_CLKREG(0x0C934)
#define S5P_CLKGATE_IP_FSYS S5P_CLKREG(0x0C940)
#define S5P_CLKGATE_IP_GPS S5P_CLKREG(0x0C94C)
@@ -93,6 +95,8 @@
#define S5P_CLKGATE_IP_PERIR (soc_is_exynos4210() ? \
S5P_CLKREG(0x0C960) : \
S5P_CLKREG(0x08960))
+#define S5P_CLKGATE_IP_PERIR_4210 S5P_CLKREG(0x0C960)
+#define S5P_CLKGATE_IP_PERIR_4212 S5P_CLKREG(0x08960)
#define S5P_CLKGATE_BLOCK S5P_CLKREG(0x0C970)
#define S5P_CLKSRC_MASK_DMC S5P_CLKREG(0x10300)
diff --git a/arch/arm/mach-exynos4/pm.c b/arch/arm/mach-exynos4/pm.c
index bc6ca94..62e4f43 100644
--- a/arch/arm/mach-exynos4/pm.c
+++ b/arch/arm/mach-exynos4/pm.c
@@ -41,7 +41,6 @@ static struct sleep_save exynos4_set_clksrc[] = {
{ .reg = S5P_CLKSRC_MASK_CAM , .val = 0x11111111, },
{ .reg = S5P_CLKSRC_MASK_TV , .val = 0x00000111, },
{ .reg = S5P_CLKSRC_MASK_LCD0 , .val = 0x00001111, },
- { .reg = S5P_CLKSRC_MASK_LCD1 , .val = 0x00001111, },
{ .reg = S5P_CLKSRC_MASK_MAUDIO , .val = 0x00000001, },
{ .reg = S5P_CLKSRC_MASK_FSYS , .val = 0x01011111, },
{ .reg = S5P_CLKSRC_MASK_PERIL0 , .val = 0x01111111, },
@@ -49,6 +48,10 @@ static struct sleep_save exynos4_set_clksrc[] = {
{ .reg = S5P_CLKSRC_MASK_DMC , .val = 0x00010000, },
};
+static struct sleep_save exynos4210_set_clksrc[] = {
+ { .reg = S5P_CLKSRC_MASK_LCD1 , .val = 0x00001111, },
+};
+
static struct sleep_save exynos4_epll_save[] = {
SAVE_ITEM(S5P_EPLL_CON0),
SAVE_ITEM(S5P_EPLL_CON1),
@@ -60,77 +63,6 @@ static struct sleep_save exynos4_vpll_save[] = {
};
static struct sleep_save exynos4_core_save[] = {
- /* CMU side */
- SAVE_ITEM(S5P_CLKDIV_LEFTBUS),
- SAVE_ITEM(S5P_CLKGATE_IP_LEFTBUS),
- SAVE_ITEM(S5P_CLKDIV_RIGHTBUS),
- SAVE_ITEM(S5P_CLKGATE_IP_RIGHTBUS),
- SAVE_ITEM(S5P_CLKSRC_TOP0),
- SAVE_ITEM(S5P_CLKSRC_TOP1),
- SAVE_ITEM(S5P_CLKSRC_CAM),
- SAVE_ITEM(S5P_CLKSRC_TV),
- SAVE_ITEM(S5P_CLKSRC_MFC),
- SAVE_ITEM(S5P_CLKSRC_G3D),
- SAVE_ITEM(S5P_CLKSRC_IMAGE),
- SAVE_ITEM(S5P_CLKSRC_LCD0),
- SAVE_ITEM(S5P_CLKSRC_LCD1),
- SAVE_ITEM(S5P_CLKSRC_MAUDIO),
- SAVE_ITEM(S5P_CLKSRC_FSYS),
- SAVE_ITEM(S5P_CLKSRC_PERIL0),
- SAVE_ITEM(S5P_CLKSRC_PERIL1),
- SAVE_ITEM(S5P_CLKDIV_CAM),
- SAVE_ITEM(S5P_CLKDIV_TV),
- SAVE_ITEM(S5P_CLKDIV_MFC),
- SAVE_ITEM(S5P_CLKDIV_G3D),
- SAVE_ITEM(S5P_CLKDIV_IMAGE),
- SAVE_ITEM(S5P_CLKDIV_LCD0),
- SAVE_ITEM(S5P_CLKDIV_LCD1),
- SAVE_ITEM(S5P_CLKDIV_MAUDIO),
- SAVE_ITEM(S5P_CLKDIV_FSYS0),
- SAVE_ITEM(S5P_CLKDIV_FSYS1),
- SAVE_ITEM(S5P_CLKDIV_FSYS2),
- SAVE_ITEM(S5P_CLKDIV_FSYS3),
- SAVE_ITEM(S5P_CLKDIV_PERIL0),
- SAVE_ITEM(S5P_CLKDIV_PERIL1),
- SAVE_ITEM(S5P_CLKDIV_PERIL2),
- SAVE_ITEM(S5P_CLKDIV_PERIL3),
- SAVE_ITEM(S5P_CLKDIV_PERIL4),
- SAVE_ITEM(S5P_CLKDIV_PERIL5),
- SAVE_ITEM(S5P_CLKDIV_TOP),
- SAVE_ITEM(S5P_CLKSRC_MASK_TOP),
- SAVE_ITEM(S5P_CLKSRC_MASK_CAM),
- SAVE_ITEM(S5P_CLKSRC_MASK_TV),
- SAVE_ITEM(S5P_CLKSRC_MASK_LCD0),
- SAVE_ITEM(S5P_CLKSRC_MASK_LCD1),
- SAVE_ITEM(S5P_CLKSRC_MASK_MAUDIO),
- SAVE_ITEM(S5P_CLKSRC_MASK_FSYS),
- SAVE_ITEM(S5P_CLKSRC_MASK_PERIL0),
- SAVE_ITEM(S5P_CLKSRC_MASK_PERIL1),
- SAVE_ITEM(S5P_CLKDIV2_RATIO),
- SAVE_ITEM(S5P_CLKGATE_SCLKCAM),
- SAVE_ITEM(S5P_CLKGATE_IP_CAM),
- SAVE_ITEM(S5P_CLKGATE_IP_TV),
- SAVE_ITEM(S5P_CLKGATE_IP_MFC),
- SAVE_ITEM(S5P_CLKGATE_IP_G3D),
- SAVE_ITEM(S5P_CLKGATE_IP_IMAGE),
- SAVE_ITEM(S5P_CLKGATE_IP_LCD0),
- SAVE_ITEM(S5P_CLKGATE_IP_LCD1),
- SAVE_ITEM(S5P_CLKGATE_IP_FSYS),
- SAVE_ITEM(S5P_CLKGATE_IP_GPS),
- SAVE_ITEM(S5P_CLKGATE_IP_PERIL),
- SAVE_ITEM(S5P_CLKGATE_IP_PERIR),
- SAVE_ITEM(S5P_CLKGATE_BLOCK),
- SAVE_ITEM(S5P_CLKSRC_MASK_DMC),
- SAVE_ITEM(S5P_CLKSRC_DMC),
- SAVE_ITEM(S5P_CLKDIV_DMC0),
- SAVE_ITEM(S5P_CLKDIV_DMC1),
- SAVE_ITEM(S5P_CLKGATE_IP_DMC),
- SAVE_ITEM(S5P_CLKSRC_CPU),
- SAVE_ITEM(S5P_CLKDIV_CPU),
- SAVE_ITEM(S5P_CLKDIV_CPU + 0x4),
- SAVE_ITEM(S5P_CLKGATE_SCLKCPU),
- SAVE_ITEM(S5P_CLKGATE_IP_CPU),
-
/* GIC side */
SAVE_ITEM(S5P_VA_GIC_CPU + 0x000),
SAVE_ITEM(S5P_VA_GIC_CPU + 0x004),
@@ -268,6 +200,9 @@ static void exynos4_pm_prepare(void)
s3c_pm_do_restore_core(exynos4_set_clksrc, ARRAY_SIZE(exynos4_set_clksrc));
+ if (soc_is_exynos4210())
+ s3c_pm_do_restore_core(exynos4210_set_clksrc, ARRAY_SIZE(exynos4210_set_clksrc));
+
}
static int exynos4_pm_add(struct sys_device *sysdev)
--
1.7.1
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH 3/5] ARM: EXYNOS4: Add support PM for EXYNOS4212
@ 2011-08-24 13:25 ` Kukjin Kim
0 siblings, 0 replies; 20+ messages in thread
From: Kukjin Kim @ 2011-08-24 13:25 UTC (permalink / raw)
To: linux-arm-kernel
From: Jonghwan Choi <jhbird.choi@samsung.com>
This patch moves regarding clock stuff of PM into clock
file to support PM on EXYNOS4210 and EXYNOS4212 with one
single kernel image. Because some clock registers are
different on each SoCs.
Signed-off-by: Jonghwan Choi <jhbird.choi@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
---
arch/arm/mach-exynos4/clock-exynos4210.c | 38 ++++++++++
arch/arm/mach-exynos4/clock-exynos4212.c | 34 +++++++++
arch/arm/mach-exynos4/clock.c | 89 +++++++++++++++++++++++
arch/arm/mach-exynos4/include/mach/regs-clock.h | 4 +
arch/arm/mach-exynos4/pm.c | 79 ++------------------
5 files changed, 172 insertions(+), 72 deletions(-)
diff --git a/arch/arm/mach-exynos4/clock-exynos4210.c b/arch/arm/mach-exynos4/clock-exynos4210.c
index fe74b91..a4b00b7 100644
--- a/arch/arm/mach-exynos4/clock-exynos4210.c
+++ b/arch/arm/mach-exynos4/clock-exynos4210.c
@@ -15,6 +15,7 @@
#include <linux/err.h>
#include <linux/clk.h>
#include <linux/io.h>
+#include <linux/syscore_ops.h>
#include <plat/cpu-freq.h>
#include <plat/clock.h>
@@ -23,12 +24,24 @@
#include <plat/s5p-clock.h>
#include <plat/clock-clksrc.h>
#include <plat/exynos4.h>
+#include <plat/pm.h>
#include <mach/hardware.h>
#include <mach/map.h>
#include <mach/regs-clock.h>
#include <mach/exynos4-clock.h>
+static struct sleep_save exynos4210_clock_save[] = {
+ SAVE_ITEM(S5P_CLKSRC_IMAGE),
+ SAVE_ITEM(S5P_CLKSRC_LCD1),
+ SAVE_ITEM(S5P_CLKDIV_IMAGE),
+ SAVE_ITEM(S5P_CLKDIV_LCD1),
+ SAVE_ITEM(S5P_CLKSRC_MASK_LCD1),
+ SAVE_ITEM(S5P_CLKGATE_IP_IMAGE_4210),
+ SAVE_ITEM(S5P_CLKGATE_IP_LCD1),
+ SAVE_ITEM(S5P_CLKGATE_IP_PERIR_4210),
+};
+
static struct clksrc_clk *sysclks[] = {
/* nothing here yet */
};
@@ -83,6 +96,29 @@ static struct clk init_clocks_off[] = {
},
};
+#ifdef CONFIG_PM
+static int exynos4210_clock_suspend(void)
+{
+ s3c_pm_do_save(exynos4210_clock_save, ARRAY_SIZE(exynos4210_clock_save));
+
+ return 0;
+}
+
+static void exynos4210_clock_resume(void)
+{
+ s3c_pm_do_restore_core(exynos4210_clock_save, ARRAY_SIZE(exynos4210_clock_save));
+}
+
+#else
+#define exynos4210_clock_suspend NULL
+#define exynos4210_clock_resume NULL
+#endif
+
+struct syscore_ops exynos4210_clock_syscore_ops = {
+ .suspend = exynos4210_clock_suspend,
+ .resume = exynos4210_clock_resume,
+};
+
void __init exynos4210_register_clocks(void)
{
int ptr;
@@ -98,4 +134,6 @@ void __init exynos4210_register_clocks(void)
s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
+
+ register_syscore_ops(&exynos4210_clock_syscore_ops);
}
diff --git a/arch/arm/mach-exynos4/clock-exynos4212.c b/arch/arm/mach-exynos4/clock-exynos4212.c
index 5a47a3f..4638a21 100644
--- a/arch/arm/mach-exynos4/clock-exynos4212.c
+++ b/arch/arm/mach-exynos4/clock-exynos4212.c
@@ -15,6 +15,7 @@
#include <linux/err.h>
#include <linux/clk.h>
#include <linux/io.h>
+#include <linux/syscore_ops.h>
#include <plat/cpu-freq.h>
#include <plat/clock.h>
@@ -23,12 +24,20 @@
#include <plat/s5p-clock.h>
#include <plat/clock-clksrc.h>
#include <plat/exynos4.h>
+#include <plat/pm.h>
#include <mach/hardware.h>
#include <mach/map.h>
#include <mach/regs-clock.h>
#include <mach/exynos4-clock.h>
+static struct sleep_save exynos4212_clock_save[] = {
+ SAVE_ITEM(S5P_CLKSRC_IMAGE),
+ SAVE_ITEM(S5P_CLKDIV_IMAGE),
+ SAVE_ITEM(S5P_CLKGATE_IP_IMAGE_4212),
+ SAVE_ITEM(S5P_CLKGATE_IP_PERIR_4212),
+};
+
static struct clk *clk_src_mpll_user_list[] = {
[0] = &clk_fin_mpll,
[1] = &clk_mout_mpll.clk,
@@ -59,6 +68,29 @@ static struct clk init_clocks_off[] = {
/* nothing here yet */
};
+#ifdef CONFIG_PM
+static int exynos4212_clock_suspend(void)
+{
+ s3c_pm_do_save(exynos4212_clock_save, ARRAY_SIZE(exynos4212_clock_save));
+
+ return 0;
+}
+
+static void exynos4212_clock_resume(void)
+{
+ s3c_pm_do_restore_core(exynos4212_clock_save, ARRAY_SIZE(exynos4212_clock_save));
+}
+
+#else
+#define exynos4212_clock_suspend NULL
+#define exynos4212_clock_resume NULL
+#endif
+
+struct syscore_ops exynos4212_clock_syscore_ops = {
+ .suspend = exynos4212_clock_suspend,
+ .resume = exynos4212_clock_resume,
+};
+
void __init exynos4212_register_clocks(void)
{
int ptr;
@@ -81,4 +113,6 @@ void __init exynos4212_register_clocks(void)
s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
+
+ register_syscore_ops(&exynos4212_clock_syscore_ops);
}
diff --git a/arch/arm/mach-exynos4/clock.c b/arch/arm/mach-exynos4/clock.c
index eb99467..99c2a1f 100644
--- a/arch/arm/mach-exynos4/clock.c
+++ b/arch/arm/mach-exynos4/clock.c
@@ -13,6 +13,7 @@
#include <linux/kernel.h>
#include <linux/err.h>
#include <linux/io.h>
+#include <linux/syscore_ops.h>
#include <plat/cpu-freq.h>
#include <plat/clock.h>
@@ -21,12 +22,77 @@
#include <plat/s5p-clock.h>
#include <plat/clock-clksrc.h>
#include <plat/exynos4.h>
+#include <plat/pm.h>
#include <mach/map.h>
#include <mach/regs-clock.h>
#include <mach/sysmmu.h>
#include <mach/exynos4-clock.h>
+static struct sleep_save exynos4_clock_save[] = {
+ SAVE_ITEM(S5P_CLKDIV_LEFTBUS),
+ SAVE_ITEM(S5P_CLKGATE_IP_LEFTBUS),
+ SAVE_ITEM(S5P_CLKDIV_RIGHTBUS),
+ SAVE_ITEM(S5P_CLKGATE_IP_RIGHTBUS),
+ SAVE_ITEM(S5P_CLKSRC_TOP0),
+ SAVE_ITEM(S5P_CLKSRC_TOP1),
+ SAVE_ITEM(S5P_CLKSRC_CAM),
+ SAVE_ITEM(S5P_CLKSRC_TV),
+ SAVE_ITEM(S5P_CLKSRC_MFC),
+ SAVE_ITEM(S5P_CLKSRC_G3D),
+ SAVE_ITEM(S5P_CLKSRC_LCD0),
+ SAVE_ITEM(S5P_CLKSRC_MAUDIO),
+ SAVE_ITEM(S5P_CLKSRC_FSYS),
+ SAVE_ITEM(S5P_CLKSRC_PERIL0),
+ SAVE_ITEM(S5P_CLKSRC_PERIL1),
+ SAVE_ITEM(S5P_CLKDIV_CAM),
+ SAVE_ITEM(S5P_CLKDIV_TV),
+ SAVE_ITEM(S5P_CLKDIV_MFC),
+ SAVE_ITEM(S5P_CLKDIV_G3D),
+ SAVE_ITEM(S5P_CLKDIV_LCD0),
+ SAVE_ITEM(S5P_CLKDIV_MAUDIO),
+ SAVE_ITEM(S5P_CLKDIV_FSYS0),
+ SAVE_ITEM(S5P_CLKDIV_FSYS1),
+ SAVE_ITEM(S5P_CLKDIV_FSYS2),
+ SAVE_ITEM(S5P_CLKDIV_FSYS3),
+ SAVE_ITEM(S5P_CLKDIV_PERIL0),
+ SAVE_ITEM(S5P_CLKDIV_PERIL1),
+ SAVE_ITEM(S5P_CLKDIV_PERIL2),
+ SAVE_ITEM(S5P_CLKDIV_PERIL3),
+ SAVE_ITEM(S5P_CLKDIV_PERIL4),
+ SAVE_ITEM(S5P_CLKDIV_PERIL5),
+ SAVE_ITEM(S5P_CLKDIV_TOP),
+ SAVE_ITEM(S5P_CLKSRC_MASK_TOP),
+ SAVE_ITEM(S5P_CLKSRC_MASK_CAM),
+ SAVE_ITEM(S5P_CLKSRC_MASK_TV),
+ SAVE_ITEM(S5P_CLKSRC_MASK_LCD0),
+ SAVE_ITEM(S5P_CLKSRC_MASK_MAUDIO),
+ SAVE_ITEM(S5P_CLKSRC_MASK_FSYS),
+ SAVE_ITEM(S5P_CLKSRC_MASK_PERIL0),
+ SAVE_ITEM(S5P_CLKSRC_MASK_PERIL1),
+ SAVE_ITEM(S5P_CLKDIV2_RATIO),
+ SAVE_ITEM(S5P_CLKGATE_SCLKCAM),
+ SAVE_ITEM(S5P_CLKGATE_IP_CAM),
+ SAVE_ITEM(S5P_CLKGATE_IP_TV),
+ SAVE_ITEM(S5P_CLKGATE_IP_MFC),
+ SAVE_ITEM(S5P_CLKGATE_IP_G3D),
+ SAVE_ITEM(S5P_CLKGATE_IP_LCD0),
+ SAVE_ITEM(S5P_CLKGATE_IP_FSYS),
+ SAVE_ITEM(S5P_CLKGATE_IP_GPS),
+ SAVE_ITEM(S5P_CLKGATE_IP_PERIL),
+ SAVE_ITEM(S5P_CLKGATE_BLOCK),
+ SAVE_ITEM(S5P_CLKSRC_MASK_DMC),
+ SAVE_ITEM(S5P_CLKSRC_DMC),
+ SAVE_ITEM(S5P_CLKDIV_DMC0),
+ SAVE_ITEM(S5P_CLKDIV_DMC1),
+ SAVE_ITEM(S5P_CLKGATE_IP_DMC),
+ SAVE_ITEM(S5P_CLKSRC_CPU),
+ SAVE_ITEM(S5P_CLKDIV_CPU),
+ SAVE_ITEM(S5P_CLKDIV_CPU + 0x4),
+ SAVE_ITEM(S5P_CLKGATE_SCLKCPU),
+ SAVE_ITEM(S5P_CLKGATE_IP_CPU),
+};
+
struct clk clk_sclk_hdmi27m = {
.name = "sclk_hdmi27m",
.rate = 27000000,
@@ -1180,6 +1246,28 @@ static struct clk *clks[] __initdata = {
/* Nothing here yet */
};
+#ifdef CONFIG_PM
+static int exynos4_clock_suspend(void)
+{
+ s3c_pm_do_save(exynos4_clock_save, ARRAY_SIZE(exynos4_clock_save));
+ return 0;
+}
+
+static void exynos4_clock_resume(void)
+{
+ s3c_pm_do_restore_core(exynos4_clock_save, ARRAY_SIZE(exynos4_clock_save));
+}
+
+#else
+#define exynos4_clock_suspend NULL
+#define exynos4_clock_resume NULL
+#endif
+
+struct syscore_ops exynos4_clock_syscore_ops = {
+ .suspend = exynos4_clock_suspend,
+ .resume = exynos4_clock_resume,
+};
+
void __init exynos4_register_clocks(void)
{
int ptr;
@@ -1195,5 +1283,6 @@ void __init exynos4_register_clocks(void)
s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
+ register_syscore_ops(&exynos4_clock_syscore_ops);
s3c_pwmclk_init();
}
diff --git a/arch/arm/mach-exynos4/include/mach/regs-clock.h b/arch/arm/mach-exynos4/include/mach/regs-clock.h
index e75d0f8..6c37ebe 100644
--- a/arch/arm/mach-exynos4/include/mach/regs-clock.h
+++ b/arch/arm/mach-exynos4/include/mach/regs-clock.h
@@ -86,6 +86,8 @@
#define S5P_CLKGATE_IP_IMAGE (soc_is_exynos4210() ? \
S5P_CLKREG(0x0C930) : \
S5P_CLKREG(0x04930))
+#define S5P_CLKGATE_IP_IMAGE_4210 S5P_CLKREG(0x0C930)
+#define S5P_CLKGATE_IP_IMAGE_4212 S5P_CLKREG(0x04930)
#define S5P_CLKGATE_IP_LCD0 S5P_CLKREG(0x0C934)
#define S5P_CLKGATE_IP_FSYS S5P_CLKREG(0x0C940)
#define S5P_CLKGATE_IP_GPS S5P_CLKREG(0x0C94C)
@@ -93,6 +95,8 @@
#define S5P_CLKGATE_IP_PERIR (soc_is_exynos4210() ? \
S5P_CLKREG(0x0C960) : \
S5P_CLKREG(0x08960))
+#define S5P_CLKGATE_IP_PERIR_4210 S5P_CLKREG(0x0C960)
+#define S5P_CLKGATE_IP_PERIR_4212 S5P_CLKREG(0x08960)
#define S5P_CLKGATE_BLOCK S5P_CLKREG(0x0C970)
#define S5P_CLKSRC_MASK_DMC S5P_CLKREG(0x10300)
diff --git a/arch/arm/mach-exynos4/pm.c b/arch/arm/mach-exynos4/pm.c
index bc6ca94..62e4f43 100644
--- a/arch/arm/mach-exynos4/pm.c
+++ b/arch/arm/mach-exynos4/pm.c
@@ -41,7 +41,6 @@ static struct sleep_save exynos4_set_clksrc[] = {
{ .reg = S5P_CLKSRC_MASK_CAM , .val = 0x11111111, },
{ .reg = S5P_CLKSRC_MASK_TV , .val = 0x00000111, },
{ .reg = S5P_CLKSRC_MASK_LCD0 , .val = 0x00001111, },
- { .reg = S5P_CLKSRC_MASK_LCD1 , .val = 0x00001111, },
{ .reg = S5P_CLKSRC_MASK_MAUDIO , .val = 0x00000001, },
{ .reg = S5P_CLKSRC_MASK_FSYS , .val = 0x01011111, },
{ .reg = S5P_CLKSRC_MASK_PERIL0 , .val = 0x01111111, },
@@ -49,6 +48,10 @@ static struct sleep_save exynos4_set_clksrc[] = {
{ .reg = S5P_CLKSRC_MASK_DMC , .val = 0x00010000, },
};
+static struct sleep_save exynos4210_set_clksrc[] = {
+ { .reg = S5P_CLKSRC_MASK_LCD1 , .val = 0x00001111, },
+};
+
static struct sleep_save exynos4_epll_save[] = {
SAVE_ITEM(S5P_EPLL_CON0),
SAVE_ITEM(S5P_EPLL_CON1),
@@ -60,77 +63,6 @@ static struct sleep_save exynos4_vpll_save[] = {
};
static struct sleep_save exynos4_core_save[] = {
- /* CMU side */
- SAVE_ITEM(S5P_CLKDIV_LEFTBUS),
- SAVE_ITEM(S5P_CLKGATE_IP_LEFTBUS),
- SAVE_ITEM(S5P_CLKDIV_RIGHTBUS),
- SAVE_ITEM(S5P_CLKGATE_IP_RIGHTBUS),
- SAVE_ITEM(S5P_CLKSRC_TOP0),
- SAVE_ITEM(S5P_CLKSRC_TOP1),
- SAVE_ITEM(S5P_CLKSRC_CAM),
- SAVE_ITEM(S5P_CLKSRC_TV),
- SAVE_ITEM(S5P_CLKSRC_MFC),
- SAVE_ITEM(S5P_CLKSRC_G3D),
- SAVE_ITEM(S5P_CLKSRC_IMAGE),
- SAVE_ITEM(S5P_CLKSRC_LCD0),
- SAVE_ITEM(S5P_CLKSRC_LCD1),
- SAVE_ITEM(S5P_CLKSRC_MAUDIO),
- SAVE_ITEM(S5P_CLKSRC_FSYS),
- SAVE_ITEM(S5P_CLKSRC_PERIL0),
- SAVE_ITEM(S5P_CLKSRC_PERIL1),
- SAVE_ITEM(S5P_CLKDIV_CAM),
- SAVE_ITEM(S5P_CLKDIV_TV),
- SAVE_ITEM(S5P_CLKDIV_MFC),
- SAVE_ITEM(S5P_CLKDIV_G3D),
- SAVE_ITEM(S5P_CLKDIV_IMAGE),
- SAVE_ITEM(S5P_CLKDIV_LCD0),
- SAVE_ITEM(S5P_CLKDIV_LCD1),
- SAVE_ITEM(S5P_CLKDIV_MAUDIO),
- SAVE_ITEM(S5P_CLKDIV_FSYS0),
- SAVE_ITEM(S5P_CLKDIV_FSYS1),
- SAVE_ITEM(S5P_CLKDIV_FSYS2),
- SAVE_ITEM(S5P_CLKDIV_FSYS3),
- SAVE_ITEM(S5P_CLKDIV_PERIL0),
- SAVE_ITEM(S5P_CLKDIV_PERIL1),
- SAVE_ITEM(S5P_CLKDIV_PERIL2),
- SAVE_ITEM(S5P_CLKDIV_PERIL3),
- SAVE_ITEM(S5P_CLKDIV_PERIL4),
- SAVE_ITEM(S5P_CLKDIV_PERIL5),
- SAVE_ITEM(S5P_CLKDIV_TOP),
- SAVE_ITEM(S5P_CLKSRC_MASK_TOP),
- SAVE_ITEM(S5P_CLKSRC_MASK_CAM),
- SAVE_ITEM(S5P_CLKSRC_MASK_TV),
- SAVE_ITEM(S5P_CLKSRC_MASK_LCD0),
- SAVE_ITEM(S5P_CLKSRC_MASK_LCD1),
- SAVE_ITEM(S5P_CLKSRC_MASK_MAUDIO),
- SAVE_ITEM(S5P_CLKSRC_MASK_FSYS),
- SAVE_ITEM(S5P_CLKSRC_MASK_PERIL0),
- SAVE_ITEM(S5P_CLKSRC_MASK_PERIL1),
- SAVE_ITEM(S5P_CLKDIV2_RATIO),
- SAVE_ITEM(S5P_CLKGATE_SCLKCAM),
- SAVE_ITEM(S5P_CLKGATE_IP_CAM),
- SAVE_ITEM(S5P_CLKGATE_IP_TV),
- SAVE_ITEM(S5P_CLKGATE_IP_MFC),
- SAVE_ITEM(S5P_CLKGATE_IP_G3D),
- SAVE_ITEM(S5P_CLKGATE_IP_IMAGE),
- SAVE_ITEM(S5P_CLKGATE_IP_LCD0),
- SAVE_ITEM(S5P_CLKGATE_IP_LCD1),
- SAVE_ITEM(S5P_CLKGATE_IP_FSYS),
- SAVE_ITEM(S5P_CLKGATE_IP_GPS),
- SAVE_ITEM(S5P_CLKGATE_IP_PERIL),
- SAVE_ITEM(S5P_CLKGATE_IP_PERIR),
- SAVE_ITEM(S5P_CLKGATE_BLOCK),
- SAVE_ITEM(S5P_CLKSRC_MASK_DMC),
- SAVE_ITEM(S5P_CLKSRC_DMC),
- SAVE_ITEM(S5P_CLKDIV_DMC0),
- SAVE_ITEM(S5P_CLKDIV_DMC1),
- SAVE_ITEM(S5P_CLKGATE_IP_DMC),
- SAVE_ITEM(S5P_CLKSRC_CPU),
- SAVE_ITEM(S5P_CLKDIV_CPU),
- SAVE_ITEM(S5P_CLKDIV_CPU + 0x4),
- SAVE_ITEM(S5P_CLKGATE_SCLKCPU),
- SAVE_ITEM(S5P_CLKGATE_IP_CPU),
-
/* GIC side */
SAVE_ITEM(S5P_VA_GIC_CPU + 0x000),
SAVE_ITEM(S5P_VA_GIC_CPU + 0x004),
@@ -268,6 +200,9 @@ static void exynos4_pm_prepare(void)
s3c_pm_do_restore_core(exynos4_set_clksrc, ARRAY_SIZE(exynos4_set_clksrc));
+ if (soc_is_exynos4210())
+ s3c_pm_do_restore_core(exynos4210_set_clksrc, ARRAY_SIZE(exynos4210_set_clksrc));
+
}
static int exynos4_pm_add(struct sys_device *sysdev)
--
1.7.1
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH 4/5] ARM: EXYNOS4: Add support SMDK4212 Board
2011-08-24 13:25 ` Kukjin Kim
@ 2011-08-24 13:25 ` Kukjin Kim
-1 siblings, 0 replies; 20+ messages in thread
From: Kukjin Kim @ 2011-08-24 13:25 UTC (permalink / raw)
To: linux-arm-kernel, linux-samsung-soc; +Cc: ben-linux, Kukjin Kim
This patch adds mach-smdk4212.c to support SMDK4212 board.
Now it can support HSMMCs, I2Cs, RTC, WDT and Keypad. Other
features will be supported next time.
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
---
arch/arm/mach-exynos4/Kconfig | 25 +++
arch/arm/mach-exynos4/Makefile | 2 +
arch/arm/mach-exynos4/mach-smdk4212.c | 292 +++++++++++++++++++++++++++++++++
3 files changed, 319 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/mach-exynos4/mach-smdk4212.c
diff --git a/arch/arm/mach-exynos4/Kconfig b/arch/arm/mach-exynos4/Kconfig
index 0b40289..f4ec583 100644
--- a/arch/arm/mach-exynos4/Kconfig
+++ b/arch/arm/mach-exynos4/Kconfig
@@ -116,6 +116,8 @@ config EXYNOS4_SETUP_USB_PHY
menu "EXYNOS4 Machines"
+comment "EXYNOS4210 Boards"
+
config MACH_SMDKC210
bool "SMDKC210"
select MACH_SMDKV310
@@ -208,6 +210,29 @@ config MACH_NURI
help
Machine support for Samsung Mobile NURI Board.
+comment "EXYNOS4212 Boards"
+
+config MACH_SMDK4212
+ bool "SMDK4212"
+ select SOC_EXYNOS4212
+ select S3C_DEV_HSMMC2
+ select S3C_DEV_HSMMC3
+ select S3C_DEV_I2C1
+ select S3C_DEV_I2C3
+ select S3C_DEV_I2C7
+ select S3C_DEV_RTC
+ select S3C_DEV_WDT
+ select SAMSUNG_DEV_BACKLIGHT
+ select SAMSUNG_DEV_KEYPAD
+ select SAMSUNG_DEV_PWM
+ select EXYNOS4_SETUP_I2C1
+ select EXYNOS4_SETUP_I2C3
+ select EXYNOS4_SETUP_I2C7
+ select EXYNOS4_SETUP_KEYPAD
+ select EXYNOS4_SETUP_SDHCI
+ help
+ Machine support for Samsung SMDK4212
+
endmenu
comment "Configuration for HSMMC bus width"
diff --git a/arch/arm/mach-exynos4/Makefile b/arch/arm/mach-exynos4/Makefile
index 4624457..64ffad4 100644
--- a/arch/arm/mach-exynos4/Makefile
+++ b/arch/arm/mach-exynos4/Makefile
@@ -33,6 +33,8 @@ obj-$(CONFIG_MACH_ARMLEX4210) += mach-armlex4210.o
obj-$(CONFIG_MACH_UNIVERSAL_C210) += mach-universal_c210.o
obj-$(CONFIG_MACH_NURI) += mach-nuri.o
+obj-$(CONFIG_MACH_SMDK4212) += mach-smdk4212.o
+
# device support
obj-y += dev-audio.o
diff --git a/arch/arm/mach-exynos4/mach-smdk4212.c b/arch/arm/mach-exynos4/mach-smdk4212.c
new file mode 100644
index 0000000..3479a93
--- /dev/null
+++ b/arch/arm/mach-exynos4/mach-smdk4212.c
@@ -0,0 +1,292 @@
+/*
+ * linux/arch/arm/mach-exynos4/mach-smdk4212.c
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/gpio.h>
+#include <linux/i2c.h>
+#include <linux/input.h>
+#include <linux/io.h>
+#include <linux/mfd/max8997.h>
+#include <linux/mmc/host.h>
+#include <linux/platform_device.h>
+#include <linux/pwm_backlight.h>
+#include <linux/regulator/machine.h>
+#include <linux/serial_core.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach-types.h>
+
+#include <plat/backlight.h>
+#include <plat/clock.h>
+#include <plat/cpu.h>
+#include <plat/devs.h>
+#include <plat/exynos4.h>
+#include <plat/gpio-cfg.h>
+#include <plat/iic.h>
+#include <plat/keypad.h>
+#include <plat/regs-serial.h>
+#include <plat/sdhci.h>
+
+#include <mach/map.h>
+
+/* Following are default values for UCON, ULCON and UFCON UART registers */
+#define SMDK4212_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
+ S3C2410_UCON_RXILEVEL | \
+ S3C2410_UCON_TXIRQMODE | \
+ S3C2410_UCON_RXIRQMODE | \
+ S3C2410_UCON_RXFIFO_TOI | \
+ S3C2443_UCON_RXERR_IRQEN)
+
+#define SMDK4212_ULCON_DEFAULT S3C2410_LCON_CS8
+
+#define SMDK4212_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \
+ S5PV210_UFCON_TXTRIG4 | \
+ S5PV210_UFCON_RXTRIG4)
+
+static struct s3c2410_uartcfg smdk4212_uartcfgs[] __initdata = {
+ [0] = {
+ .hwport = 0,
+ .flags = 0,
+ .ucon = SMDK4212_UCON_DEFAULT,
+ .ulcon = SMDK4212_ULCON_DEFAULT,
+ .ufcon = SMDK4212_UFCON_DEFAULT,
+ },
+ [1] = {
+ .hwport = 1,
+ .flags = 0,
+ .ucon = SMDK4212_UCON_DEFAULT,
+ .ulcon = SMDK4212_ULCON_DEFAULT,
+ .ufcon = SMDK4212_UFCON_DEFAULT,
+ },
+ [2] = {
+ .hwport = 2,
+ .flags = 0,
+ .ucon = SMDK4212_UCON_DEFAULT,
+ .ulcon = SMDK4212_ULCON_DEFAULT,
+ .ufcon = SMDK4212_UFCON_DEFAULT,
+ },
+ [3] = {
+ .hwport = 3,
+ .flags = 0,
+ .ucon = SMDK4212_UCON_DEFAULT,
+ .ulcon = SMDK4212_ULCON_DEFAULT,
+ .ufcon = SMDK4212_UFCON_DEFAULT,
+ },
+};
+
+static struct s3c_sdhci_platdata smdk4212_hsmmc2_pdata __initdata = {
+ .cd_type = S3C_SDHCI_CD_INTERNAL,
+ .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
+#ifdef CONFIG_EXYNOS4_SDHCI_CH2_8BIT
+ .max_width = 8,
+ .host_caps = MMC_CAP_8_BIT_DATA,
+#endif
+};
+
+static struct s3c_sdhci_platdata smdk4212_hsmmc3_pdata __initdata = {
+ .cd_type = S3C_SDHCI_CD_INTERNAL,
+ .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
+};
+
+static struct regulator_consumer_supply max8997_buck1 =
+ REGULATOR_SUPPLY("vdd_arm", NULL);
+
+static struct regulator_consumer_supply max8997_buck2 =
+ REGULATOR_SUPPLY("vdd_int", NULL);
+
+static struct regulator_consumer_supply max8997_buck3 =
+ REGULATOR_SUPPLY("vdd_g3d", NULL);
+
+static struct regulator_init_data max8997_buck1_data = {
+ .constraints = {
+ .name = "VDD_ARM_SMDK4212",
+ .min_uV = 925000,
+ .max_uV = 1350000,
+ .always_on = 1,
+ .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
+ .state_mem = {
+ .disabled = 1,
+ },
+ },
+ .num_consumer_supplies = 1,
+ .consumer_supplies = &max8997_buck1,
+};
+
+static struct regulator_init_data max8997_buck2_data = {
+ .constraints = {
+ .name = "VDD_INT_SMDK4212",
+ .min_uV = 950000,
+ .max_uV = 1150000,
+ .always_on = 1,
+ .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
+ .state_mem = {
+ .disabled = 1,
+ },
+ },
+ .num_consumer_supplies = 1,
+ .consumer_supplies = &max8997_buck2,
+};
+
+static struct regulator_init_data max8997_buck3_data = {
+ .constraints = {
+ .name = "VDD_G3D_SMDK4212",
+ .min_uV = 950000,
+ .max_uV = 1150000,
+ .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
+ REGULATOR_CHANGE_STATUS,
+ .state_mem = {
+ .disabled = 1,
+ },
+ },
+ .num_consumer_supplies = 1,
+ .consumer_supplies = &max8997_buck3,
+};
+
+static struct max8997_regulator_data smdk4212_max8997_regulators[] = {
+ { MAX8997_BUCK1, &max8997_buck1_data },
+ { MAX8997_BUCK2, &max8997_buck2_data },
+ { MAX8997_BUCK3, &max8997_buck3_data },
+};
+
+static struct max8997_platform_data smdk4212_max8997_pdata = {
+ .num_regulators = ARRAY_SIZE(smdk4212_max8997_regulators),
+ .regulators = smdk4212_max8997_regulators,
+
+ .buck1_voltage[0] = 1100000, /* 1.1V */
+ .buck1_voltage[1] = 1100000, /* 1.1V */
+ .buck1_voltage[2] = 1100000, /* 1.1V */
+ .buck1_voltage[3] = 1100000, /* 1.1V */
+ .buck1_voltage[4] = 1100000, /* 1.1V */
+ .buck1_voltage[5] = 1100000, /* 1.1V */
+ .buck1_voltage[6] = 1000000, /* 1.0V */
+ .buck1_voltage[7] = 950000, /* 0.95V */
+
+ .buck2_voltage[0] = 1100000, /* 1.1V */
+ .buck2_voltage[1] = 1000000, /* 1.0V */
+ .buck2_voltage[2] = 950000, /* 0.95V */
+ .buck2_voltage[3] = 900000, /* 0.9V */
+ .buck2_voltage[4] = 1100000, /* 1.1V */
+ .buck2_voltage[5] = 1000000, /* 1.0V */
+ .buck2_voltage[6] = 950000, /* 0.95V */
+ .buck2_voltage[7] = 900000, /* 0.9V */
+
+ .buck5_voltage[0] = 1100000, /* 1.1V */
+ .buck5_voltage[1] = 1100000, /* 1.1V */
+ .buck5_voltage[2] = 1100000, /* 1.1V */
+ .buck5_voltage[3] = 1100000, /* 1.1V */
+ .buck5_voltage[4] = 1100000, /* 1.1V */
+ .buck5_voltage[5] = 1100000, /* 1.1V */
+ .buck5_voltage[6] = 1100000, /* 1.1V */
+ .buck5_voltage[7] = 1100000, /* 1.1V */
+};
+
+static struct i2c_board_info smdk4212_i2c_devs0[] __initdata = {
+ {
+ I2C_BOARD_INFO("max8997", 0x66),
+ .platform_data = &smdk4212_max8997_pdata,
+ }
+};
+
+static struct i2c_board_info smdk4212_i2c_devs1[] __initdata = {
+ { I2C_BOARD_INFO("wm8994", 0x1a), }
+};
+
+static struct i2c_board_info smdk4212_i2c_devs3[] __initdata = {
+ /* nothing here yet */
+};
+
+static struct i2c_board_info smdk4212_i2c_devs7[] __initdata = {
+ /* nothing here yet */
+};
+
+static struct samsung_bl_gpio_info smdk4212_bl_gpio_info = {
+ .no = EXYNOS4_GPD0(1),
+ .func = S3C_GPIO_SFN(2),
+};
+
+static struct platform_pwm_backlight_data smdk4212_bl_data = {
+ .pwm_id = 1,
+ .pwm_period_ns = 1000,
+};
+
+static uint32_t smdk4212_keymap[] __initdata = {
+ /* KEY(row, col, keycode) */
+ KEY(1, 0, KEY_D), KEY(1, 1, KEY_A), KEY(1, 2, KEY_B),
+ KEY(1, 3, KEY_E), KEY(1, 4, KEY_C)
+};
+
+static struct matrix_keymap_data smdk4212_keymap_data __initdata = {
+ .keymap = smdk4212_keymap,
+ .keymap_size = ARRAY_SIZE(smdk4212_keymap),
+};
+
+static struct samsung_keypad_platdata smdk4212_keypad_data __initdata = {
+ .keymap_data = &smdk4212_keymap_data,
+ .rows = 2,
+ .cols = 5,
+};
+
+static struct platform_device *smdk4212_devices[] __initdata = {
+ &s3c_device_hsmmc2,
+ &s3c_device_hsmmc3,
+ &s3c_device_i2c0,
+ &s3c_device_i2c1,
+ &s3c_device_i2c3,
+ &s3c_device_i2c7,
+ &s3c_device_rtc,
+ &s3c_device_wdt,
+ &samsung_device_keypad,
+};
+
+static void __init smdk4212_map_io(void)
+{
+ clk_xusbxti.rate = 24000000;
+
+ s5p_init_io(NULL, 0, S5P_VA_CHIPID);
+ s3c24xx_init_clocks(clk_xusbxti.rate);
+ s3c24xx_init_uarts(smdk4212_uartcfgs, ARRAY_SIZE(smdk4212_uartcfgs));
+}
+
+static void __init smdk4212_machine_init(void)
+{
+ s3c_i2c0_set_platdata(NULL);
+ i2c_register_board_info(0, smdk4212_i2c_devs0,
+ ARRAY_SIZE(smdk4212_i2c_devs0));
+
+ s3c_i2c1_set_platdata(NULL);
+ i2c_register_board_info(1, smdk4212_i2c_devs1,
+ ARRAY_SIZE(smdk4212_i2c_devs1));
+
+ s3c_i2c3_set_platdata(NULL);
+ i2c_register_board_info(3, smdk4212_i2c_devs3,
+ ARRAY_SIZE(smdk4212_i2c_devs3));
+
+ s3c_i2c7_set_platdata(NULL);
+ i2c_register_board_info(7, smdk4212_i2c_devs7,
+ ARRAY_SIZE(smdk4212_i2c_devs7));
+
+ samsung_bl_set(&smdk4212_bl_gpio_info, &smdk4212_bl_data);
+
+ samsung_keypad_set_platdata(&smdk4212_keypad_data);
+
+ s3c_sdhci2_set_platdata(&smdk4212_hsmmc2_pdata);
+ s3c_sdhci3_set_platdata(&smdk4212_hsmmc3_pdata);
+
+ platform_add_devices(smdk4212_devices, ARRAY_SIZE(smdk4212_devices));
+}
+
+MACHINE_START(SMDK4212, "SMDK4212")
+ /* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
+ .boot_params = S5P_PA_SDRAM + 0x100,
+ .init_irq = exynos4_init_irq,
+ .map_io = smdk4212_map_io,
+ .init_machine = smdk4212_machine_init,
+ .timer = &exynos4_timer,
+MACHINE_END
--
1.7.1
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH 4/5] ARM: EXYNOS4: Add support SMDK4212 Board
@ 2011-08-24 13:25 ` Kukjin Kim
0 siblings, 0 replies; 20+ messages in thread
From: Kukjin Kim @ 2011-08-24 13:25 UTC (permalink / raw)
To: linux-arm-kernel
This patch adds mach-smdk4212.c to support SMDK4212 board.
Now it can support HSMMCs, I2Cs, RTC, WDT and Keypad. Other
features will be supported next time.
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
---
arch/arm/mach-exynos4/Kconfig | 25 +++
arch/arm/mach-exynos4/Makefile | 2 +
arch/arm/mach-exynos4/mach-smdk4212.c | 292 +++++++++++++++++++++++++++++++++
3 files changed, 319 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/mach-exynos4/mach-smdk4212.c
diff --git a/arch/arm/mach-exynos4/Kconfig b/arch/arm/mach-exynos4/Kconfig
index 0b40289..f4ec583 100644
--- a/arch/arm/mach-exynos4/Kconfig
+++ b/arch/arm/mach-exynos4/Kconfig
@@ -116,6 +116,8 @@ config EXYNOS4_SETUP_USB_PHY
menu "EXYNOS4 Machines"
+comment "EXYNOS4210 Boards"
+
config MACH_SMDKC210
bool "SMDKC210"
select MACH_SMDKV310
@@ -208,6 +210,29 @@ config MACH_NURI
help
Machine support for Samsung Mobile NURI Board.
+comment "EXYNOS4212 Boards"
+
+config MACH_SMDK4212
+ bool "SMDK4212"
+ select SOC_EXYNOS4212
+ select S3C_DEV_HSMMC2
+ select S3C_DEV_HSMMC3
+ select S3C_DEV_I2C1
+ select S3C_DEV_I2C3
+ select S3C_DEV_I2C7
+ select S3C_DEV_RTC
+ select S3C_DEV_WDT
+ select SAMSUNG_DEV_BACKLIGHT
+ select SAMSUNG_DEV_KEYPAD
+ select SAMSUNG_DEV_PWM
+ select EXYNOS4_SETUP_I2C1
+ select EXYNOS4_SETUP_I2C3
+ select EXYNOS4_SETUP_I2C7
+ select EXYNOS4_SETUP_KEYPAD
+ select EXYNOS4_SETUP_SDHCI
+ help
+ Machine support for Samsung SMDK4212
+
endmenu
comment "Configuration for HSMMC bus width"
diff --git a/arch/arm/mach-exynos4/Makefile b/arch/arm/mach-exynos4/Makefile
index 4624457..64ffad4 100644
--- a/arch/arm/mach-exynos4/Makefile
+++ b/arch/arm/mach-exynos4/Makefile
@@ -33,6 +33,8 @@ obj-$(CONFIG_MACH_ARMLEX4210) += mach-armlex4210.o
obj-$(CONFIG_MACH_UNIVERSAL_C210) += mach-universal_c210.o
obj-$(CONFIG_MACH_NURI) += mach-nuri.o
+obj-$(CONFIG_MACH_SMDK4212) += mach-smdk4212.o
+
# device support
obj-y += dev-audio.o
diff --git a/arch/arm/mach-exynos4/mach-smdk4212.c b/arch/arm/mach-exynos4/mach-smdk4212.c
new file mode 100644
index 0000000..3479a93
--- /dev/null
+++ b/arch/arm/mach-exynos4/mach-smdk4212.c
@@ -0,0 +1,292 @@
+/*
+ * linux/arch/arm/mach-exynos4/mach-smdk4212.c
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/gpio.h>
+#include <linux/i2c.h>
+#include <linux/input.h>
+#include <linux/io.h>
+#include <linux/mfd/max8997.h>
+#include <linux/mmc/host.h>
+#include <linux/platform_device.h>
+#include <linux/pwm_backlight.h>
+#include <linux/regulator/machine.h>
+#include <linux/serial_core.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach-types.h>
+
+#include <plat/backlight.h>
+#include <plat/clock.h>
+#include <plat/cpu.h>
+#include <plat/devs.h>
+#include <plat/exynos4.h>
+#include <plat/gpio-cfg.h>
+#include <plat/iic.h>
+#include <plat/keypad.h>
+#include <plat/regs-serial.h>
+#include <plat/sdhci.h>
+
+#include <mach/map.h>
+
+/* Following are default values for UCON, ULCON and UFCON UART registers */
+#define SMDK4212_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
+ S3C2410_UCON_RXILEVEL | \
+ S3C2410_UCON_TXIRQMODE | \
+ S3C2410_UCON_RXIRQMODE | \
+ S3C2410_UCON_RXFIFO_TOI | \
+ S3C2443_UCON_RXERR_IRQEN)
+
+#define SMDK4212_ULCON_DEFAULT S3C2410_LCON_CS8
+
+#define SMDK4212_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \
+ S5PV210_UFCON_TXTRIG4 | \
+ S5PV210_UFCON_RXTRIG4)
+
+static struct s3c2410_uartcfg smdk4212_uartcfgs[] __initdata = {
+ [0] = {
+ .hwport = 0,
+ .flags = 0,
+ .ucon = SMDK4212_UCON_DEFAULT,
+ .ulcon = SMDK4212_ULCON_DEFAULT,
+ .ufcon = SMDK4212_UFCON_DEFAULT,
+ },
+ [1] = {
+ .hwport = 1,
+ .flags = 0,
+ .ucon = SMDK4212_UCON_DEFAULT,
+ .ulcon = SMDK4212_ULCON_DEFAULT,
+ .ufcon = SMDK4212_UFCON_DEFAULT,
+ },
+ [2] = {
+ .hwport = 2,
+ .flags = 0,
+ .ucon = SMDK4212_UCON_DEFAULT,
+ .ulcon = SMDK4212_ULCON_DEFAULT,
+ .ufcon = SMDK4212_UFCON_DEFAULT,
+ },
+ [3] = {
+ .hwport = 3,
+ .flags = 0,
+ .ucon = SMDK4212_UCON_DEFAULT,
+ .ulcon = SMDK4212_ULCON_DEFAULT,
+ .ufcon = SMDK4212_UFCON_DEFAULT,
+ },
+};
+
+static struct s3c_sdhci_platdata smdk4212_hsmmc2_pdata __initdata = {
+ .cd_type = S3C_SDHCI_CD_INTERNAL,
+ .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
+#ifdef CONFIG_EXYNOS4_SDHCI_CH2_8BIT
+ .max_width = 8,
+ .host_caps = MMC_CAP_8_BIT_DATA,
+#endif
+};
+
+static struct s3c_sdhci_platdata smdk4212_hsmmc3_pdata __initdata = {
+ .cd_type = S3C_SDHCI_CD_INTERNAL,
+ .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
+};
+
+static struct regulator_consumer_supply max8997_buck1 =
+ REGULATOR_SUPPLY("vdd_arm", NULL);
+
+static struct regulator_consumer_supply max8997_buck2 =
+ REGULATOR_SUPPLY("vdd_int", NULL);
+
+static struct regulator_consumer_supply max8997_buck3 =
+ REGULATOR_SUPPLY("vdd_g3d", NULL);
+
+static struct regulator_init_data max8997_buck1_data = {
+ .constraints = {
+ .name = "VDD_ARM_SMDK4212",
+ .min_uV = 925000,
+ .max_uV = 1350000,
+ .always_on = 1,
+ .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
+ .state_mem = {
+ .disabled = 1,
+ },
+ },
+ .num_consumer_supplies = 1,
+ .consumer_supplies = &max8997_buck1,
+};
+
+static struct regulator_init_data max8997_buck2_data = {
+ .constraints = {
+ .name = "VDD_INT_SMDK4212",
+ .min_uV = 950000,
+ .max_uV = 1150000,
+ .always_on = 1,
+ .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
+ .state_mem = {
+ .disabled = 1,
+ },
+ },
+ .num_consumer_supplies = 1,
+ .consumer_supplies = &max8997_buck2,
+};
+
+static struct regulator_init_data max8997_buck3_data = {
+ .constraints = {
+ .name = "VDD_G3D_SMDK4212",
+ .min_uV = 950000,
+ .max_uV = 1150000,
+ .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
+ REGULATOR_CHANGE_STATUS,
+ .state_mem = {
+ .disabled = 1,
+ },
+ },
+ .num_consumer_supplies = 1,
+ .consumer_supplies = &max8997_buck3,
+};
+
+static struct max8997_regulator_data smdk4212_max8997_regulators[] = {
+ { MAX8997_BUCK1, &max8997_buck1_data },
+ { MAX8997_BUCK2, &max8997_buck2_data },
+ { MAX8997_BUCK3, &max8997_buck3_data },
+};
+
+static struct max8997_platform_data smdk4212_max8997_pdata = {
+ .num_regulators = ARRAY_SIZE(smdk4212_max8997_regulators),
+ .regulators = smdk4212_max8997_regulators,
+
+ .buck1_voltage[0] = 1100000, /* 1.1V */
+ .buck1_voltage[1] = 1100000, /* 1.1V */
+ .buck1_voltage[2] = 1100000, /* 1.1V */
+ .buck1_voltage[3] = 1100000, /* 1.1V */
+ .buck1_voltage[4] = 1100000, /* 1.1V */
+ .buck1_voltage[5] = 1100000, /* 1.1V */
+ .buck1_voltage[6] = 1000000, /* 1.0V */
+ .buck1_voltage[7] = 950000, /* 0.95V */
+
+ .buck2_voltage[0] = 1100000, /* 1.1V */
+ .buck2_voltage[1] = 1000000, /* 1.0V */
+ .buck2_voltage[2] = 950000, /* 0.95V */
+ .buck2_voltage[3] = 900000, /* 0.9V */
+ .buck2_voltage[4] = 1100000, /* 1.1V */
+ .buck2_voltage[5] = 1000000, /* 1.0V */
+ .buck2_voltage[6] = 950000, /* 0.95V */
+ .buck2_voltage[7] = 900000, /* 0.9V */
+
+ .buck5_voltage[0] = 1100000, /* 1.1V */
+ .buck5_voltage[1] = 1100000, /* 1.1V */
+ .buck5_voltage[2] = 1100000, /* 1.1V */
+ .buck5_voltage[3] = 1100000, /* 1.1V */
+ .buck5_voltage[4] = 1100000, /* 1.1V */
+ .buck5_voltage[5] = 1100000, /* 1.1V */
+ .buck5_voltage[6] = 1100000, /* 1.1V */
+ .buck5_voltage[7] = 1100000, /* 1.1V */
+};
+
+static struct i2c_board_info smdk4212_i2c_devs0[] __initdata = {
+ {
+ I2C_BOARD_INFO("max8997", 0x66),
+ .platform_data = &smdk4212_max8997_pdata,
+ }
+};
+
+static struct i2c_board_info smdk4212_i2c_devs1[] __initdata = {
+ { I2C_BOARD_INFO("wm8994", 0x1a), }
+};
+
+static struct i2c_board_info smdk4212_i2c_devs3[] __initdata = {
+ /* nothing here yet */
+};
+
+static struct i2c_board_info smdk4212_i2c_devs7[] __initdata = {
+ /* nothing here yet */
+};
+
+static struct samsung_bl_gpio_info smdk4212_bl_gpio_info = {
+ .no = EXYNOS4_GPD0(1),
+ .func = S3C_GPIO_SFN(2),
+};
+
+static struct platform_pwm_backlight_data smdk4212_bl_data = {
+ .pwm_id = 1,
+ .pwm_period_ns = 1000,
+};
+
+static uint32_t smdk4212_keymap[] __initdata = {
+ /* KEY(row, col, keycode) */
+ KEY(1, 0, KEY_D), KEY(1, 1, KEY_A), KEY(1, 2, KEY_B),
+ KEY(1, 3, KEY_E), KEY(1, 4, KEY_C)
+};
+
+static struct matrix_keymap_data smdk4212_keymap_data __initdata = {
+ .keymap = smdk4212_keymap,
+ .keymap_size = ARRAY_SIZE(smdk4212_keymap),
+};
+
+static struct samsung_keypad_platdata smdk4212_keypad_data __initdata = {
+ .keymap_data = &smdk4212_keymap_data,
+ .rows = 2,
+ .cols = 5,
+};
+
+static struct platform_device *smdk4212_devices[] __initdata = {
+ &s3c_device_hsmmc2,
+ &s3c_device_hsmmc3,
+ &s3c_device_i2c0,
+ &s3c_device_i2c1,
+ &s3c_device_i2c3,
+ &s3c_device_i2c7,
+ &s3c_device_rtc,
+ &s3c_device_wdt,
+ &samsung_device_keypad,
+};
+
+static void __init smdk4212_map_io(void)
+{
+ clk_xusbxti.rate = 24000000;
+
+ s5p_init_io(NULL, 0, S5P_VA_CHIPID);
+ s3c24xx_init_clocks(clk_xusbxti.rate);
+ s3c24xx_init_uarts(smdk4212_uartcfgs, ARRAY_SIZE(smdk4212_uartcfgs));
+}
+
+static void __init smdk4212_machine_init(void)
+{
+ s3c_i2c0_set_platdata(NULL);
+ i2c_register_board_info(0, smdk4212_i2c_devs0,
+ ARRAY_SIZE(smdk4212_i2c_devs0));
+
+ s3c_i2c1_set_platdata(NULL);
+ i2c_register_board_info(1, smdk4212_i2c_devs1,
+ ARRAY_SIZE(smdk4212_i2c_devs1));
+
+ s3c_i2c3_set_platdata(NULL);
+ i2c_register_board_info(3, smdk4212_i2c_devs3,
+ ARRAY_SIZE(smdk4212_i2c_devs3));
+
+ s3c_i2c7_set_platdata(NULL);
+ i2c_register_board_info(7, smdk4212_i2c_devs7,
+ ARRAY_SIZE(smdk4212_i2c_devs7));
+
+ samsung_bl_set(&smdk4212_bl_gpio_info, &smdk4212_bl_data);
+
+ samsung_keypad_set_platdata(&smdk4212_keypad_data);
+
+ s3c_sdhci2_set_platdata(&smdk4212_hsmmc2_pdata);
+ s3c_sdhci3_set_platdata(&smdk4212_hsmmc3_pdata);
+
+ platform_add_devices(smdk4212_devices, ARRAY_SIZE(smdk4212_devices));
+}
+
+MACHINE_START(SMDK4212, "SMDK4212")
+ /* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
+ .boot_params = S5P_PA_SDRAM + 0x100,
+ .init_irq = exynos4_init_irq,
+ .map_io = smdk4212_map_io,
+ .init_machine = smdk4212_machine_init,
+ .timer = &exynos4_timer,
+MACHINE_END
--
1.7.1
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH 5/5] tty: Add support serial for EXYNOS4212 SoC
2011-08-24 13:25 ` Kukjin Kim
@ 2011-08-24 13:25 ` Kukjin Kim
-1 siblings, 0 replies; 20+ messages in thread
From: Kukjin Kim @ 2011-08-24 13:25 UTC (permalink / raw)
To: linux-arm-kernel, linux-samsung-soc
Cc: ben-linux, Kukjin Kim, Alan Cox, Greg Kroah-Hartman
According to add support EXYNOS4212 SoC, we need to enable
SERIAL_S5PV210 on EXYNOS4212.
Cc: Alan Cox <alan@lxorguk.ukuu.org.uk>
Cc: Greg Kroah-Hartman <gregkh@suse.de>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
---
drivers/tty/serial/Kconfig | 4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/tty/serial/Kconfig b/drivers/tty/serial/Kconfig
index 4dcb37b..bff6943 100644
--- a/drivers/tty/serial/Kconfig
+++ b/drivers/tty/serial/Kconfig
@@ -522,8 +522,8 @@ config SERIAL_S3C6400
config SERIAL_S5PV210
tristate "Samsung S5PV210 Serial port support"
- depends on SERIAL_SAMSUNG && (CPU_S5PV210 || CPU_EXYNOS4210)
- select SERIAL_SAMSUNG_UARTS_4 if (CPU_S5PV210 || CPU_EXYNOS4210)
+ depends on SERIAL_SAMSUNG && (CPU_S5PV210 || CPU_EXYNOS4210 || SOC_EXYNOS4212)
+ select SERIAL_SAMSUNG_UARTS_4 if (CPU_S5PV210 || CPU_EXYNOS4210 || SOC_EXYNOS4212)
default y
help
Serial port support for Samsung's S5P Family of SoC's
--
1.7.1
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH 5/5] tty: Add support serial for EXYNOS4212 SoC
@ 2011-08-24 13:25 ` Kukjin Kim
0 siblings, 0 replies; 20+ messages in thread
From: Kukjin Kim @ 2011-08-24 13:25 UTC (permalink / raw)
To: linux-arm-kernel
According to add support EXYNOS4212 SoC, we need to enable
SERIAL_S5PV210 on EXYNOS4212.
Cc: Alan Cox <alan@lxorguk.ukuu.org.uk>
Cc: Greg Kroah-Hartman <gregkh@suse.de>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
---
drivers/tty/serial/Kconfig | 4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/tty/serial/Kconfig b/drivers/tty/serial/Kconfig
index 4dcb37b..bff6943 100644
--- a/drivers/tty/serial/Kconfig
+++ b/drivers/tty/serial/Kconfig
@@ -522,8 +522,8 @@ config SERIAL_S3C6400
config SERIAL_S5PV210
tristate "Samsung S5PV210 Serial port support"
- depends on SERIAL_SAMSUNG && (CPU_S5PV210 || CPU_EXYNOS4210)
- select SERIAL_SAMSUNG_UARTS_4 if (CPU_S5PV210 || CPU_EXYNOS4210)
+ depends on SERIAL_SAMSUNG && (CPU_S5PV210 || CPU_EXYNOS4210 || SOC_EXYNOS4212)
+ select SERIAL_SAMSUNG_UARTS_4 if (CPU_S5PV210 || CPU_EXYNOS4210 || SOC_EXYNOS4212)
default y
help
Serial port support for Samsung's S5P Family of SoC's
--
1.7.1
^ permalink raw reply related [flat|nested] 20+ messages in thread
* Re: [PATCH 3/5] ARM: EXYNOS4: Add support PM for EXYNOS4212
2011-08-24 13:25 ` Kukjin Kim
@ 2011-08-25 7:46 ` MyungJoo Ham
-1 siblings, 0 replies; 20+ messages in thread
From: MyungJoo Ham @ 2011-08-25 7:46 UTC (permalink / raw)
To: Kukjin Kim; +Cc: linux-arm-kernel, linux-samsung-soc, ben-linux, Jonghwan Choi
On Wed, Aug 24, 2011 at 10:25 PM, Kukjin Kim <kgene.kim@samsung.com> wrote:
> From: Jonghwan Choi <jhbird.choi@samsung.com>
>
> This patch moves regarding clock stuff of PM into clock
> file to support PM on EXYNOS4210 and EXYNOS4212 with one
> single kernel image. Because some clock registers are
> different on each SoCs.
>
> Signed-off-by: Jonghwan Choi <jhbird.choi@samsung.com>
> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
> ---
> arch/arm/mach-exynos4/clock-exynos4210.c | 38 ++++++++++
> arch/arm/mach-exynos4/clock-exynos4212.c | 34 +++++++++
> arch/arm/mach-exynos4/clock.c | 89 +++++++++++++++++++++++
> arch/arm/mach-exynos4/include/mach/regs-clock.h | 4 +
> arch/arm/mach-exynos4/pm.c | 79 ++------------------
> 5 files changed, 172 insertions(+), 72 deletions(-)
>
> diff --git a/arch/arm/mach-exynos4/clock-exynos4210.c b/arch/arm/mach-exynos4/clock-exynos4210.c
> index fe74b91..a4b00b7 100644
> --- a/arch/arm/mach-exynos4/clock-exynos4210.c
> +++ b/arch/arm/mach-exynos4/clock-exynos4210.c
> +static struct sleep_save exynos4210_clock_save[] = {
> + SAVE_ITEM(S5P_CLKSRC_IMAGE),
> + SAVE_ITEM(S5P_CLKSRC_LCD1),
> + SAVE_ITEM(S5P_CLKDIV_IMAGE),
> + SAVE_ITEM(S5P_CLKDIV_LCD1),
> + SAVE_ITEM(S5P_CLKSRC_MASK_LCD1),
> + SAVE_ITEM(S5P_CLKGATE_IP_IMAGE_4210),
> + SAVE_ITEM(S5P_CLKGATE_IP_LCD1),
> + SAVE_ITEM(S5P_CLKGATE_IP_PERIR_4210),
> +};
> +
> --- a/arch/arm/mach-exynos4/clock-exynos4212.c
> +++ b/arch/arm/mach-exynos4/clock-exynos4212.c
> +static struct sleep_save exynos4212_clock_save[] = {
> + SAVE_ITEM(S5P_CLKSRC_IMAGE),
> + SAVE_ITEM(S5P_CLKDIV_IMAGE),
> + SAVE_ITEM(S5P_CLKGATE_IP_IMAGE_4212),
> + SAVE_ITEM(S5P_CLKGATE_IP_PERIR_4212),
> +};
> +
> --- a/arch/arm/mach-exynos4/clock.c
> +++ b/arch/arm/mach-exynos4/clock.c
> +static struct sleep_save exynos4_clock_save[] = {
Hello,
Is there any reason to have the following two
SAVE_ITEM(S5P_CLKSRC_IMAGE),
SAVE_ITEM(S5P_CLKDIV_IMAGE
defined at both clock-exynos4210.c and clock-exynos4212.c, not defined
at clock.c once?
Also, consider using CONFIG_PM_SLEEP rather than CONFIG_PM for
suspend/resume ops.
Cheers!
MyungJoo
--
MyungJoo Ham, Ph.D.
Mobile Software Platform Lab, DMC Business, Samsung Electronics
^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH 3/5] ARM: EXYNOS4: Add support PM for EXYNOS4212
@ 2011-08-25 7:46 ` MyungJoo Ham
0 siblings, 0 replies; 20+ messages in thread
From: MyungJoo Ham @ 2011-08-25 7:46 UTC (permalink / raw)
To: linux-arm-kernel
On Wed, Aug 24, 2011 at 10:25 PM, Kukjin Kim <kgene.kim@samsung.com> wrote:
> From: Jonghwan Choi <jhbird.choi@samsung.com>
>
> This patch moves regarding clock stuff of PM into clock
> file to support PM on EXYNOS4210 and EXYNOS4212 with one
> single kernel image. Because some clock registers are
> different on each SoCs.
>
> Signed-off-by: Jonghwan Choi <jhbird.choi@samsung.com>
> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
> ---
> ?arch/arm/mach-exynos4/clock-exynos4210.c ? ? ? ?| ? 38 ++++++++++
> ?arch/arm/mach-exynos4/clock-exynos4212.c ? ? ? ?| ? 34 +++++++++
> ?arch/arm/mach-exynos4/clock.c ? ? ? ? ? ? ? ? ? | ? 89 +++++++++++++++++++++++
> ?arch/arm/mach-exynos4/include/mach/regs-clock.h | ? ?4 +
> ?arch/arm/mach-exynos4/pm.c ? ? ? ? ? ? ? ? ? ? ?| ? 79 ++------------------
> ?5 files changed, 172 insertions(+), 72 deletions(-)
>
> diff --git a/arch/arm/mach-exynos4/clock-exynos4210.c b/arch/arm/mach-exynos4/clock-exynos4210.c
> index fe74b91..a4b00b7 100644
> --- a/arch/arm/mach-exynos4/clock-exynos4210.c
> +++ b/arch/arm/mach-exynos4/clock-exynos4210.c
> +static struct sleep_save exynos4210_clock_save[] = {
> + ? ? ? SAVE_ITEM(S5P_CLKSRC_IMAGE),
> + ? ? ? SAVE_ITEM(S5P_CLKSRC_LCD1),
> + ? ? ? SAVE_ITEM(S5P_CLKDIV_IMAGE),
> + ? ? ? SAVE_ITEM(S5P_CLKDIV_LCD1),
> + ? ? ? SAVE_ITEM(S5P_CLKSRC_MASK_LCD1),
> + ? ? ? SAVE_ITEM(S5P_CLKGATE_IP_IMAGE_4210),
> + ? ? ? SAVE_ITEM(S5P_CLKGATE_IP_LCD1),
> + ? ? ? SAVE_ITEM(S5P_CLKGATE_IP_PERIR_4210),
> +};
> +
> --- a/arch/arm/mach-exynos4/clock-exynos4212.c
> +++ b/arch/arm/mach-exynos4/clock-exynos4212.c
> +static struct sleep_save exynos4212_clock_save[] = {
> + ? ? ? SAVE_ITEM(S5P_CLKSRC_IMAGE),
> + ? ? ? SAVE_ITEM(S5P_CLKDIV_IMAGE),
> + ? ? ? SAVE_ITEM(S5P_CLKGATE_IP_IMAGE_4212),
> + ? ? ? SAVE_ITEM(S5P_CLKGATE_IP_PERIR_4212),
> +};
> +
> --- a/arch/arm/mach-exynos4/clock.c
> +++ b/arch/arm/mach-exynos4/clock.c
> +static struct sleep_save exynos4_clock_save[] = {
Hello,
Is there any reason to have the following two
SAVE_ITEM(S5P_CLKSRC_IMAGE),
SAVE_ITEM(S5P_CLKDIV_IMAGE
defined at both clock-exynos4210.c and clock-exynos4212.c, not defined
at clock.c once?
Also, consider using CONFIG_PM_SLEEP rather than CONFIG_PM for
suspend/resume ops.
Cheers!
MyungJoo
--
MyungJoo Ham, Ph.D.
Mobile Software Platform Lab, DMC Business, Samsung Electronics
^ permalink raw reply [flat|nested] 20+ messages in thread
* RE: [PATCH 3/5] ARM: EXYNOS4: Add support PM for EXYNOS4212
2011-08-25 7:46 ` MyungJoo Ham
@ 2011-08-25 23:33 ` Kukjin Kim
-1 siblings, 0 replies; 20+ messages in thread
From: Kukjin Kim @ 2011-08-25 23:33 UTC (permalink / raw)
To: 'MyungJoo Ham'
Cc: linux-arm-kernel, linux-samsung-soc, ben-linux,
'Jonghwan Choi', 'Rafael J. Wysocki'
MyungJoo Ham wrote:
>
> On Wed, Aug 24, 2011 at 10:25 PM, Kukjin Kim <kgene.kim@samsung.com>
wrote:
> > From: Jonghwan Choi <jhbird.choi@samsung.com>
> >
> > This patch moves regarding clock stuff of PM into clock
> > file to support PM on EXYNOS4210 and EXYNOS4212 with one
> > single kernel image. Because some clock registers are
> > different on each SoCs.
> >
> > Signed-off-by: Jonghwan Choi <jhbird.choi@samsung.com>
> > Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
> > ---
> > arch/arm/mach-exynos4/clock-exynos4210.c | 38 ++++++++++
> > arch/arm/mach-exynos4/clock-exynos4212.c | 34 +++++++++
> > arch/arm/mach-exynos4/clock.c | 89
> +++++++++++++++++++++++
> > arch/arm/mach-exynos4/include/mach/regs-clock.h | 4 +
> > arch/arm/mach-exynos4/pm.c | 79
++------------------
> > 5 files changed, 172 insertions(+), 72 deletions(-)
> >
> > diff --git a/arch/arm/mach-exynos4/clock-exynos4210.c b/arch/arm/mach-
> exynos4/clock-exynos4210.c
> > index fe74b91..a4b00b7 100644
> > --- a/arch/arm/mach-exynos4/clock-exynos4210.c
> > +++ b/arch/arm/mach-exynos4/clock-exynos4210.c
> > +static struct sleep_save exynos4210_clock_save[] = {
> > + SAVE_ITEM(S5P_CLKSRC_IMAGE),
> > + SAVE_ITEM(S5P_CLKSRC_LCD1),
> > + SAVE_ITEM(S5P_CLKDIV_IMAGE),
> > + SAVE_ITEM(S5P_CLKDIV_LCD1),
> > + SAVE_ITEM(S5P_CLKSRC_MASK_LCD1),
> > + SAVE_ITEM(S5P_CLKGATE_IP_IMAGE_4210),
> > + SAVE_ITEM(S5P_CLKGATE_IP_LCD1),
> > + SAVE_ITEM(S5P_CLKGATE_IP_PERIR_4210),
> > +};
> > +
> > --- a/arch/arm/mach-exynos4/clock-exynos4212.c
> > +++ b/arch/arm/mach-exynos4/clock-exynos4212.c
> > +static struct sleep_save exynos4212_clock_save[] = {
> > + SAVE_ITEM(S5P_CLKSRC_IMAGE),
> > + SAVE_ITEM(S5P_CLKDIV_IMAGE),
> > + SAVE_ITEM(S5P_CLKGATE_IP_IMAGE_4212),
> > + SAVE_ITEM(S5P_CLKGATE_IP_PERIR_4212),
> > +};
> > +
> > --- a/arch/arm/mach-exynos4/clock.c
> > +++ b/arch/arm/mach-exynos4/clock.c
> > +static struct sleep_save exynos4_clock_save[] = {
>
> Hello,
>
Hi,
> Is there any reason to have the following two
> SAVE_ITEM(S5P_CLKSRC_IMAGE),
> SAVE_ITEM(S5P_CLKDIV_IMAGE
> defined at both clock-exynos4210.c and clock-exynos4212.c, not defined
> at clock.c once?
>
Yes, I know. I just wanted to keep in mind there is a different
value(CLKGATE_IP_IMAGE) in regarding IMAGE clocks on each SoCs, and I think
need it now. Anyway thanks for your pointing out.
> Also, consider using CONFIG_PM_SLEEP rather than CONFIG_PM for
> suspend/resume ops.
>
(Cc'ed Rafael)
Well, even though CONFIG_PM_SLEEP is used in regarding syscore_ops, in this
case, using CONFIG_PM looks better.
If ARCH_SUSPEND_POSSIBLE will be selected, then CONFIG_SUSPEND is selected
and CONFIG_PM_SLEEP is selected in kernel/power/Kconfig and of course,
ARCH_SUSPEND_POSSIBLE is selected in arch/arm/Kconfig. However above
everything depends on CONFIG_PM. So I think to use CONFIG_PM is more
reasonable. In addition, it is more popular in other mainline codes now.
Hi Rafael,
How do you think about this?
Its original code is below.
---
#ifdef CONFIG_PM
static int exynos4210_clock_suspend(void)
{
s3c_pm_do_save(exynos4210_clock_save,
ARRAY_SIZE(exynos4210_clock_save));
return 0;
}
static void exynos4210_clock_resume(void)
{
s3c_pm_do_restore_core(exynos4210_clock_save,
ARRAY_SIZE(exynos4210_clock_save));
}
#else
#define exynos4210_clock_suspend NULL
#define exynos4210_clock_resume NULL
#endif
struct syscore_ops exynos4210_clock_syscore_ops = {
.suspend = exynos4210_clock_suspend,
.resume = exynos4210_clock_resume,
};
---
Thanks.
Best regards,
Kgene.
--
Kukjin Kim <kgene.kim@samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.
^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH 3/5] ARM: EXYNOS4: Add support PM for EXYNOS4212
@ 2011-08-25 23:33 ` Kukjin Kim
0 siblings, 0 replies; 20+ messages in thread
From: Kukjin Kim @ 2011-08-25 23:33 UTC (permalink / raw)
To: linux-arm-kernel
MyungJoo Ham wrote:
>
> On Wed, Aug 24, 2011 at 10:25 PM, Kukjin Kim <kgene.kim@samsung.com>
wrote:
> > From: Jonghwan Choi <jhbird.choi@samsung.com>
> >
> > This patch moves regarding clock stuff of PM into clock
> > file to support PM on EXYNOS4210 and EXYNOS4212 with one
> > single kernel image. Because some clock registers are
> > different on each SoCs.
> >
> > Signed-off-by: Jonghwan Choi <jhbird.choi@samsung.com>
> > Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
> > ---
> > ?arch/arm/mach-exynos4/clock-exynos4210.c ? ? ? ?| ? 38 ++++++++++
> > ?arch/arm/mach-exynos4/clock-exynos4212.c ? ? ? ?| ? 34 +++++++++
> > ?arch/arm/mach-exynos4/clock.c ? ? ? ? ? ? ? ? ? | ? 89
> +++++++++++++++++++++++
> > ?arch/arm/mach-exynos4/include/mach/regs-clock.h | ? ?4 +
> > ?arch/arm/mach-exynos4/pm.c ? ? ? ? ? ? ? ? ? ? ?| ? 79
++------------------
> > ?5 files changed, 172 insertions(+), 72 deletions(-)
> >
> > diff --git a/arch/arm/mach-exynos4/clock-exynos4210.c b/arch/arm/mach-
> exynos4/clock-exynos4210.c
> > index fe74b91..a4b00b7 100644
> > --- a/arch/arm/mach-exynos4/clock-exynos4210.c
> > +++ b/arch/arm/mach-exynos4/clock-exynos4210.c
> > +static struct sleep_save exynos4210_clock_save[] = {
> > + ? ? ? SAVE_ITEM(S5P_CLKSRC_IMAGE),
> > + ? ? ? SAVE_ITEM(S5P_CLKSRC_LCD1),
> > + ? ? ? SAVE_ITEM(S5P_CLKDIV_IMAGE),
> > + ? ? ? SAVE_ITEM(S5P_CLKDIV_LCD1),
> > + ? ? ? SAVE_ITEM(S5P_CLKSRC_MASK_LCD1),
> > + ? ? ? SAVE_ITEM(S5P_CLKGATE_IP_IMAGE_4210),
> > + ? ? ? SAVE_ITEM(S5P_CLKGATE_IP_LCD1),
> > + ? ? ? SAVE_ITEM(S5P_CLKGATE_IP_PERIR_4210),
> > +};
> > +
> > --- a/arch/arm/mach-exynos4/clock-exynos4212.c
> > +++ b/arch/arm/mach-exynos4/clock-exynos4212.c
> > +static struct sleep_save exynos4212_clock_save[] = {
> > + ? ? ? SAVE_ITEM(S5P_CLKSRC_IMAGE),
> > + ? ? ? SAVE_ITEM(S5P_CLKDIV_IMAGE),
> > + ? ? ? SAVE_ITEM(S5P_CLKGATE_IP_IMAGE_4212),
> > + ? ? ? SAVE_ITEM(S5P_CLKGATE_IP_PERIR_4212),
> > +};
> > +
> > --- a/arch/arm/mach-exynos4/clock.c
> > +++ b/arch/arm/mach-exynos4/clock.c
> > +static struct sleep_save exynos4_clock_save[] = {
>
> Hello,
>
Hi,
> Is there any reason to have the following two
> SAVE_ITEM(S5P_CLKSRC_IMAGE),
> SAVE_ITEM(S5P_CLKDIV_IMAGE
> defined at both clock-exynos4210.c and clock-exynos4212.c, not defined
> at clock.c once?
>
Yes, I know. I just wanted to keep in mind there is a different
value(CLKGATE_IP_IMAGE) in regarding IMAGE clocks on each SoCs, and I think
need it now. Anyway thanks for your pointing out.
> Also, consider using CONFIG_PM_SLEEP rather than CONFIG_PM for
> suspend/resume ops.
>
(Cc'ed Rafael)
Well, even though CONFIG_PM_SLEEP is used in regarding syscore_ops, in this
case, using CONFIG_PM looks better.
If ARCH_SUSPEND_POSSIBLE will be selected, then CONFIG_SUSPEND is selected
and CONFIG_PM_SLEEP is selected in kernel/power/Kconfig and of course,
ARCH_SUSPEND_POSSIBLE is selected in arch/arm/Kconfig. However above
everything depends on CONFIG_PM. So I think to use CONFIG_PM is more
reasonable. In addition, it is more popular in other mainline codes now.
Hi Rafael,
How do you think about this?
Its original code is below.
---
#ifdef CONFIG_PM
static int exynos4210_clock_suspend(void)
{
s3c_pm_do_save(exynos4210_clock_save,
ARRAY_SIZE(exynos4210_clock_save));
return 0;
}
static void exynos4210_clock_resume(void)
{
s3c_pm_do_restore_core(exynos4210_clock_save,
ARRAY_SIZE(exynos4210_clock_save));
}
#else
#define exynos4210_clock_suspend NULL
#define exynos4210_clock_resume NULL
#endif
struct syscore_ops exynos4210_clock_syscore_ops = {
.suspend = exynos4210_clock_suspend,
.resume = exynos4210_clock_resume,
};
---
Thanks.
Best regards,
Kgene.
--
Kukjin Kim <kgene.kim@samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH 3/5] ARM: EXYNOS4: Add support PM for EXYNOS4212
2011-08-25 23:33 ` Kukjin Kim
@ 2011-08-26 20:36 ` Rafael J. Wysocki
-1 siblings, 0 replies; 20+ messages in thread
From: Rafael J. Wysocki @ 2011-08-26 20:36 UTC (permalink / raw)
To: Kukjin Kim
Cc: linux-samsung-soc, 'MyungJoo Ham',
'Jonghwan Choi',
ben-linux, linux-arm-kernel
On Friday, August 26, 2011, Kukjin Kim wrote:
> MyungJoo Ham wrote:
> >
> > On Wed, Aug 24, 2011 at 10:25 PM, Kukjin Kim <kgene.kim@samsung.com>
> wrote:
> > > From: Jonghwan Choi <jhbird.choi@samsung.com>
> > >
> > > This patch moves regarding clock stuff of PM into clock
> > > file to support PM on EXYNOS4210 and EXYNOS4212 with one
> > > single kernel image. Because some clock registers are
> > > different on each SoCs.
> > >
> > > Signed-off-by: Jonghwan Choi <jhbird.choi@samsung.com>
> > > Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
> > > ---
> > > arch/arm/mach-exynos4/clock-exynos4210.c | 38 ++++++++++
> > > arch/arm/mach-exynos4/clock-exynos4212.c | 34 +++++++++
> > > arch/arm/mach-exynos4/clock.c | 89
> > +++++++++++++++++++++++
> > > arch/arm/mach-exynos4/include/mach/regs-clock.h | 4 +
> > > arch/arm/mach-exynos4/pm.c | 79
> ++------------------
> > > 5 files changed, 172 insertions(+), 72 deletions(-)
> > >
> > > diff --git a/arch/arm/mach-exynos4/clock-exynos4210.c b/arch/arm/mach-
> > exynos4/clock-exynos4210.c
> > > index fe74b91..a4b00b7 100644
> > > --- a/arch/arm/mach-exynos4/clock-exynos4210.c
> > > +++ b/arch/arm/mach-exynos4/clock-exynos4210.c
> > > +static struct sleep_save exynos4210_clock_save[] = {
> > > + SAVE_ITEM(S5P_CLKSRC_IMAGE),
> > > + SAVE_ITEM(S5P_CLKSRC_LCD1),
> > > + SAVE_ITEM(S5P_CLKDIV_IMAGE),
> > > + SAVE_ITEM(S5P_CLKDIV_LCD1),
> > > + SAVE_ITEM(S5P_CLKSRC_MASK_LCD1),
> > > + SAVE_ITEM(S5P_CLKGATE_IP_IMAGE_4210),
> > > + SAVE_ITEM(S5P_CLKGATE_IP_LCD1),
> > > + SAVE_ITEM(S5P_CLKGATE_IP_PERIR_4210),
> > > +};
> > > +
> > > --- a/arch/arm/mach-exynos4/clock-exynos4212.c
> > > +++ b/arch/arm/mach-exynos4/clock-exynos4212.c
> > > +static struct sleep_save exynos4212_clock_save[] = {
> > > + SAVE_ITEM(S5P_CLKSRC_IMAGE),
> > > + SAVE_ITEM(S5P_CLKDIV_IMAGE),
> > > + SAVE_ITEM(S5P_CLKGATE_IP_IMAGE_4212),
> > > + SAVE_ITEM(S5P_CLKGATE_IP_PERIR_4212),
> > > +};
> > > +
> > > --- a/arch/arm/mach-exynos4/clock.c
> > > +++ b/arch/arm/mach-exynos4/clock.c
> > > +static struct sleep_save exynos4_clock_save[] = {
> >
> > Hello,
> >
> Hi,
>
> > Is there any reason to have the following two
> > SAVE_ITEM(S5P_CLKSRC_IMAGE),
> > SAVE_ITEM(S5P_CLKDIV_IMAGE
> > defined at both clock-exynos4210.c and clock-exynos4212.c, not defined
> > at clock.c once?
> >
> Yes, I know. I just wanted to keep in mind there is a different
> value(CLKGATE_IP_IMAGE) in regarding IMAGE clocks on each SoCs, and I think
> need it now. Anyway thanks for your pointing out.
>
> > Also, consider using CONFIG_PM_SLEEP rather than CONFIG_PM for
> > suspend/resume ops.
> >
> (Cc'ed Rafael)
>
> Well, even though CONFIG_PM_SLEEP is used in regarding syscore_ops, in this
> case, using CONFIG_PM looks better.
>
> If ARCH_SUSPEND_POSSIBLE will be selected, then CONFIG_SUSPEND is selected
> and CONFIG_PM_SLEEP is selected in kernel/power/Kconfig and of course,
> ARCH_SUSPEND_POSSIBLE is selected in arch/arm/Kconfig. However above
> everything depends on CONFIG_PM. So I think to use CONFIG_PM is more
> reasonable. In addition, it is more popular in other mainline codes now.
>
> Hi Rafael,
> How do you think about this?
If you make syscore_ops depend on CONFIG_PM, they will be built but not
used when CONFIG_PM_RUNTIME is set and CONFIG_PM_SLEEP is unset. If you
think that's acceptable, I guess you can do it (although you may get a
few "defined but not used" warnings in that case, which don't look nice).
Thanks,
Rafael
^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH 3/5] ARM: EXYNOS4: Add support PM for EXYNOS4212
@ 2011-08-26 20:36 ` Rafael J. Wysocki
0 siblings, 0 replies; 20+ messages in thread
From: Rafael J. Wysocki @ 2011-08-26 20:36 UTC (permalink / raw)
To: linux-arm-kernel
On Friday, August 26, 2011, Kukjin Kim wrote:
> MyungJoo Ham wrote:
> >
> > On Wed, Aug 24, 2011 at 10:25 PM, Kukjin Kim <kgene.kim@samsung.com>
> wrote:
> > > From: Jonghwan Choi <jhbird.choi@samsung.com>
> > >
> > > This patch moves regarding clock stuff of PM into clock
> > > file to support PM on EXYNOS4210 and EXYNOS4212 with one
> > > single kernel image. Because some clock registers are
> > > different on each SoCs.
> > >
> > > Signed-off-by: Jonghwan Choi <jhbird.choi@samsung.com>
> > > Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
> > > ---
> > > arch/arm/mach-exynos4/clock-exynos4210.c | 38 ++++++++++
> > > arch/arm/mach-exynos4/clock-exynos4212.c | 34 +++++++++
> > > arch/arm/mach-exynos4/clock.c | 89
> > +++++++++++++++++++++++
> > > arch/arm/mach-exynos4/include/mach/regs-clock.h | 4 +
> > > arch/arm/mach-exynos4/pm.c | 79
> ++------------------
> > > 5 files changed, 172 insertions(+), 72 deletions(-)
> > >
> > > diff --git a/arch/arm/mach-exynos4/clock-exynos4210.c b/arch/arm/mach-
> > exynos4/clock-exynos4210.c
> > > index fe74b91..a4b00b7 100644
> > > --- a/arch/arm/mach-exynos4/clock-exynos4210.c
> > > +++ b/arch/arm/mach-exynos4/clock-exynos4210.c
> > > +static struct sleep_save exynos4210_clock_save[] = {
> > > + SAVE_ITEM(S5P_CLKSRC_IMAGE),
> > > + SAVE_ITEM(S5P_CLKSRC_LCD1),
> > > + SAVE_ITEM(S5P_CLKDIV_IMAGE),
> > > + SAVE_ITEM(S5P_CLKDIV_LCD1),
> > > + SAVE_ITEM(S5P_CLKSRC_MASK_LCD1),
> > > + SAVE_ITEM(S5P_CLKGATE_IP_IMAGE_4210),
> > > + SAVE_ITEM(S5P_CLKGATE_IP_LCD1),
> > > + SAVE_ITEM(S5P_CLKGATE_IP_PERIR_4210),
> > > +};
> > > +
> > > --- a/arch/arm/mach-exynos4/clock-exynos4212.c
> > > +++ b/arch/arm/mach-exynos4/clock-exynos4212.c
> > > +static struct sleep_save exynos4212_clock_save[] = {
> > > + SAVE_ITEM(S5P_CLKSRC_IMAGE),
> > > + SAVE_ITEM(S5P_CLKDIV_IMAGE),
> > > + SAVE_ITEM(S5P_CLKGATE_IP_IMAGE_4212),
> > > + SAVE_ITEM(S5P_CLKGATE_IP_PERIR_4212),
> > > +};
> > > +
> > > --- a/arch/arm/mach-exynos4/clock.c
> > > +++ b/arch/arm/mach-exynos4/clock.c
> > > +static struct sleep_save exynos4_clock_save[] = {
> >
> > Hello,
> >
> Hi,
>
> > Is there any reason to have the following two
> > SAVE_ITEM(S5P_CLKSRC_IMAGE),
> > SAVE_ITEM(S5P_CLKDIV_IMAGE
> > defined at both clock-exynos4210.c and clock-exynos4212.c, not defined
> > at clock.c once?
> >
> Yes, I know. I just wanted to keep in mind there is a different
> value(CLKGATE_IP_IMAGE) in regarding IMAGE clocks on each SoCs, and I think
> need it now. Anyway thanks for your pointing out.
>
> > Also, consider using CONFIG_PM_SLEEP rather than CONFIG_PM for
> > suspend/resume ops.
> >
> (Cc'ed Rafael)
>
> Well, even though CONFIG_PM_SLEEP is used in regarding syscore_ops, in this
> case, using CONFIG_PM looks better.
>
> If ARCH_SUSPEND_POSSIBLE will be selected, then CONFIG_SUSPEND is selected
> and CONFIG_PM_SLEEP is selected in kernel/power/Kconfig and of course,
> ARCH_SUSPEND_POSSIBLE is selected in arch/arm/Kconfig. However above
> everything depends on CONFIG_PM. So I think to use CONFIG_PM is more
> reasonable. In addition, it is more popular in other mainline codes now.
>
> Hi Rafael,
> How do you think about this?
If you make syscore_ops depend on CONFIG_PM, they will be built but not
used when CONFIG_PM_RUNTIME is set and CONFIG_PM_SLEEP is unset. If you
think that's acceptable, I guess you can do it (although you may get a
few "defined but not used" warnings in that case, which don't look nice).
Thanks,
Rafael
^ permalink raw reply [flat|nested] 20+ messages in thread
* RE: [PATCH 3/5] ARM: EXYNOS4: Add support PM for EXYNOS4212
2011-08-26 20:36 ` Rafael J. Wysocki
@ 2011-08-30 23:48 ` Kukjin Kim
-1 siblings, 0 replies; 20+ messages in thread
From: Kukjin Kim @ 2011-08-30 23:48 UTC (permalink / raw)
To: 'Rafael J. Wysocki'
Cc: 'MyungJoo Ham',
linux-arm-kernel, linux-samsung-soc, ben-linux,
'Jonghwan Choi'
Rafael J. Wysocki wrote:
>
> On Friday, August 26, 2011, Kukjin Kim wrote:
> > MyungJoo Ham wrote:
> > >
> > > On Wed, Aug 24, 2011 at 10:25 PM, Kukjin Kim <kgene.kim@samsung.com>
> > wrote:
> > > > From: Jonghwan Choi <jhbird.choi@samsung.com>
> > > >
> > > > This patch moves regarding clock stuff of PM into clock
> > > > file to support PM on EXYNOS4210 and EXYNOS4212 with one
> > > > single kernel image. Because some clock registers are
> > > > different on each SoCs.
> > > >
> > > > Signed-off-by: Jonghwan Choi <jhbird.choi@samsung.com>
> > > > Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
> > > > ---
> > > > arch/arm/mach-exynos4/clock-exynos4210.c | 38 ++++++++++
> > > > arch/arm/mach-exynos4/clock-exynos4212.c | 34 +++++++++
> > > > arch/arm/mach-exynos4/clock.c | 89
> > > +++++++++++++++++++++++
> > > > arch/arm/mach-exynos4/include/mach/regs-clock.h | 4 +
> > > > arch/arm/mach-exynos4/pm.c | 79
> > ++------------------
> > > > 5 files changed, 172 insertions(+), 72 deletions(-)
> > > >
> > > > diff --git a/arch/arm/mach-exynos4/clock-exynos4210.c
b/arch/arm/mach-
> > > exynos4/clock-exynos4210.c
> > > > index fe74b91..a4b00b7 100644
> > > > --- a/arch/arm/mach-exynos4/clock-exynos4210.c
> > > > +++ b/arch/arm/mach-exynos4/clock-exynos4210.c
> > > > +static struct sleep_save exynos4210_clock_save[] = {
> > > > + SAVE_ITEM(S5P_CLKSRC_IMAGE),
> > > > + SAVE_ITEM(S5P_CLKSRC_LCD1),
> > > > + SAVE_ITEM(S5P_CLKDIV_IMAGE),
> > > > + SAVE_ITEM(S5P_CLKDIV_LCD1),
> > > > + SAVE_ITEM(S5P_CLKSRC_MASK_LCD1),
> > > > + SAVE_ITEM(S5P_CLKGATE_IP_IMAGE_4210),
> > > > + SAVE_ITEM(S5P_CLKGATE_IP_LCD1),
> > > > + SAVE_ITEM(S5P_CLKGATE_IP_PERIR_4210),
> > > > +};
> > > > +
> > > > --- a/arch/arm/mach-exynos4/clock-exynos4212.c
> > > > +++ b/arch/arm/mach-exynos4/clock-exynos4212.c
> > > > +static struct sleep_save exynos4212_clock_save[] = {
> > > > + SAVE_ITEM(S5P_CLKSRC_IMAGE),
> > > > + SAVE_ITEM(S5P_CLKDIV_IMAGE),
> > > > + SAVE_ITEM(S5P_CLKGATE_IP_IMAGE_4212),
> > > > + SAVE_ITEM(S5P_CLKGATE_IP_PERIR_4212),
> > > > +};
> > > > +
> > > > --- a/arch/arm/mach-exynos4/clock.c
> > > > +++ b/arch/arm/mach-exynos4/clock.c
> > > > +static struct sleep_save exynos4_clock_save[] = {
> > >
> > > Hello,
> > >
> > Hi,
> >
> > > Is there any reason to have the following two
> > > SAVE_ITEM(S5P_CLKSRC_IMAGE),
> > > SAVE_ITEM(S5P_CLKDIV_IMAGE
> > > defined at both clock-exynos4210.c and clock-exynos4212.c, not defined
> > > at clock.c once?
> > >
> > Yes, I know. I just wanted to keep in mind there is a different
> > value(CLKGATE_IP_IMAGE) in regarding IMAGE clocks on each SoCs, and I
> think
> > need it now. Anyway thanks for your pointing out.
> >
> > > Also, consider using CONFIG_PM_SLEEP rather than CONFIG_PM for
> > > suspend/resume ops.
> > >
> > (Cc'ed Rafael)
> >
> > Well, even though CONFIG_PM_SLEEP is used in regarding syscore_ops, in
this
> > case, using CONFIG_PM looks better.
> >
> > If ARCH_SUSPEND_POSSIBLE will be selected, then CONFIG_SUSPEND is
> selected
> > and CONFIG_PM_SLEEP is selected in kernel/power/Kconfig and of course,
> > ARCH_SUSPEND_POSSIBLE is selected in arch/arm/Kconfig. However above
> > everything depends on CONFIG_PM. So I think to use CONFIG_PM is more
> > reasonable. In addition, it is more popular in other mainline codes now.
> >
> > Hi Rafael,
> > How do you think about this?
>
> If you make syscore_ops depend on CONFIG_PM, they will be built but not
> used when CONFIG_PM_RUNTIME is set and CONFIG_PM_SLEEP is unset. If
> you
> think that's acceptable, I guess you can do it (although you may get a
> few "defined but not used" warnings in that case, which don't look nice).
>
Hmm...ok, I understand you mean CONFIG_PM_SLEEP is better in this case to
reduce useless warnings. Will use CONFIG_PM_SLEEP.
Rafael and MyungJoo, Thanks.
Best regards,
Kgene.
--
Kukjin Kim <kgene.kim@samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.
^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH 3/5] ARM: EXYNOS4: Add support PM for EXYNOS4212
@ 2011-08-30 23:48 ` Kukjin Kim
0 siblings, 0 replies; 20+ messages in thread
From: Kukjin Kim @ 2011-08-30 23:48 UTC (permalink / raw)
To: linux-arm-kernel
Rafael J. Wysocki wrote:
>
> On Friday, August 26, 2011, Kukjin Kim wrote:
> > MyungJoo Ham wrote:
> > >
> > > On Wed, Aug 24, 2011 at 10:25 PM, Kukjin Kim <kgene.kim@samsung.com>
> > wrote:
> > > > From: Jonghwan Choi <jhbird.choi@samsung.com>
> > > >
> > > > This patch moves regarding clock stuff of PM into clock
> > > > file to support PM on EXYNOS4210 and EXYNOS4212 with one
> > > > single kernel image. Because some clock registers are
> > > > different on each SoCs.
> > > >
> > > > Signed-off-by: Jonghwan Choi <jhbird.choi@samsung.com>
> > > > Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
> > > > ---
> > > > arch/arm/mach-exynos4/clock-exynos4210.c | 38 ++++++++++
> > > > arch/arm/mach-exynos4/clock-exynos4212.c | 34 +++++++++
> > > > arch/arm/mach-exynos4/clock.c | 89
> > > +++++++++++++++++++++++
> > > > arch/arm/mach-exynos4/include/mach/regs-clock.h | 4 +
> > > > arch/arm/mach-exynos4/pm.c | 79
> > ++------------------
> > > > 5 files changed, 172 insertions(+), 72 deletions(-)
> > > >
> > > > diff --git a/arch/arm/mach-exynos4/clock-exynos4210.c
b/arch/arm/mach-
> > > exynos4/clock-exynos4210.c
> > > > index fe74b91..a4b00b7 100644
> > > > --- a/arch/arm/mach-exynos4/clock-exynos4210.c
> > > > +++ b/arch/arm/mach-exynos4/clock-exynos4210.c
> > > > +static struct sleep_save exynos4210_clock_save[] = {
> > > > + SAVE_ITEM(S5P_CLKSRC_IMAGE),
> > > > + SAVE_ITEM(S5P_CLKSRC_LCD1),
> > > > + SAVE_ITEM(S5P_CLKDIV_IMAGE),
> > > > + SAVE_ITEM(S5P_CLKDIV_LCD1),
> > > > + SAVE_ITEM(S5P_CLKSRC_MASK_LCD1),
> > > > + SAVE_ITEM(S5P_CLKGATE_IP_IMAGE_4210),
> > > > + SAVE_ITEM(S5P_CLKGATE_IP_LCD1),
> > > > + SAVE_ITEM(S5P_CLKGATE_IP_PERIR_4210),
> > > > +};
> > > > +
> > > > --- a/arch/arm/mach-exynos4/clock-exynos4212.c
> > > > +++ b/arch/arm/mach-exynos4/clock-exynos4212.c
> > > > +static struct sleep_save exynos4212_clock_save[] = {
> > > > + SAVE_ITEM(S5P_CLKSRC_IMAGE),
> > > > + SAVE_ITEM(S5P_CLKDIV_IMAGE),
> > > > + SAVE_ITEM(S5P_CLKGATE_IP_IMAGE_4212),
> > > > + SAVE_ITEM(S5P_CLKGATE_IP_PERIR_4212),
> > > > +};
> > > > +
> > > > --- a/arch/arm/mach-exynos4/clock.c
> > > > +++ b/arch/arm/mach-exynos4/clock.c
> > > > +static struct sleep_save exynos4_clock_save[] = {
> > >
> > > Hello,
> > >
> > Hi,
> >
> > > Is there any reason to have the following two
> > > SAVE_ITEM(S5P_CLKSRC_IMAGE),
> > > SAVE_ITEM(S5P_CLKDIV_IMAGE
> > > defined at both clock-exynos4210.c and clock-exynos4212.c, not defined
> > > at clock.c once?
> > >
> > Yes, I know. I just wanted to keep in mind there is a different
> > value(CLKGATE_IP_IMAGE) in regarding IMAGE clocks on each SoCs, and I
> think
> > need it now. Anyway thanks for your pointing out.
> >
> > > Also, consider using CONFIG_PM_SLEEP rather than CONFIG_PM for
> > > suspend/resume ops.
> > >
> > (Cc'ed Rafael)
> >
> > Well, even though CONFIG_PM_SLEEP is used in regarding syscore_ops, in
this
> > case, using CONFIG_PM looks better.
> >
> > If ARCH_SUSPEND_POSSIBLE will be selected, then CONFIG_SUSPEND is
> selected
> > and CONFIG_PM_SLEEP is selected in kernel/power/Kconfig and of course,
> > ARCH_SUSPEND_POSSIBLE is selected in arch/arm/Kconfig. However above
> > everything depends on CONFIG_PM. So I think to use CONFIG_PM is more
> > reasonable. In addition, it is more popular in other mainline codes now.
> >
> > Hi Rafael,
> > How do you think about this?
>
> If you make syscore_ops depend on CONFIG_PM, they will be built but not
> used when CONFIG_PM_RUNTIME is set and CONFIG_PM_SLEEP is unset. If
> you
> think that's acceptable, I guess you can do it (although you may get a
> few "defined but not used" warnings in that case, which don't look nice).
>
Hmm...ok, I understand you mean CONFIG_PM_SLEEP is better in this case to
reduce useless warnings. Will use CONFIG_PM_SLEEP.
Rafael and MyungJoo, Thanks.
Best regards,
Kgene.
--
Kukjin Kim <kgene.kim@samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.
^ permalink raw reply [flat|nested] 20+ messages in thread
end of thread, other threads:[~2011-08-30 23:48 UTC | newest]
Thread overview: 20+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2011-08-24 13:25 [PATCH 0/5] ARM: EXYNOS4: Add support new EXYNOS4212 SoC Kukjin Kim
2011-08-24 13:25 ` Kukjin Kim
2011-08-24 13:25 ` [PATCH 1/5] " Kukjin Kim
2011-08-24 13:25 ` Kukjin Kim
2011-08-24 13:25 ` [PATCH 2/5] ARM: EXYNOS4: Add support clock for EXYNOS4212 Kukjin Kim
2011-08-24 13:25 ` Kukjin Kim
2011-08-24 13:25 ` [PATCH 3/5] ARM: EXYNOS4: Add support PM " Kukjin Kim
2011-08-24 13:25 ` Kukjin Kim
2011-08-25 7:46 ` MyungJoo Ham
2011-08-25 7:46 ` MyungJoo Ham
2011-08-25 23:33 ` Kukjin Kim
2011-08-25 23:33 ` Kukjin Kim
2011-08-26 20:36 ` Rafael J. Wysocki
2011-08-26 20:36 ` Rafael J. Wysocki
2011-08-30 23:48 ` Kukjin Kim
2011-08-30 23:48 ` Kukjin Kim
2011-08-24 13:25 ` [PATCH 4/5] ARM: EXYNOS4: Add support SMDK4212 Board Kukjin Kim
2011-08-24 13:25 ` Kukjin Kim
2011-08-24 13:25 ` [PATCH 5/5] tty: Add support serial for EXYNOS4212 SoC Kukjin Kim
2011-08-24 13:25 ` Kukjin Kim
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