From: Guo Ren <guoren@kernel.org>
To: Jisheng Zhang <jszhang@kernel.org>
Cc: Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH v3 4/4] riscv: entry: consolidate general regs saving/restoring
Date: Wed, 5 Oct 2022 00:03:33 +0800 [thread overview]
Message-ID: <CAJF2gTQckQaq1c-P6dJ5O3S6fmMQ2-uxNhQHfn+o=W7bphZg6g@mail.gmail.com> (raw)
In-Reply-To: <20221003102921.3973-5-jszhang@kernel.org>
Reviewed-by: Guo Ren <guoren@kernel.org>
On Mon, Oct 3, 2022 at 6:39 PM Jisheng Zhang <jszhang@kernel.org> wrote:
>
> Consolidate the saving/restoring GPs(except zero, ra, sp, gp and tp) into
> save_from_x5_to_x31/restore_from_x5_to_x31 macros.
>
> No functional change intended.
>
> Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
> ---
> arch/riscv/include/asm/asm.h | 63 +++++++++++++++++++++++++
> arch/riscv/kernel/entry.S | 84 ++--------------------------------
> arch/riscv/kernel/mcount-dyn.S | 56 +----------------------
> 3 files changed, 68 insertions(+), 135 deletions(-)
>
> diff --git a/arch/riscv/include/asm/asm.h b/arch/riscv/include/asm/asm.h
> index 1b471ff73178..bf5247aa317d 100644
> --- a/arch/riscv/include/asm/asm.h
> +++ b/arch/riscv/include/asm/asm.h
> @@ -68,6 +68,7 @@
> #endif
>
> #ifdef __ASSEMBLY__
> +#include <asm/asm-offsets.h>
>
> /* Common assembly source macros */
>
> @@ -80,6 +81,68 @@
> .endr
> .endm
>
> + /* save all GPs except zero, ra, sp, gp and tp */
> + .macro save_from_x5_to_x31
> + REG_S x5, PT_T0(sp)
> + REG_S x6, PT_T1(sp)
> + REG_S x7, PT_T2(sp)
> + REG_S x8, PT_S0(sp)
> + REG_S x9, PT_S1(sp)
> + REG_S x10, PT_A0(sp)
> + REG_S x11, PT_A1(sp)
> + REG_S x12, PT_A2(sp)
> + REG_S x13, PT_A3(sp)
> + REG_S x14, PT_A4(sp)
> + REG_S x15, PT_A5(sp)
> + REG_S x16, PT_A6(sp)
> + REG_S x17, PT_A7(sp)
> + REG_S x18, PT_S2(sp)
> + REG_S x19, PT_S3(sp)
> + REG_S x20, PT_S4(sp)
> + REG_S x21, PT_S5(sp)
> + REG_S x22, PT_S6(sp)
> + REG_S x23, PT_S7(sp)
> + REG_S x24, PT_S8(sp)
> + REG_S x25, PT_S9(sp)
> + REG_S x26, PT_S10(sp)
> + REG_S x27, PT_S11(sp)
> + REG_S x28, PT_T3(sp)
> + REG_S x29, PT_T4(sp)
> + REG_S x30, PT_T5(sp)
> + REG_S x31, PT_T6(sp)
> + .endm
> +
> + /* restore all GPs except zero, ra, sp, gp and tp */
> + .macro restore_from_x5_to_x31
> + REG_L x5, PT_T0(sp)
> + REG_L x6, PT_T1(sp)
> + REG_L x7, PT_T2(sp)
> + REG_L x8, PT_S0(sp)
> + REG_L x9, PT_S1(sp)
> + REG_L x10, PT_A0(sp)
> + REG_L x11, PT_A1(sp)
> + REG_L x12, PT_A2(sp)
> + REG_L x13, PT_A3(sp)
> + REG_L x14, PT_A4(sp)
> + REG_L x15, PT_A5(sp)
> + REG_L x16, PT_A6(sp)
> + REG_L x17, PT_A7(sp)
> + REG_L x18, PT_S2(sp)
> + REG_L x19, PT_S3(sp)
> + REG_L x20, PT_S4(sp)
> + REG_L x21, PT_S5(sp)
> + REG_L x22, PT_S6(sp)
> + REG_L x23, PT_S7(sp)
> + REG_L x24, PT_S8(sp)
> + REG_L x25, PT_S9(sp)
> + REG_L x26, PT_S10(sp)
> + REG_L x27, PT_S11(sp)
> + REG_L x28, PT_T3(sp)
> + REG_L x29, PT_T4(sp)
> + REG_L x30, PT_T5(sp)
> + REG_L x31, PT_T6(sp)
> + .endm
> +
> #endif /* __ASSEMBLY__ */
>
> #endif /* _ASM_RISCV_ASM_H */
> diff --git a/arch/riscv/kernel/entry.S b/arch/riscv/kernel/entry.S
> index 48ed1df7a792..7ba3826dde84 100644
> --- a/arch/riscv/kernel/entry.S
> +++ b/arch/riscv/kernel/entry.S
> @@ -41,33 +41,7 @@ _save_context:
> addi sp, sp, -(PT_SIZE_ON_STACK)
> REG_S x1, PT_RA(sp)
> REG_S x3, PT_GP(sp)
> - REG_S x5, PT_T0(sp)
> - REG_S x6, PT_T1(sp)
> - REG_S x7, PT_T2(sp)
> - REG_S x8, PT_S0(sp)
> - REG_S x9, PT_S1(sp)
> - REG_S x10, PT_A0(sp)
> - REG_S x11, PT_A1(sp)
> - REG_S x12, PT_A2(sp)
> - REG_S x13, PT_A3(sp)
> - REG_S x14, PT_A4(sp)
> - REG_S x15, PT_A5(sp)
> - REG_S x16, PT_A6(sp)
> - REG_S x17, PT_A7(sp)
> - REG_S x18, PT_S2(sp)
> - REG_S x19, PT_S3(sp)
> - REG_S x20, PT_S4(sp)
> - REG_S x21, PT_S5(sp)
> - REG_S x22, PT_S6(sp)
> - REG_S x23, PT_S7(sp)
> - REG_S x24, PT_S8(sp)
> - REG_S x25, PT_S9(sp)
> - REG_S x26, PT_S10(sp)
> - REG_S x27, PT_S11(sp)
> - REG_S x28, PT_T3(sp)
> - REG_S x29, PT_T4(sp)
> - REG_S x30, PT_T5(sp)
> - REG_S x31, PT_T6(sp)
> + save_from_x5_to_x31
>
> /*
> * Disable user-mode memory access as it should only be set in the
> @@ -184,33 +158,7 @@ ENTRY(ret_from_exception)
> REG_L x1, PT_RA(sp)
> REG_L x3, PT_GP(sp)
> REG_L x4, PT_TP(sp)
> - REG_L x5, PT_T0(sp)
> - REG_L x6, PT_T1(sp)
> - REG_L x7, PT_T2(sp)
> - REG_L x8, PT_S0(sp)
> - REG_L x9, PT_S1(sp)
> - REG_L x10, PT_A0(sp)
> - REG_L x11, PT_A1(sp)
> - REG_L x12, PT_A2(sp)
> - REG_L x13, PT_A3(sp)
> - REG_L x14, PT_A4(sp)
> - REG_L x15, PT_A5(sp)
> - REG_L x16, PT_A6(sp)
> - REG_L x17, PT_A7(sp)
> - REG_L x18, PT_S2(sp)
> - REG_L x19, PT_S3(sp)
> - REG_L x20, PT_S4(sp)
> - REG_L x21, PT_S5(sp)
> - REG_L x22, PT_S6(sp)
> - REG_L x23, PT_S7(sp)
> - REG_L x24, PT_S8(sp)
> - REG_L x25, PT_S9(sp)
> - REG_L x26, PT_S10(sp)
> - REG_L x27, PT_S11(sp)
> - REG_L x28, PT_T3(sp)
> - REG_L x29, PT_T4(sp)
> - REG_L x30, PT_T5(sp)
> - REG_L x31, PT_T6(sp)
> + restore_from_x5_to_x31
>
> REG_L x2, PT_SP(sp)
>
> @@ -238,33 +186,7 @@ ENTRY(handle_kernel_stack_overflow)
> //save context to overflow stack
> REG_S x1, PT_RA(sp)
> REG_S x3, PT_GP(sp)
> - REG_S x5, PT_T0(sp)
> - REG_S x6, PT_T1(sp)
> - REG_S x7, PT_T2(sp)
> - REG_S x8, PT_S0(sp)
> - REG_S x9, PT_S1(sp)
> - REG_S x10, PT_A0(sp)
> - REG_S x11, PT_A1(sp)
> - REG_S x12, PT_A2(sp)
> - REG_S x13, PT_A3(sp)
> - REG_S x14, PT_A4(sp)
> - REG_S x15, PT_A5(sp)
> - REG_S x16, PT_A6(sp)
> - REG_S x17, PT_A7(sp)
> - REG_S x18, PT_S2(sp)
> - REG_S x19, PT_S3(sp)
> - REG_S x20, PT_S4(sp)
> - REG_S x21, PT_S5(sp)
> - REG_S x22, PT_S6(sp)
> - REG_S x23, PT_S7(sp)
> - REG_S x24, PT_S8(sp)
> - REG_S x25, PT_S9(sp)
> - REG_S x26, PT_S10(sp)
> - REG_S x27, PT_S11(sp)
> - REG_S x28, PT_T3(sp)
> - REG_S x29, PT_T4(sp)
> - REG_S x30, PT_T5(sp)
> - REG_S x31, PT_T6(sp)
> + save_from_x5_to_x31
>
> REG_L s0, TASK_TI_KERNEL_SP(tp)
> csrr s1, CSR_STATUS
> diff --git a/arch/riscv/kernel/mcount-dyn.S b/arch/riscv/kernel/mcount-dyn.S
> index d171eca623b6..040d098279a9 100644
> --- a/arch/riscv/kernel/mcount-dyn.S
> +++ b/arch/riscv/kernel/mcount-dyn.S
> @@ -70,33 +70,7 @@
> REG_S x2, PT_SP(sp)
> REG_S x3, PT_GP(sp)
> REG_S x4, PT_TP(sp)
> - REG_S x5, PT_T0(sp)
> - REG_S x6, PT_T1(sp)
> - REG_S x7, PT_T2(sp)
> - REG_S x8, PT_S0(sp)
> - REG_S x9, PT_S1(sp)
> - REG_S x10, PT_A0(sp)
> - REG_S x11, PT_A1(sp)
> - REG_S x12, PT_A2(sp)
> - REG_S x13, PT_A3(sp)
> - REG_S x14, PT_A4(sp)
> - REG_S x15, PT_A5(sp)
> - REG_S x16, PT_A6(sp)
> - REG_S x17, PT_A7(sp)
> - REG_S x18, PT_S2(sp)
> - REG_S x19, PT_S3(sp)
> - REG_S x20, PT_S4(sp)
> - REG_S x21, PT_S5(sp)
> - REG_S x22, PT_S6(sp)
> - REG_S x23, PT_S7(sp)
> - REG_S x24, PT_S8(sp)
> - REG_S x25, PT_S9(sp)
> - REG_S x26, PT_S10(sp)
> - REG_S x27, PT_S11(sp)
> - REG_S x28, PT_T3(sp)
> - REG_S x29, PT_T4(sp)
> - REG_S x30, PT_T5(sp)
> - REG_S x31, PT_T6(sp)
> + save_from_x5_to_x31
> .endm
>
> .macro RESTORE_ALL
> @@ -108,33 +82,7 @@
> REG_L x2, PT_SP(sp)
> REG_L x3, PT_GP(sp)
> REG_L x4, PT_TP(sp)
> - REG_L x5, PT_T0(sp)
> - REG_L x6, PT_T1(sp)
> - REG_L x7, PT_T2(sp)
> - REG_L x8, PT_S0(sp)
> - REG_L x9, PT_S1(sp)
> - REG_L x10, PT_A0(sp)
> - REG_L x11, PT_A1(sp)
> - REG_L x12, PT_A2(sp)
> - REG_L x13, PT_A3(sp)
> - REG_L x14, PT_A4(sp)
> - REG_L x15, PT_A5(sp)
> - REG_L x16, PT_A6(sp)
> - REG_L x17, PT_A7(sp)
> - REG_L x18, PT_S2(sp)
> - REG_L x19, PT_S3(sp)
> - REG_L x20, PT_S4(sp)
> - REG_L x21, PT_S5(sp)
> - REG_L x22, PT_S6(sp)
> - REG_L x23, PT_S7(sp)
> - REG_L x24, PT_S8(sp)
> - REG_L x25, PT_S9(sp)
> - REG_L x26, PT_S10(sp)
> - REG_L x27, PT_S11(sp)
> - REG_L x28, PT_T3(sp)
> - REG_L x29, PT_T4(sp)
> - REG_L x30, PT_T5(sp)
> - REG_L x31, PT_T6(sp)
> + restore_from_x5_to_x31
>
> addi sp, sp, PT_SIZE_ON_STACK
> addi sp, sp, SZREG
> --
> 2.37.2
>
--
Best Regards
Guo Ren
WARNING: multiple messages have this Message-ID (diff)
From: Guo Ren <guoren@kernel.org>
To: Jisheng Zhang <jszhang@kernel.org>
Cc: Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH v3 4/4] riscv: entry: consolidate general regs saving/restoring
Date: Wed, 5 Oct 2022 00:03:33 +0800 [thread overview]
Message-ID: <CAJF2gTQckQaq1c-P6dJ5O3S6fmMQ2-uxNhQHfn+o=W7bphZg6g@mail.gmail.com> (raw)
In-Reply-To: <20221003102921.3973-5-jszhang@kernel.org>
Reviewed-by: Guo Ren <guoren@kernel.org>
On Mon, Oct 3, 2022 at 6:39 PM Jisheng Zhang <jszhang@kernel.org> wrote:
>
> Consolidate the saving/restoring GPs(except zero, ra, sp, gp and tp) into
> save_from_x5_to_x31/restore_from_x5_to_x31 macros.
>
> No functional change intended.
>
> Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
> ---
> arch/riscv/include/asm/asm.h | 63 +++++++++++++++++++++++++
> arch/riscv/kernel/entry.S | 84 ++--------------------------------
> arch/riscv/kernel/mcount-dyn.S | 56 +----------------------
> 3 files changed, 68 insertions(+), 135 deletions(-)
>
> diff --git a/arch/riscv/include/asm/asm.h b/arch/riscv/include/asm/asm.h
> index 1b471ff73178..bf5247aa317d 100644
> --- a/arch/riscv/include/asm/asm.h
> +++ b/arch/riscv/include/asm/asm.h
> @@ -68,6 +68,7 @@
> #endif
>
> #ifdef __ASSEMBLY__
> +#include <asm/asm-offsets.h>
>
> /* Common assembly source macros */
>
> @@ -80,6 +81,68 @@
> .endr
> .endm
>
> + /* save all GPs except zero, ra, sp, gp and tp */
> + .macro save_from_x5_to_x31
> + REG_S x5, PT_T0(sp)
> + REG_S x6, PT_T1(sp)
> + REG_S x7, PT_T2(sp)
> + REG_S x8, PT_S0(sp)
> + REG_S x9, PT_S1(sp)
> + REG_S x10, PT_A0(sp)
> + REG_S x11, PT_A1(sp)
> + REG_S x12, PT_A2(sp)
> + REG_S x13, PT_A3(sp)
> + REG_S x14, PT_A4(sp)
> + REG_S x15, PT_A5(sp)
> + REG_S x16, PT_A6(sp)
> + REG_S x17, PT_A7(sp)
> + REG_S x18, PT_S2(sp)
> + REG_S x19, PT_S3(sp)
> + REG_S x20, PT_S4(sp)
> + REG_S x21, PT_S5(sp)
> + REG_S x22, PT_S6(sp)
> + REG_S x23, PT_S7(sp)
> + REG_S x24, PT_S8(sp)
> + REG_S x25, PT_S9(sp)
> + REG_S x26, PT_S10(sp)
> + REG_S x27, PT_S11(sp)
> + REG_S x28, PT_T3(sp)
> + REG_S x29, PT_T4(sp)
> + REG_S x30, PT_T5(sp)
> + REG_S x31, PT_T6(sp)
> + .endm
> +
> + /* restore all GPs except zero, ra, sp, gp and tp */
> + .macro restore_from_x5_to_x31
> + REG_L x5, PT_T0(sp)
> + REG_L x6, PT_T1(sp)
> + REG_L x7, PT_T2(sp)
> + REG_L x8, PT_S0(sp)
> + REG_L x9, PT_S1(sp)
> + REG_L x10, PT_A0(sp)
> + REG_L x11, PT_A1(sp)
> + REG_L x12, PT_A2(sp)
> + REG_L x13, PT_A3(sp)
> + REG_L x14, PT_A4(sp)
> + REG_L x15, PT_A5(sp)
> + REG_L x16, PT_A6(sp)
> + REG_L x17, PT_A7(sp)
> + REG_L x18, PT_S2(sp)
> + REG_L x19, PT_S3(sp)
> + REG_L x20, PT_S4(sp)
> + REG_L x21, PT_S5(sp)
> + REG_L x22, PT_S6(sp)
> + REG_L x23, PT_S7(sp)
> + REG_L x24, PT_S8(sp)
> + REG_L x25, PT_S9(sp)
> + REG_L x26, PT_S10(sp)
> + REG_L x27, PT_S11(sp)
> + REG_L x28, PT_T3(sp)
> + REG_L x29, PT_T4(sp)
> + REG_L x30, PT_T5(sp)
> + REG_L x31, PT_T6(sp)
> + .endm
> +
> #endif /* __ASSEMBLY__ */
>
> #endif /* _ASM_RISCV_ASM_H */
> diff --git a/arch/riscv/kernel/entry.S b/arch/riscv/kernel/entry.S
> index 48ed1df7a792..7ba3826dde84 100644
> --- a/arch/riscv/kernel/entry.S
> +++ b/arch/riscv/kernel/entry.S
> @@ -41,33 +41,7 @@ _save_context:
> addi sp, sp, -(PT_SIZE_ON_STACK)
> REG_S x1, PT_RA(sp)
> REG_S x3, PT_GP(sp)
> - REG_S x5, PT_T0(sp)
> - REG_S x6, PT_T1(sp)
> - REG_S x7, PT_T2(sp)
> - REG_S x8, PT_S0(sp)
> - REG_S x9, PT_S1(sp)
> - REG_S x10, PT_A0(sp)
> - REG_S x11, PT_A1(sp)
> - REG_S x12, PT_A2(sp)
> - REG_S x13, PT_A3(sp)
> - REG_S x14, PT_A4(sp)
> - REG_S x15, PT_A5(sp)
> - REG_S x16, PT_A6(sp)
> - REG_S x17, PT_A7(sp)
> - REG_S x18, PT_S2(sp)
> - REG_S x19, PT_S3(sp)
> - REG_S x20, PT_S4(sp)
> - REG_S x21, PT_S5(sp)
> - REG_S x22, PT_S6(sp)
> - REG_S x23, PT_S7(sp)
> - REG_S x24, PT_S8(sp)
> - REG_S x25, PT_S9(sp)
> - REG_S x26, PT_S10(sp)
> - REG_S x27, PT_S11(sp)
> - REG_S x28, PT_T3(sp)
> - REG_S x29, PT_T4(sp)
> - REG_S x30, PT_T5(sp)
> - REG_S x31, PT_T6(sp)
> + save_from_x5_to_x31
>
> /*
> * Disable user-mode memory access as it should only be set in the
> @@ -184,33 +158,7 @@ ENTRY(ret_from_exception)
> REG_L x1, PT_RA(sp)
> REG_L x3, PT_GP(sp)
> REG_L x4, PT_TP(sp)
> - REG_L x5, PT_T0(sp)
> - REG_L x6, PT_T1(sp)
> - REG_L x7, PT_T2(sp)
> - REG_L x8, PT_S0(sp)
> - REG_L x9, PT_S1(sp)
> - REG_L x10, PT_A0(sp)
> - REG_L x11, PT_A1(sp)
> - REG_L x12, PT_A2(sp)
> - REG_L x13, PT_A3(sp)
> - REG_L x14, PT_A4(sp)
> - REG_L x15, PT_A5(sp)
> - REG_L x16, PT_A6(sp)
> - REG_L x17, PT_A7(sp)
> - REG_L x18, PT_S2(sp)
> - REG_L x19, PT_S3(sp)
> - REG_L x20, PT_S4(sp)
> - REG_L x21, PT_S5(sp)
> - REG_L x22, PT_S6(sp)
> - REG_L x23, PT_S7(sp)
> - REG_L x24, PT_S8(sp)
> - REG_L x25, PT_S9(sp)
> - REG_L x26, PT_S10(sp)
> - REG_L x27, PT_S11(sp)
> - REG_L x28, PT_T3(sp)
> - REG_L x29, PT_T4(sp)
> - REG_L x30, PT_T5(sp)
> - REG_L x31, PT_T6(sp)
> + restore_from_x5_to_x31
>
> REG_L x2, PT_SP(sp)
>
> @@ -238,33 +186,7 @@ ENTRY(handle_kernel_stack_overflow)
> //save context to overflow stack
> REG_S x1, PT_RA(sp)
> REG_S x3, PT_GP(sp)
> - REG_S x5, PT_T0(sp)
> - REG_S x6, PT_T1(sp)
> - REG_S x7, PT_T2(sp)
> - REG_S x8, PT_S0(sp)
> - REG_S x9, PT_S1(sp)
> - REG_S x10, PT_A0(sp)
> - REG_S x11, PT_A1(sp)
> - REG_S x12, PT_A2(sp)
> - REG_S x13, PT_A3(sp)
> - REG_S x14, PT_A4(sp)
> - REG_S x15, PT_A5(sp)
> - REG_S x16, PT_A6(sp)
> - REG_S x17, PT_A7(sp)
> - REG_S x18, PT_S2(sp)
> - REG_S x19, PT_S3(sp)
> - REG_S x20, PT_S4(sp)
> - REG_S x21, PT_S5(sp)
> - REG_S x22, PT_S6(sp)
> - REG_S x23, PT_S7(sp)
> - REG_S x24, PT_S8(sp)
> - REG_S x25, PT_S9(sp)
> - REG_S x26, PT_S10(sp)
> - REG_S x27, PT_S11(sp)
> - REG_S x28, PT_T3(sp)
> - REG_S x29, PT_T4(sp)
> - REG_S x30, PT_T5(sp)
> - REG_S x31, PT_T6(sp)
> + save_from_x5_to_x31
>
> REG_L s0, TASK_TI_KERNEL_SP(tp)
> csrr s1, CSR_STATUS
> diff --git a/arch/riscv/kernel/mcount-dyn.S b/arch/riscv/kernel/mcount-dyn.S
> index d171eca623b6..040d098279a9 100644
> --- a/arch/riscv/kernel/mcount-dyn.S
> +++ b/arch/riscv/kernel/mcount-dyn.S
> @@ -70,33 +70,7 @@
> REG_S x2, PT_SP(sp)
> REG_S x3, PT_GP(sp)
> REG_S x4, PT_TP(sp)
> - REG_S x5, PT_T0(sp)
> - REG_S x6, PT_T1(sp)
> - REG_S x7, PT_T2(sp)
> - REG_S x8, PT_S0(sp)
> - REG_S x9, PT_S1(sp)
> - REG_S x10, PT_A0(sp)
> - REG_S x11, PT_A1(sp)
> - REG_S x12, PT_A2(sp)
> - REG_S x13, PT_A3(sp)
> - REG_S x14, PT_A4(sp)
> - REG_S x15, PT_A5(sp)
> - REG_S x16, PT_A6(sp)
> - REG_S x17, PT_A7(sp)
> - REG_S x18, PT_S2(sp)
> - REG_S x19, PT_S3(sp)
> - REG_S x20, PT_S4(sp)
> - REG_S x21, PT_S5(sp)
> - REG_S x22, PT_S6(sp)
> - REG_S x23, PT_S7(sp)
> - REG_S x24, PT_S8(sp)
> - REG_S x25, PT_S9(sp)
> - REG_S x26, PT_S10(sp)
> - REG_S x27, PT_S11(sp)
> - REG_S x28, PT_T3(sp)
> - REG_S x29, PT_T4(sp)
> - REG_S x30, PT_T5(sp)
> - REG_S x31, PT_T6(sp)
> + save_from_x5_to_x31
> .endm
>
> .macro RESTORE_ALL
> @@ -108,33 +82,7 @@
> REG_L x2, PT_SP(sp)
> REG_L x3, PT_GP(sp)
> REG_L x4, PT_TP(sp)
> - REG_L x5, PT_T0(sp)
> - REG_L x6, PT_T1(sp)
> - REG_L x7, PT_T2(sp)
> - REG_L x8, PT_S0(sp)
> - REG_L x9, PT_S1(sp)
> - REG_L x10, PT_A0(sp)
> - REG_L x11, PT_A1(sp)
> - REG_L x12, PT_A2(sp)
> - REG_L x13, PT_A3(sp)
> - REG_L x14, PT_A4(sp)
> - REG_L x15, PT_A5(sp)
> - REG_L x16, PT_A6(sp)
> - REG_L x17, PT_A7(sp)
> - REG_L x18, PT_S2(sp)
> - REG_L x19, PT_S3(sp)
> - REG_L x20, PT_S4(sp)
> - REG_L x21, PT_S5(sp)
> - REG_L x22, PT_S6(sp)
> - REG_L x23, PT_S7(sp)
> - REG_L x24, PT_S8(sp)
> - REG_L x25, PT_S9(sp)
> - REG_L x26, PT_S10(sp)
> - REG_L x27, PT_S11(sp)
> - REG_L x28, PT_T3(sp)
> - REG_L x29, PT_T4(sp)
> - REG_L x30, PT_T5(sp)
> - REG_L x31, PT_T6(sp)
> + restore_from_x5_to_x31
>
> addi sp, sp, PT_SIZE_ON_STACK
> addi sp, sp, SZREG
> --
> 2.37.2
>
--
Best Regards
Guo Ren
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next prev parent reply other threads:[~2022-10-04 16:03 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-10-03 10:29 [PATCH v3 0/4] riscv: entry: further clean up and VMAP_STACK fix Jisheng Zhang
2022-10-03 10:29 ` Jisheng Zhang
2022-10-03 10:29 ` [PATCH v3 1/4] riscv: process: fix kernel info leakage Jisheng Zhang
2022-10-03 10:29 ` Jisheng Zhang
2022-10-04 16:04 ` Guo Ren
2022-10-04 16:04 ` Guo Ren
2022-10-03 10:29 ` [PATCH v3 2/4] riscv: consolidate ret_from_kernel_thread into ret_from_fork Jisheng Zhang
2022-10-03 10:29 ` Jisheng Zhang
2022-10-03 10:29 ` [PATCH v3 3/4] riscv: fix race when vmap stack overflow and remove shadow_stack Jisheng Zhang
2022-10-03 10:29 ` Jisheng Zhang
2022-10-03 10:29 ` [PATCH v3 4/4] riscv: entry: consolidate general regs saving/restoring Jisheng Zhang
2022-10-03 10:29 ` Jisheng Zhang
2022-10-04 16:03 ` Guo Ren [this message]
2022-10-04 16:03 ` Guo Ren
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