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From: Guo Ren <guoren@kernel.org>
To: Heiko Stuebner <heiko@sntech.de>
Cc: paul.walmsley@sifive.com, palmer@dabbelt.com,
	aou@eecs.berkeley.edu, apatel@ventanamicro.com,
	atishp@rivosinc.com, linux-riscv@lists.infradead.org,
	linux-kernel@vger.kernel.org,
	Conor Dooley <conor.dooley@microchip.com>,
	Andrew Jones <ajones@ventanamicro.com>
Subject: Re: [PATCH v2 5/5] riscv: check for kernel config option in t-head memory types errata
Date: Tue, 6 Sep 2022 09:33:45 +0800	[thread overview]
Message-ID: <CAJF2gTRB6Rq=MbFDuoEeU4-0B1N-JVjuxrHFK6YDg59ya2R9GQ@mail.gmail.com> (raw)
In-Reply-To: <20220905111027.2463297-6-heiko@sntech.de>

Reviewed-by: Guo Ren <guoren@kernel.org>

On Mon, Sep 5, 2022 at 7:10 PM Heiko Stuebner <heiko@sntech.de> wrote:
>
> The t-head variant of page-based memory types should also check first
> for the enabled kernel config option.
>
> Fixes: a35707c3d850 ("riscv: add memory-type errata for T-Head")
> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
> Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
> Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
> ---
>  arch/riscv/errata/thead/errata.c | 3 +++
>  1 file changed, 3 insertions(+)
>
> diff --git a/arch/riscv/errata/thead/errata.c b/arch/riscv/errata/thead/errata.c
> index a6f4bd8ccf3f..902e12452821 100644
> --- a/arch/riscv/errata/thead/errata.c
> +++ b/arch/riscv/errata/thead/errata.c
> @@ -17,6 +17,9 @@
>  static bool errata_probe_pbmt(unsigned int stage,
>                               unsigned long arch_id, unsigned long impid)
>  {
> +       if (!IS_ENABLED(CONFIG_ERRATA_THEAD_PBMT))
> +               return false;
> +
>         if (arch_id != 0 || impid != 0)
>                 return false;
>
> --
> 2.35.1
>


-- 
Best Regards
 Guo Ren

WARNING: multiple messages have this Message-ID (diff)
From: Guo Ren <guoren@kernel.org>
To: Heiko Stuebner <heiko@sntech.de>
Cc: paul.walmsley@sifive.com, palmer@dabbelt.com,
	aou@eecs.berkeley.edu,  apatel@ventanamicro.com,
	atishp@rivosinc.com, linux-riscv@lists.infradead.org,
	 linux-kernel@vger.kernel.org,
	Conor Dooley <conor.dooley@microchip.com>,
	 Andrew Jones <ajones@ventanamicro.com>
Subject: Re: [PATCH v2 5/5] riscv: check for kernel config option in t-head memory types errata
Date: Tue, 6 Sep 2022 09:33:45 +0800	[thread overview]
Message-ID: <CAJF2gTRB6Rq=MbFDuoEeU4-0B1N-JVjuxrHFK6YDg59ya2R9GQ@mail.gmail.com> (raw)
In-Reply-To: <20220905111027.2463297-6-heiko@sntech.de>

Reviewed-by: Guo Ren <guoren@kernel.org>

On Mon, Sep 5, 2022 at 7:10 PM Heiko Stuebner <heiko@sntech.de> wrote:
>
> The t-head variant of page-based memory types should also check first
> for the enabled kernel config option.
>
> Fixes: a35707c3d850 ("riscv: add memory-type errata for T-Head")
> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
> Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
> Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
> ---
>  arch/riscv/errata/thead/errata.c | 3 +++
>  1 file changed, 3 insertions(+)
>
> diff --git a/arch/riscv/errata/thead/errata.c b/arch/riscv/errata/thead/errata.c
> index a6f4bd8ccf3f..902e12452821 100644
> --- a/arch/riscv/errata/thead/errata.c
> +++ b/arch/riscv/errata/thead/errata.c
> @@ -17,6 +17,9 @@
>  static bool errata_probe_pbmt(unsigned int stage,
>                               unsigned long arch_id, unsigned long impid)
>  {
> +       if (!IS_ENABLED(CONFIG_ERRATA_THEAD_PBMT))
> +               return false;
> +
>         if (arch_id != 0 || impid != 0)
>                 return false;
>
> --
> 2.35.1
>


-- 
Best Regards
 Guo Ren

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  reply	other threads:[~2022-09-06  1:34 UTC|newest]

Thread overview: 26+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-09-05 11:10 [PATCH v2 0/5] Some style cleanups for recent extension additions Heiko Stuebner
2022-09-05 11:10 ` Heiko Stuebner
2022-09-05 11:10 ` [PATCH v2 1/5] riscv: cleanup svpbmt cpufeature probing Heiko Stuebner
2022-09-05 11:10   ` Heiko Stuebner
2022-09-05 11:10 ` [PATCH v2 2/5] riscv: drop some idefs from CMO initialization Heiko Stuebner
2022-09-05 11:10   ` Heiko Stuebner
2022-09-05 11:10 ` [PATCH v2 3/5] riscv: use BIT() macros in t-head errata init Heiko Stuebner
2022-09-05 11:10   ` Heiko Stuebner
2022-09-05 11:10 ` [PATCH v2 4/5] riscv: use BIT() marco for cpufeature probing Heiko Stuebner
2022-09-05 11:10   ` Heiko Stuebner
2022-09-05 11:19   ` Conor.Dooley
2022-09-05 11:19     ` Conor.Dooley
2022-09-05 11:23     ` Heiko Stübner
2022-09-05 11:23       ` Heiko Stübner
2022-09-05 14:12       ` Heiko Stübner
2022-09-05 14:12         ` Heiko Stübner
2022-09-05 14:16         ` Conor.Dooley
2022-09-05 14:16           ` Conor.Dooley
     [not found]   ` <CAOnJCUJ9hC2xhoxuBPCNHEEZACeWckEL-Tc7xS6ECWrfx5KXhg@mail.gmail.com>
2022-09-07 23:12     ` Guo Ren
2022-09-07 23:12       ` Guo Ren
2022-09-05 11:10 ` [PATCH v2 5/5] riscv: check for kernel config option in t-head memory types errata Heiko Stuebner
2022-09-05 11:10   ` Heiko Stuebner
2022-09-06  1:33   ` Guo Ren [this message]
2022-09-06  1:33     ` Guo Ren
2022-10-13 16:58 ` [PATCH v2 0/5] Some style cleanups for recent extension additions Palmer Dabbelt
2022-10-13 16:58   ` Palmer Dabbelt

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