From: Guo Ren <guoren@kernel.org> To: Icenowy Zheng <uwu@icenowy.me> Cc: Paul Walmsley <paul.walmsley@sifive.com>, Palmer Dabbelt <palmer@dabbelt.com>, Albert Ou <aou@eecs.berkeley.edu>, Heiko Stuebner <heiko@sntech.de>, Nathan Chancellor <nathan@kernel.org>, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 1/2] riscv: errata: fix T-Head dcache.cva encoding Date: Tue, 27 Dec 2022 10:47:31 +0800 [thread overview] Message-ID: <CAJF2gTSGvEnTqEqR9f+zU8T3VS8FoCtsgSk=9hz6cWxAL630zQ@mail.gmail.com> (raw) In-Reply-To: <20221227020258.303900-1-uwu@icenowy.me> Good catch. But I hope c906/910 can directly use paddr here. It's unnecessary to cause software translation & mmu translation here. diff --git a/arch/riscv/mm/dma-noncoherent.c b/arch/riscv/mm/dma-noncoherent.c index b0add983530a..30650a0c4481 100644 --- a/arch/riscv/mm/dma-noncoherent.c +++ b/arch/riscv/mm/dma-noncoherent.c @@ -24,13 +24,13 @@ void arch_sync_dma_for_device(phys_addr_t paddr, size_t size, switch (dir) { case DMA_TO_DEVICE: - ALT_CMO_OP(clean, vaddr, size, riscv_cbom_block_size); + ALT_CMO_OP(clean, vaddr, paddr, size, riscv_cbom_block_size); break; case DMA_FROM_DEVICE: - ALT_CMO_OP(clean, vaddr, size, riscv_cbom_block_size); + ALT_CMO_OP(clean, vaddr, paddr, size, riscv_cbom_block_size); break; case DMA_BIDIRECTIONAL: - ALT_CMO_OP(flush, vaddr, size, riscv_cbom_block_size); + ALT_CMO_OP(flush, vaddr, paddr, size, riscv_cbom_block_size); break; default: break; @@ -47,7 +47,7 @@ void arch_sync_dma_for_cpu(phys_addr_t paddr, size_t size, break; case DMA_FROM_DEVICE: case DMA_BIDIRECTIONAL: - ALT_CMO_OP(flush, vaddr, size, riscv_cbom_block_size); + ALT_CMO_OP(flush, vaddr, paddr, size, riscv_cbom_block_size); break; default: break; @@ -57,8 +57,9 @@ void arch_sync_dma_for_cpu(phys_addr_t paddr, size_t size, void arch_dma_prep_coherent(struct page *page, size_t size) { void *flush_addr = page_address(page); + phys_addr_t paddr = PFN_PHYS(page_to_pfn(x)); - ALT_CMO_OP(flush, flush_addr, size, riscv_cbom_block_size); + ALT_CMO_OP(flush, flush_addr, paddr, size, riscv_cbom_block_size); } On Tue, Dec 27, 2022 at 10:03 AM Icenowy Zheng <uwu@icenowy.me> wrote: > > The dcache.cva encoding shown in the comments are wrong, it's for > dcache.cval1 (which is restricted to L1) instead. > > Fix this in the comment and in the hardcoded instruction. > > Signed-off-by: Icenowy Zheng <uwu@icenowy.me> > --- > The code is tested on a LiteX SoC with OpenC906 core, and it > successfully boots to Systemd on a SD card connected to LiteSDCard. > > This change should be not noticable on C906, but on multi-core C910 > cluster it should fixes something. Unfortunately TH1520 seems to be not > so ready to test mainline patches on. > > arch/riscv/include/asm/errata_list.h | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/arch/riscv/include/asm/errata_list.h b/arch/riscv/include/asm/errata_list.h > index 4180312d2a70..605800bd390e 100644 > --- a/arch/riscv/include/asm/errata_list.h > +++ b/arch/riscv/include/asm/errata_list.h > @@ -102,7 +102,7 @@ asm volatile(ALTERNATIVE( \ > * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 | > * 0000001 01001 rs1 000 00000 0001011 > * dcache.cva rs1 (clean, virtual address) > - * 0000001 00100 rs1 000 00000 0001011 > + * 0000001 00101 rs1 000 00000 0001011 > * > * dcache.cipa rs1 (clean then invalidate, physical address) > * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 | > @@ -115,7 +115,7 @@ asm volatile(ALTERNATIVE( \ > * 0000000 11001 00000 000 00000 0001011 > */ > #define THEAD_inval_A0 ".long 0x0265000b" > -#define THEAD_clean_A0 ".long 0x0245000b" > +#define THEAD_clean_A0 ".long 0x0255000b" > #define THEAD_flush_A0 ".long 0x0275000b" > #define THEAD_SYNC_S ".long 0x0190000b" > > -- > 2.38.1 > -- Best Regards Guo Ren _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
WARNING: multiple messages have this Message-ID (diff)
From: Guo Ren <guoren@kernel.org> To: Icenowy Zheng <uwu@icenowy.me> Cc: Paul Walmsley <paul.walmsley@sifive.com>, Palmer Dabbelt <palmer@dabbelt.com>, Albert Ou <aou@eecs.berkeley.edu>, Heiko Stuebner <heiko@sntech.de>, Nathan Chancellor <nathan@kernel.org>, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 1/2] riscv: errata: fix T-Head dcache.cva encoding Date: Tue, 27 Dec 2022 10:47:31 +0800 [thread overview] Message-ID: <CAJF2gTSGvEnTqEqR9f+zU8T3VS8FoCtsgSk=9hz6cWxAL630zQ@mail.gmail.com> (raw) In-Reply-To: <20221227020258.303900-1-uwu@icenowy.me> Good catch. But I hope c906/910 can directly use paddr here. It's unnecessary to cause software translation & mmu translation here. diff --git a/arch/riscv/mm/dma-noncoherent.c b/arch/riscv/mm/dma-noncoherent.c index b0add983530a..30650a0c4481 100644 --- a/arch/riscv/mm/dma-noncoherent.c +++ b/arch/riscv/mm/dma-noncoherent.c @@ -24,13 +24,13 @@ void arch_sync_dma_for_device(phys_addr_t paddr, size_t size, switch (dir) { case DMA_TO_DEVICE: - ALT_CMO_OP(clean, vaddr, size, riscv_cbom_block_size); + ALT_CMO_OP(clean, vaddr, paddr, size, riscv_cbom_block_size); break; case DMA_FROM_DEVICE: - ALT_CMO_OP(clean, vaddr, size, riscv_cbom_block_size); + ALT_CMO_OP(clean, vaddr, paddr, size, riscv_cbom_block_size); break; case DMA_BIDIRECTIONAL: - ALT_CMO_OP(flush, vaddr, size, riscv_cbom_block_size); + ALT_CMO_OP(flush, vaddr, paddr, size, riscv_cbom_block_size); break; default: break; @@ -47,7 +47,7 @@ void arch_sync_dma_for_cpu(phys_addr_t paddr, size_t size, break; case DMA_FROM_DEVICE: case DMA_BIDIRECTIONAL: - ALT_CMO_OP(flush, vaddr, size, riscv_cbom_block_size); + ALT_CMO_OP(flush, vaddr, paddr, size, riscv_cbom_block_size); break; default: break; @@ -57,8 +57,9 @@ void arch_sync_dma_for_cpu(phys_addr_t paddr, size_t size, void arch_dma_prep_coherent(struct page *page, size_t size) { void *flush_addr = page_address(page); + phys_addr_t paddr = PFN_PHYS(page_to_pfn(x)); - ALT_CMO_OP(flush, flush_addr, size, riscv_cbom_block_size); + ALT_CMO_OP(flush, flush_addr, paddr, size, riscv_cbom_block_size); } On Tue, Dec 27, 2022 at 10:03 AM Icenowy Zheng <uwu@icenowy.me> wrote: > > The dcache.cva encoding shown in the comments are wrong, it's for > dcache.cval1 (which is restricted to L1) instead. > > Fix this in the comment and in the hardcoded instruction. > > Signed-off-by: Icenowy Zheng <uwu@icenowy.me> > --- > The code is tested on a LiteX SoC with OpenC906 core, and it > successfully boots to Systemd on a SD card connected to LiteSDCard. > > This change should be not noticable on C906, but on multi-core C910 > cluster it should fixes something. Unfortunately TH1520 seems to be not > so ready to test mainline patches on. > > arch/riscv/include/asm/errata_list.h | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/arch/riscv/include/asm/errata_list.h b/arch/riscv/include/asm/errata_list.h > index 4180312d2a70..605800bd390e 100644 > --- a/arch/riscv/include/asm/errata_list.h > +++ b/arch/riscv/include/asm/errata_list.h > @@ -102,7 +102,7 @@ asm volatile(ALTERNATIVE( \ > * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 | > * 0000001 01001 rs1 000 00000 0001011 > * dcache.cva rs1 (clean, virtual address) > - * 0000001 00100 rs1 000 00000 0001011 > + * 0000001 00101 rs1 000 00000 0001011 > * > * dcache.cipa rs1 (clean then invalidate, physical address) > * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 | > @@ -115,7 +115,7 @@ asm volatile(ALTERNATIVE( \ > * 0000000 11001 00000 000 00000 0001011 > */ > #define THEAD_inval_A0 ".long 0x0265000b" > -#define THEAD_clean_A0 ".long 0x0245000b" > +#define THEAD_clean_A0 ".long 0x0255000b" > #define THEAD_flush_A0 ".long 0x0275000b" > #define THEAD_SYNC_S ".long 0x0190000b" > > -- > 2.38.1 > -- Best Regards Guo Ren
next prev parent reply other threads:[~2022-12-27 2:48 UTC|newest] Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top 2022-12-27 2:02 [PATCH 1/2] riscv: errata: fix T-Head dcache.cva encoding Icenowy Zheng 2022-12-27 2:02 ` [PATCH 2/2] riscv: errata: prefix T-Head mnemonics with th Icenowy Zheng 2022-12-27 2:47 ` Guo Ren [this message] 2022-12-27 2:47 ` [PATCH 1/2] riscv: errata: fix T-Head dcache.cva encoding Guo Ren 2022-12-27 10:04 ` Icenowy Zheng 2022-12-27 10:04 ` Icenowy Zheng 2022-12-27 12:18 ` Conor Dooley 2022-12-27 12:18 ` Conor Dooley 2022-12-30 22:12 ` Sergey Matyukevich 2022-12-30 22:12 ` Sergey Matyukevich 2022-12-31 4:36 ` Icenowy Zheng 2022-12-31 4:36 ` Icenowy Zheng 2022-12-27 10:31 ` Heiko Stuebner 2022-12-27 10:31 ` Heiko Stuebner
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