[PATCH v2 1/2] arm64: dts: mt8173: Set uart to mmio32 iotype

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* [PATCH v2 1/2] arm64: dts: mt8173: Set uart to mmio32 iotype
@ 2020-09-10  8:43 ` Hsin-Yi Wang
  0 siblings, 0 replies; 15+ messages in thread
From: Hsin-Yi Wang @ 2020-09-10  8:43 UTC (permalink / raw)
  To: linux-mediatek
  Cc: Rob Herring, Matthias Brugger, devicetree, linux-arm-kernel,
	linux-kernel, Enric Balletbo i Serra

Set uart iotype to mmio32 to make earlycon work with stdout-path.

Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org>
---
 arch/arm64/boot/dts/mediatek/mt8173.dtsi | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
index 5e046f9d48ce9..ca6ea71f5f435 100644
--- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
@@ -613,6 +613,8 @@ uart0: serial@11002000 {
 			interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>;
 			clocks = <&pericfg CLK_PERI_UART0_SEL>, <&pericfg CLK_PERI_UART0>;
 			clock-names = "baud", "bus";
+			reg-io-width = <4>;
+			reg-shift = <2>;
 			status = "disabled";
 		};
 
@@ -623,6 +625,8 @@ uart1: serial@11003000 {
 			interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>;
 			clocks = <&pericfg CLK_PERI_UART1_SEL>, <&pericfg CLK_PERI_UART1>;
 			clock-names = "baud", "bus";
+			reg-io-width = <4>;
+			reg-shift = <2>;
 			status = "disabled";
 		};
 
@@ -633,6 +637,8 @@ uart2: serial@11004000 {
 			interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>;
 			clocks = <&pericfg CLK_PERI_UART2_SEL>, <&pericfg CLK_PERI_UART2>;
 			clock-names = "baud", "bus";
+			reg-io-width = <4>;
+			reg-shift = <2>;
 			status = "disabled";
 		};
 
@@ -643,6 +649,8 @@ uart3: serial@11005000 {
 			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>;
 			clocks = <&pericfg CLK_PERI_UART3_SEL>, <&pericfg CLK_PERI_UART3>;
 			clock-names = "baud", "bus";
+			reg-io-width = <4>;
+			reg-shift = <2>;
 			status = "disabled";
 		};
 
-- 
2.28.0.526.ge36021eeef-goog


^ permalink raw reply related	[flat|nested] 15+ messages in thread

* [PATCH v2 1/2] arm64: dts: mt8173: Set uart to mmio32 iotype
@ 2020-09-10  8:43 ` Hsin-Yi Wang
  0 siblings, 0 replies; 15+ messages in thread
From: Hsin-Yi Wang @ 2020-09-10  8:43 UTC (permalink / raw)
  To: linux-mediatek
  Cc: devicetree, linux-kernel, Enric Balletbo i Serra, Rob Herring,
	Matthias Brugger, linux-arm-kernel

Set uart iotype to mmio32 to make earlycon work with stdout-path.

Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org>
---
 arch/arm64/boot/dts/mediatek/mt8173.dtsi | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
index 5e046f9d48ce9..ca6ea71f5f435 100644
--- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
@@ -613,6 +613,8 @@ uart0: serial@11002000 {
 			interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>;
 			clocks = <&pericfg CLK_PERI_UART0_SEL>, <&pericfg CLK_PERI_UART0>;
 			clock-names = "baud", "bus";
+			reg-io-width = <4>;
+			reg-shift = <2>;
 			status = "disabled";
 		};
 
@@ -623,6 +625,8 @@ uart1: serial@11003000 {
 			interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>;
 			clocks = <&pericfg CLK_PERI_UART1_SEL>, <&pericfg CLK_PERI_UART1>;
 			clock-names = "baud", "bus";
+			reg-io-width = <4>;
+			reg-shift = <2>;
 			status = "disabled";
 		};
 
@@ -633,6 +637,8 @@ uart2: serial@11004000 {
 			interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>;
 			clocks = <&pericfg CLK_PERI_UART2_SEL>, <&pericfg CLK_PERI_UART2>;
 			clock-names = "baud", "bus";
+			reg-io-width = <4>;
+			reg-shift = <2>;
 			status = "disabled";
 		};
 
@@ -643,6 +649,8 @@ uart3: serial@11005000 {
 			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>;
 			clocks = <&pericfg CLK_PERI_UART3_SEL>, <&pericfg CLK_PERI_UART3>;
 			clock-names = "baud", "bus";
+			reg-io-width = <4>;
+			reg-shift = <2>;
 			status = "disabled";
 		};
 
-- 
2.28.0.526.ge36021eeef-goog


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply related	[flat|nested] 15+ messages in thread

* [PATCH v2 1/2] arm64: dts: mt8173: Set uart to mmio32 iotype
@ 2020-09-10  8:43 ` Hsin-Yi Wang
  0 siblings, 0 replies; 15+ messages in thread
From: Hsin-Yi Wang @ 2020-09-10  8:43 UTC (permalink / raw)
  To: linux-mediatek
  Cc: devicetree, linux-kernel, Enric Balletbo i Serra, Rob Herring,
	Matthias Brugger, linux-arm-kernel

Set uart iotype to mmio32 to make earlycon work with stdout-path.

Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org>
---
 arch/arm64/boot/dts/mediatek/mt8173.dtsi | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
index 5e046f9d48ce9..ca6ea71f5f435 100644
--- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
@@ -613,6 +613,8 @@ uart0: serial@11002000 {
 			interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>;
 			clocks = <&pericfg CLK_PERI_UART0_SEL>, <&pericfg CLK_PERI_UART0>;
 			clock-names = "baud", "bus";
+			reg-io-width = <4>;
+			reg-shift = <2>;
 			status = "disabled";
 		};
 
@@ -623,6 +625,8 @@ uart1: serial@11003000 {
 			interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>;
 			clocks = <&pericfg CLK_PERI_UART1_SEL>, <&pericfg CLK_PERI_UART1>;
 			clock-names = "baud", "bus";
+			reg-io-width = <4>;
+			reg-shift = <2>;
 			status = "disabled";
 		};
 
@@ -633,6 +637,8 @@ uart2: serial@11004000 {
 			interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>;
 			clocks = <&pericfg CLK_PERI_UART2_SEL>, <&pericfg CLK_PERI_UART2>;
 			clock-names = "baud", "bus";
+			reg-io-width = <4>;
+			reg-shift = <2>;
 			status = "disabled";
 		};
 
@@ -643,6 +649,8 @@ uart3: serial@11005000 {
 			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>;
 			clocks = <&pericfg CLK_PERI_UART3_SEL>, <&pericfg CLK_PERI_UART3>;
 			clock-names = "baud", "bus";
+			reg-io-width = <4>;
+			reg-shift = <2>;
 			status = "disabled";
 		};
 
-- 
2.28.0.526.ge36021eeef-goog


_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek

^ permalink raw reply related	[flat|nested] 15+ messages in thread

* [PATCH v2 2/2] arm64: dts: mt8183: Set uart to mmio32 iotype
  2020-09-10  8:43 ` Hsin-Yi Wang
  (?)
@ 2020-09-10  8:43   ` Hsin-Yi Wang
  -1 siblings, 0 replies; 15+ messages in thread
From: Hsin-Yi Wang @ 2020-09-10  8:43 UTC (permalink / raw)
  To: linux-mediatek
  Cc: Rob Herring, Matthias Brugger, devicetree, linux-arm-kernel,
	linux-kernel, Enric Balletbo i Serra

Set uart iotype to mmio32 to make earlycon work with stdout-path.

Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org>
---
 arch/arm64/boot/dts/mediatek/mt8183.dtsi | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
index 102105871db25..0bda97f912789 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
@@ -374,6 +374,8 @@ uart0: serial@11002000 {
 			interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
 			clocks = <&clk26m>, <&infracfg CLK_INFRA_UART0>;
 			clock-names = "baud", "bus";
+			reg-io-width = <4>;
+			reg-shift = <2>;
 			status = "disabled";
 		};
 
@@ -384,6 +386,8 @@ uart1: serial@11003000 {
 			interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>;
 			clocks = <&clk26m>, <&infracfg CLK_INFRA_UART1>;
 			clock-names = "baud", "bus";
+			reg-io-width = <4>;
+			reg-shift = <2>;
 			status = "disabled";
 		};
 
@@ -394,6 +398,8 @@ uart2: serial@11004000 {
 			interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>;
 			clocks = <&clk26m>, <&infracfg CLK_INFRA_UART2>;
 			clock-names = "baud", "bus";
+			reg-io-width = <4>;
+			reg-shift = <2>;
 			status = "disabled";
 		};
 
-- 
2.28.0.526.ge36021eeef-goog


^ permalink raw reply related	[flat|nested] 15+ messages in thread

* [PATCH v2 2/2] arm64: dts: mt8183: Set uart to mmio32 iotype
@ 2020-09-10  8:43   ` Hsin-Yi Wang
  0 siblings, 0 replies; 15+ messages in thread
From: Hsin-Yi Wang @ 2020-09-10  8:43 UTC (permalink / raw)
  To: linux-mediatek
  Cc: devicetree, linux-kernel, Enric Balletbo i Serra, Rob Herring,
	Matthias Brugger, linux-arm-kernel

Set uart iotype to mmio32 to make earlycon work with stdout-path.

Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org>
---
 arch/arm64/boot/dts/mediatek/mt8183.dtsi | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
index 102105871db25..0bda97f912789 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
@@ -374,6 +374,8 @@ uart0: serial@11002000 {
 			interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
 			clocks = <&clk26m>, <&infracfg CLK_INFRA_UART0>;
 			clock-names = "baud", "bus";
+			reg-io-width = <4>;
+			reg-shift = <2>;
 			status = "disabled";
 		};
 
@@ -384,6 +386,8 @@ uart1: serial@11003000 {
 			interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>;
 			clocks = <&clk26m>, <&infracfg CLK_INFRA_UART1>;
 			clock-names = "baud", "bus";
+			reg-io-width = <4>;
+			reg-shift = <2>;
 			status = "disabled";
 		};
 
@@ -394,6 +398,8 @@ uart2: serial@11004000 {
 			interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>;
 			clocks = <&clk26m>, <&infracfg CLK_INFRA_UART2>;
 			clock-names = "baud", "bus";
+			reg-io-width = <4>;
+			reg-shift = <2>;
 			status = "disabled";
 		};
 
-- 
2.28.0.526.ge36021eeef-goog


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply related	[flat|nested] 15+ messages in thread

* [PATCH v2 2/2] arm64: dts: mt8183: Set uart to mmio32 iotype
@ 2020-09-10  8:43   ` Hsin-Yi Wang
  0 siblings, 0 replies; 15+ messages in thread
From: Hsin-Yi Wang @ 2020-09-10  8:43 UTC (permalink / raw)
  To: linux-mediatek
  Cc: devicetree, linux-kernel, Enric Balletbo i Serra, Rob Herring,
	Matthias Brugger, linux-arm-kernel

Set uart iotype to mmio32 to make earlycon work with stdout-path.

Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org>
---
 arch/arm64/boot/dts/mediatek/mt8183.dtsi | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
index 102105871db25..0bda97f912789 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
@@ -374,6 +374,8 @@ uart0: serial@11002000 {
 			interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
 			clocks = <&clk26m>, <&infracfg CLK_INFRA_UART0>;
 			clock-names = "baud", "bus";
+			reg-io-width = <4>;
+			reg-shift = <2>;
 			status = "disabled";
 		};
 
@@ -384,6 +386,8 @@ uart1: serial@11003000 {
 			interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>;
 			clocks = <&clk26m>, <&infracfg CLK_INFRA_UART1>;
 			clock-names = "baud", "bus";
+			reg-io-width = <4>;
+			reg-shift = <2>;
 			status = "disabled";
 		};
 
@@ -394,6 +398,8 @@ uart2: serial@11004000 {
 			interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>;
 			clocks = <&clk26m>, <&infracfg CLK_INFRA_UART2>;
 			clock-names = "baud", "bus";
+			reg-io-width = <4>;
+			reg-shift = <2>;
 			status = "disabled";
 		};
 
-- 
2.28.0.526.ge36021eeef-goog


_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek

^ permalink raw reply related	[flat|nested] 15+ messages in thread

* Re: [PATCH v2 1/2] arm64: dts: mt8173: Set uart to mmio32 iotype
  2020-09-10  8:43 ` Hsin-Yi Wang
  (?)
@ 2020-09-10 10:25   ` Matthias Brugger
  -1 siblings, 0 replies; 15+ messages in thread
From: Matthias Brugger @ 2020-09-10 10:25 UTC (permalink / raw)
  To: Hsin-Yi Wang, linux-mediatek
  Cc: Rob Herring, devicetree, linux-arm-kernel, linux-kernel,
	Enric Balletbo i Serra, Eddie Huang

Hi,

On 10/09/2020 10:43, Hsin-Yi Wang wrote:
> Set uart iotype to mmio32 to make earlycon work with stdout-path.
> 
> Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org>
> ---
>   arch/arm64/boot/dts/mediatek/mt8173.dtsi | 8 ++++++++
>   1 file changed, 8 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> index 5e046f9d48ce9..ca6ea71f5f435 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> @@ -613,6 +613,8 @@ uart0: serial@11002000 {
>   			interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>;
>   			clocks = <&pericfg CLK_PERI_UART0_SEL>, <&pericfg CLK_PERI_UART0>;
>   			clock-names = "baud", "bus";
> +			reg-io-width = <4>;

Why do we need that, we have
device->port.iotype = UPIO_MEM32;
in early_mtk8250_setup(). That should do the job already.


> +			reg-shift = <2>;

Can't we just add
device->port.regshift = 2;
to early_mtk8250_setup()? I think that would be a cleaner solution. As the 
serial device is the same for all SoCs, I don't expect any regression here.

CCing Eddie to correct me, if I'm wrong :)

Regards,
Matthias

>   			status = "disabled";
>   		};
>   
> @@ -623,6 +625,8 @@ uart1: serial@11003000 {
>   			interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>;
>   			clocks = <&pericfg CLK_PERI_UART1_SEL>, <&pericfg CLK_PERI_UART1>;
>   			clock-names = "baud", "bus";
> +			reg-io-width = <4>;
> +			reg-shift = <2>;
>   			status = "disabled";
>   		};
>   
> @@ -633,6 +637,8 @@ uart2: serial@11004000 {
>   			interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>;
>   			clocks = <&pericfg CLK_PERI_UART2_SEL>, <&pericfg CLK_PERI_UART2>;
>   			clock-names = "baud", "bus";
> +			reg-io-width = <4>;
> +			reg-shift = <2>;
>   			status = "disabled";
>   		};
>   
> @@ -643,6 +649,8 @@ uart3: serial@11005000 {
>   			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>;
>   			clocks = <&pericfg CLK_PERI_UART3_SEL>, <&pericfg CLK_PERI_UART3>;
>   			clock-names = "baud", "bus";
> +			reg-io-width = <4>;
> +			reg-shift = <2>;
>   			status = "disabled";
>   		};
>   
> 

^ permalink raw reply	[flat|nested] 15+ messages in thread

* Re: [PATCH v2 1/2] arm64: dts: mt8173: Set uart to mmio32 iotype
@ 2020-09-10 10:25   ` Matthias Brugger
  0 siblings, 0 replies; 15+ messages in thread
From: Matthias Brugger @ 2020-09-10 10:25 UTC (permalink / raw)
  To: Hsin-Yi Wang, linux-mediatek
  Cc: devicetree, linux-kernel, Rob Herring, Enric Balletbo i Serra,
	Eddie Huang, linux-arm-kernel

Hi,

On 10/09/2020 10:43, Hsin-Yi Wang wrote:
> Set uart iotype to mmio32 to make earlycon work with stdout-path.
> 
> Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org>
> ---
>   arch/arm64/boot/dts/mediatek/mt8173.dtsi | 8 ++++++++
>   1 file changed, 8 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> index 5e046f9d48ce9..ca6ea71f5f435 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> @@ -613,6 +613,8 @@ uart0: serial@11002000 {
>   			interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>;
>   			clocks = <&pericfg CLK_PERI_UART0_SEL>, <&pericfg CLK_PERI_UART0>;
>   			clock-names = "baud", "bus";
> +			reg-io-width = <4>;

Why do we need that, we have
device->port.iotype = UPIO_MEM32;
in early_mtk8250_setup(). That should do the job already.


> +			reg-shift = <2>;

Can't we just add
device->port.regshift = 2;
to early_mtk8250_setup()? I think that would be a cleaner solution. As the 
serial device is the same for all SoCs, I don't expect any regression here.

CCing Eddie to correct me, if I'm wrong :)

Regards,
Matthias

>   			status = "disabled";
>   		};
>   
> @@ -623,6 +625,8 @@ uart1: serial@11003000 {
>   			interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>;
>   			clocks = <&pericfg CLK_PERI_UART1_SEL>, <&pericfg CLK_PERI_UART1>;
>   			clock-names = "baud", "bus";
> +			reg-io-width = <4>;
> +			reg-shift = <2>;
>   			status = "disabled";
>   		};
>   
> @@ -633,6 +637,8 @@ uart2: serial@11004000 {
>   			interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>;
>   			clocks = <&pericfg CLK_PERI_UART2_SEL>, <&pericfg CLK_PERI_UART2>;
>   			clock-names = "baud", "bus";
> +			reg-io-width = <4>;
> +			reg-shift = <2>;
>   			status = "disabled";
>   		};
>   
> @@ -643,6 +649,8 @@ uart3: serial@11005000 {
>   			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>;
>   			clocks = <&pericfg CLK_PERI_UART3_SEL>, <&pericfg CLK_PERI_UART3>;
>   			clock-names = "baud", "bus";
> +			reg-io-width = <4>;
> +			reg-shift = <2>;
>   			status = "disabled";
>   		};
>   
> 

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 15+ messages in thread

* Re: [PATCH v2 1/2] arm64: dts: mt8173: Set uart to mmio32 iotype
@ 2020-09-10 10:25   ` Matthias Brugger
  0 siblings, 0 replies; 15+ messages in thread
From: Matthias Brugger @ 2020-09-10 10:25 UTC (permalink / raw)
  To: Hsin-Yi Wang, linux-mediatek
  Cc: devicetree, linux-kernel, Rob Herring, Enric Balletbo i Serra,
	Eddie Huang, linux-arm-kernel

Hi,

On 10/09/2020 10:43, Hsin-Yi Wang wrote:
> Set uart iotype to mmio32 to make earlycon work with stdout-path.
> 
> Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org>
> ---
>   arch/arm64/boot/dts/mediatek/mt8173.dtsi | 8 ++++++++
>   1 file changed, 8 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> index 5e046f9d48ce9..ca6ea71f5f435 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> @@ -613,6 +613,8 @@ uart0: serial@11002000 {
>   			interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>;
>   			clocks = <&pericfg CLK_PERI_UART0_SEL>, <&pericfg CLK_PERI_UART0>;
>   			clock-names = "baud", "bus";
> +			reg-io-width = <4>;

Why do we need that, we have
device->port.iotype = UPIO_MEM32;
in early_mtk8250_setup(). That should do the job already.


> +			reg-shift = <2>;

Can't we just add
device->port.regshift = 2;
to early_mtk8250_setup()? I think that would be a cleaner solution. As the 
serial device is the same for all SoCs, I don't expect any regression here.

CCing Eddie to correct me, if I'm wrong :)

Regards,
Matthias

>   			status = "disabled";
>   		};
>   
> @@ -623,6 +625,8 @@ uart1: serial@11003000 {
>   			interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>;
>   			clocks = <&pericfg CLK_PERI_UART1_SEL>, <&pericfg CLK_PERI_UART1>;
>   			clock-names = "baud", "bus";
> +			reg-io-width = <4>;
> +			reg-shift = <2>;
>   			status = "disabled";
>   		};
>   
> @@ -633,6 +637,8 @@ uart2: serial@11004000 {
>   			interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>;
>   			clocks = <&pericfg CLK_PERI_UART2_SEL>, <&pericfg CLK_PERI_UART2>;
>   			clock-names = "baud", "bus";
> +			reg-io-width = <4>;
> +			reg-shift = <2>;
>   			status = "disabled";
>   		};
>   
> @@ -643,6 +649,8 @@ uart3: serial@11005000 {
>   			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>;
>   			clocks = <&pericfg CLK_PERI_UART3_SEL>, <&pericfg CLK_PERI_UART3>;
>   			clock-names = "baud", "bus";
> +			reg-io-width = <4>;
> +			reg-shift = <2>;
>   			status = "disabled";
>   		};
>   
> 

_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek

^ permalink raw reply	[flat|nested] 15+ messages in thread

* Re: [PATCH v2 1/2] arm64: dts: mt8173: Set uart to mmio32 iotype
  2020-09-10 10:25   ` Matthias Brugger
  (?)
@ 2020-09-10 13:40     ` Hsin-Yi Wang
  -1 siblings, 0 replies; 15+ messages in thread
From: Hsin-Yi Wang @ 2020-09-10 13:40 UTC (permalink / raw)
  To: Matthias Brugger
  Cc: moderated list:ARM/Mediatek SoC support, Rob Herring,
	Devicetree List,
	moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE, lkml,
	Enric Balletbo i Serra, Eddie Huang

On Thu, Sep 10, 2020 at 6:25 PM Matthias Brugger <matthias.bgg@gmail.com> wrote:
>
> Hi,
>
> On 10/09/2020 10:43, Hsin-Yi Wang wrote:
> > Set uart iotype to mmio32 to make earlycon work with stdout-path.
> >
> > Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org>
> > ---
> >   arch/arm64/boot/dts/mediatek/mt8173.dtsi | 8 ++++++++
> >   1 file changed, 8 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> > index 5e046f9d48ce9..ca6ea71f5f435 100644
> > --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> > +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> > @@ -613,6 +613,8 @@ uart0: serial@11002000 {
> >                       interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>;
> >                       clocks = <&pericfg CLK_PERI_UART0_SEL>, <&pericfg CLK_PERI_UART0>;
> >                       clock-names = "baud", "bus";
> > +                     reg-io-width = <4>;
>
> Why do we need that, we have
> device->port.iotype = UPIO_MEM32;
> in early_mtk8250_setup(). That should do the job already.
>
>

But if we don't change in dts, we would see
[    0.000000] earlycon: mtk8250 at MMIO 0x0000000011002000 (options '115200n8')
instead of
[    0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options
'115200n8')

Perhaps we should move the pr_info part in earlycon_init() after
match->setup(). Since setup may change iotype. What do you think?


> > +                     reg-shift = <2>;
>
> Can't we just add
> device->port.regshift = 2;
> to early_mtk8250_setup()? I think that would be a cleaner solution. As the
> serial device is the same for all SoCs, I don't expect any regression here.
>
> CCing Eddie to correct me, if I'm wrong :)
>
> Regards,
> Matthias
>
> >                       status = "disabled";
> >               };
> >
> > @@ -623,6 +625,8 @@ uart1: serial@11003000 {
> >                       interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>;
> >                       clocks = <&pericfg CLK_PERI_UART1_SEL>, <&pericfg CLK_PERI_UART1>;
> >                       clock-names = "baud", "bus";
> > +                     reg-io-width = <4>;
> > +                     reg-shift = <2>;
> >                       status = "disabled";
> >               };
> >
> > @@ -633,6 +637,8 @@ uart2: serial@11004000 {
> >                       interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>;
> >                       clocks = <&pericfg CLK_PERI_UART2_SEL>, <&pericfg CLK_PERI_UART2>;
> >                       clock-names = "baud", "bus";
> > +                     reg-io-width = <4>;
> > +                     reg-shift = <2>;
> >                       status = "disabled";
> >               };
> >
> > @@ -643,6 +649,8 @@ uart3: serial@11005000 {
> >                       interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>;
> >                       clocks = <&pericfg CLK_PERI_UART3_SEL>, <&pericfg CLK_PERI_UART3>;
> >                       clock-names = "baud", "bus";
> > +                     reg-io-width = <4>;
> > +                     reg-shift = <2>;
> >                       status = "disabled";
> >               };
> >
> >

^ permalink raw reply	[flat|nested] 15+ messages in thread

* Re: [PATCH v2 1/2] arm64: dts: mt8173: Set uart to mmio32 iotype
@ 2020-09-10 13:40     ` Hsin-Yi Wang
  0 siblings, 0 replies; 15+ messages in thread
From: Hsin-Yi Wang @ 2020-09-10 13:40 UTC (permalink / raw)
  To: Matthias Brugger
  Cc: Devicetree List, lkml, Rob Herring,
	moderated list:ARM/Mediatek SoC support, Enric Balletbo i Serra,
	Eddie Huang,
	moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE

On Thu, Sep 10, 2020 at 6:25 PM Matthias Brugger <matthias.bgg@gmail.com> wrote:
>
> Hi,
>
> On 10/09/2020 10:43, Hsin-Yi Wang wrote:
> > Set uart iotype to mmio32 to make earlycon work with stdout-path.
> >
> > Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org>
> > ---
> >   arch/arm64/boot/dts/mediatek/mt8173.dtsi | 8 ++++++++
> >   1 file changed, 8 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> > index 5e046f9d48ce9..ca6ea71f5f435 100644
> > --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> > +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> > @@ -613,6 +613,8 @@ uart0: serial@11002000 {
> >                       interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>;
> >                       clocks = <&pericfg CLK_PERI_UART0_SEL>, <&pericfg CLK_PERI_UART0>;
> >                       clock-names = "baud", "bus";
> > +                     reg-io-width = <4>;
>
> Why do we need that, we have
> device->port.iotype = UPIO_MEM32;
> in early_mtk8250_setup(). That should do the job already.
>
>

But if we don't change in dts, we would see
[    0.000000] earlycon: mtk8250 at MMIO 0x0000000011002000 (options '115200n8')
instead of
[    0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options
'115200n8')

Perhaps we should move the pr_info part in earlycon_init() after
match->setup(). Since setup may change iotype. What do you think?


> > +                     reg-shift = <2>;
>
> Can't we just add
> device->port.regshift = 2;
> to early_mtk8250_setup()? I think that would be a cleaner solution. As the
> serial device is the same for all SoCs, I don't expect any regression here.
>
> CCing Eddie to correct me, if I'm wrong :)
>
> Regards,
> Matthias
>
> >                       status = "disabled";
> >               };
> >
> > @@ -623,6 +625,8 @@ uart1: serial@11003000 {
> >                       interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>;
> >                       clocks = <&pericfg CLK_PERI_UART1_SEL>, <&pericfg CLK_PERI_UART1>;
> >                       clock-names = "baud", "bus";
> > +                     reg-io-width = <4>;
> > +                     reg-shift = <2>;
> >                       status = "disabled";
> >               };
> >
> > @@ -633,6 +637,8 @@ uart2: serial@11004000 {
> >                       interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>;
> >                       clocks = <&pericfg CLK_PERI_UART2_SEL>, <&pericfg CLK_PERI_UART2>;
> >                       clock-names = "baud", "bus";
> > +                     reg-io-width = <4>;
> > +                     reg-shift = <2>;
> >                       status = "disabled";
> >               };
> >
> > @@ -643,6 +649,8 @@ uart3: serial@11005000 {
> >                       interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>;
> >                       clocks = <&pericfg CLK_PERI_UART3_SEL>, <&pericfg CLK_PERI_UART3>;
> >                       clock-names = "baud", "bus";
> > +                     reg-io-width = <4>;
> > +                     reg-shift = <2>;
> >                       status = "disabled";
> >               };
> >
> >

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 15+ messages in thread

* Re: [PATCH v2 1/2] arm64: dts: mt8173: Set uart to mmio32 iotype
@ 2020-09-10 13:40     ` Hsin-Yi Wang
  0 siblings, 0 replies; 15+ messages in thread
From: Hsin-Yi Wang @ 2020-09-10 13:40 UTC (permalink / raw)
  To: Matthias Brugger
  Cc: Devicetree List, lkml, Rob Herring,
	moderated list:ARM/Mediatek SoC support, Enric Balletbo i Serra,
	Eddie Huang,
	moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE

On Thu, Sep 10, 2020 at 6:25 PM Matthias Brugger <matthias.bgg@gmail.com> wrote:
>
> Hi,
>
> On 10/09/2020 10:43, Hsin-Yi Wang wrote:
> > Set uart iotype to mmio32 to make earlycon work with stdout-path.
> >
> > Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org>
> > ---
> >   arch/arm64/boot/dts/mediatek/mt8173.dtsi | 8 ++++++++
> >   1 file changed, 8 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> > index 5e046f9d48ce9..ca6ea71f5f435 100644
> > --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> > +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> > @@ -613,6 +613,8 @@ uart0: serial@11002000 {
> >                       interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>;
> >                       clocks = <&pericfg CLK_PERI_UART0_SEL>, <&pericfg CLK_PERI_UART0>;
> >                       clock-names = "baud", "bus";
> > +                     reg-io-width = <4>;
>
> Why do we need that, we have
> device->port.iotype = UPIO_MEM32;
> in early_mtk8250_setup(). That should do the job already.
>
>

But if we don't change in dts, we would see
[    0.000000] earlycon: mtk8250 at MMIO 0x0000000011002000 (options '115200n8')
instead of
[    0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options
'115200n8')

Perhaps we should move the pr_info part in earlycon_init() after
match->setup(). Since setup may change iotype. What do you think?


> > +                     reg-shift = <2>;
>
> Can't we just add
> device->port.regshift = 2;
> to early_mtk8250_setup()? I think that would be a cleaner solution. As the
> serial device is the same for all SoCs, I don't expect any regression here.
>
> CCing Eddie to correct me, if I'm wrong :)
>
> Regards,
> Matthias
>
> >                       status = "disabled";
> >               };
> >
> > @@ -623,6 +625,8 @@ uart1: serial@11003000 {
> >                       interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>;
> >                       clocks = <&pericfg CLK_PERI_UART1_SEL>, <&pericfg CLK_PERI_UART1>;
> >                       clock-names = "baud", "bus";
> > +                     reg-io-width = <4>;
> > +                     reg-shift = <2>;
> >                       status = "disabled";
> >               };
> >
> > @@ -633,6 +637,8 @@ uart2: serial@11004000 {
> >                       interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>;
> >                       clocks = <&pericfg CLK_PERI_UART2_SEL>, <&pericfg CLK_PERI_UART2>;
> >                       clock-names = "baud", "bus";
> > +                     reg-io-width = <4>;
> > +                     reg-shift = <2>;
> >                       status = "disabled";
> >               };
> >
> > @@ -643,6 +649,8 @@ uart3: serial@11005000 {
> >                       interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>;
> >                       clocks = <&pericfg CLK_PERI_UART3_SEL>, <&pericfg CLK_PERI_UART3>;
> >                       clock-names = "baud", "bus";
> > +                     reg-io-width = <4>;
> > +                     reg-shift = <2>;
> >                       status = "disabled";
> >               };
> >
> >

_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek

^ permalink raw reply	[flat|nested] 15+ messages in thread

* Re: [PATCH v2 1/2] arm64: dts: mt8173: Set uart to mmio32 iotype
  2020-09-10 13:40     ` Hsin-Yi Wang
  (?)
@ 2020-09-11  9:43       ` Hsin-Yi Wang
  -1 siblings, 0 replies; 15+ messages in thread
From: Hsin-Yi Wang @ 2020-09-11  9:43 UTC (permalink / raw)
  To: Matthias Brugger
  Cc: moderated list:ARM/Mediatek SoC support, Rob Herring,
	Devicetree List,
	moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE, lkml,
	Enric Balletbo i Serra, Eddie Huang

On Thu, Sep 10, 2020 at 9:40 PM Hsin-Yi Wang <hsinyi@chromium.org> wrote:
>
> On Thu, Sep 10, 2020 at 6:25 PM Matthias Brugger <matthias.bgg@gmail.com> wrote:
> >
> > Hi,
> >
> > On 10/09/2020 10:43, Hsin-Yi Wang wrote:
> > > Set uart iotype to mmio32 to make earlycon work with stdout-path.
> > >
> > > Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org>
> > > ---
> > >   arch/arm64/boot/dts/mediatek/mt8173.dtsi | 8 ++++++++
> > >   1 file changed, 8 insertions(+)
> > >
> > > diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> > > index 5e046f9d48ce9..ca6ea71f5f435 100644
> > > --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> > > +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> > > @@ -613,6 +613,8 @@ uart0: serial@11002000 {
> > >                       interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>;
> > >                       clocks = <&pericfg CLK_PERI_UART0_SEL>, <&pericfg CLK_PERI_UART0>;
> > >                       clock-names = "baud", "bus";
> > > +                     reg-io-width = <4>;
> >
> > Why do we need that, we have
> > device->port.iotype = UPIO_MEM32;
> > in early_mtk8250_setup(). That should do the job already.
> >
> >
>
> But if we don't change in dts, we would see
> [    0.000000] earlycon: mtk8250 at MMIO 0x0000000011002000 (options '115200n8')
> instead of
> [    0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options
> '115200n8')
>
> Perhaps we should move the pr_info part in earlycon_init() after
> match->setup(). Since setup may change iotype. What do you think?
>

The series is sent here: https://lore.kernel.org/patchwork/patch/1304227/

Thanks.

^ permalink raw reply	[flat|nested] 15+ messages in thread

* Re: [PATCH v2 1/2] arm64: dts: mt8173: Set uart to mmio32 iotype
@ 2020-09-11  9:43       ` Hsin-Yi Wang
  0 siblings, 0 replies; 15+ messages in thread
From: Hsin-Yi Wang @ 2020-09-11  9:43 UTC (permalink / raw)
  To: Matthias Brugger
  Cc: Devicetree List, lkml, Rob Herring,
	moderated list:ARM/Mediatek SoC support, Enric Balletbo i Serra,
	Eddie Huang,
	moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE

On Thu, Sep 10, 2020 at 9:40 PM Hsin-Yi Wang <hsinyi@chromium.org> wrote:
>
> On Thu, Sep 10, 2020 at 6:25 PM Matthias Brugger <matthias.bgg@gmail.com> wrote:
> >
> > Hi,
> >
> > On 10/09/2020 10:43, Hsin-Yi Wang wrote:
> > > Set uart iotype to mmio32 to make earlycon work with stdout-path.
> > >
> > > Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org>
> > > ---
> > >   arch/arm64/boot/dts/mediatek/mt8173.dtsi | 8 ++++++++
> > >   1 file changed, 8 insertions(+)
> > >
> > > diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> > > index 5e046f9d48ce9..ca6ea71f5f435 100644
> > > --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> > > +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> > > @@ -613,6 +613,8 @@ uart0: serial@11002000 {
> > >                       interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>;
> > >                       clocks = <&pericfg CLK_PERI_UART0_SEL>, <&pericfg CLK_PERI_UART0>;
> > >                       clock-names = "baud", "bus";
> > > +                     reg-io-width = <4>;
> >
> > Why do we need that, we have
> > device->port.iotype = UPIO_MEM32;
> > in early_mtk8250_setup(). That should do the job already.
> >
> >
>
> But if we don't change in dts, we would see
> [    0.000000] earlycon: mtk8250 at MMIO 0x0000000011002000 (options '115200n8')
> instead of
> [    0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options
> '115200n8')
>
> Perhaps we should move the pr_info part in earlycon_init() after
> match->setup(). Since setup may change iotype. What do you think?
>

The series is sent here: https://lore.kernel.org/patchwork/patch/1304227/

Thanks.

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 15+ messages in thread

* Re: [PATCH v2 1/2] arm64: dts: mt8173: Set uart to mmio32 iotype
@ 2020-09-11  9:43       ` Hsin-Yi Wang
  0 siblings, 0 replies; 15+ messages in thread
From: Hsin-Yi Wang @ 2020-09-11  9:43 UTC (permalink / raw)
  To: Matthias Brugger
  Cc: Devicetree List, lkml, Rob Herring,
	moderated list:ARM/Mediatek SoC support, Enric Balletbo i Serra,
	Eddie Huang,
	moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE

On Thu, Sep 10, 2020 at 9:40 PM Hsin-Yi Wang <hsinyi@chromium.org> wrote:
>
> On Thu, Sep 10, 2020 at 6:25 PM Matthias Brugger <matthias.bgg@gmail.com> wrote:
> >
> > Hi,
> >
> > On 10/09/2020 10:43, Hsin-Yi Wang wrote:
> > > Set uart iotype to mmio32 to make earlycon work with stdout-path.
> > >
> > > Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org>
> > > ---
> > >   arch/arm64/boot/dts/mediatek/mt8173.dtsi | 8 ++++++++
> > >   1 file changed, 8 insertions(+)
> > >
> > > diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> > > index 5e046f9d48ce9..ca6ea71f5f435 100644
> > > --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> > > +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> > > @@ -613,6 +613,8 @@ uart0: serial@11002000 {
> > >                       interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>;
> > >                       clocks = <&pericfg CLK_PERI_UART0_SEL>, <&pericfg CLK_PERI_UART0>;
> > >                       clock-names = "baud", "bus";
> > > +                     reg-io-width = <4>;
> >
> > Why do we need that, we have
> > device->port.iotype = UPIO_MEM32;
> > in early_mtk8250_setup(). That should do the job already.
> >
> >
>
> But if we don't change in dts, we would see
> [    0.000000] earlycon: mtk8250 at MMIO 0x0000000011002000 (options '115200n8')
> instead of
> [    0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options
> '115200n8')
>
> Perhaps we should move the pr_info part in earlycon_init() after
> match->setup(). Since setup may change iotype. What do you think?
>

The series is sent here: https://lore.kernel.org/patchwork/patch/1304227/

Thanks.

_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek

^ permalink raw reply	[flat|nested] 15+ messages in thread

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2020-09-10  8:43 [PATCH v2 1/2] arm64: dts: mt8173: Set uart to mmio32 iotype Hsin-Yi Wang
2020-09-10  8:43 ` Hsin-Yi Wang
2020-09-10  8:43 ` Hsin-Yi Wang
2020-09-10  8:43 ` [PATCH v2 2/2] arm64: dts: mt8183: " Hsin-Yi Wang
2020-09-10  8:43   ` Hsin-Yi Wang
2020-09-10  8:43   ` Hsin-Yi Wang
2020-09-10 10:25 ` [PATCH v2 1/2] arm64: dts: mt8173: " Matthias Brugger
2020-09-10 10:25   ` Matthias Brugger
2020-09-10 10:25   ` Matthias Brugger
2020-09-10 13:40   ` Hsin-Yi Wang
2020-09-10 13:40     ` Hsin-Yi Wang
2020-09-10 13:40     ` Hsin-Yi Wang
2020-09-11  9:43     ` Hsin-Yi Wang
2020-09-11  9:43       ` Hsin-Yi Wang
2020-09-11  9:43       ` Hsin-Yi Wang

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