* [PATCH v2 0/7] Add basic node support for Mediatek MT8186 SoC
@ 2022-01-05 2:27 ` allen-kh.cheng
0 siblings, 0 replies; 21+ messages in thread
From: allen-kh.cheng @ 2022-01-05 2:27 UTC (permalink / raw)
To: Ulf Hansson, Rob Herring, Matthias Brugger,
Kishon Vijay Abraham I, Vinod Koul, Greg Kroah-Hartman,
Daniel Lezcano, Thomas Gleixner, Wim Van Sebroeck, Guenter Roeck
Cc: hsinyi, Project_Global_Chrome_Upstream_Group, linux-kernel,
devicetree, linux-mediatek, linux-arm-kernel, linux-iio,
linux-mmc, linux-serial, linux-spi, linux-watchdog,
Allen-KH Cheng
From: Allen-KH Cheng <Allen-KH.Cheng@mediatek.com>
MT8186 is a SoC based on 64bit ARMv8 architecture.
It contains 6 CA55 and 2 CA78 cores.
MT8186 share many HW IP with MT65xx series.
This patchset was tested on MT8186 evaluation board to shell.
Based on v5.16-rc8
changes since v1:
- add dt-bindings: arm: Add compatible for Mediatek MT8186
Allen-KH Cheng (7):
dt-bindings: timer: Add compatible for Mediatek MT8186
dt-bindings: serial: Add compatible for Mediatek MT8186
dt-bindings: watchdog: Add compatible for Mediatek MT8186
dt-bindings: mmc: Add compatible for Mediatek MT8186
dt-bindings: phy: Add compatible for Mediatek MT8186
dt-bindings: arm: Add compatible for Mediatek MT8186
arm64: dts: Add Mediatek SoC MT8186 dts and evaluation board and
Makefile
.../devicetree/bindings/arm/mediatek.yaml | 4 +
.../devicetree/bindings/mmc/mtk-sd.yaml | 3 +
.../bindings/phy/mediatek,tphy.yaml | 1 +
.../devicetree/bindings/serial/mtk-uart.txt | 1 +
.../bindings/timer/mediatek,mtk-timer.txt | 1 +
.../devicetree/bindings/watchdog/mtk-wdt.txt | 1 +
arch/arm64/boot/dts/mediatek/Makefile | 1 +
arch/arm64/boot/dts/mediatek/mt8186-evb.dts | 24 ++
arch/arm64/boot/dts/mediatek/mt8186.dtsi | 352 ++++++++++++++++++
9 files changed, 388 insertions(+)
create mode 100644 arch/arm64/boot/dts/mediatek/mt8186-evb.dts
create mode 100644 arch/arm64/boot/dts/mediatek/mt8186.dtsi
--
2.18.0
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 21+ messages in thread
* [PATCH v2 0/7] Add basic node support for Mediatek MT8186 SoC
@ 2022-01-05 2:27 ` allen-kh.cheng
0 siblings, 0 replies; 21+ messages in thread
From: allen-kh.cheng @ 2022-01-05 2:27 UTC (permalink / raw)
To: Ulf Hansson, Rob Herring, Matthias Brugger,
Kishon Vijay Abraham I, Vinod Koul, Greg Kroah-Hartman,
Daniel Lezcano, Thomas Gleixner, Wim Van Sebroeck, Guenter Roeck
Cc: hsinyi, Project_Global_Chrome_Upstream_Group, linux-kernel,
devicetree, linux-mediatek, linux-arm-kernel, linux-iio,
linux-mmc, linux-serial, linux-spi, linux-watchdog,
Allen-KH Cheng
From: Allen-KH Cheng <Allen-KH.Cheng@mediatek.com>
MT8186 is a SoC based on 64bit ARMv8 architecture.
It contains 6 CA55 and 2 CA78 cores.
MT8186 share many HW IP with MT65xx series.
This patchset was tested on MT8186 evaluation board to shell.
Based on v5.16-rc8
changes since v1:
- add dt-bindings: arm: Add compatible for Mediatek MT8186
Allen-KH Cheng (7):
dt-bindings: timer: Add compatible for Mediatek MT8186
dt-bindings: serial: Add compatible for Mediatek MT8186
dt-bindings: watchdog: Add compatible for Mediatek MT8186
dt-bindings: mmc: Add compatible for Mediatek MT8186
dt-bindings: phy: Add compatible for Mediatek MT8186
dt-bindings: arm: Add compatible for Mediatek MT8186
arm64: dts: Add Mediatek SoC MT8186 dts and evaluation board and
Makefile
.../devicetree/bindings/arm/mediatek.yaml | 4 +
.../devicetree/bindings/mmc/mtk-sd.yaml | 3 +
.../bindings/phy/mediatek,tphy.yaml | 1 +
.../devicetree/bindings/serial/mtk-uart.txt | 1 +
.../bindings/timer/mediatek,mtk-timer.txt | 1 +
.../devicetree/bindings/watchdog/mtk-wdt.txt | 1 +
arch/arm64/boot/dts/mediatek/Makefile | 1 +
arch/arm64/boot/dts/mediatek/mt8186-evb.dts | 24 ++
arch/arm64/boot/dts/mediatek/mt8186.dtsi | 352 ++++++++++++++++++
9 files changed, 388 insertions(+)
create mode 100644 arch/arm64/boot/dts/mediatek/mt8186-evb.dts
create mode 100644 arch/arm64/boot/dts/mediatek/mt8186.dtsi
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 21+ messages in thread
* [PATCH v2 1/7] dt-bindings: timer: Add compatible for Mediatek MT8186
2022-01-05 2:27 ` allen-kh.cheng
@ 2022-01-05 2:27 ` allen-kh.cheng
-1 siblings, 0 replies; 21+ messages in thread
From: allen-kh.cheng @ 2022-01-05 2:27 UTC (permalink / raw)
To: Ulf Hansson, Rob Herring, Matthias Brugger,
Kishon Vijay Abraham I, Vinod Koul, Greg Kroah-Hartman,
Daniel Lezcano, Thomas Gleixner, Wim Van Sebroeck, Guenter Roeck
Cc: hsinyi, Project_Global_Chrome_Upstream_Group, linux-kernel,
devicetree, linux-mediatek, linux-arm-kernel, linux-iio,
linux-mmc, linux-serial, linux-spi, linux-watchdog,
Allen-KH Cheng
From: Allen-KH Cheng <Allen-KH.Cheng@mediatek.com>
This commit adds dt-binding documentation of timer for Mediatek MT8186 SoC
Platform.
Signed-off-by: Allen-KH Cheng <Allen-KH.Cheng@mediatek.com>
---
Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt b/Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt
index e5c57d6e0186..e0d20d6adf81 100644
--- a/Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt
+++ b/Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt
@@ -22,6 +22,7 @@ Required properties:
For those SoCs that use SYST
* "mediatek,mt8183-timer" for MT8183 compatible timers (SYST)
+ * "mediatek,mt8186-timer" for MT8186 compatible timers (SYST)
* "mediatek,mt8192-timer" for MT8192 compatible timers (SYST)
* "mediatek,mt8195-timer" for MT8195 compatible timers (SYST)
* "mediatek,mt7629-timer" for MT7629 compatible timers (SYST)
--
2.18.0
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH v2 1/7] dt-bindings: timer: Add compatible for Mediatek MT8186
@ 2022-01-05 2:27 ` allen-kh.cheng
0 siblings, 0 replies; 21+ messages in thread
From: allen-kh.cheng @ 2022-01-05 2:27 UTC (permalink / raw)
To: Ulf Hansson, Rob Herring, Matthias Brugger,
Kishon Vijay Abraham I, Vinod Koul, Greg Kroah-Hartman,
Daniel Lezcano, Thomas Gleixner, Wim Van Sebroeck, Guenter Roeck
Cc: hsinyi, Project_Global_Chrome_Upstream_Group, linux-kernel,
devicetree, linux-mediatek, linux-arm-kernel, linux-iio,
linux-mmc, linux-serial, linux-spi, linux-watchdog,
Allen-KH Cheng
From: Allen-KH Cheng <Allen-KH.Cheng@mediatek.com>
This commit adds dt-binding documentation of timer for Mediatek MT8186 SoC
Platform.
Signed-off-by: Allen-KH Cheng <Allen-KH.Cheng@mediatek.com>
---
Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt b/Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt
index e5c57d6e0186..e0d20d6adf81 100644
--- a/Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt
+++ b/Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt
@@ -22,6 +22,7 @@ Required properties:
For those SoCs that use SYST
* "mediatek,mt8183-timer" for MT8183 compatible timers (SYST)
+ * "mediatek,mt8186-timer" for MT8186 compatible timers (SYST)
* "mediatek,mt8192-timer" for MT8192 compatible timers (SYST)
* "mediatek,mt8195-timer" for MT8195 compatible timers (SYST)
* "mediatek,mt7629-timer" for MT7629 compatible timers (SYST)
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH v2 2/7] dt-bindings: serial: Add compatible for Mediatek MT8186
2022-01-05 2:27 ` allen-kh.cheng
@ 2022-01-05 2:27 ` allen-kh.cheng
-1 siblings, 0 replies; 21+ messages in thread
From: allen-kh.cheng @ 2022-01-05 2:27 UTC (permalink / raw)
To: Ulf Hansson, Rob Herring, Matthias Brugger,
Kishon Vijay Abraham I, Vinod Koul, Greg Kroah-Hartman,
Daniel Lezcano, Thomas Gleixner, Wim Van Sebroeck, Guenter Roeck
Cc: hsinyi, Project_Global_Chrome_Upstream_Group, linux-kernel,
devicetree, linux-mediatek, linux-arm-kernel, linux-iio,
linux-mmc, linux-serial, linux-spi, linux-watchdog,
Allen-KH Cheng
From: Allen-KH Cheng <Allen-KH.Cheng@mediatek.com>
This commit adds dt-binding documentation of uart for Mediatek MT8186 SoC
Platform.
Signed-off-by: Allen-KH Cheng <Allen-KH.Cheng@mediatek.com>
---
Documentation/devicetree/bindings/serial/mtk-uart.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/serial/mtk-uart.txt b/Documentation/devicetree/bindings/serial/mtk-uart.txt
index b3a0bfef0d54..113b5d6a2245 100644
--- a/Documentation/devicetree/bindings/serial/mtk-uart.txt
+++ b/Documentation/devicetree/bindings/serial/mtk-uart.txt
@@ -20,6 +20,7 @@ Required properties:
* "mediatek,mt8135-uart" for MT8135 compatible UARTS
* "mediatek,mt8173-uart" for MT8173 compatible UARTS
* "mediatek,mt8183-uart", "mediatek,mt6577-uart" for MT8183 compatible UARTS
+ * "mediatek,mt8186-uart", "mediatek,mt6577-uart" for MT8183 compatible UARTS
* "mediatek,mt8192-uart", "mediatek,mt6577-uart" for MT8192 compatible UARTS
* "mediatek,mt8195-uart", "mediatek,mt6577-uart" for MT8195 compatible UARTS
* "mediatek,mt8516-uart" for MT8516 compatible UARTS
--
2.18.0
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH v2 2/7] dt-bindings: serial: Add compatible for Mediatek MT8186
@ 2022-01-05 2:27 ` allen-kh.cheng
0 siblings, 0 replies; 21+ messages in thread
From: allen-kh.cheng @ 2022-01-05 2:27 UTC (permalink / raw)
To: Ulf Hansson, Rob Herring, Matthias Brugger,
Kishon Vijay Abraham I, Vinod Koul, Greg Kroah-Hartman,
Daniel Lezcano, Thomas Gleixner, Wim Van Sebroeck, Guenter Roeck
Cc: hsinyi, Project_Global_Chrome_Upstream_Group, linux-kernel,
devicetree, linux-mediatek, linux-arm-kernel, linux-iio,
linux-mmc, linux-serial, linux-spi, linux-watchdog,
Allen-KH Cheng
From: Allen-KH Cheng <Allen-KH.Cheng@mediatek.com>
This commit adds dt-binding documentation of uart for Mediatek MT8186 SoC
Platform.
Signed-off-by: Allen-KH Cheng <Allen-KH.Cheng@mediatek.com>
---
Documentation/devicetree/bindings/serial/mtk-uart.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/serial/mtk-uart.txt b/Documentation/devicetree/bindings/serial/mtk-uart.txt
index b3a0bfef0d54..113b5d6a2245 100644
--- a/Documentation/devicetree/bindings/serial/mtk-uart.txt
+++ b/Documentation/devicetree/bindings/serial/mtk-uart.txt
@@ -20,6 +20,7 @@ Required properties:
* "mediatek,mt8135-uart" for MT8135 compatible UARTS
* "mediatek,mt8173-uart" for MT8173 compatible UARTS
* "mediatek,mt8183-uart", "mediatek,mt6577-uart" for MT8183 compatible UARTS
+ * "mediatek,mt8186-uart", "mediatek,mt6577-uart" for MT8183 compatible UARTS
* "mediatek,mt8192-uart", "mediatek,mt6577-uart" for MT8192 compatible UARTS
* "mediatek,mt8195-uart", "mediatek,mt6577-uart" for MT8195 compatible UARTS
* "mediatek,mt8516-uart" for MT8516 compatible UARTS
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH v2 3/7] dt-bindings: watchdog: Add compatible for Mediatek MT8186
2022-01-05 2:27 ` allen-kh.cheng
@ 2022-01-05 2:27 ` allen-kh.cheng
-1 siblings, 0 replies; 21+ messages in thread
From: allen-kh.cheng @ 2022-01-05 2:27 UTC (permalink / raw)
To: Ulf Hansson, Rob Herring, Matthias Brugger,
Kishon Vijay Abraham I, Vinod Koul, Greg Kroah-Hartman,
Daniel Lezcano, Thomas Gleixner, Wim Van Sebroeck, Guenter Roeck
Cc: hsinyi, Project_Global_Chrome_Upstream_Group, linux-kernel,
devicetree, linux-mediatek, linux-arm-kernel, linux-iio,
linux-mmc, linux-serial, linux-spi, linux-watchdog,
Allen-KH Cheng
From: Allen-KH Cheng <Allen-KH.Cheng@mediatek.com>
This commit adds dt-binding documentation of watchdog for Mediatek MT8186 SoC
Platform.
Signed-off-by: Allen-KH Cheng <Allen-KH.Cheng@mediatek.com>
---
Documentation/devicetree/bindings/watchdog/mtk-wdt.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt b/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt
index 0114871f887a..74db01e3658b 100644
--- a/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt
+++ b/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt
@@ -15,6 +15,7 @@ Required properties:
"mediatek,mt7629-wdt", "mediatek,mt6589-wdt": for MT7629
"mediatek,mt7986-wdt", "mediatek,mt6589-wdt": for MT7986
"mediatek,mt8183-wdt": for MT8183
+ "mediatek,mt8186-wdt", "mediatek,mt6589-wdt": for MT8186
"mediatek,mt8516-wdt", "mediatek,mt6589-wdt": for MT8516
"mediatek,mt8192-wdt": for MT8192
"mediatek,mt8195-wdt", "mediatek,mt6589-wdt": for MT8195
--
2.18.0
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH v2 3/7] dt-bindings: watchdog: Add compatible for Mediatek MT8186
@ 2022-01-05 2:27 ` allen-kh.cheng
0 siblings, 0 replies; 21+ messages in thread
From: allen-kh.cheng @ 2022-01-05 2:27 UTC (permalink / raw)
To: Ulf Hansson, Rob Herring, Matthias Brugger,
Kishon Vijay Abraham I, Vinod Koul, Greg Kroah-Hartman,
Daniel Lezcano, Thomas Gleixner, Wim Van Sebroeck, Guenter Roeck
Cc: hsinyi, Project_Global_Chrome_Upstream_Group, linux-kernel,
devicetree, linux-mediatek, linux-arm-kernel, linux-iio,
linux-mmc, linux-serial, linux-spi, linux-watchdog,
Allen-KH Cheng
From: Allen-KH Cheng <Allen-KH.Cheng@mediatek.com>
This commit adds dt-binding documentation of watchdog for Mediatek MT8186 SoC
Platform.
Signed-off-by: Allen-KH Cheng <Allen-KH.Cheng@mediatek.com>
---
Documentation/devicetree/bindings/watchdog/mtk-wdt.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt b/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt
index 0114871f887a..74db01e3658b 100644
--- a/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt
+++ b/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt
@@ -15,6 +15,7 @@ Required properties:
"mediatek,mt7629-wdt", "mediatek,mt6589-wdt": for MT7629
"mediatek,mt7986-wdt", "mediatek,mt6589-wdt": for MT7986
"mediatek,mt8183-wdt": for MT8183
+ "mediatek,mt8186-wdt", "mediatek,mt6589-wdt": for MT8186
"mediatek,mt8516-wdt", "mediatek,mt6589-wdt": for MT8516
"mediatek,mt8192-wdt": for MT8192
"mediatek,mt8195-wdt", "mediatek,mt6589-wdt": for MT8195
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH v2 4/7] dt-bindings: mmc: Add compatible for Mediatek MT8186
2022-01-05 2:27 ` allen-kh.cheng
@ 2022-01-05 2:27 ` allen-kh.cheng
-1 siblings, 0 replies; 21+ messages in thread
From: allen-kh.cheng @ 2022-01-05 2:27 UTC (permalink / raw)
To: Ulf Hansson, Rob Herring, Matthias Brugger,
Kishon Vijay Abraham I, Vinod Koul, Greg Kroah-Hartman,
Daniel Lezcano, Thomas Gleixner, Wim Van Sebroeck, Guenter Roeck
Cc: hsinyi, Project_Global_Chrome_Upstream_Group, linux-kernel,
devicetree, linux-mediatek, linux-arm-kernel, linux-iio,
linux-mmc, linux-serial, linux-spi, linux-watchdog,
Allen-KH Cheng
From: Allen-KH Cheng <Allen-KH.Cheng@mediatek.com>
This commit adds dt-binding documentation of mmc for Mediatek MT8186 SoC
Platform.
Signed-off-by: Allen-KH Cheng <Allen-KH.Cheng@mediatek.com>
---
Documentation/devicetree/bindings/mmc/mtk-sd.yaml | 3 +++
1 file changed, 3 insertions(+)
diff --git a/Documentation/devicetree/bindings/mmc/mtk-sd.yaml b/Documentation/devicetree/bindings/mmc/mtk-sd.yaml
index 82768a807294..164df702482f 100644
--- a/Documentation/devicetree/bindings/mmc/mtk-sd.yaml
+++ b/Documentation/devicetree/bindings/mmc/mtk-sd.yaml
@@ -29,6 +29,9 @@ properties:
- items:
- const: mediatek,mt7623-mmc
- const: mediatek,mt2701-mmc
+ - items:
+ - const: mediatek,mt8186-mmc
+ - const: mediatek,mt8183-mmc
- items:
- const: mediatek,mt8192-mmc
- const: mediatek,mt8183-mmc
--
2.18.0
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH v2 4/7] dt-bindings: mmc: Add compatible for Mediatek MT8186
@ 2022-01-05 2:27 ` allen-kh.cheng
0 siblings, 0 replies; 21+ messages in thread
From: allen-kh.cheng @ 2022-01-05 2:27 UTC (permalink / raw)
To: Ulf Hansson, Rob Herring, Matthias Brugger,
Kishon Vijay Abraham I, Vinod Koul, Greg Kroah-Hartman,
Daniel Lezcano, Thomas Gleixner, Wim Van Sebroeck, Guenter Roeck
Cc: hsinyi, Project_Global_Chrome_Upstream_Group, linux-kernel,
devicetree, linux-mediatek, linux-arm-kernel, linux-iio,
linux-mmc, linux-serial, linux-spi, linux-watchdog,
Allen-KH Cheng
From: Allen-KH Cheng <Allen-KH.Cheng@mediatek.com>
This commit adds dt-binding documentation of mmc for Mediatek MT8186 SoC
Platform.
Signed-off-by: Allen-KH Cheng <Allen-KH.Cheng@mediatek.com>
---
Documentation/devicetree/bindings/mmc/mtk-sd.yaml | 3 +++
1 file changed, 3 insertions(+)
diff --git a/Documentation/devicetree/bindings/mmc/mtk-sd.yaml b/Documentation/devicetree/bindings/mmc/mtk-sd.yaml
index 82768a807294..164df702482f 100644
--- a/Documentation/devicetree/bindings/mmc/mtk-sd.yaml
+++ b/Documentation/devicetree/bindings/mmc/mtk-sd.yaml
@@ -29,6 +29,9 @@ properties:
- items:
- const: mediatek,mt7623-mmc
- const: mediatek,mt2701-mmc
+ - items:
+ - const: mediatek,mt8186-mmc
+ - const: mediatek,mt8183-mmc
- items:
- const: mediatek,mt8192-mmc
- const: mediatek,mt8183-mmc
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH v2 5/7] dt-bindings: phy: Add compatible for Mediatek MT8186
2022-01-05 2:27 ` allen-kh.cheng
@ 2022-01-05 2:27 ` allen-kh.cheng
-1 siblings, 0 replies; 21+ messages in thread
From: allen-kh.cheng @ 2022-01-05 2:27 UTC (permalink / raw)
To: Ulf Hansson, Rob Herring, Matthias Brugger,
Kishon Vijay Abraham I, Vinod Koul, Greg Kroah-Hartman,
Daniel Lezcano, Thomas Gleixner, Wim Van Sebroeck, Guenter Roeck
Cc: hsinyi, Project_Global_Chrome_Upstream_Group, linux-kernel,
devicetree, linux-mediatek, linux-arm-kernel, linux-iio,
linux-mmc, linux-serial, linux-spi, linux-watchdog,
Allen-KH Cheng
From: Allen-KH Cheng <Allen-KH.Cheng@mediatek.com>
This commit adds dt-binding documentation of T-Phy for Mediatek MT8186 SoC
Platform.
Signed-off-by: Allen-KH Cheng <Allen-KH.Cheng@mediatek.com>
---
Documentation/devicetree/bindings/phy/mediatek,tphy.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/phy/mediatek,tphy.yaml b/Documentation/devicetree/bindings/phy/mediatek,tphy.yaml
index 9e6c0f43f1c6..cadbc696b3f5 100644
--- a/Documentation/devicetree/bindings/phy/mediatek,tphy.yaml
+++ b/Documentation/devicetree/bindings/phy/mediatek,tphy.yaml
@@ -80,6 +80,7 @@ properties:
- mediatek,mt2712-tphy
- mediatek,mt7629-tphy
- mediatek,mt8183-tphy
+ - mediatek,mt8186-tphy
- const: mediatek,generic-tphy-v2
- items:
- enum:
--
2.18.0
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH v2 5/7] dt-bindings: phy: Add compatible for Mediatek MT8186
@ 2022-01-05 2:27 ` allen-kh.cheng
0 siblings, 0 replies; 21+ messages in thread
From: allen-kh.cheng @ 2022-01-05 2:27 UTC (permalink / raw)
To: Ulf Hansson, Rob Herring, Matthias Brugger,
Kishon Vijay Abraham I, Vinod Koul, Greg Kroah-Hartman,
Daniel Lezcano, Thomas Gleixner, Wim Van Sebroeck, Guenter Roeck
Cc: hsinyi, Project_Global_Chrome_Upstream_Group, linux-kernel,
devicetree, linux-mediatek, linux-arm-kernel, linux-iio,
linux-mmc, linux-serial, linux-spi, linux-watchdog,
Allen-KH Cheng
From: Allen-KH Cheng <Allen-KH.Cheng@mediatek.com>
This commit adds dt-binding documentation of T-Phy for Mediatek MT8186 SoC
Platform.
Signed-off-by: Allen-KH Cheng <Allen-KH.Cheng@mediatek.com>
---
Documentation/devicetree/bindings/phy/mediatek,tphy.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/phy/mediatek,tphy.yaml b/Documentation/devicetree/bindings/phy/mediatek,tphy.yaml
index 9e6c0f43f1c6..cadbc696b3f5 100644
--- a/Documentation/devicetree/bindings/phy/mediatek,tphy.yaml
+++ b/Documentation/devicetree/bindings/phy/mediatek,tphy.yaml
@@ -80,6 +80,7 @@ properties:
- mediatek,mt2712-tphy
- mediatek,mt7629-tphy
- mediatek,mt8183-tphy
+ - mediatek,mt8186-tphy
- const: mediatek,generic-tphy-v2
- items:
- enum:
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH v2 6/7] dt-bindings: arm: Add compatible for Mediatek MT8186
2022-01-05 2:27 ` allen-kh.cheng
@ 2022-01-05 2:27 ` allen-kh.cheng
-1 siblings, 0 replies; 21+ messages in thread
From: allen-kh.cheng @ 2022-01-05 2:27 UTC (permalink / raw)
To: Ulf Hansson, Rob Herring, Matthias Brugger,
Kishon Vijay Abraham I, Vinod Koul, Greg Kroah-Hartman,
Daniel Lezcano, Thomas Gleixner, Wim Van Sebroeck, Guenter Roeck
Cc: hsinyi, Project_Global_Chrome_Upstream_Group, linux-kernel,
devicetree, linux-mediatek, linux-arm-kernel, linux-iio,
linux-mmc, linux-serial, linux-spi, linux-watchdog,
Allen-KH Cheng
From: Allen-KH Cheng <Allen-KH.Cheng@mediatek.com>
This commit adds dt-binding documentation for the Mediatek MT8186
reference board.
Signed-off-by: Allen-KH Cheng <Allen-KH.Cheng@mediatek.com>
---
Documentation/devicetree/bindings/arm/mediatek.yaml | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/mediatek.yaml b/Documentation/devicetree/bindings/arm/mediatek.yaml
index 0fa55497b96f..8fd78bd9931c 100644
--- a/Documentation/devicetree/bindings/arm/mediatek.yaml
+++ b/Documentation/devicetree/bindings/arm/mediatek.yaml
@@ -119,6 +119,10 @@ properties:
- enum:
- mediatek,mt8183-evb
- const: mediatek,mt8183
+ - items:
+ - enum:
+ - mediatek,mt8186-evb
+ - const: mediatek,mt8186
- items:
- enum:
- mediatek,mt8195-evb
--
2.18.0
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH v2 6/7] dt-bindings: arm: Add compatible for Mediatek MT8186
@ 2022-01-05 2:27 ` allen-kh.cheng
0 siblings, 0 replies; 21+ messages in thread
From: allen-kh.cheng @ 2022-01-05 2:27 UTC (permalink / raw)
To: Ulf Hansson, Rob Herring, Matthias Brugger,
Kishon Vijay Abraham I, Vinod Koul, Greg Kroah-Hartman,
Daniel Lezcano, Thomas Gleixner, Wim Van Sebroeck, Guenter Roeck
Cc: hsinyi, Project_Global_Chrome_Upstream_Group, linux-kernel,
devicetree, linux-mediatek, linux-arm-kernel, linux-iio,
linux-mmc, linux-serial, linux-spi, linux-watchdog,
Allen-KH Cheng
From: Allen-KH Cheng <Allen-KH.Cheng@mediatek.com>
This commit adds dt-binding documentation for the Mediatek MT8186
reference board.
Signed-off-by: Allen-KH Cheng <Allen-KH.Cheng@mediatek.com>
---
Documentation/devicetree/bindings/arm/mediatek.yaml | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/mediatek.yaml b/Documentation/devicetree/bindings/arm/mediatek.yaml
index 0fa55497b96f..8fd78bd9931c 100644
--- a/Documentation/devicetree/bindings/arm/mediatek.yaml
+++ b/Documentation/devicetree/bindings/arm/mediatek.yaml
@@ -119,6 +119,10 @@ properties:
- enum:
- mediatek,mt8183-evb
- const: mediatek,mt8183
+ - items:
+ - enum:
+ - mediatek,mt8186-evb
+ - const: mediatek,mt8186
- items:
- enum:
- mediatek,mt8195-evb
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH v2 7/7] arm64: dts: Add Mediatek SoC MT8186 dts and evaluation board and Makefile
2022-01-05 2:27 ` allen-kh.cheng
@ 2022-01-05 2:27 ` allen-kh.cheng
-1 siblings, 0 replies; 21+ messages in thread
From: allen-kh.cheng @ 2022-01-05 2:27 UTC (permalink / raw)
To: Ulf Hansson, Rob Herring, Matthias Brugger,
Kishon Vijay Abraham I, Vinod Koul, Greg Kroah-Hartman,
Daniel Lezcano, Thomas Gleixner, Wim Van Sebroeck, Guenter Roeck
Cc: hsinyi, Project_Global_Chrome_Upstream_Group, linux-kernel,
devicetree, linux-mediatek, linux-arm-kernel, linux-iio,
linux-mmc, linux-serial, linux-spi, linux-watchdog,
Allen-KH Cheng
From: Allen-KH Cheng <Allen-KH.Cheng@mediatek.com>
Add basic chip support for Mediatek MT8186
Signed-off-by: Allen-KH Cheng <Allen-KH.Cheng@mediatek.com>
---
arch/arm64/boot/dts/mediatek/Makefile | 1 +
arch/arm64/boot/dts/mediatek/mt8186-evb.dts | 24 ++
arch/arm64/boot/dts/mediatek/mt8186.dtsi | 352 ++++++++++++++++++++
3 files changed, 377 insertions(+)
create mode 100644 arch/arm64/boot/dts/mediatek/mt8186-evb.dts
create mode 100644 arch/arm64/boot/dts/mediatek/mt8186.dtsi
diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile
index 4f68ebed2e31..2271c3452c64 100644
--- a/arch/arm64/boot/dts/mediatek/Makefile
+++ b/arch/arm64/boot/dts/mediatek/Makefile
@@ -31,5 +31,6 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-kodama-sku32.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-krane-sku0.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-krane-sku176.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-pumpkin.dtb
+dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-evb.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8192-evb.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8516-pumpkin.dtb
diff --git a/arch/arm64/boot/dts/mediatek/mt8186-evb.dts b/arch/arm64/boot/dts/mediatek/mt8186-evb.dts
new file mode 100644
index 000000000000..eb23d1f19f87
--- /dev/null
+++ b/arch/arm64/boot/dts/mediatek/mt8186-evb.dts
@@ -0,0 +1,24 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2022 MediaTek Inc.
+ */
+/dts-v1/;
+#include "mt8186.dtsi"
+
+/ {
+ model = "MediaTek MT8186 evaluation board";
+ compatible = "mediatek,mt8186-evb", "mediatek,mt8186";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:921600n8";
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0 0x40000000 0 0x80000000>;
+ };
+};
diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
new file mode 100644
index 000000000000..fce84c341291
--- /dev/null
+++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
@@ -0,0 +1,352 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2022 MediaTek Inc.
+ */
+/dts-v1/;
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/phy/phy.h>
+
+/ {
+ compatible = "mediatek,mt8186";
+ interrupt-parent = <&gic>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu@000 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55", "arm,armv8";
+ reg = <0x0000>;
+ enable-method = "psci";
+ clock-frequency = <2000000000>;
+ cpu-idle-states = <&cpuoff_l &clusteroff_l &mcusysoff>;
+ next-level-cache = <&l2_0>;
+ };
+
+ cpu1: cpu@001 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55", "arm,armv8";
+ reg = <0x0100>;
+ enable-method = "psci";
+ clock-frequency = <2000000000>;
+ cpu-idle-states = <&cpuoff_l &clusteroff_l &mcusysoff>;
+ next-level-cache = <&l2_0>;
+ };
+
+ cpu2: cpu@002 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55", "arm,armv8";
+ reg = <0x0200>;
+ enable-method = "psci";
+ clock-frequency = <2000000000>;
+ cpu-idle-states = <&cpuoff_l &clusteroff_l &mcusysoff>;
+ next-level-cache = <&l2_0>;
+ };
+
+ cpu3: cpu@003 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55", "arm,armv8";
+ reg = <0x0300>;
+ enable-method = "psci";
+ clock-frequency = <2000000000>;
+ cpu-idle-states = <&cpuoff_l &clusteroff_l &mcusysoff>;
+ next-level-cache = <&l2_0>;
+ };
+
+ cpu4: cpu@100 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55", "arm,armv8";
+ reg = <0x0400>;
+ enable-method = "psci";
+ clock-frequency = <2000000000>;
+ cpu-idle-states = <&cpuoff_l &clusteroff_l &mcusysoff>;
+ next-level-cache = <&l2_0>;
+ };
+
+ cpu5: cpu@101 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55", "arm,armv8";
+ reg = <0x0500>;
+ enable-method = "psci";
+ clock-frequency = <2000000000>;
+ cpu-idle-states = <&cpuoff_l &clusteroff_l &mcusysoff>;
+ next-level-cache = <&l2_0>;
+ };
+
+ cpu6: cpu@102 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a75", "arm,armv8";
+ reg = <0x0600>;
+ enable-method = "psci";
+ clock-frequency = <2050000000>;
+ cpu-idle-states = <&cpuoff_b &clusteroff_b &mcusysoff>;
+ next-level-cache = <&l2_1>;
+ };
+
+ cpu7: cpu@103 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a75", "arm,armv8";
+ reg = <0x0700>;
+ enable-method = "psci";
+ clock-frequency = <2050000000>;
+ cpu-idle-states = <&cpuoff_b &clusteroff_b &mcusysoff>;
+ next-level-cache = <&l2_1>;
+ };
+
+ cpu-map {
+ cluster0 {
+ core0 {
+ cpu = <&cpu0>;
+ };
+
+ core1 {
+ cpu = <&cpu1>;
+ };
+
+ core2 {
+ cpu = <&cpu2>;
+ };
+
+ core3 {
+ cpu = <&cpu3>;
+ };
+
+ core4 {
+ cpu = <&cpu4>;
+ };
+
+ core5 {
+ cpu = <&cpu5>;
+ };
+
+ };
+ cluster1 {
+ core0 {
+ cpu = <&cpu6>;
+ };
+
+ core1 {
+ cpu = <&cpu7>;
+ };
+ };
+ };
+
+ idle-states {
+ entry-method = "psci";
+
+ cpuoff_l: cpu-off-l {
+ compatible = "arm,idle-state";
+ arm,psci-suspend-param = <0x00010001>;
+ local-timer-stop;
+ entry-latency-us = <50>;
+ exit-latency-us = <100>;
+ min-residency-us = <1600>;
+ };
+
+ cpuoff_b: cpu-off-b {
+ compatible = "arm,idle-state";
+ arm,psci-suspend-param = <0x00010001>;
+ local-timer-stop;
+ entry-latency-us = <50>;
+ exit-latency-us = <100>;
+ min-residency-us = <1400>;
+ };
+
+ clusteroff_l: cluster-off-l {
+ compatible = "arm,idle-state";
+ arm,psci-suspend-param = <0x01010001>;
+ local-timer-stop;
+ entry-latency-us = <100>;
+ exit-latency-us = <250>;
+ min-residency-us = <2100>;
+ };
+
+ clusteroff_b: cluster-off-b {
+ compatible = "arm,idle-state";
+ arm,psci-suspend-param = <0x01010001>;
+ local-timer-stop;
+ entry-latency-us = <100>;
+ exit-latency-us = <250>;
+ min-residency-us = <1900>;
+ };
+
+ mcusysoff: mcusys-off {
+ compatible = "arm,idle-state";
+ arm,psci-suspend-param = <0x01010002>;
+ local-timer-stop;
+ entry-latency-us = <300>;
+ exit-latency-us = <1200>;
+ min-residency-us = <2600>;
+ };
+ };
+
+ l2_0: l2-cache0 {
+ compatible = "cache";
+ next-level-cache = <&l3_0>;
+ };
+
+ l2_1: l2-cache1 {
+ compatible = "cache";
+ next-level-cache = <&l3_0>;
+ };
+
+ l3_0: l3-cache {
+ compatible = "cache";
+ };
+ };
+
+ clk26m: oscillator-26m {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <26000000>;
+ };
+
+ clk32k: oscillator-32k {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32000>;
+ };
+
+ psci {
+ compatible = "arm,psci-1.0";
+ method = "smc";
+ };
+
+ gic: interrupt-controller {
+ compatible = "arm,gic-v3";
+ #interrupt-cells = <3>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ #redistributor-regions = <1>;
+ interrupt-parent = <&gic>;
+ interrupt-controller;
+ reg = <0 0x0c000000 0 0x40000>, // distributor
+ <0 0x0c040000 0 0x200000>; // redistributor
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ watchdog: watchdog@10007000 {
+ compatible = "mediatek,mt8186-wdt",
+ "mediatek,mt6589-wdt";
+ reg = <0 0x10007000 0 0x1000>;
+ };
+
+ sys_timer@10017000 {
+ compatible = "mediatek,mt8186_timer",
+ "mediatek,mt6765-timer";
+ reg = <0 0x10017000 0 0x1000>;
+ interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk26m>;
+ };
+
+ timer: timer {
+ compatible = "arm,armv8-timer";
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
+ clock-frequency = <13000000>;
+ };
+
+ uart0: serial@11002000 {
+ compatible = "mediatek,mt8186-uart",
+ "mediatek,mt6577-uart";
+ reg = <0 0x11002000 0 0x1000>;
+ interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk26m>, <&clk26m>;
+ clock-names = "baud", "bus";
+ };
+
+ uart1: serial@11003000 {
+ compatible = "mediatek,mt8186-uart",
+ "mediatek,mt6577-uart";
+ reg = <0 0x11003000 0 0x1000>;
+ interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk26m>, <&clk26m>;
+ clock-names = "baud", "bus";
+ status = "disabled";
+ };
+
+ uart2: serial@11018000 {
+ compatible = "mediatek,mt8186-uart",
+ "mediatek,mt6577-uart";
+ reg = <0 0x11018000 0 0x1000>;
+ interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk26m>, <&clk26m>;
+ clock-names = "baud", "bus";
+ status = "disabled";
+ };
+
+ mmc0: mmc@11230000 {
+ compatible = "mediatek,mt8186-mmc", "mediatek,mt8183-mmc";
+ reg = <0 0x11230000 0 0x1000>,
+ <0 0x11cd0000 0 0x1000>;
+ interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk26m>,
+ <&clk26m>,
+ <&clk26m>,
+ <&clk26m>;
+ clock-names = "source", "hclk", "source_cg",
+ "ahb_clk";
+ status = "disabled";
+ };
+
+ mmc1: mmc@11240000 {
+ compatible = "mediatek,mt8186-mmc", "mediatek,mt8183-mmc";
+ reg = <0 0x11240000 0 0x1000>,
+ <0 0x11c90000 0 0x1000>;
+ interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk26m>,
+ <&clk26m>,
+ <&clk26m>;
+ clock-names = "source", "hclk", "source_cg";
+ status = "disabled";
+ };
+
+ u3phy1: usb-phy1@11c80000 {
+ compatible = "mediatek,mt8186-tphy", "mediatek,generic-tphy-v2";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ status = "okay";
+
+ u2port1: usb2-phy1@11c80000 {
+ reg = <0 0x11c80000 0 0x700>;
+ clocks = <&clk26m>;
+ clock-names = "ref";
+ #phy-cells = <1>;
+ status = "okay";
+ };
+
+ u3port1: usb3-phy1@11c80900 {
+ reg = <0 0x11c80900 0 0x700>;
+ clocks = <&clk26m>;
+ clock-names = "ref";
+ #phy-cells = <1>;
+ status = "okay";
+ };
+ };
+
+ u3phy0: usb-phy@11ca0000 {
+ compatible = "mediatek,mt8186-tphy", "mediatek,generic-tphy-v2";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ status = "okay";
+
+ u2port0: usb2-phy@11ca0000 {
+ reg = <0 0x11ca0000 0 0x700>;
+ clocks = <&clk26m>;
+ clock-names = "ref";
+ #phy-cells = <1>;
+ mediatek,discth = <0x8>;
+ status = "okay";
+ };
+ };
+};
--
2.18.0
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH v2 7/7] arm64: dts: Add Mediatek SoC MT8186 dts and evaluation board and Makefile
@ 2022-01-05 2:27 ` allen-kh.cheng
0 siblings, 0 replies; 21+ messages in thread
From: allen-kh.cheng @ 2022-01-05 2:27 UTC (permalink / raw)
To: Ulf Hansson, Rob Herring, Matthias Brugger,
Kishon Vijay Abraham I, Vinod Koul, Greg Kroah-Hartman,
Daniel Lezcano, Thomas Gleixner, Wim Van Sebroeck, Guenter Roeck
Cc: hsinyi, Project_Global_Chrome_Upstream_Group, linux-kernel,
devicetree, linux-mediatek, linux-arm-kernel, linux-iio,
linux-mmc, linux-serial, linux-spi, linux-watchdog,
Allen-KH Cheng
From: Allen-KH Cheng <Allen-KH.Cheng@mediatek.com>
Add basic chip support for Mediatek MT8186
Signed-off-by: Allen-KH Cheng <Allen-KH.Cheng@mediatek.com>
---
arch/arm64/boot/dts/mediatek/Makefile | 1 +
arch/arm64/boot/dts/mediatek/mt8186-evb.dts | 24 ++
arch/arm64/boot/dts/mediatek/mt8186.dtsi | 352 ++++++++++++++++++++
3 files changed, 377 insertions(+)
create mode 100644 arch/arm64/boot/dts/mediatek/mt8186-evb.dts
create mode 100644 arch/arm64/boot/dts/mediatek/mt8186.dtsi
diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile
index 4f68ebed2e31..2271c3452c64 100644
--- a/arch/arm64/boot/dts/mediatek/Makefile
+++ b/arch/arm64/boot/dts/mediatek/Makefile
@@ -31,5 +31,6 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-kodama-sku32.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-krane-sku0.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-krane-sku176.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-pumpkin.dtb
+dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-evb.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8192-evb.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8516-pumpkin.dtb
diff --git a/arch/arm64/boot/dts/mediatek/mt8186-evb.dts b/arch/arm64/boot/dts/mediatek/mt8186-evb.dts
new file mode 100644
index 000000000000..eb23d1f19f87
--- /dev/null
+++ b/arch/arm64/boot/dts/mediatek/mt8186-evb.dts
@@ -0,0 +1,24 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2022 MediaTek Inc.
+ */
+/dts-v1/;
+#include "mt8186.dtsi"
+
+/ {
+ model = "MediaTek MT8186 evaluation board";
+ compatible = "mediatek,mt8186-evb", "mediatek,mt8186";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:921600n8";
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0 0x40000000 0 0x80000000>;
+ };
+};
diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
new file mode 100644
index 000000000000..fce84c341291
--- /dev/null
+++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
@@ -0,0 +1,352 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2022 MediaTek Inc.
+ */
+/dts-v1/;
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/phy/phy.h>
+
+/ {
+ compatible = "mediatek,mt8186";
+ interrupt-parent = <&gic>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu@000 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55", "arm,armv8";
+ reg = <0x0000>;
+ enable-method = "psci";
+ clock-frequency = <2000000000>;
+ cpu-idle-states = <&cpuoff_l &clusteroff_l &mcusysoff>;
+ next-level-cache = <&l2_0>;
+ };
+
+ cpu1: cpu@001 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55", "arm,armv8";
+ reg = <0x0100>;
+ enable-method = "psci";
+ clock-frequency = <2000000000>;
+ cpu-idle-states = <&cpuoff_l &clusteroff_l &mcusysoff>;
+ next-level-cache = <&l2_0>;
+ };
+
+ cpu2: cpu@002 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55", "arm,armv8";
+ reg = <0x0200>;
+ enable-method = "psci";
+ clock-frequency = <2000000000>;
+ cpu-idle-states = <&cpuoff_l &clusteroff_l &mcusysoff>;
+ next-level-cache = <&l2_0>;
+ };
+
+ cpu3: cpu@003 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55", "arm,armv8";
+ reg = <0x0300>;
+ enable-method = "psci";
+ clock-frequency = <2000000000>;
+ cpu-idle-states = <&cpuoff_l &clusteroff_l &mcusysoff>;
+ next-level-cache = <&l2_0>;
+ };
+
+ cpu4: cpu@100 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55", "arm,armv8";
+ reg = <0x0400>;
+ enable-method = "psci";
+ clock-frequency = <2000000000>;
+ cpu-idle-states = <&cpuoff_l &clusteroff_l &mcusysoff>;
+ next-level-cache = <&l2_0>;
+ };
+
+ cpu5: cpu@101 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55", "arm,armv8";
+ reg = <0x0500>;
+ enable-method = "psci";
+ clock-frequency = <2000000000>;
+ cpu-idle-states = <&cpuoff_l &clusteroff_l &mcusysoff>;
+ next-level-cache = <&l2_0>;
+ };
+
+ cpu6: cpu@102 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a75", "arm,armv8";
+ reg = <0x0600>;
+ enable-method = "psci";
+ clock-frequency = <2050000000>;
+ cpu-idle-states = <&cpuoff_b &clusteroff_b &mcusysoff>;
+ next-level-cache = <&l2_1>;
+ };
+
+ cpu7: cpu@103 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a75", "arm,armv8";
+ reg = <0x0700>;
+ enable-method = "psci";
+ clock-frequency = <2050000000>;
+ cpu-idle-states = <&cpuoff_b &clusteroff_b &mcusysoff>;
+ next-level-cache = <&l2_1>;
+ };
+
+ cpu-map {
+ cluster0 {
+ core0 {
+ cpu = <&cpu0>;
+ };
+
+ core1 {
+ cpu = <&cpu1>;
+ };
+
+ core2 {
+ cpu = <&cpu2>;
+ };
+
+ core3 {
+ cpu = <&cpu3>;
+ };
+
+ core4 {
+ cpu = <&cpu4>;
+ };
+
+ core5 {
+ cpu = <&cpu5>;
+ };
+
+ };
+ cluster1 {
+ core0 {
+ cpu = <&cpu6>;
+ };
+
+ core1 {
+ cpu = <&cpu7>;
+ };
+ };
+ };
+
+ idle-states {
+ entry-method = "psci";
+
+ cpuoff_l: cpu-off-l {
+ compatible = "arm,idle-state";
+ arm,psci-suspend-param = <0x00010001>;
+ local-timer-stop;
+ entry-latency-us = <50>;
+ exit-latency-us = <100>;
+ min-residency-us = <1600>;
+ };
+
+ cpuoff_b: cpu-off-b {
+ compatible = "arm,idle-state";
+ arm,psci-suspend-param = <0x00010001>;
+ local-timer-stop;
+ entry-latency-us = <50>;
+ exit-latency-us = <100>;
+ min-residency-us = <1400>;
+ };
+
+ clusteroff_l: cluster-off-l {
+ compatible = "arm,idle-state";
+ arm,psci-suspend-param = <0x01010001>;
+ local-timer-stop;
+ entry-latency-us = <100>;
+ exit-latency-us = <250>;
+ min-residency-us = <2100>;
+ };
+
+ clusteroff_b: cluster-off-b {
+ compatible = "arm,idle-state";
+ arm,psci-suspend-param = <0x01010001>;
+ local-timer-stop;
+ entry-latency-us = <100>;
+ exit-latency-us = <250>;
+ min-residency-us = <1900>;
+ };
+
+ mcusysoff: mcusys-off {
+ compatible = "arm,idle-state";
+ arm,psci-suspend-param = <0x01010002>;
+ local-timer-stop;
+ entry-latency-us = <300>;
+ exit-latency-us = <1200>;
+ min-residency-us = <2600>;
+ };
+ };
+
+ l2_0: l2-cache0 {
+ compatible = "cache";
+ next-level-cache = <&l3_0>;
+ };
+
+ l2_1: l2-cache1 {
+ compatible = "cache";
+ next-level-cache = <&l3_0>;
+ };
+
+ l3_0: l3-cache {
+ compatible = "cache";
+ };
+ };
+
+ clk26m: oscillator-26m {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <26000000>;
+ };
+
+ clk32k: oscillator-32k {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32000>;
+ };
+
+ psci {
+ compatible = "arm,psci-1.0";
+ method = "smc";
+ };
+
+ gic: interrupt-controller {
+ compatible = "arm,gic-v3";
+ #interrupt-cells = <3>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ #redistributor-regions = <1>;
+ interrupt-parent = <&gic>;
+ interrupt-controller;
+ reg = <0 0x0c000000 0 0x40000>, // distributor
+ <0 0x0c040000 0 0x200000>; // redistributor
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ watchdog: watchdog@10007000 {
+ compatible = "mediatek,mt8186-wdt",
+ "mediatek,mt6589-wdt";
+ reg = <0 0x10007000 0 0x1000>;
+ };
+
+ sys_timer@10017000 {
+ compatible = "mediatek,mt8186_timer",
+ "mediatek,mt6765-timer";
+ reg = <0 0x10017000 0 0x1000>;
+ interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk26m>;
+ };
+
+ timer: timer {
+ compatible = "arm,armv8-timer";
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
+ clock-frequency = <13000000>;
+ };
+
+ uart0: serial@11002000 {
+ compatible = "mediatek,mt8186-uart",
+ "mediatek,mt6577-uart";
+ reg = <0 0x11002000 0 0x1000>;
+ interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk26m>, <&clk26m>;
+ clock-names = "baud", "bus";
+ };
+
+ uart1: serial@11003000 {
+ compatible = "mediatek,mt8186-uart",
+ "mediatek,mt6577-uart";
+ reg = <0 0x11003000 0 0x1000>;
+ interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk26m>, <&clk26m>;
+ clock-names = "baud", "bus";
+ status = "disabled";
+ };
+
+ uart2: serial@11018000 {
+ compatible = "mediatek,mt8186-uart",
+ "mediatek,mt6577-uart";
+ reg = <0 0x11018000 0 0x1000>;
+ interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk26m>, <&clk26m>;
+ clock-names = "baud", "bus";
+ status = "disabled";
+ };
+
+ mmc0: mmc@11230000 {
+ compatible = "mediatek,mt8186-mmc", "mediatek,mt8183-mmc";
+ reg = <0 0x11230000 0 0x1000>,
+ <0 0x11cd0000 0 0x1000>;
+ interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk26m>,
+ <&clk26m>,
+ <&clk26m>,
+ <&clk26m>;
+ clock-names = "source", "hclk", "source_cg",
+ "ahb_clk";
+ status = "disabled";
+ };
+
+ mmc1: mmc@11240000 {
+ compatible = "mediatek,mt8186-mmc", "mediatek,mt8183-mmc";
+ reg = <0 0x11240000 0 0x1000>,
+ <0 0x11c90000 0 0x1000>;
+ interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk26m>,
+ <&clk26m>,
+ <&clk26m>;
+ clock-names = "source", "hclk", "source_cg";
+ status = "disabled";
+ };
+
+ u3phy1: usb-phy1@11c80000 {
+ compatible = "mediatek,mt8186-tphy", "mediatek,generic-tphy-v2";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ status = "okay";
+
+ u2port1: usb2-phy1@11c80000 {
+ reg = <0 0x11c80000 0 0x700>;
+ clocks = <&clk26m>;
+ clock-names = "ref";
+ #phy-cells = <1>;
+ status = "okay";
+ };
+
+ u3port1: usb3-phy1@11c80900 {
+ reg = <0 0x11c80900 0 0x700>;
+ clocks = <&clk26m>;
+ clock-names = "ref";
+ #phy-cells = <1>;
+ status = "okay";
+ };
+ };
+
+ u3phy0: usb-phy@11ca0000 {
+ compatible = "mediatek,mt8186-tphy", "mediatek,generic-tphy-v2";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ status = "okay";
+
+ u2port0: usb2-phy@11ca0000 {
+ reg = <0 0x11ca0000 0 0x700>;
+ clocks = <&clk26m>;
+ clock-names = "ref";
+ #phy-cells = <1>;
+ mediatek,discth = <0x8>;
+ status = "okay";
+ };
+ };
+};
--
2.18.0
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^ permalink raw reply related [flat|nested] 21+ messages in thread
* Re: [PATCH v2 7/7] arm64: dts: Add Mediatek SoC MT8186 dts and evaluation board and Makefile
2022-01-05 2:27 ` allen-kh.cheng
(?)
@ 2022-01-27 6:17 ` Hsin-Yi Wang
-1 siblings, 0 replies; 21+ messages in thread
From: Hsin-Yi Wang @ 2022-01-27 6:17 UTC (permalink / raw)
To: allen-kh.cheng
Cc: Ulf Hansson, Rob Herring, Matthias Brugger,
Kishon Vijay Abraham I, Vinod Koul, Greg Kroah-Hartman,
Daniel Lezcano, Thomas Gleixner, Wim Van Sebroeck, Guenter Roeck,
Project_Global_Chrome_Upstream_Group, linux-kernel, devicetree,
linux-mediatek, linux-arm-kernel, linux-iio, linux-mmc,
linux-serial, linux-spi, linux-watchdog
On Wed, Jan 5, 2022 at 10:27 AM allen-kh.cheng
<allen-kh.cheng@mediatek.com> wrote:
>
> From: Allen-KH Cheng <Allen-KH.Cheng@mediatek.com>
>
> Add basic chip support for Mediatek MT8186
>
> Signed-off-by: Allen-KH Cheng <Allen-KH.Cheng@mediatek.com>
> ---
> arch/arm64/boot/dts/mediatek/Makefile | 1 +
> arch/arm64/boot/dts/mediatek/mt8186-evb.dts | 24 ++
> arch/arm64/boot/dts/mediatek/mt8186.dtsi | 352 ++++++++++++++++++++
> 3 files changed, 377 insertions(+)
> create mode 100644 arch/arm64/boot/dts/mediatek/mt8186-evb.dts
> create mode 100644 arch/arm64/boot/dts/mediatek/mt8186.dtsi
>
> diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile
> index 4f68ebed2e31..2271c3452c64 100644
> --- a/arch/arm64/boot/dts/mediatek/Makefile
> +++ b/arch/arm64/boot/dts/mediatek/Makefile
> @@ -31,5 +31,6 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-kodama-sku32.dtb
> dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-krane-sku0.dtb
> dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-krane-sku176.dtb
> dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-pumpkin.dtb
> +dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-evb.dtb
> dtb-$(CONFIG_ARCH_MEDIATEK) += mt8192-evb.dtb
> dtb-$(CONFIG_ARCH_MEDIATEK) += mt8516-pumpkin.dtb
> diff --git a/arch/arm64/boot/dts/mediatek/mt8186-evb.dts b/arch/arm64/boot/dts/mediatek/mt8186-evb.dts
> new file mode 100644
> index 000000000000..eb23d1f19f87
> --- /dev/null
> +++ b/arch/arm64/boot/dts/mediatek/mt8186-evb.dts
> @@ -0,0 +1,24 @@
> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> +/*
> + * Copyright (C) 2022 MediaTek Inc.
> + */
> +/dts-v1/;
> +#include "mt8186.dtsi"
> +
> +/ {
> + model = "MediaTek MT8186 evaluation board";
> + compatible = "mediatek,mt8186-evb", "mediatek,mt8186";
> +
> + aliases {
> + serial0 = &uart0;
> + };
> +
> + chosen {
> + stdout-path = "serial0:921600n8";
> + };
> +
> + memory {
> + device_type = "memory";
> + reg = <0 0x40000000 0 0x80000000>;
> + };
> +};
> diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
> new file mode 100644
> index 000000000000..fce84c341291
> --- /dev/null
> +++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
> @@ -0,0 +1,352 @@
> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> +/*
> + * Copyright (C) 2022 MediaTek Inc.
> + */
> +/dts-v1/;
> +
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/interrupt-controller/irq.h>
> +#include <dt-bindings/phy/phy.h>
> +
> +/ {
> + compatible = "mediatek,mt8186";
> + interrupt-parent = <&gic>;
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + cpu0: cpu@000 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a55", "arm,armv8";
> + reg = <0x0000>;
> + enable-method = "psci";
> + clock-frequency = <2000000000>;
> + cpu-idle-states = <&cpuoff_l &clusteroff_l &mcusysoff>;
> + next-level-cache = <&l2_0>;
> + };
> +
> + cpu1: cpu@001 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a55", "arm,armv8";
> + reg = <0x0100>;
> + enable-method = "psci";
> + clock-frequency = <2000000000>;
> + cpu-idle-states = <&cpuoff_l &clusteroff_l &mcusysoff>;
> + next-level-cache = <&l2_0>;
> + };
> +
> + cpu2: cpu@002 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a55", "arm,armv8";
> + reg = <0x0200>;
> + enable-method = "psci";
> + clock-frequency = <2000000000>;
> + cpu-idle-states = <&cpuoff_l &clusteroff_l &mcusysoff>;
> + next-level-cache = <&l2_0>;
> + };
> +
> + cpu3: cpu@003 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a55", "arm,armv8";
> + reg = <0x0300>;
> + enable-method = "psci";
> + clock-frequency = <2000000000>;
> + cpu-idle-states = <&cpuoff_l &clusteroff_l &mcusysoff>;
> + next-level-cache = <&l2_0>;
> + };
> +
> + cpu4: cpu@100 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a55", "arm,armv8";
> + reg = <0x0400>;
> + enable-method = "psci";
> + clock-frequency = <2000000000>;
> + cpu-idle-states = <&cpuoff_l &clusteroff_l &mcusysoff>;
> + next-level-cache = <&l2_0>;
> + };
> +
> + cpu5: cpu@101 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a55", "arm,armv8";
> + reg = <0x0500>;
> + enable-method = "psci";
> + clock-frequency = <2000000000>;
> + cpu-idle-states = <&cpuoff_l &clusteroff_l &mcusysoff>;
> + next-level-cache = <&l2_0>;
> + };
> +
> + cpu6: cpu@102 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a75", "arm,armv8";
> + reg = <0x0600>;
> + enable-method = "psci";
> + clock-frequency = <2050000000>;
> + cpu-idle-states = <&cpuoff_b &clusteroff_b &mcusysoff>;
> + next-level-cache = <&l2_1>;
> + };
> +
> + cpu7: cpu@103 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a75", "arm,armv8";
> + reg = <0x0700>;
> + enable-method = "psci";
> + clock-frequency = <2050000000>;
> + cpu-idle-states = <&cpuoff_b &clusteroff_b &mcusysoff>;
> + next-level-cache = <&l2_1>;
> + };
> +
> + cpu-map {
> + cluster0 {
> + core0 {
> + cpu = <&cpu0>;
> + };
> +
> + core1 {
> + cpu = <&cpu1>;
> + };
> +
> + core2 {
> + cpu = <&cpu2>;
> + };
> +
> + core3 {
> + cpu = <&cpu3>;
> + };
> +
> + core4 {
> + cpu = <&cpu4>;
> + };
> +
> + core5 {
> + cpu = <&cpu5>;
> + };
> +
> + };
> + cluster1 {
> + core0 {
> + cpu = <&cpu6>;
> + };
> +
> + core1 {
> + cpu = <&cpu7>;
> + };
> + };
> + };
> +
> + idle-states {
> + entry-method = "psci";
> +
> + cpuoff_l: cpu-off-l {
> + compatible = "arm,idle-state";
> + arm,psci-suspend-param = <0x00010001>;
> + local-timer-stop;
> + entry-latency-us = <50>;
> + exit-latency-us = <100>;
> + min-residency-us = <1600>;
> + };
> +
> + cpuoff_b: cpu-off-b {
> + compatible = "arm,idle-state";
> + arm,psci-suspend-param = <0x00010001>;
> + local-timer-stop;
> + entry-latency-us = <50>;
> + exit-latency-us = <100>;
> + min-residency-us = <1400>;
> + };
> +
> + clusteroff_l: cluster-off-l {
> + compatible = "arm,idle-state";
> + arm,psci-suspend-param = <0x01010001>;
> + local-timer-stop;
> + entry-latency-us = <100>;
> + exit-latency-us = <250>;
> + min-residency-us = <2100>;
> + };
> +
> + clusteroff_b: cluster-off-b {
> + compatible = "arm,idle-state";
> + arm,psci-suspend-param = <0x01010001>;
> + local-timer-stop;
> + entry-latency-us = <100>;
> + exit-latency-us = <250>;
> + min-residency-us = <1900>;
> + };
> +
> + mcusysoff: mcusys-off {
> + compatible = "arm,idle-state";
> + arm,psci-suspend-param = <0x01010002>;
> + local-timer-stop;
> + entry-latency-us = <300>;
> + exit-latency-us = <1200>;
> + min-residency-us = <2600>;
> + };
> + };
> +
> + l2_0: l2-cache0 {
> + compatible = "cache";
> + next-level-cache = <&l3_0>;
> + };
> +
> + l2_1: l2-cache1 {
> + compatible = "cache";
> + next-level-cache = <&l3_0>;
> + };
> +
> + l3_0: l3-cache {
> + compatible = "cache";
> + };
> + };
> +
> + clk26m: oscillator-26m {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <26000000>;
> + };
> +
> + clk32k: oscillator-32k {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <32000>;
> + };
> +
> + psci {
> + compatible = "arm,psci-1.0";
> + method = "smc";
> + };
> +
please move below nodes into soc {}
> + gic: interrupt-controller {
> + compatible = "arm,gic-v3";
> + #interrupt-cells = <3>;
> + #address-cells = <2>;
> + #size-cells = <2>;
> + #redistributor-regions = <1>;
> + interrupt-parent = <&gic>;
> + interrupt-controller;
> + reg = <0 0x0c000000 0 0x40000>, // distributor
> + <0 0x0c040000 0 0x200000>; // redistributor
> + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
> + };
> +
> + watchdog: watchdog@10007000 {
> + compatible = "mediatek,mt8186-wdt",
> + "mediatek,mt6589-wdt";
> + reg = <0 0x10007000 0 0x1000>;
> + };
> +
> + sys_timer@10017000 {
> + compatible = "mediatek,mt8186_timer",
> + "mediatek,mt6765-timer";
> + reg = <0 0x10017000 0 0x1000>;
> + interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk26m>;
> + };
> +
> + timer: timer {
> + compatible = "arm,armv8-timer";
> + interrupt-parent = <&gic>;
> + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
> + <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
> + <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
> + <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
> + clock-frequency = <13000000>;
> + };
> +
> + uart0: serial@11002000 {
> + compatible = "mediatek,mt8186-uart",
> + "mediatek,mt6577-uart";
> + reg = <0 0x11002000 0 0x1000>;
> + interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk26m>, <&clk26m>;
> + clock-names = "baud", "bus";
> + };
> +
> + uart1: serial@11003000 {
> + compatible = "mediatek,mt8186-uart",
> + "mediatek,mt6577-uart";
> + reg = <0 0x11003000 0 0x1000>;
> + interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk26m>, <&clk26m>;
> + clock-names = "baud", "bus";
> + status = "disabled";
> + };
> +
> + uart2: serial@11018000 {
> + compatible = "mediatek,mt8186-uart",
> + "mediatek,mt6577-uart";
> + reg = <0 0x11018000 0 0x1000>;
> + interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk26m>, <&clk26m>;
> + clock-names = "baud", "bus";
> + status = "disabled";
> + };
> +
> + mmc0: mmc@11230000 {
> + compatible = "mediatek,mt8186-mmc", "mediatek,mt8183-mmc";
> + reg = <0 0x11230000 0 0x1000>,
> + <0 0x11cd0000 0 0x1000>;
> + interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk26m>,
> + <&clk26m>,
> + <&clk26m>,
> + <&clk26m>;
> + clock-names = "source", "hclk", "source_cg",
> + "ahb_clk";
> + status = "disabled";
> + };
> +
> + mmc1: mmc@11240000 {
> + compatible = "mediatek,mt8186-mmc", "mediatek,mt8183-mmc";
> + reg = <0 0x11240000 0 0x1000>,
> + <0 0x11c90000 0 0x1000>;
> + interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk26m>,
> + <&clk26m>,
> + <&clk26m>;
> + clock-names = "source", "hclk", "source_cg";
> + status = "disabled";
> + };
> +
> + u3phy1: usb-phy1@11c80000 {
> + compatible = "mediatek,mt8186-tphy", "mediatek,generic-tphy-v2";
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> + status = "okay";
> +
> + u2port1: usb2-phy1@11c80000 {
> + reg = <0 0x11c80000 0 0x700>;
> + clocks = <&clk26m>;
> + clock-names = "ref";
> + #phy-cells = <1>;
> + status = "okay";
> + };
> +
> + u3port1: usb3-phy1@11c80900 {
> + reg = <0 0x11c80900 0 0x700>;
> + clocks = <&clk26m>;
> + clock-names = "ref";
> + #phy-cells = <1>;
> + status = "okay";
> + };
> + };
> +
> + u3phy0: usb-phy@11ca0000 {
> + compatible = "mediatek,mt8186-tphy", "mediatek,generic-tphy-v2";
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> + status = "okay";
> +
> + u2port0: usb2-phy@11ca0000 {
> + reg = <0 0x11ca0000 0 0x700>;
> + clocks = <&clk26m>;
> + clock-names = "ref";
> + #phy-cells = <1>;
> + mediatek,discth = <0x8>;
> + status = "okay";
> + };
> + };
> +};
> --
> 2.18.0
>
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH v2 7/7] arm64: dts: Add Mediatek SoC MT8186 dts and evaluation board and Makefile
@ 2022-01-27 6:17 ` Hsin-Yi Wang
0 siblings, 0 replies; 21+ messages in thread
From: Hsin-Yi Wang @ 2022-01-27 6:17 UTC (permalink / raw)
To: allen-kh.cheng
Cc: Ulf Hansson, Rob Herring, Matthias Brugger,
Kishon Vijay Abraham I, Vinod Koul, Greg Kroah-Hartman,
Daniel Lezcano, Thomas Gleixner, Wim Van Sebroeck, Guenter Roeck,
Project_Global_Chrome_Upstream_Group, linux-kernel, devicetree,
linux-mediatek, linux-arm-kernel, linux-iio, linux-mmc,
linux-serial, linux-spi, linux-watchdog
On Wed, Jan 5, 2022 at 10:27 AM allen-kh.cheng
<allen-kh.cheng@mediatek.com> wrote:
>
> From: Allen-KH Cheng <Allen-KH.Cheng@mediatek.com>
>
> Add basic chip support for Mediatek MT8186
>
> Signed-off-by: Allen-KH Cheng <Allen-KH.Cheng@mediatek.com>
> ---
> arch/arm64/boot/dts/mediatek/Makefile | 1 +
> arch/arm64/boot/dts/mediatek/mt8186-evb.dts | 24 ++
> arch/arm64/boot/dts/mediatek/mt8186.dtsi | 352 ++++++++++++++++++++
> 3 files changed, 377 insertions(+)
> create mode 100644 arch/arm64/boot/dts/mediatek/mt8186-evb.dts
> create mode 100644 arch/arm64/boot/dts/mediatek/mt8186.dtsi
>
> diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile
> index 4f68ebed2e31..2271c3452c64 100644
> --- a/arch/arm64/boot/dts/mediatek/Makefile
> +++ b/arch/arm64/boot/dts/mediatek/Makefile
> @@ -31,5 +31,6 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-kodama-sku32.dtb
> dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-krane-sku0.dtb
> dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-krane-sku176.dtb
> dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-pumpkin.dtb
> +dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-evb.dtb
> dtb-$(CONFIG_ARCH_MEDIATEK) += mt8192-evb.dtb
> dtb-$(CONFIG_ARCH_MEDIATEK) += mt8516-pumpkin.dtb
> diff --git a/arch/arm64/boot/dts/mediatek/mt8186-evb.dts b/arch/arm64/boot/dts/mediatek/mt8186-evb.dts
> new file mode 100644
> index 000000000000..eb23d1f19f87
> --- /dev/null
> +++ b/arch/arm64/boot/dts/mediatek/mt8186-evb.dts
> @@ -0,0 +1,24 @@
> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> +/*
> + * Copyright (C) 2022 MediaTek Inc.
> + */
> +/dts-v1/;
> +#include "mt8186.dtsi"
> +
> +/ {
> + model = "MediaTek MT8186 evaluation board";
> + compatible = "mediatek,mt8186-evb", "mediatek,mt8186";
> +
> + aliases {
> + serial0 = &uart0;
> + };
> +
> + chosen {
> + stdout-path = "serial0:921600n8";
> + };
> +
> + memory {
> + device_type = "memory";
> + reg = <0 0x40000000 0 0x80000000>;
> + };
> +};
> diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
> new file mode 100644
> index 000000000000..fce84c341291
> --- /dev/null
> +++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
> @@ -0,0 +1,352 @@
> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> +/*
> + * Copyright (C) 2022 MediaTek Inc.
> + */
> +/dts-v1/;
> +
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/interrupt-controller/irq.h>
> +#include <dt-bindings/phy/phy.h>
> +
> +/ {
> + compatible = "mediatek,mt8186";
> + interrupt-parent = <&gic>;
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + cpu0: cpu@000 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a55", "arm,armv8";
> + reg = <0x0000>;
> + enable-method = "psci";
> + clock-frequency = <2000000000>;
> + cpu-idle-states = <&cpuoff_l &clusteroff_l &mcusysoff>;
> + next-level-cache = <&l2_0>;
> + };
> +
> + cpu1: cpu@001 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a55", "arm,armv8";
> + reg = <0x0100>;
> + enable-method = "psci";
> + clock-frequency = <2000000000>;
> + cpu-idle-states = <&cpuoff_l &clusteroff_l &mcusysoff>;
> + next-level-cache = <&l2_0>;
> + };
> +
> + cpu2: cpu@002 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a55", "arm,armv8";
> + reg = <0x0200>;
> + enable-method = "psci";
> + clock-frequency = <2000000000>;
> + cpu-idle-states = <&cpuoff_l &clusteroff_l &mcusysoff>;
> + next-level-cache = <&l2_0>;
> + };
> +
> + cpu3: cpu@003 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a55", "arm,armv8";
> + reg = <0x0300>;
> + enable-method = "psci";
> + clock-frequency = <2000000000>;
> + cpu-idle-states = <&cpuoff_l &clusteroff_l &mcusysoff>;
> + next-level-cache = <&l2_0>;
> + };
> +
> + cpu4: cpu@100 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a55", "arm,armv8";
> + reg = <0x0400>;
> + enable-method = "psci";
> + clock-frequency = <2000000000>;
> + cpu-idle-states = <&cpuoff_l &clusteroff_l &mcusysoff>;
> + next-level-cache = <&l2_0>;
> + };
> +
> + cpu5: cpu@101 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a55", "arm,armv8";
> + reg = <0x0500>;
> + enable-method = "psci";
> + clock-frequency = <2000000000>;
> + cpu-idle-states = <&cpuoff_l &clusteroff_l &mcusysoff>;
> + next-level-cache = <&l2_0>;
> + };
> +
> + cpu6: cpu@102 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a75", "arm,armv8";
> + reg = <0x0600>;
> + enable-method = "psci";
> + clock-frequency = <2050000000>;
> + cpu-idle-states = <&cpuoff_b &clusteroff_b &mcusysoff>;
> + next-level-cache = <&l2_1>;
> + };
> +
> + cpu7: cpu@103 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a75", "arm,armv8";
> + reg = <0x0700>;
> + enable-method = "psci";
> + clock-frequency = <2050000000>;
> + cpu-idle-states = <&cpuoff_b &clusteroff_b &mcusysoff>;
> + next-level-cache = <&l2_1>;
> + };
> +
> + cpu-map {
> + cluster0 {
> + core0 {
> + cpu = <&cpu0>;
> + };
> +
> + core1 {
> + cpu = <&cpu1>;
> + };
> +
> + core2 {
> + cpu = <&cpu2>;
> + };
> +
> + core3 {
> + cpu = <&cpu3>;
> + };
> +
> + core4 {
> + cpu = <&cpu4>;
> + };
> +
> + core5 {
> + cpu = <&cpu5>;
> + };
> +
> + };
> + cluster1 {
> + core0 {
> + cpu = <&cpu6>;
> + };
> +
> + core1 {
> + cpu = <&cpu7>;
> + };
> + };
> + };
> +
> + idle-states {
> + entry-method = "psci";
> +
> + cpuoff_l: cpu-off-l {
> + compatible = "arm,idle-state";
> + arm,psci-suspend-param = <0x00010001>;
> + local-timer-stop;
> + entry-latency-us = <50>;
> + exit-latency-us = <100>;
> + min-residency-us = <1600>;
> + };
> +
> + cpuoff_b: cpu-off-b {
> + compatible = "arm,idle-state";
> + arm,psci-suspend-param = <0x00010001>;
> + local-timer-stop;
> + entry-latency-us = <50>;
> + exit-latency-us = <100>;
> + min-residency-us = <1400>;
> + };
> +
> + clusteroff_l: cluster-off-l {
> + compatible = "arm,idle-state";
> + arm,psci-suspend-param = <0x01010001>;
> + local-timer-stop;
> + entry-latency-us = <100>;
> + exit-latency-us = <250>;
> + min-residency-us = <2100>;
> + };
> +
> + clusteroff_b: cluster-off-b {
> + compatible = "arm,idle-state";
> + arm,psci-suspend-param = <0x01010001>;
> + local-timer-stop;
> + entry-latency-us = <100>;
> + exit-latency-us = <250>;
> + min-residency-us = <1900>;
> + };
> +
> + mcusysoff: mcusys-off {
> + compatible = "arm,idle-state";
> + arm,psci-suspend-param = <0x01010002>;
> + local-timer-stop;
> + entry-latency-us = <300>;
> + exit-latency-us = <1200>;
> + min-residency-us = <2600>;
> + };
> + };
> +
> + l2_0: l2-cache0 {
> + compatible = "cache";
> + next-level-cache = <&l3_0>;
> + };
> +
> + l2_1: l2-cache1 {
> + compatible = "cache";
> + next-level-cache = <&l3_0>;
> + };
> +
> + l3_0: l3-cache {
> + compatible = "cache";
> + };
> + };
> +
> + clk26m: oscillator-26m {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <26000000>;
> + };
> +
> + clk32k: oscillator-32k {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <32000>;
> + };
> +
> + psci {
> + compatible = "arm,psci-1.0";
> + method = "smc";
> + };
> +
please move below nodes into soc {}
> + gic: interrupt-controller {
> + compatible = "arm,gic-v3";
> + #interrupt-cells = <3>;
> + #address-cells = <2>;
> + #size-cells = <2>;
> + #redistributor-regions = <1>;
> + interrupt-parent = <&gic>;
> + interrupt-controller;
> + reg = <0 0x0c000000 0 0x40000>, // distributor
> + <0 0x0c040000 0 0x200000>; // redistributor
> + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
> + };
> +
> + watchdog: watchdog@10007000 {
> + compatible = "mediatek,mt8186-wdt",
> + "mediatek,mt6589-wdt";
> + reg = <0 0x10007000 0 0x1000>;
> + };
> +
> + sys_timer@10017000 {
> + compatible = "mediatek,mt8186_timer",
> + "mediatek,mt6765-timer";
> + reg = <0 0x10017000 0 0x1000>;
> + interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk26m>;
> + };
> +
> + timer: timer {
> + compatible = "arm,armv8-timer";
> + interrupt-parent = <&gic>;
> + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
> + <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
> + <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
> + <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
> + clock-frequency = <13000000>;
> + };
> +
> + uart0: serial@11002000 {
> + compatible = "mediatek,mt8186-uart",
> + "mediatek,mt6577-uart";
> + reg = <0 0x11002000 0 0x1000>;
> + interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk26m>, <&clk26m>;
> + clock-names = "baud", "bus";
> + };
> +
> + uart1: serial@11003000 {
> + compatible = "mediatek,mt8186-uart",
> + "mediatek,mt6577-uart";
> + reg = <0 0x11003000 0 0x1000>;
> + interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk26m>, <&clk26m>;
> + clock-names = "baud", "bus";
> + status = "disabled";
> + };
> +
> + uart2: serial@11018000 {
> + compatible = "mediatek,mt8186-uart",
> + "mediatek,mt6577-uart";
> + reg = <0 0x11018000 0 0x1000>;
> + interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk26m>, <&clk26m>;
> + clock-names = "baud", "bus";
> + status = "disabled";
> + };
> +
> + mmc0: mmc@11230000 {
> + compatible = "mediatek,mt8186-mmc", "mediatek,mt8183-mmc";
> + reg = <0 0x11230000 0 0x1000>,
> + <0 0x11cd0000 0 0x1000>;
> + interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk26m>,
> + <&clk26m>,
> + <&clk26m>,
> + <&clk26m>;
> + clock-names = "source", "hclk", "source_cg",
> + "ahb_clk";
> + status = "disabled";
> + };
> +
> + mmc1: mmc@11240000 {
> + compatible = "mediatek,mt8186-mmc", "mediatek,mt8183-mmc";
> + reg = <0 0x11240000 0 0x1000>,
> + <0 0x11c90000 0 0x1000>;
> + interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk26m>,
> + <&clk26m>,
> + <&clk26m>;
> + clock-names = "source", "hclk", "source_cg";
> + status = "disabled";
> + };
> +
> + u3phy1: usb-phy1@11c80000 {
> + compatible = "mediatek,mt8186-tphy", "mediatek,generic-tphy-v2";
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> + status = "okay";
> +
> + u2port1: usb2-phy1@11c80000 {
> + reg = <0 0x11c80000 0 0x700>;
> + clocks = <&clk26m>;
> + clock-names = "ref";
> + #phy-cells = <1>;
> + status = "okay";
> + };
> +
> + u3port1: usb3-phy1@11c80900 {
> + reg = <0 0x11c80900 0 0x700>;
> + clocks = <&clk26m>;
> + clock-names = "ref";
> + #phy-cells = <1>;
> + status = "okay";
> + };
> + };
> +
> + u3phy0: usb-phy@11ca0000 {
> + compatible = "mediatek,mt8186-tphy", "mediatek,generic-tphy-v2";
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> + status = "okay";
> +
> + u2port0: usb2-phy@11ca0000 {
> + reg = <0 0x11ca0000 0 0x700>;
> + clocks = <&clk26m>;
> + clock-names = "ref";
> + #phy-cells = <1>;
> + mediatek,discth = <0x8>;
> + status = "okay";
> + };
> + };
> +};
> --
> 2.18.0
>
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH v2 7/7] arm64: dts: Add Mediatek SoC MT8186 dts and evaluation board and Makefile
@ 2022-01-27 6:17 ` Hsin-Yi Wang
0 siblings, 0 replies; 21+ messages in thread
From: Hsin-Yi Wang @ 2022-01-27 6:17 UTC (permalink / raw)
To: allen-kh.cheng
Cc: Ulf Hansson, Rob Herring, Matthias Brugger,
Kishon Vijay Abraham I, Vinod Koul, Greg Kroah-Hartman,
Daniel Lezcano, Thomas Gleixner, Wim Van Sebroeck, Guenter Roeck,
Project_Global_Chrome_Upstream_Group, linux-kernel, devicetree,
linux-mediatek, linux-arm-kernel, linux-iio, linux-mmc,
linux-serial, linux-spi, linux-watchdog
On Wed, Jan 5, 2022 at 10:27 AM allen-kh.cheng
<allen-kh.cheng@mediatek.com> wrote:
>
> From: Allen-KH Cheng <Allen-KH.Cheng@mediatek.com>
>
> Add basic chip support for Mediatek MT8186
>
> Signed-off-by: Allen-KH Cheng <Allen-KH.Cheng@mediatek.com>
> ---
> arch/arm64/boot/dts/mediatek/Makefile | 1 +
> arch/arm64/boot/dts/mediatek/mt8186-evb.dts | 24 ++
> arch/arm64/boot/dts/mediatek/mt8186.dtsi | 352 ++++++++++++++++++++
> 3 files changed, 377 insertions(+)
> create mode 100644 arch/arm64/boot/dts/mediatek/mt8186-evb.dts
> create mode 100644 arch/arm64/boot/dts/mediatek/mt8186.dtsi
>
> diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile
> index 4f68ebed2e31..2271c3452c64 100644
> --- a/arch/arm64/boot/dts/mediatek/Makefile
> +++ b/arch/arm64/boot/dts/mediatek/Makefile
> @@ -31,5 +31,6 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-kodama-sku32.dtb
> dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-krane-sku0.dtb
> dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-krane-sku176.dtb
> dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-pumpkin.dtb
> +dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-evb.dtb
> dtb-$(CONFIG_ARCH_MEDIATEK) += mt8192-evb.dtb
> dtb-$(CONFIG_ARCH_MEDIATEK) += mt8516-pumpkin.dtb
> diff --git a/arch/arm64/boot/dts/mediatek/mt8186-evb.dts b/arch/arm64/boot/dts/mediatek/mt8186-evb.dts
> new file mode 100644
> index 000000000000..eb23d1f19f87
> --- /dev/null
> +++ b/arch/arm64/boot/dts/mediatek/mt8186-evb.dts
> @@ -0,0 +1,24 @@
> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> +/*
> + * Copyright (C) 2022 MediaTek Inc.
> + */
> +/dts-v1/;
> +#include "mt8186.dtsi"
> +
> +/ {
> + model = "MediaTek MT8186 evaluation board";
> + compatible = "mediatek,mt8186-evb", "mediatek,mt8186";
> +
> + aliases {
> + serial0 = &uart0;
> + };
> +
> + chosen {
> + stdout-path = "serial0:921600n8";
> + };
> +
> + memory {
> + device_type = "memory";
> + reg = <0 0x40000000 0 0x80000000>;
> + };
> +};
> diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
> new file mode 100644
> index 000000000000..fce84c341291
> --- /dev/null
> +++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
> @@ -0,0 +1,352 @@
> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> +/*
> + * Copyright (C) 2022 MediaTek Inc.
> + */
> +/dts-v1/;
> +
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/interrupt-controller/irq.h>
> +#include <dt-bindings/phy/phy.h>
> +
> +/ {
> + compatible = "mediatek,mt8186";
> + interrupt-parent = <&gic>;
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + cpu0: cpu@000 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a55", "arm,armv8";
> + reg = <0x0000>;
> + enable-method = "psci";
> + clock-frequency = <2000000000>;
> + cpu-idle-states = <&cpuoff_l &clusteroff_l &mcusysoff>;
> + next-level-cache = <&l2_0>;
> + };
> +
> + cpu1: cpu@001 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a55", "arm,armv8";
> + reg = <0x0100>;
> + enable-method = "psci";
> + clock-frequency = <2000000000>;
> + cpu-idle-states = <&cpuoff_l &clusteroff_l &mcusysoff>;
> + next-level-cache = <&l2_0>;
> + };
> +
> + cpu2: cpu@002 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a55", "arm,armv8";
> + reg = <0x0200>;
> + enable-method = "psci";
> + clock-frequency = <2000000000>;
> + cpu-idle-states = <&cpuoff_l &clusteroff_l &mcusysoff>;
> + next-level-cache = <&l2_0>;
> + };
> +
> + cpu3: cpu@003 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a55", "arm,armv8";
> + reg = <0x0300>;
> + enable-method = "psci";
> + clock-frequency = <2000000000>;
> + cpu-idle-states = <&cpuoff_l &clusteroff_l &mcusysoff>;
> + next-level-cache = <&l2_0>;
> + };
> +
> + cpu4: cpu@100 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a55", "arm,armv8";
> + reg = <0x0400>;
> + enable-method = "psci";
> + clock-frequency = <2000000000>;
> + cpu-idle-states = <&cpuoff_l &clusteroff_l &mcusysoff>;
> + next-level-cache = <&l2_0>;
> + };
> +
> + cpu5: cpu@101 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a55", "arm,armv8";
> + reg = <0x0500>;
> + enable-method = "psci";
> + clock-frequency = <2000000000>;
> + cpu-idle-states = <&cpuoff_l &clusteroff_l &mcusysoff>;
> + next-level-cache = <&l2_0>;
> + };
> +
> + cpu6: cpu@102 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a75", "arm,armv8";
> + reg = <0x0600>;
> + enable-method = "psci";
> + clock-frequency = <2050000000>;
> + cpu-idle-states = <&cpuoff_b &clusteroff_b &mcusysoff>;
> + next-level-cache = <&l2_1>;
> + };
> +
> + cpu7: cpu@103 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a75", "arm,armv8";
> + reg = <0x0700>;
> + enable-method = "psci";
> + clock-frequency = <2050000000>;
> + cpu-idle-states = <&cpuoff_b &clusteroff_b &mcusysoff>;
> + next-level-cache = <&l2_1>;
> + };
> +
> + cpu-map {
> + cluster0 {
> + core0 {
> + cpu = <&cpu0>;
> + };
> +
> + core1 {
> + cpu = <&cpu1>;
> + };
> +
> + core2 {
> + cpu = <&cpu2>;
> + };
> +
> + core3 {
> + cpu = <&cpu3>;
> + };
> +
> + core4 {
> + cpu = <&cpu4>;
> + };
> +
> + core5 {
> + cpu = <&cpu5>;
> + };
> +
> + };
> + cluster1 {
> + core0 {
> + cpu = <&cpu6>;
> + };
> +
> + core1 {
> + cpu = <&cpu7>;
> + };
> + };
> + };
> +
> + idle-states {
> + entry-method = "psci";
> +
> + cpuoff_l: cpu-off-l {
> + compatible = "arm,idle-state";
> + arm,psci-suspend-param = <0x00010001>;
> + local-timer-stop;
> + entry-latency-us = <50>;
> + exit-latency-us = <100>;
> + min-residency-us = <1600>;
> + };
> +
> + cpuoff_b: cpu-off-b {
> + compatible = "arm,idle-state";
> + arm,psci-suspend-param = <0x00010001>;
> + local-timer-stop;
> + entry-latency-us = <50>;
> + exit-latency-us = <100>;
> + min-residency-us = <1400>;
> + };
> +
> + clusteroff_l: cluster-off-l {
> + compatible = "arm,idle-state";
> + arm,psci-suspend-param = <0x01010001>;
> + local-timer-stop;
> + entry-latency-us = <100>;
> + exit-latency-us = <250>;
> + min-residency-us = <2100>;
> + };
> +
> + clusteroff_b: cluster-off-b {
> + compatible = "arm,idle-state";
> + arm,psci-suspend-param = <0x01010001>;
> + local-timer-stop;
> + entry-latency-us = <100>;
> + exit-latency-us = <250>;
> + min-residency-us = <1900>;
> + };
> +
> + mcusysoff: mcusys-off {
> + compatible = "arm,idle-state";
> + arm,psci-suspend-param = <0x01010002>;
> + local-timer-stop;
> + entry-latency-us = <300>;
> + exit-latency-us = <1200>;
> + min-residency-us = <2600>;
> + };
> + };
> +
> + l2_0: l2-cache0 {
> + compatible = "cache";
> + next-level-cache = <&l3_0>;
> + };
> +
> + l2_1: l2-cache1 {
> + compatible = "cache";
> + next-level-cache = <&l3_0>;
> + };
> +
> + l3_0: l3-cache {
> + compatible = "cache";
> + };
> + };
> +
> + clk26m: oscillator-26m {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <26000000>;
> + };
> +
> + clk32k: oscillator-32k {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <32000>;
> + };
> +
> + psci {
> + compatible = "arm,psci-1.0";
> + method = "smc";
> + };
> +
please move below nodes into soc {}
> + gic: interrupt-controller {
> + compatible = "arm,gic-v3";
> + #interrupt-cells = <3>;
> + #address-cells = <2>;
> + #size-cells = <2>;
> + #redistributor-regions = <1>;
> + interrupt-parent = <&gic>;
> + interrupt-controller;
> + reg = <0 0x0c000000 0 0x40000>, // distributor
> + <0 0x0c040000 0 0x200000>; // redistributor
> + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
> + };
> +
> + watchdog: watchdog@10007000 {
> + compatible = "mediatek,mt8186-wdt",
> + "mediatek,mt6589-wdt";
> + reg = <0 0x10007000 0 0x1000>;
> + };
> +
> + sys_timer@10017000 {
> + compatible = "mediatek,mt8186_timer",
> + "mediatek,mt6765-timer";
> + reg = <0 0x10017000 0 0x1000>;
> + interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk26m>;
> + };
> +
> + timer: timer {
> + compatible = "arm,armv8-timer";
> + interrupt-parent = <&gic>;
> + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
> + <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
> + <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
> + <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
> + clock-frequency = <13000000>;
> + };
> +
> + uart0: serial@11002000 {
> + compatible = "mediatek,mt8186-uart",
> + "mediatek,mt6577-uart";
> + reg = <0 0x11002000 0 0x1000>;
> + interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk26m>, <&clk26m>;
> + clock-names = "baud", "bus";
> + };
> +
> + uart1: serial@11003000 {
> + compatible = "mediatek,mt8186-uart",
> + "mediatek,mt6577-uart";
> + reg = <0 0x11003000 0 0x1000>;
> + interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk26m>, <&clk26m>;
> + clock-names = "baud", "bus";
> + status = "disabled";
> + };
> +
> + uart2: serial@11018000 {
> + compatible = "mediatek,mt8186-uart",
> + "mediatek,mt6577-uart";
> + reg = <0 0x11018000 0 0x1000>;
> + interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk26m>, <&clk26m>;
> + clock-names = "baud", "bus";
> + status = "disabled";
> + };
> +
> + mmc0: mmc@11230000 {
> + compatible = "mediatek,mt8186-mmc", "mediatek,mt8183-mmc";
> + reg = <0 0x11230000 0 0x1000>,
> + <0 0x11cd0000 0 0x1000>;
> + interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk26m>,
> + <&clk26m>,
> + <&clk26m>,
> + <&clk26m>;
> + clock-names = "source", "hclk", "source_cg",
> + "ahb_clk";
> + status = "disabled";
> + };
> +
> + mmc1: mmc@11240000 {
> + compatible = "mediatek,mt8186-mmc", "mediatek,mt8183-mmc";
> + reg = <0 0x11240000 0 0x1000>,
> + <0 0x11c90000 0 0x1000>;
> + interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk26m>,
> + <&clk26m>,
> + <&clk26m>;
> + clock-names = "source", "hclk", "source_cg";
> + status = "disabled";
> + };
> +
> + u3phy1: usb-phy1@11c80000 {
> + compatible = "mediatek,mt8186-tphy", "mediatek,generic-tphy-v2";
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> + status = "okay";
> +
> + u2port1: usb2-phy1@11c80000 {
> + reg = <0 0x11c80000 0 0x700>;
> + clocks = <&clk26m>;
> + clock-names = "ref";
> + #phy-cells = <1>;
> + status = "okay";
> + };
> +
> + u3port1: usb3-phy1@11c80900 {
> + reg = <0 0x11c80900 0 0x700>;
> + clocks = <&clk26m>;
> + clock-names = "ref";
> + #phy-cells = <1>;
> + status = "okay";
> + };
> + };
> +
> + u3phy0: usb-phy@11ca0000 {
> + compatible = "mediatek,mt8186-tphy", "mediatek,generic-tphy-v2";
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> + status = "okay";
> +
> + u2port0: usb2-phy@11ca0000 {
> + reg = <0 0x11ca0000 0 0x700>;
> + clocks = <&clk26m>;
> + clock-names = "ref";
> + #phy-cells = <1>;
> + mediatek,discth = <0x8>;
> + status = "okay";
> + };
> + };
> +};
> --
> 2.18.0
>
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^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH v2 7/7] arm64: dts: Add Mediatek SoC MT8186 dts and evaluation board and Makefile
2022-01-27 6:17 ` Hsin-Yi Wang
@ 2022-01-28 1:09 ` allen-kh.cheng
-1 siblings, 0 replies; 21+ messages in thread
From: allen-kh.cheng @ 2022-01-28 1:09 UTC (permalink / raw)
To: Hsin-Yi Wang
Cc: Ulf Hansson, Rob Herring, Matthias Brugger,
Kishon Vijay Abraham I, Vinod Koul, Greg Kroah-Hartman,
Daniel Lezcano, Thomas Gleixner, Wim Van Sebroeck, Guenter Roeck,
Project_Global_Chrome_Upstream_Group, linux-kernel, devicetree,
linux-mediatek, linux-arm-kernel, linux-iio, linux-mmc,
linux-serial, linux-spi, linux-watchdog
On Thu, 2022-01-27 at 14:17 +0800, Hsin-Yi Wang wrote:
> On Wed, Jan 5, 2022 at 10:27 AM allen-kh.cheng
> <allen-kh.cheng@mediatek.com> wrote:
> >
> > From: Allen-KH Cheng <Allen-KH.Cheng@mediatek.com>
> >
> > Add basic chip support for Mediatek MT8186
> >
> > Signed-off-by: Allen-KH Cheng <Allen-KH.Cheng@mediatek.com>
> > ---
> > arch/arm64/boot/dts/mediatek/Makefile | 1 +
> > arch/arm64/boot/dts/mediatek/mt8186-evb.dts | 24 ++
> > arch/arm64/boot/dts/mediatek/mt8186.dtsi | 352
> > ++++++++++++++++++++
> > 3 files changed, 377 insertions(+)
> > create mode 100644 arch/arm64/boot/dts/mediatek/mt8186-evb.dts
> > create mode 100644 arch/arm64/boot/dts/mediatek/mt8186.dtsi
> >
> > diff --git a/arch/arm64/boot/dts/mediatek/Makefile
> > b/arch/arm64/boot/dts/mediatek/Makefile
> > index 4f68ebed2e31..2271c3452c64 100644
> > --- a/arch/arm64/boot/dts/mediatek/Makefile
> > +++ b/arch/arm64/boot/dts/mediatek/Makefile
> > @@ -31,5 +31,6 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-
> > kodama-sku32.dtb
> > dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-krane-sku0.dtb
> > dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-krane-sku176.dtb
> > dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-pumpkin.dtb
> > +dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-evb.dtb
> > dtb-$(CONFIG_ARCH_MEDIATEK) += mt8192-evb.dtb
> > dtb-$(CONFIG_ARCH_MEDIATEK) += mt8516-pumpkin.dtb
> > diff --git a/arch/arm64/boot/dts/mediatek/mt8186-evb.dts
> > b/arch/arm64/boot/dts/mediatek/mt8186-evb.dts
> > new file mode 100644
> > index 000000000000..eb23d1f19f87
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/mediatek/mt8186-evb.dts
> > @@ -0,0 +1,24 @@
> > +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> > +/*
> > + * Copyright (C) 2022 MediaTek Inc.
> > + */
> > +/dts-v1/;
> > +#include "mt8186.dtsi"
> > +
> > +/ {
> > + model = "MediaTek MT8186 evaluation board";
> > + compatible = "mediatek,mt8186-evb", "mediatek,mt8186";
> > +
> > + aliases {
> > + serial0 = &uart0;
> > + };
> > +
> > + chosen {
> > + stdout-path = "serial0:921600n8";
> > + };
> > +
> > + memory {
> > + device_type = "memory";
> > + reg = <0 0x40000000 0 0x80000000>;
> > + };
> > +};
> > diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi
> > b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
> > new file mode 100644
> > index 000000000000..fce84c341291
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
> > @@ -0,0 +1,352 @@
> > +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> > +/*
> > + * Copyright (C) 2022 MediaTek Inc.
> > + */
> > +/dts-v1/;
> > +
> > +#include <dt-bindings/interrupt-controller/arm-gic.h>
> > +#include <dt-bindings/interrupt-controller/irq.h>
> > +#include <dt-bindings/phy/phy.h>
> > +
> > +/ {
> > + compatible = "mediatek,mt8186";
> > + interrupt-parent = <&gic>;
> > + #address-cells = <2>;
> > + #size-cells = <2>;
> > +
> > + cpus {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > +
> > + cpu0: cpu@000 {
> > + device_type = "cpu";
> > + compatible = "arm,cortex-a55", "arm,armv8";
> > + reg = <0x0000>;
> > + enable-method = "psci";
> > + clock-frequency = <2000000000>;
> > + cpu-idle-states = <&cpuoff_l &clusteroff_l
> > &mcusysoff>;
> > + next-level-cache = <&l2_0>;
> > + };
> > +
> > + cpu1: cpu@001 {
> > + device_type = "cpu";
> > + compatible = "arm,cortex-a55", "arm,armv8";
> > + reg = <0x0100>;
> > + enable-method = "psci";
> > + clock-frequency = <2000000000>;
> > + cpu-idle-states = <&cpuoff_l &clusteroff_l
> > &mcusysoff>;
> > + next-level-cache = <&l2_0>;
> > + };
> > +
> > + cpu2: cpu@002 {
> > + device_type = "cpu";
> > + compatible = "arm,cortex-a55", "arm,armv8";
> > + reg = <0x0200>;
> > + enable-method = "psci";
> > + clock-frequency = <2000000000>;
> > + cpu-idle-states = <&cpuoff_l &clusteroff_l
> > &mcusysoff>;
> > + next-level-cache = <&l2_0>;
> > + };
> > +
> > + cpu3: cpu@003 {
> > + device_type = "cpu";
> > + compatible = "arm,cortex-a55", "arm,armv8";
> > + reg = <0x0300>;
> > + enable-method = "psci";
> > + clock-frequency = <2000000000>;
> > + cpu-idle-states = <&cpuoff_l &clusteroff_l
> > &mcusysoff>;
> > + next-level-cache = <&l2_0>;
> > + };
> > +
> > + cpu4: cpu@100 {
> > + device_type = "cpu";
> > + compatible = "arm,cortex-a55", "arm,armv8";
> > + reg = <0x0400>;
> > + enable-method = "psci";
> > + clock-frequency = <2000000000>;
> > + cpu-idle-states = <&cpuoff_l &clusteroff_l
> > &mcusysoff>;
> > + next-level-cache = <&l2_0>;
> > + };
> > +
> > + cpu5: cpu@101 {
> > + device_type = "cpu";
> > + compatible = "arm,cortex-a55", "arm,armv8";
> > + reg = <0x0500>;
> > + enable-method = "psci";
> > + clock-frequency = <2000000000>;
> > + cpu-idle-states = <&cpuoff_l &clusteroff_l
> > &mcusysoff>;
> > + next-level-cache = <&l2_0>;
> > + };
> > +
> > + cpu6: cpu@102 {
> > + device_type = "cpu";
> > + compatible = "arm,cortex-a75", "arm,armv8";
> > + reg = <0x0600>;
> > + enable-method = "psci";
> > + clock-frequency = <2050000000>;
> > + cpu-idle-states = <&cpuoff_b &clusteroff_b
> > &mcusysoff>;
> > + next-level-cache = <&l2_1>;
> > + };
> > +
> > + cpu7: cpu@103 {
> > + device_type = "cpu";
> > + compatible = "arm,cortex-a75", "arm,armv8";
> > + reg = <0x0700>;
> > + enable-method = "psci";
> > + clock-frequency = <2050000000>;
> > + cpu-idle-states = <&cpuoff_b &clusteroff_b
> > &mcusysoff>;
> > + next-level-cache = <&l2_1>;
> > + };
> > +
> > + cpu-map {
> > + cluster0 {
> > + core0 {
> > + cpu = <&cpu0>;
> > + };
> > +
> > + core1 {
> > + cpu = <&cpu1>;
> > + };
> > +
> > + core2 {
> > + cpu = <&cpu2>;
> > + };
> > +
> > + core3 {
> > + cpu = <&cpu3>;
> > + };
> > +
> > + core4 {
> > + cpu = <&cpu4>;
> > + };
> > +
> > + core5 {
> > + cpu = <&cpu5>;
> > + };
> > +
> > + };
> > + cluster1 {
> > + core0 {
> > + cpu = <&cpu6>;
> > + };
> > +
> > + core1 {
> > + cpu = <&cpu7>;
> > + };
> > + };
> > + };
> > +
> > + idle-states {
> > + entry-method = "psci";
> > +
> > + cpuoff_l: cpu-off-l {
> > + compatible = "arm,idle-state";
> > + arm,psci-suspend-param =
> > <0x00010001>;
> > + local-timer-stop;
> > + entry-latency-us = <50>;
> > + exit-latency-us = <100>;
> > + min-residency-us = <1600>;
> > + };
> > +
> > + cpuoff_b: cpu-off-b {
> > + compatible = "arm,idle-state";
> > + arm,psci-suspend-param =
> > <0x00010001>;
> > + local-timer-stop;
> > + entry-latency-us = <50>;
> > + exit-latency-us = <100>;
> > + min-residency-us = <1400>;
> > + };
> > +
> > + clusteroff_l: cluster-off-l {
> > + compatible = "arm,idle-state";
> > + arm,psci-suspend-param =
> > <0x01010001>;
> > + local-timer-stop;
> > + entry-latency-us = <100>;
> > + exit-latency-us = <250>;
> > + min-residency-us = <2100>;
> > + };
> > +
> > + clusteroff_b: cluster-off-b {
> > + compatible = "arm,idle-state";
> > + arm,psci-suspend-param =
> > <0x01010001>;
> > + local-timer-stop;
> > + entry-latency-us = <100>;
> > + exit-latency-us = <250>;
> > + min-residency-us = <1900>;
> > + };
> > +
> > + mcusysoff: mcusys-off {
> > + compatible = "arm,idle-state";
> > + arm,psci-suspend-param =
> > <0x01010002>;
> > + local-timer-stop;
> > + entry-latency-us = <300>;
> > + exit-latency-us = <1200>;
> > + min-residency-us = <2600>;
> > + };
> > + };
> > +
> > + l2_0: l2-cache0 {
> > + compatible = "cache";
> > + next-level-cache = <&l3_0>;
> > + };
> > +
> > + l2_1: l2-cache1 {
> > + compatible = "cache";
> > + next-level-cache = <&l3_0>;
> > + };
> > +
> > + l3_0: l3-cache {
> > + compatible = "cache";
> > + };
> > + };
> > +
> > + clk26m: oscillator-26m {
> > + compatible = "fixed-clock";
> > + #clock-cells = <0>;
> > + clock-frequency = <26000000>;
> > + };
> > +
> > + clk32k: oscillator-32k {
> > + compatible = "fixed-clock";
> > + #clock-cells = <0>;
> > + clock-frequency = <32000>;
> > + };
> > +
> > + psci {
> > + compatible = "arm,psci-1.0";
> > + method = "smc";
> > + };
> > +
>
> please move below nodes into soc {}
Hi Hsin-Yi,
Thanks you for your feedback.
I will add soc {} in next version.
>
>
> > + gic: interrupt-controller {
> > + compatible = "arm,gic-v3";
> > + #interrupt-cells = <3>;
> > + #address-cells = <2>;
> > + #size-cells = <2>;
> > + #redistributor-regions = <1>;
> > + interrupt-parent = <&gic>;
> > + interrupt-controller;
> > + reg = <0 0x0c000000 0 0x40000>, // distributor
> > + <0 0x0c040000 0 0x200000>; // redistributor
> > + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
> > + };
> > +
> > + watchdog: watchdog@10007000 {
> > + compatible = "mediatek,mt8186-wdt",
> > + "mediatek,mt6589-wdt";
> > + reg = <0 0x10007000 0 0x1000>;
> > + };
> > +
> > + sys_timer@10017000 {
> > + compatible = "mediatek,mt8186_timer",
> > + "mediatek,mt6765-timer";
> > + reg = <0 0x10017000 0 0x1000>;
> > + interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
> > + clocks = <&clk26m>;
> > + };
> > +
> > + timer: timer {
> > + compatible = "arm,armv8-timer";
> > + interrupt-parent = <&gic>;
> > + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
> > + <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
> > + <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
> > + <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
> > + clock-frequency = <13000000>;
> > + };
> > +
> > + uart0: serial@11002000 {
> > + compatible = "mediatek,mt8186-uart",
> > + "mediatek,mt6577-uart";
> > + reg = <0 0x11002000 0 0x1000>;
> > + interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
> > + clocks = <&clk26m>, <&clk26m>;
> > + clock-names = "baud", "bus";
> > + };
> > +
> > + uart1: serial@11003000 {
> > + compatible = "mediatek,mt8186-uart",
> > + "mediatek,mt6577-uart";
> > + reg = <0 0x11003000 0 0x1000>;
> > + interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
> > + clocks = <&clk26m>, <&clk26m>;
> > + clock-names = "baud", "bus";
> > + status = "disabled";
> > + };
> > +
> > + uart2: serial@11018000 {
> > + compatible = "mediatek,mt8186-uart",
> > + "mediatek,mt6577-uart";
> > + reg = <0 0x11018000 0 0x1000>;
> > + interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
> > + clocks = <&clk26m>, <&clk26m>;
> > + clock-names = "baud", "bus";
> > + status = "disabled";
> > + };
> > +
> > + mmc0: mmc@11230000 {
> > + compatible = "mediatek,mt8186-mmc",
> > "mediatek,mt8183-mmc";
> > + reg = <0 0x11230000 0 0x1000>,
> > + <0 0x11cd0000 0 0x1000>;
> > + interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
> > + clocks = <&clk26m>,
> > + <&clk26m>,
> > + <&clk26m>,
> > + <&clk26m>;
> > + clock-names = "source", "hclk", "source_cg",
> > + "ahb_clk";
> > + status = "disabled";
> > + };
> > +
> > + mmc1: mmc@11240000 {
> > + compatible = "mediatek,mt8186-mmc",
> > "mediatek,mt8183-mmc";
> > + reg = <0 0x11240000 0 0x1000>,
> > + <0 0x11c90000 0 0x1000>;
> > + interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
> > + clocks = <&clk26m>,
> > + <&clk26m>,
> > + <&clk26m>;
> > + clock-names = "source", "hclk", "source_cg";
> > + status = "disabled";
> > + };
> > +
> > + u3phy1: usb-phy1@11c80000 {
> > + compatible = "mediatek,mt8186-tphy",
> > "mediatek,generic-tphy-v2";
> > + #address-cells = <2>;
> > + #size-cells = <2>;
> > + ranges;
> > + status = "okay";
> > +
> > + u2port1: usb2-phy1@11c80000 {
> > + reg = <0 0x11c80000 0 0x700>;
> > + clocks = <&clk26m>;
> > + clock-names = "ref";
> > + #phy-cells = <1>;
> > + status = "okay";
> > + };
> > +
> > + u3port1: usb3-phy1@11c80900 {
> > + reg = <0 0x11c80900 0 0x700>;
> > + clocks = <&clk26m>;
> > + clock-names = "ref";
> > + #phy-cells = <1>;
> > + status = "okay";
> > + };
> > + };
> > +
> > + u3phy0: usb-phy@11ca0000 {
> > + compatible = "mediatek,mt8186-tphy",
> > "mediatek,generic-tphy-v2";
> > + #address-cells = <2>;
> > + #size-cells = <2>;
> > + ranges;
> > + status = "okay";
> > +
> > + u2port0: usb2-phy@11ca0000 {
> > + reg = <0 0x11ca0000 0 0x700>;
> > + clocks = <&clk26m>;
> > + clock-names = "ref";
> > + #phy-cells = <1>;
> > + mediatek,discth = <0x8>;
> > + status = "okay";
> > + };
> > + };
> > +};
> > --
> > 2.18.0
> >
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^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH v2 7/7] arm64: dts: Add Mediatek SoC MT8186 dts and evaluation board and Makefile
@ 2022-01-28 1:09 ` allen-kh.cheng
0 siblings, 0 replies; 21+ messages in thread
From: allen-kh.cheng @ 2022-01-28 1:09 UTC (permalink / raw)
To: Hsin-Yi Wang
Cc: Ulf Hansson, Rob Herring, Matthias Brugger,
Kishon Vijay Abraham I, Vinod Koul, Greg Kroah-Hartman,
Daniel Lezcano, Thomas Gleixner, Wim Van Sebroeck, Guenter Roeck,
Project_Global_Chrome_Upstream_Group, linux-kernel, devicetree,
linux-mediatek, linux-arm-kernel, linux-iio, linux-mmc,
linux-serial, linux-spi, linux-watchdog
On Thu, 2022-01-27 at 14:17 +0800, Hsin-Yi Wang wrote:
> On Wed, Jan 5, 2022 at 10:27 AM allen-kh.cheng
> <allen-kh.cheng@mediatek.com> wrote:
> >
> > From: Allen-KH Cheng <Allen-KH.Cheng@mediatek.com>
> >
> > Add basic chip support for Mediatek MT8186
> >
> > Signed-off-by: Allen-KH Cheng <Allen-KH.Cheng@mediatek.com>
> > ---
> > arch/arm64/boot/dts/mediatek/Makefile | 1 +
> > arch/arm64/boot/dts/mediatek/mt8186-evb.dts | 24 ++
> > arch/arm64/boot/dts/mediatek/mt8186.dtsi | 352
> > ++++++++++++++++++++
> > 3 files changed, 377 insertions(+)
> > create mode 100644 arch/arm64/boot/dts/mediatek/mt8186-evb.dts
> > create mode 100644 arch/arm64/boot/dts/mediatek/mt8186.dtsi
> >
> > diff --git a/arch/arm64/boot/dts/mediatek/Makefile
> > b/arch/arm64/boot/dts/mediatek/Makefile
> > index 4f68ebed2e31..2271c3452c64 100644
> > --- a/arch/arm64/boot/dts/mediatek/Makefile
> > +++ b/arch/arm64/boot/dts/mediatek/Makefile
> > @@ -31,5 +31,6 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-
> > kodama-sku32.dtb
> > dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-krane-sku0.dtb
> > dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-krane-sku176.dtb
> > dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-pumpkin.dtb
> > +dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-evb.dtb
> > dtb-$(CONFIG_ARCH_MEDIATEK) += mt8192-evb.dtb
> > dtb-$(CONFIG_ARCH_MEDIATEK) += mt8516-pumpkin.dtb
> > diff --git a/arch/arm64/boot/dts/mediatek/mt8186-evb.dts
> > b/arch/arm64/boot/dts/mediatek/mt8186-evb.dts
> > new file mode 100644
> > index 000000000000..eb23d1f19f87
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/mediatek/mt8186-evb.dts
> > @@ -0,0 +1,24 @@
> > +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> > +/*
> > + * Copyright (C) 2022 MediaTek Inc.
> > + */
> > +/dts-v1/;
> > +#include "mt8186.dtsi"
> > +
> > +/ {
> > + model = "MediaTek MT8186 evaluation board";
> > + compatible = "mediatek,mt8186-evb", "mediatek,mt8186";
> > +
> > + aliases {
> > + serial0 = &uart0;
> > + };
> > +
> > + chosen {
> > + stdout-path = "serial0:921600n8";
> > + };
> > +
> > + memory {
> > + device_type = "memory";
> > + reg = <0 0x40000000 0 0x80000000>;
> > + };
> > +};
> > diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi
> > b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
> > new file mode 100644
> > index 000000000000..fce84c341291
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
> > @@ -0,0 +1,352 @@
> > +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> > +/*
> > + * Copyright (C) 2022 MediaTek Inc.
> > + */
> > +/dts-v1/;
> > +
> > +#include <dt-bindings/interrupt-controller/arm-gic.h>
> > +#include <dt-bindings/interrupt-controller/irq.h>
> > +#include <dt-bindings/phy/phy.h>
> > +
> > +/ {
> > + compatible = "mediatek,mt8186";
> > + interrupt-parent = <&gic>;
> > + #address-cells = <2>;
> > + #size-cells = <2>;
> > +
> > + cpus {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > +
> > + cpu0: cpu@000 {
> > + device_type = "cpu";
> > + compatible = "arm,cortex-a55", "arm,armv8";
> > + reg = <0x0000>;
> > + enable-method = "psci";
> > + clock-frequency = <2000000000>;
> > + cpu-idle-states = <&cpuoff_l &clusteroff_l
> > &mcusysoff>;
> > + next-level-cache = <&l2_0>;
> > + };
> > +
> > + cpu1: cpu@001 {
> > + device_type = "cpu";
> > + compatible = "arm,cortex-a55", "arm,armv8";
> > + reg = <0x0100>;
> > + enable-method = "psci";
> > + clock-frequency = <2000000000>;
> > + cpu-idle-states = <&cpuoff_l &clusteroff_l
> > &mcusysoff>;
> > + next-level-cache = <&l2_0>;
> > + };
> > +
> > + cpu2: cpu@002 {
> > + device_type = "cpu";
> > + compatible = "arm,cortex-a55", "arm,armv8";
> > + reg = <0x0200>;
> > + enable-method = "psci";
> > + clock-frequency = <2000000000>;
> > + cpu-idle-states = <&cpuoff_l &clusteroff_l
> > &mcusysoff>;
> > + next-level-cache = <&l2_0>;
> > + };
> > +
> > + cpu3: cpu@003 {
> > + device_type = "cpu";
> > + compatible = "arm,cortex-a55", "arm,armv8";
> > + reg = <0x0300>;
> > + enable-method = "psci";
> > + clock-frequency = <2000000000>;
> > + cpu-idle-states = <&cpuoff_l &clusteroff_l
> > &mcusysoff>;
> > + next-level-cache = <&l2_0>;
> > + };
> > +
> > + cpu4: cpu@100 {
> > + device_type = "cpu";
> > + compatible = "arm,cortex-a55", "arm,armv8";
> > + reg = <0x0400>;
> > + enable-method = "psci";
> > + clock-frequency = <2000000000>;
> > + cpu-idle-states = <&cpuoff_l &clusteroff_l
> > &mcusysoff>;
> > + next-level-cache = <&l2_0>;
> > + };
> > +
> > + cpu5: cpu@101 {
> > + device_type = "cpu";
> > + compatible = "arm,cortex-a55", "arm,armv8";
> > + reg = <0x0500>;
> > + enable-method = "psci";
> > + clock-frequency = <2000000000>;
> > + cpu-idle-states = <&cpuoff_l &clusteroff_l
> > &mcusysoff>;
> > + next-level-cache = <&l2_0>;
> > + };
> > +
> > + cpu6: cpu@102 {
> > + device_type = "cpu";
> > + compatible = "arm,cortex-a75", "arm,armv8";
> > + reg = <0x0600>;
> > + enable-method = "psci";
> > + clock-frequency = <2050000000>;
> > + cpu-idle-states = <&cpuoff_b &clusteroff_b
> > &mcusysoff>;
> > + next-level-cache = <&l2_1>;
> > + };
> > +
> > + cpu7: cpu@103 {
> > + device_type = "cpu";
> > + compatible = "arm,cortex-a75", "arm,armv8";
> > + reg = <0x0700>;
> > + enable-method = "psci";
> > + clock-frequency = <2050000000>;
> > + cpu-idle-states = <&cpuoff_b &clusteroff_b
> > &mcusysoff>;
> > + next-level-cache = <&l2_1>;
> > + };
> > +
> > + cpu-map {
> > + cluster0 {
> > + core0 {
> > + cpu = <&cpu0>;
> > + };
> > +
> > + core1 {
> > + cpu = <&cpu1>;
> > + };
> > +
> > + core2 {
> > + cpu = <&cpu2>;
> > + };
> > +
> > + core3 {
> > + cpu = <&cpu3>;
> > + };
> > +
> > + core4 {
> > + cpu = <&cpu4>;
> > + };
> > +
> > + core5 {
> > + cpu = <&cpu5>;
> > + };
> > +
> > + };
> > + cluster1 {
> > + core0 {
> > + cpu = <&cpu6>;
> > + };
> > +
> > + core1 {
> > + cpu = <&cpu7>;
> > + };
> > + };
> > + };
> > +
> > + idle-states {
> > + entry-method = "psci";
> > +
> > + cpuoff_l: cpu-off-l {
> > + compatible = "arm,idle-state";
> > + arm,psci-suspend-param =
> > <0x00010001>;
> > + local-timer-stop;
> > + entry-latency-us = <50>;
> > + exit-latency-us = <100>;
> > + min-residency-us = <1600>;
> > + };
> > +
> > + cpuoff_b: cpu-off-b {
> > + compatible = "arm,idle-state";
> > + arm,psci-suspend-param =
> > <0x00010001>;
> > + local-timer-stop;
> > + entry-latency-us = <50>;
> > + exit-latency-us = <100>;
> > + min-residency-us = <1400>;
> > + };
> > +
> > + clusteroff_l: cluster-off-l {
> > + compatible = "arm,idle-state";
> > + arm,psci-suspend-param =
> > <0x01010001>;
> > + local-timer-stop;
> > + entry-latency-us = <100>;
> > + exit-latency-us = <250>;
> > + min-residency-us = <2100>;
> > + };
> > +
> > + clusteroff_b: cluster-off-b {
> > + compatible = "arm,idle-state";
> > + arm,psci-suspend-param =
> > <0x01010001>;
> > + local-timer-stop;
> > + entry-latency-us = <100>;
> > + exit-latency-us = <250>;
> > + min-residency-us = <1900>;
> > + };
> > +
> > + mcusysoff: mcusys-off {
> > + compatible = "arm,idle-state";
> > + arm,psci-suspend-param =
> > <0x01010002>;
> > + local-timer-stop;
> > + entry-latency-us = <300>;
> > + exit-latency-us = <1200>;
> > + min-residency-us = <2600>;
> > + };
> > + };
> > +
> > + l2_0: l2-cache0 {
> > + compatible = "cache";
> > + next-level-cache = <&l3_0>;
> > + };
> > +
> > + l2_1: l2-cache1 {
> > + compatible = "cache";
> > + next-level-cache = <&l3_0>;
> > + };
> > +
> > + l3_0: l3-cache {
> > + compatible = "cache";
> > + };
> > + };
> > +
> > + clk26m: oscillator-26m {
> > + compatible = "fixed-clock";
> > + #clock-cells = <0>;
> > + clock-frequency = <26000000>;
> > + };
> > +
> > + clk32k: oscillator-32k {
> > + compatible = "fixed-clock";
> > + #clock-cells = <0>;
> > + clock-frequency = <32000>;
> > + };
> > +
> > + psci {
> > + compatible = "arm,psci-1.0";
> > + method = "smc";
> > + };
> > +
>
> please move below nodes into soc {}
Hi Hsin-Yi,
Thanks you for your feedback.
I will add soc {} in next version.
>
>
> > + gic: interrupt-controller {
> > + compatible = "arm,gic-v3";
> > + #interrupt-cells = <3>;
> > + #address-cells = <2>;
> > + #size-cells = <2>;
> > + #redistributor-regions = <1>;
> > + interrupt-parent = <&gic>;
> > + interrupt-controller;
> > + reg = <0 0x0c000000 0 0x40000>, // distributor
> > + <0 0x0c040000 0 0x200000>; // redistributor
> > + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
> > + };
> > +
> > + watchdog: watchdog@10007000 {
> > + compatible = "mediatek,mt8186-wdt",
> > + "mediatek,mt6589-wdt";
> > + reg = <0 0x10007000 0 0x1000>;
> > + };
> > +
> > + sys_timer@10017000 {
> > + compatible = "mediatek,mt8186_timer",
> > + "mediatek,mt6765-timer";
> > + reg = <0 0x10017000 0 0x1000>;
> > + interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
> > + clocks = <&clk26m>;
> > + };
> > +
> > + timer: timer {
> > + compatible = "arm,armv8-timer";
> > + interrupt-parent = <&gic>;
> > + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
> > + <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
> > + <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
> > + <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
> > + clock-frequency = <13000000>;
> > + };
> > +
> > + uart0: serial@11002000 {
> > + compatible = "mediatek,mt8186-uart",
> > + "mediatek,mt6577-uart";
> > + reg = <0 0x11002000 0 0x1000>;
> > + interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
> > + clocks = <&clk26m>, <&clk26m>;
> > + clock-names = "baud", "bus";
> > + };
> > +
> > + uart1: serial@11003000 {
> > + compatible = "mediatek,mt8186-uart",
> > + "mediatek,mt6577-uart";
> > + reg = <0 0x11003000 0 0x1000>;
> > + interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
> > + clocks = <&clk26m>, <&clk26m>;
> > + clock-names = "baud", "bus";
> > + status = "disabled";
> > + };
> > +
> > + uart2: serial@11018000 {
> > + compatible = "mediatek,mt8186-uart",
> > + "mediatek,mt6577-uart";
> > + reg = <0 0x11018000 0 0x1000>;
> > + interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
> > + clocks = <&clk26m>, <&clk26m>;
> > + clock-names = "baud", "bus";
> > + status = "disabled";
> > + };
> > +
> > + mmc0: mmc@11230000 {
> > + compatible = "mediatek,mt8186-mmc",
> > "mediatek,mt8183-mmc";
> > + reg = <0 0x11230000 0 0x1000>,
> > + <0 0x11cd0000 0 0x1000>;
> > + interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
> > + clocks = <&clk26m>,
> > + <&clk26m>,
> > + <&clk26m>,
> > + <&clk26m>;
> > + clock-names = "source", "hclk", "source_cg",
> > + "ahb_clk";
> > + status = "disabled";
> > + };
> > +
> > + mmc1: mmc@11240000 {
> > + compatible = "mediatek,mt8186-mmc",
> > "mediatek,mt8183-mmc";
> > + reg = <0 0x11240000 0 0x1000>,
> > + <0 0x11c90000 0 0x1000>;
> > + interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
> > + clocks = <&clk26m>,
> > + <&clk26m>,
> > + <&clk26m>;
> > + clock-names = "source", "hclk", "source_cg";
> > + status = "disabled";
> > + };
> > +
> > + u3phy1: usb-phy1@11c80000 {
> > + compatible = "mediatek,mt8186-tphy",
> > "mediatek,generic-tphy-v2";
> > + #address-cells = <2>;
> > + #size-cells = <2>;
> > + ranges;
> > + status = "okay";
> > +
> > + u2port1: usb2-phy1@11c80000 {
> > + reg = <0 0x11c80000 0 0x700>;
> > + clocks = <&clk26m>;
> > + clock-names = "ref";
> > + #phy-cells = <1>;
> > + status = "okay";
> > + };
> > +
> > + u3port1: usb3-phy1@11c80900 {
> > + reg = <0 0x11c80900 0 0x700>;
> > + clocks = <&clk26m>;
> > + clock-names = "ref";
> > + #phy-cells = <1>;
> > + status = "okay";
> > + };
> > + };
> > +
> > + u3phy0: usb-phy@11ca0000 {
> > + compatible = "mediatek,mt8186-tphy",
> > "mediatek,generic-tphy-v2";
> > + #address-cells = <2>;
> > + #size-cells = <2>;
> > + ranges;
> > + status = "okay";
> > +
> > + u2port0: usb2-phy@11ca0000 {
> > + reg = <0 0x11ca0000 0 0x700>;
> > + clocks = <&clk26m>;
> > + clock-names = "ref";
> > + #phy-cells = <1>;
> > + mediatek,discth = <0x8>;
> > + status = "okay";
> > + };
> > + };
> > +};
> > --
> > 2.18.0
> >
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^ permalink raw reply [flat|nested] 21+ messages in thread
end of thread, other threads:[~2022-01-28 1:13 UTC | newest]
Thread overview: 21+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-01-05 2:27 [PATCH v2 0/7] Add basic node support for Mediatek MT8186 SoC allen-kh.cheng
2022-01-05 2:27 ` allen-kh.cheng
2022-01-05 2:27 ` [PATCH v2 1/7] dt-bindings: timer: Add compatible for Mediatek MT8186 allen-kh.cheng
2022-01-05 2:27 ` allen-kh.cheng
2022-01-05 2:27 ` [PATCH v2 2/7] dt-bindings: serial: " allen-kh.cheng
2022-01-05 2:27 ` allen-kh.cheng
2022-01-05 2:27 ` [PATCH v2 3/7] dt-bindings: watchdog: " allen-kh.cheng
2022-01-05 2:27 ` allen-kh.cheng
2022-01-05 2:27 ` [PATCH v2 4/7] dt-bindings: mmc: " allen-kh.cheng
2022-01-05 2:27 ` allen-kh.cheng
2022-01-05 2:27 ` [PATCH v2 5/7] dt-bindings: phy: " allen-kh.cheng
2022-01-05 2:27 ` allen-kh.cheng
2022-01-05 2:27 ` [PATCH v2 6/7] dt-bindings: arm: " allen-kh.cheng
2022-01-05 2:27 ` allen-kh.cheng
2022-01-05 2:27 ` [PATCH v2 7/7] arm64: dts: Add Mediatek SoC MT8186 dts and evaluation board and Makefile allen-kh.cheng
2022-01-05 2:27 ` allen-kh.cheng
2022-01-27 6:17 ` Hsin-Yi Wang
2022-01-27 6:17 ` Hsin-Yi Wang
2022-01-27 6:17 ` Hsin-Yi Wang
2022-01-28 1:09 ` allen-kh.cheng
2022-01-28 1:09 ` allen-kh.cheng
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