From: "Burton, Ross" <ross.burton@intel.com>
To: Khem Raj <raj.khem@gmail.com>
Cc: OE-core <openembedded-core@lists.openembedded.org>
Subject: Re: [PATCH 06/10] binutils: Convert SRC_URI and SRCREV to weak defines
Date: Fri, 6 Oct 2017 11:22:54 +0100 [thread overview]
Message-ID: <CAJTo0Lb=YeOC-B5xQa8jPPsja+DCTdq9SAAOm4FfWzsMdcisvw@mail.gmail.com> (raw)
In-Reply-To: <1231bf23c001d44632edf9061b87ac6629d2fc83.1507250774.git.raj.khem@gmail.com>
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On 6 October 2017 at 01:50, Khem Raj <raj.khem@gmail.com> wrote:
> This makes it easy to override them in bbappends
>
Doesn't a straight forward assignment work in a bbappend?
Ross
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next prev parent reply other threads:[~2017-10-06 10:23 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-10-06 0:50 [PATCH 00/10] Add foundation for riscv architecture Khem Raj
2017-10-06 0:50 ` [PATCH 01/10] site: Add riscv32 and riscv64 Khem Raj
2017-10-06 0:50 ` [PATCH 02/10] insane: Add entries for riscv 32bit/64bit Khem Raj
2017-10-06 0:50 ` [PATCH 03/10] siteinfo: Define data for riscv32 and riscv64 Khem Raj
2017-10-06 0:50 ` [PATCH 04/10] kernel-arch.bbclass: Add riscv to kernel arch map Khem Raj
2017-10-06 0:50 ` [PATCH 05/10] runqemu: Add riscv support for qemu machines Khem Raj
2017-10-06 0:50 ` [PATCH 06/10] binutils: Convert SRC_URI and SRCREV to weak defines Khem Raj
2017-10-06 10:22 ` Burton, Ross [this message]
2017-10-06 13:23 ` Khem Raj
2017-10-06 0:50 ` [PATCH 07/10] gcc: Backport fix for a segfault on riscv Khem Raj
2017-10-06 0:50 ` [PATCH 08/10] gcc-runtime: Disable libitm " Khem Raj
2017-10-06 0:50 ` [PATCH 09/10] elfutils: Fix missing library on linker cmdline Khem Raj
2017-10-06 0:50 ` [PATCH 10/10] openssl: Add support for riscv32/riscv64 Khem Raj
2017-10-06 1:00 ` ✗ patchtest: failure for Add foundation for riscv architecture Patchwork
2017-10-15 20:36 ` [PATCH 00/10] " Trevor Woerner
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