* [PATCH] x86: intel_epb: Allow model specific normal EPB value
@ 2021-12-11 16:33 Srinivas Pandruvada
2021-12-13 10:00 ` Rafael J. Wysocki
0 siblings, 1 reply; 3+ messages in thread
From: Srinivas Pandruvada @ 2021-12-11 16:33 UTC (permalink / raw)
To: tglx, mingo, bp, dave.hansen, hpa, peterz, rafael
Cc: x86, linux-kernel, Srinivas Pandruvada
The current EPB "normal" is defined as 6 and set whenever power-up EPB
value is 0. This setting resulted in the desired out of box power and
performance for several CPU generations. But this value is not suitable
for AlderLake mobile CPUs, as this resulted in higher uncore power.
Since EPB is model specific, this is not unreasonable to have different
behavior.
Allow a capability where "normal" EPB can be redefined. For AlderLake
mobile CPUs this desired normal value is 7.
Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
---
arch/x86/kernel/cpu/intel_epb.c | 45 +++++++++++++++++++++++----------
1 file changed, 32 insertions(+), 13 deletions(-)
diff --git a/arch/x86/kernel/cpu/intel_epb.c b/arch/x86/kernel/cpu/intel_epb.c
index f4dd73396f28..fbaf12e43f41 100644
--- a/arch/x86/kernel/cpu/intel_epb.c
+++ b/arch/x86/kernel/cpu/intel_epb.c
@@ -16,6 +16,7 @@
#include <linux/syscore_ops.h>
#include <linux/pm.h>
+#include <asm/cpu_device_id.h>
#include <asm/cpufeature.h>
#include <asm/msr.h>
@@ -58,6 +59,22 @@ static DEFINE_PER_CPU(u8, saved_epb);
#define EPB_SAVED 0x10ULL
#define MAX_EPB EPB_MASK
+enum energy_perf_value_index {
+ EPB_INDEX_PERFORMANCE,
+ EPB_INDEX_BALANCE_PERFORMANCE,
+ EPB_INDEX_NORMAL,
+ EPB_INDEX_BALANCE_POWERSAVE,
+ EPB_INDEX_POWERSAVE,
+};
+
+static u8 energ_perf_values[] = {
+ [EPB_INDEX_PERFORMANCE] = ENERGY_PERF_BIAS_PERFORMANCE,
+ [EPB_INDEX_BALANCE_PERFORMANCE] = ENERGY_PERF_BIAS_BALANCE_PERFORMANCE,
+ [EPB_INDEX_NORMAL] = ENERGY_PERF_BIAS_NORMAL,
+ [EPB_INDEX_BALANCE_POWERSAVE] = ENERGY_PERF_BIAS_BALANCE_POWERSAVE,
+ [EPB_INDEX_POWERSAVE] = ENERGY_PERF_BIAS_POWERSAVE,
+};
+
static int intel_epb_save(void)
{
u64 epb;
@@ -90,7 +107,7 @@ static void intel_epb_restore(void)
*/
val = epb & EPB_MASK;
if (val == ENERGY_PERF_BIAS_PERFORMANCE) {
- val = ENERGY_PERF_BIAS_NORMAL;
+ val = energ_perf_values[EPB_INDEX_NORMAL];
pr_warn_once("ENERGY_PERF_BIAS: Set to 'normal', was 'performance'\n");
}
}
@@ -103,18 +120,11 @@ static struct syscore_ops intel_epb_syscore_ops = {
};
static const char * const energy_perf_strings[] = {
- "performance",
- "balance-performance",
- "normal",
- "balance-power",
- "power"
-};
-static const u8 energ_perf_values[] = {
- ENERGY_PERF_BIAS_PERFORMANCE,
- ENERGY_PERF_BIAS_BALANCE_PERFORMANCE,
- ENERGY_PERF_BIAS_NORMAL,
- ENERGY_PERF_BIAS_BALANCE_POWERSAVE,
- ENERGY_PERF_BIAS_POWERSAVE
+ [EPB_INDEX_PERFORMANCE] = "performance",
+ [EPB_INDEX_BALANCE_PERFORMANCE] = "balance-performance",
+ [EPB_INDEX_NORMAL] = "normal",
+ [EPB_INDEX_BALANCE_POWERSAVE] = "balance-power",
+ [EPB_INDEX_POWERSAVE] = "power",
};
static ssize_t energy_perf_bias_show(struct device *dev,
@@ -193,13 +203,22 @@ static int intel_epb_offline(unsigned int cpu)
return 0;
}
+static const struct x86_cpu_id intel_epb_normal[] = {
+ X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE_L, 7),
+ {}
+};
+
static __init int intel_epb_init(void)
{
+ const struct x86_cpu_id *id = x86_match_cpu(intel_epb_normal);
int ret;
if (!boot_cpu_has(X86_FEATURE_EPB))
return -ENODEV;
+ if (id)
+ energ_perf_values[EPB_INDEX_NORMAL] = id->driver_data;
+
ret = cpuhp_setup_state(CPUHP_AP_X86_INTEL_EPB_ONLINE,
"x86/intel/epb:online", intel_epb_online,
intel_epb_offline);
--
2.31.1
^ permalink raw reply related [flat|nested] 3+ messages in thread
* Re: [PATCH] x86: intel_epb: Allow model specific normal EPB value
2021-12-11 16:33 [PATCH] x86: intel_epb: Allow model specific normal EPB value Srinivas Pandruvada
@ 2021-12-13 10:00 ` Rafael J. Wysocki
2022-01-04 15:26 ` Rafael J. Wysocki
0 siblings, 1 reply; 3+ messages in thread
From: Rafael J. Wysocki @ 2021-12-13 10:00 UTC (permalink / raw)
To: Srinivas Pandruvada
Cc: Thomas Gleixner, Ingo Molnar, Borislav Petkov, Dave Hansen,
H. Peter Anvin, Peter Zijlstra, Rafael J. Wysocki,
the arch/x86 maintainers, Linux Kernel Mailing List
On Sat, Dec 11, 2021 at 5:33 PM Srinivas Pandruvada
<srinivas.pandruvada@linux.intel.com> wrote:
>
> The current EPB "normal" is defined as 6 and set whenever power-up EPB
> value is 0. This setting resulted in the desired out of box power and
> performance for several CPU generations. But this value is not suitable
> for AlderLake mobile CPUs, as this resulted in higher uncore power.
> Since EPB is model specific, this is not unreasonable to have different
> behavior.
>
> Allow a capability where "normal" EPB can be redefined. For AlderLake
> mobile CPUs this desired normal value is 7.
>
> Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
Reviewed-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
> ---
> arch/x86/kernel/cpu/intel_epb.c | 45 +++++++++++++++++++++++----------
> 1 file changed, 32 insertions(+), 13 deletions(-)
>
> diff --git a/arch/x86/kernel/cpu/intel_epb.c b/arch/x86/kernel/cpu/intel_epb.c
> index f4dd73396f28..fbaf12e43f41 100644
> --- a/arch/x86/kernel/cpu/intel_epb.c
> +++ b/arch/x86/kernel/cpu/intel_epb.c
> @@ -16,6 +16,7 @@
> #include <linux/syscore_ops.h>
> #include <linux/pm.h>
>
> +#include <asm/cpu_device_id.h>
> #include <asm/cpufeature.h>
> #include <asm/msr.h>
>
> @@ -58,6 +59,22 @@ static DEFINE_PER_CPU(u8, saved_epb);
> #define EPB_SAVED 0x10ULL
> #define MAX_EPB EPB_MASK
>
> +enum energy_perf_value_index {
> + EPB_INDEX_PERFORMANCE,
> + EPB_INDEX_BALANCE_PERFORMANCE,
> + EPB_INDEX_NORMAL,
> + EPB_INDEX_BALANCE_POWERSAVE,
> + EPB_INDEX_POWERSAVE,
> +};
> +
> +static u8 energ_perf_values[] = {
> + [EPB_INDEX_PERFORMANCE] = ENERGY_PERF_BIAS_PERFORMANCE,
> + [EPB_INDEX_BALANCE_PERFORMANCE] = ENERGY_PERF_BIAS_BALANCE_PERFORMANCE,
> + [EPB_INDEX_NORMAL] = ENERGY_PERF_BIAS_NORMAL,
> + [EPB_INDEX_BALANCE_POWERSAVE] = ENERGY_PERF_BIAS_BALANCE_POWERSAVE,
> + [EPB_INDEX_POWERSAVE] = ENERGY_PERF_BIAS_POWERSAVE,
> +};
> +
> static int intel_epb_save(void)
> {
> u64 epb;
> @@ -90,7 +107,7 @@ static void intel_epb_restore(void)
> */
> val = epb & EPB_MASK;
> if (val == ENERGY_PERF_BIAS_PERFORMANCE) {
> - val = ENERGY_PERF_BIAS_NORMAL;
> + val = energ_perf_values[EPB_INDEX_NORMAL];
> pr_warn_once("ENERGY_PERF_BIAS: Set to 'normal', was 'performance'\n");
> }
> }
> @@ -103,18 +120,11 @@ static struct syscore_ops intel_epb_syscore_ops = {
> };
>
> static const char * const energy_perf_strings[] = {
> - "performance",
> - "balance-performance",
> - "normal",
> - "balance-power",
> - "power"
> -};
> -static const u8 energ_perf_values[] = {
> - ENERGY_PERF_BIAS_PERFORMANCE,
> - ENERGY_PERF_BIAS_BALANCE_PERFORMANCE,
> - ENERGY_PERF_BIAS_NORMAL,
> - ENERGY_PERF_BIAS_BALANCE_POWERSAVE,
> - ENERGY_PERF_BIAS_POWERSAVE
> + [EPB_INDEX_PERFORMANCE] = "performance",
> + [EPB_INDEX_BALANCE_PERFORMANCE] = "balance-performance",
> + [EPB_INDEX_NORMAL] = "normal",
> + [EPB_INDEX_BALANCE_POWERSAVE] = "balance-power",
> + [EPB_INDEX_POWERSAVE] = "power",
> };
>
> static ssize_t energy_perf_bias_show(struct device *dev,
> @@ -193,13 +203,22 @@ static int intel_epb_offline(unsigned int cpu)
> return 0;
> }
>
> +static const struct x86_cpu_id intel_epb_normal[] = {
> + X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE_L, 7),
> + {}
> +};
> +
> static __init int intel_epb_init(void)
> {
> + const struct x86_cpu_id *id = x86_match_cpu(intel_epb_normal);
> int ret;
>
> if (!boot_cpu_has(X86_FEATURE_EPB))
> return -ENODEV;
>
> + if (id)
> + energ_perf_values[EPB_INDEX_NORMAL] = id->driver_data;
> +
> ret = cpuhp_setup_state(CPUHP_AP_X86_INTEL_EPB_ONLINE,
> "x86/intel/epb:online", intel_epb_online,
> intel_epb_offline);
> --
> 2.31.1
>
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH] x86: intel_epb: Allow model specific normal EPB value
2021-12-13 10:00 ` Rafael J. Wysocki
@ 2022-01-04 15:26 ` Rafael J. Wysocki
0 siblings, 0 replies; 3+ messages in thread
From: Rafael J. Wysocki @ 2022-01-04 15:26 UTC (permalink / raw)
To: Rafael J. Wysocki
Cc: Srinivas Pandruvada, Thomas Gleixner, Ingo Molnar,
Borislav Petkov, Dave Hansen, H. Peter Anvin, Peter Zijlstra,
the arch/x86 maintainers, Linux Kernel Mailing List
On Mon, Dec 13, 2021 at 11:00 AM Rafael J. Wysocki <rafael@kernel.org> wrote:
>
> On Sat, Dec 11, 2021 at 5:33 PM Srinivas Pandruvada
> <srinivas.pandruvada@linux.intel.com> wrote:
> >
> > The current EPB "normal" is defined as 6 and set whenever power-up EPB
> > value is 0. This setting resulted in the desired out of box power and
> > performance for several CPU generations. But this value is not suitable
> > for AlderLake mobile CPUs, as this resulted in higher uncore power.
> > Since EPB is model specific, this is not unreasonable to have different
> > behavior.
> >
> > Allow a capability where "normal" EPB can be redefined. For AlderLake
> > mobile CPUs this desired normal value is 7.
> >
> > Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
>
> Reviewed-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
And since there don't seem to be any concerns regarding this, I'm
going to apply it.
> > ---
> > arch/x86/kernel/cpu/intel_epb.c | 45 +++++++++++++++++++++++----------
> > 1 file changed, 32 insertions(+), 13 deletions(-)
> >
> > diff --git a/arch/x86/kernel/cpu/intel_epb.c b/arch/x86/kernel/cpu/intel_epb.c
> > index f4dd73396f28..fbaf12e43f41 100644
> > --- a/arch/x86/kernel/cpu/intel_epb.c
> > +++ b/arch/x86/kernel/cpu/intel_epb.c
> > @@ -16,6 +16,7 @@
> > #include <linux/syscore_ops.h>
> > #include <linux/pm.h>
> >
> > +#include <asm/cpu_device_id.h>
> > #include <asm/cpufeature.h>
> > #include <asm/msr.h>
> >
> > @@ -58,6 +59,22 @@ static DEFINE_PER_CPU(u8, saved_epb);
> > #define EPB_SAVED 0x10ULL
> > #define MAX_EPB EPB_MASK
> >
> > +enum energy_perf_value_index {
> > + EPB_INDEX_PERFORMANCE,
> > + EPB_INDEX_BALANCE_PERFORMANCE,
> > + EPB_INDEX_NORMAL,
> > + EPB_INDEX_BALANCE_POWERSAVE,
> > + EPB_INDEX_POWERSAVE,
> > +};
> > +
> > +static u8 energ_perf_values[] = {
> > + [EPB_INDEX_PERFORMANCE] = ENERGY_PERF_BIAS_PERFORMANCE,
> > + [EPB_INDEX_BALANCE_PERFORMANCE] = ENERGY_PERF_BIAS_BALANCE_PERFORMANCE,
> > + [EPB_INDEX_NORMAL] = ENERGY_PERF_BIAS_NORMAL,
> > + [EPB_INDEX_BALANCE_POWERSAVE] = ENERGY_PERF_BIAS_BALANCE_POWERSAVE,
> > + [EPB_INDEX_POWERSAVE] = ENERGY_PERF_BIAS_POWERSAVE,
> > +};
> > +
> > static int intel_epb_save(void)
> > {
> > u64 epb;
> > @@ -90,7 +107,7 @@ static void intel_epb_restore(void)
> > */
> > val = epb & EPB_MASK;
> > if (val == ENERGY_PERF_BIAS_PERFORMANCE) {
> > - val = ENERGY_PERF_BIAS_NORMAL;
> > + val = energ_perf_values[EPB_INDEX_NORMAL];
> > pr_warn_once("ENERGY_PERF_BIAS: Set to 'normal', was 'performance'\n");
> > }
> > }
> > @@ -103,18 +120,11 @@ static struct syscore_ops intel_epb_syscore_ops = {
> > };
> >
> > static const char * const energy_perf_strings[] = {
> > - "performance",
> > - "balance-performance",
> > - "normal",
> > - "balance-power",
> > - "power"
> > -};
> > -static const u8 energ_perf_values[] = {
> > - ENERGY_PERF_BIAS_PERFORMANCE,
> > - ENERGY_PERF_BIAS_BALANCE_PERFORMANCE,
> > - ENERGY_PERF_BIAS_NORMAL,
> > - ENERGY_PERF_BIAS_BALANCE_POWERSAVE,
> > - ENERGY_PERF_BIAS_POWERSAVE
> > + [EPB_INDEX_PERFORMANCE] = "performance",
> > + [EPB_INDEX_BALANCE_PERFORMANCE] = "balance-performance",
> > + [EPB_INDEX_NORMAL] = "normal",
> > + [EPB_INDEX_BALANCE_POWERSAVE] = "balance-power",
> > + [EPB_INDEX_POWERSAVE] = "power",
> > };
> >
> > static ssize_t energy_perf_bias_show(struct device *dev,
> > @@ -193,13 +203,22 @@ static int intel_epb_offline(unsigned int cpu)
> > return 0;
> > }
> >
> > +static const struct x86_cpu_id intel_epb_normal[] = {
> > + X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE_L, 7),
> > + {}
> > +};
> > +
> > static __init int intel_epb_init(void)
> > {
> > + const struct x86_cpu_id *id = x86_match_cpu(intel_epb_normal);
> > int ret;
> >
> > if (!boot_cpu_has(X86_FEATURE_EPB))
> > return -ENODEV;
> >
> > + if (id)
> > + energ_perf_values[EPB_INDEX_NORMAL] = id->driver_data;
> > +
> > ret = cpuhp_setup_state(CPUHP_AP_X86_INTEL_EPB_ONLINE,
> > "x86/intel/epb:online", intel_epb_online,
> > intel_epb_offline);
> > --
> > 2.31.1
> >
^ permalink raw reply [flat|nested] 3+ messages in thread
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2021-12-11 16:33 [PATCH] x86: intel_epb: Allow model specific normal EPB value Srinivas Pandruvada
2021-12-13 10:00 ` Rafael J. Wysocki
2022-01-04 15:26 ` Rafael J. Wysocki
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