* [PATCH 1/3] powercap: intel_rapl: Add support for Cannon Lake
@ 2018-03-09 12:15 Harry Pan
2018-03-09 12:15 ` [PATCH 2/3] perf/x86/intel: Add Cannon Lake support of RAPL profiling Harry Pan
` (4 more replies)
0 siblings, 5 replies; 13+ messages in thread
From: Harry Pan @ 2018-03-09 12:15 UTC (permalink / raw)
To: LKML; +Cc: gs0622, Harry Pan, rjw, linux-pm
Cannon Lake microarchitecture is similar to Kaby Lake in terms of
RAPL, this patch enables CNL RAPL support.
Signed-off-by: Harry Pan <harry.pan@intel.com>
---
drivers/powercap/intel_rapl.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/powercap/intel_rapl.c b/drivers/powercap/intel_rapl.c
index 35636e1d8a3d..295d8dcba48c 100644
--- a/drivers/powercap/intel_rapl.c
+++ b/drivers/powercap/intel_rapl.c
@@ -1162,6 +1162,7 @@ static const struct x86_cpu_id rapl_ids[] __initconst = {
RAPL_CPU(INTEL_FAM6_SKYLAKE_X, rapl_defaults_hsw_server),
RAPL_CPU(INTEL_FAM6_KABYLAKE_MOBILE, rapl_defaults_core),
RAPL_CPU(INTEL_FAM6_KABYLAKE_DESKTOP, rapl_defaults_core),
+ RAPL_CPU(INTEL_FAM6_CANNONLAKE_MOBILE, rapl_defaults_core),
RAPL_CPU(INTEL_FAM6_ATOM_SILVERMONT1, rapl_defaults_byt),
RAPL_CPU(INTEL_FAM6_ATOM_AIRMONT, rapl_defaults_cht),
--
2.13.5
^ permalink raw reply related [flat|nested] 13+ messages in thread* [PATCH 2/3] perf/x86/intel: Add Cannon Lake support of RAPL profiling 2018-03-09 12:15 [PATCH 1/3] powercap: intel_rapl: Add support for Cannon Lake Harry Pan @ 2018-03-09 12:15 ` Harry Pan 2018-03-19 23:05 ` Benson Leung 2018-03-31 10:19 ` [tip:perf/core] perf/x86/intel: Add Cannon Lake support for " tip-bot for Harry Pan 2018-03-09 12:15 ` [PATCH 3/3] perf/x86/intel: Enable C-state residency events for Cannon Lake Harry Pan ` (3 subsequent siblings) 4 siblings, 2 replies; 13+ messages in thread From: Harry Pan @ 2018-03-09 12:15 UTC (permalink / raw) To: LKML Cc: gs0622, Harry Pan, tglx, mingo, hpa, x86, kan.liang, vincent.weaver, peterz, colin.king This patch enables RAPL counters (energy consumption counters) support for Cannon Lake processors. ESU and power domains refer to Intel Software Developers' Manual, Vol. 4, Order No. 335592. Usage example: $ perf list $ perf stat -a -e power/energy-cores/,power/energy-pkg/ sleep 10 Signed-off-by: Harry Pan <harry.pan@intel.com> --- arch/x86/events/intel/rapl.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/x86/events/intel/rapl.c b/arch/x86/events/intel/rapl.c index a2efb490f743..32f3e9423e99 100644 --- a/arch/x86/events/intel/rapl.c +++ b/arch/x86/events/intel/rapl.c @@ -774,6 +774,8 @@ static const struct x86_cpu_id rapl_cpu_match[] __initconst = { X86_RAPL_MODEL_MATCH(INTEL_FAM6_KABYLAKE_MOBILE, skl_rapl_init), X86_RAPL_MODEL_MATCH(INTEL_FAM6_KABYLAKE_DESKTOP, skl_rapl_init), + X86_RAPL_MODEL_MATCH(INTEL_FAM6_CANNONLAKE_MOBILE, skl_rapl_init), + X86_RAPL_MODEL_MATCH(INTEL_FAM6_ATOM_GOLDMONT, hsw_rapl_init), X86_RAPL_MODEL_MATCH(INTEL_FAM6_ATOM_DENVERTON, hsw_rapl_init), -- 2.13.5 ^ permalink raw reply related [flat|nested] 13+ messages in thread
* Re: [PATCH 2/3] perf/x86/intel: Add Cannon Lake support of RAPL profiling 2018-03-09 12:15 ` [PATCH 2/3] perf/x86/intel: Add Cannon Lake support of RAPL profiling Harry Pan @ 2018-03-19 23:05 ` Benson Leung 2018-03-19 23:11 ` Puthikorn Voravootivat 2018-03-31 10:19 ` [tip:perf/core] perf/x86/intel: Add Cannon Lake support for " tip-bot for Harry Pan 1 sibling, 1 reply; 13+ messages in thread From: Benson Leung @ 2018-03-19 23:05 UTC (permalink / raw) To: Harry Pan, LKML Cc: gs0622, tglx, mingo, hpa, x86, kan.liang, vincent.weaver, peterz, colin.king, puthik, bleung, Benson Leung [-- Attachment #1.1: Type: text/plain, Size: 1367 bytes --] Hi Harry, On 03/09/2018 04:15 AM, Harry Pan wrote: > This patch enables RAPL counters (energy consumption counters) > support for Cannon Lake processors. > > ESU and power domains refer to Intel Software Developers' Manual, > Vol. 4, Order No. 335592. > > Usage example: > > $ perf list > $ perf stat -a -e power/energy-cores/,power/energy-pkg/ sleep 10 > > Signed-off-by: Harry Pan <harry.pan@intel.com> Reviewed-by: Benson Leung <bleung@chromium.org> > --- > arch/x86/events/intel/rapl.c | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/arch/x86/events/intel/rapl.c b/arch/x86/events/intel/rapl.c > index a2efb490f743..32f3e9423e99 100644 > --- a/arch/x86/events/intel/rapl.c > +++ b/arch/x86/events/intel/rapl.c > @@ -774,6 +774,8 @@ static const struct x86_cpu_id rapl_cpu_match[] __initconst = { > X86_RAPL_MODEL_MATCH(INTEL_FAM6_KABYLAKE_MOBILE, skl_rapl_init), > X86_RAPL_MODEL_MATCH(INTEL_FAM6_KABYLAKE_DESKTOP, skl_rapl_init), > > + X86_RAPL_MODEL_MATCH(INTEL_FAM6_CANNONLAKE_MOBILE, skl_rapl_init), > + > X86_RAPL_MODEL_MATCH(INTEL_FAM6_ATOM_GOLDMONT, hsw_rapl_init), > X86_RAPL_MODEL_MATCH(INTEL_FAM6_ATOM_DENVERTON, hsw_rapl_init), > > Thanks, -- Benson Leung Staff Software Engineer Chrome OS Kernel Google Inc. bleung@google.com Chromium OS Project bleung@chromium.org [-- Attachment #2: OpenPGP digital signature --] [-- Type: application/pgp-signature, Size: 833 bytes --] ^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH 2/3] perf/x86/intel: Add Cannon Lake support of RAPL profiling 2018-03-19 23:05 ` Benson Leung @ 2018-03-19 23:11 ` Puthikorn Voravootivat 0 siblings, 0 replies; 13+ messages in thread From: Puthikorn Voravootivat @ 2018-03-19 23:11 UTC (permalink / raw) To: harry.pan Cc: linux-kernel, gs0622, tglx, mingo, hpa, x86, kan.liang, vincent.weaver, peterz, colin.king, bleung, Benson Leung On Mon, Mar 19, 2018 at 4:05 PM Benson Leung <bleung@google.com> wrote: > Hi Harry, > On 03/09/2018 04:15 AM, Harry Pan wrote: > > This patch enables RAPL counters (energy consumption counters) > > support for Cannon Lake processors. > > > > ESU and power domains refer to Intel Software Developers' Manual, > > Vol. 4, Order No. 335592. > > > > Usage example: > > > > $ perf list > > $ perf stat -a -e power/energy-cores/,power/energy-pkg/ sleep 10 > > > > Signed-off-by: Harry Pan <harry.pan@intel.com> > Reviewed-by: Benson Leung <bleung@chromium.org> Tested-by: Puthikorn Voravootivat <puthik@chromium.org> > > --- > > arch/x86/events/intel/rapl.c | 2 ++ > > 1 file changed, 2 insertions(+) > > > > diff --git a/arch/x86/events/intel/rapl.c b/arch/x86/events/intel/rapl.c > > index a2efb490f743..32f3e9423e99 100644 > > --- a/arch/x86/events/intel/rapl.c > > +++ b/arch/x86/events/intel/rapl.c > > @@ -774,6 +774,8 @@ static const struct x86_cpu_id rapl_cpu_match[] __initconst = { > > X86_RAPL_MODEL_MATCH(INTEL_FAM6_KABYLAKE_MOBILE, skl_rapl_init), > > X86_RAPL_MODEL_MATCH(INTEL_FAM6_KABYLAKE_DESKTOP, skl_rapl_init), > > > > + X86_RAPL_MODEL_MATCH(INTEL_FAM6_CANNONLAKE_MOBILE, skl_rapl_init), > > + > > X86_RAPL_MODEL_MATCH(INTEL_FAM6_ATOM_GOLDMONT, hsw_rapl_init), > > X86_RAPL_MODEL_MATCH(INTEL_FAM6_ATOM_DENVERTON, hsw_rapl_init), > > > > > Thanks, > -- > Benson Leung > Staff Software Engineer > Chrome OS Kernel > Google Inc. > bleung@google.com > Chromium OS Project > bleung@chromium.org ^ permalink raw reply [flat|nested] 13+ messages in thread
* [tip:perf/core] perf/x86/intel: Add Cannon Lake support for RAPL profiling 2018-03-09 12:15 ` [PATCH 2/3] perf/x86/intel: Add Cannon Lake support of RAPL profiling Harry Pan 2018-03-19 23:05 ` Benson Leung @ 2018-03-31 10:19 ` tip-bot for Harry Pan 1 sibling, 0 replies; 13+ messages in thread From: tip-bot for Harry Pan @ 2018-03-31 10:19 UTC (permalink / raw) To: linux-tip-commits Cc: peterz, mingo, vincent.weaver, torvalds, harry.pan, bleung, hpa, jolsa, puthik, acme, tglx, eranian, alexander.shishkin, linux-kernel Commit-ID: 490d03e83da2a5e9d7db84b1ec30a9c95415787e Gitweb: https://git.kernel.org/tip/490d03e83da2a5e9d7db84b1ec30a9c95415787e Author: Harry Pan <harry.pan@intel.com> AuthorDate: Fri, 9 Mar 2018 20:15:47 +0800 Committer: Ingo Molnar <mingo@kernel.org> CommitDate: Sat, 31 Mar 2018 11:28:36 +0200 perf/x86/intel: Add Cannon Lake support for RAPL profiling This patch enables RAPL counters (energy consumption counters) support for Cannon Lake processors. ( ESU and power domains refer to Intel Software Developers' Manual, Vol. 4, Order No. 335592. ) Usage example: $ perf list $ perf stat -a -e power/energy-cores/,power/energy-pkg/ sleep 10 Tested-by: Puthikorn Voravootivat <puthik@chromium.org> Signed-off-by: Harry Pan <harry.pan@intel.com> Reviewed-by: Benson Leung <bleung@chromium.org> Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com> Cc: Arnaldo Carvalho de Melo <acme@redhat.com> Cc: Jiri Olsa <jolsa@redhat.com> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Stephane Eranian <eranian@google.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Vince Weaver <vincent.weaver@maine.edu> Cc: colin.king@canonical.com Cc: gs0622@gmail.com Cc: kan.liang@linux.intel.com Link: http://lkml.kernel.org/r/20180309121549.630-2-harry.pan@intel.com Signed-off-by: Ingo Molnar <mingo@kernel.org> --- arch/x86/events/intel/rapl.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/x86/events/intel/rapl.c b/arch/x86/events/intel/rapl.c index a2efb490f743..32f3e9423e99 100644 --- a/arch/x86/events/intel/rapl.c +++ b/arch/x86/events/intel/rapl.c @@ -774,6 +774,8 @@ static const struct x86_cpu_id rapl_cpu_match[] __initconst = { X86_RAPL_MODEL_MATCH(INTEL_FAM6_KABYLAKE_MOBILE, skl_rapl_init), X86_RAPL_MODEL_MATCH(INTEL_FAM6_KABYLAKE_DESKTOP, skl_rapl_init), + X86_RAPL_MODEL_MATCH(INTEL_FAM6_CANNONLAKE_MOBILE, skl_rapl_init), + X86_RAPL_MODEL_MATCH(INTEL_FAM6_ATOM_GOLDMONT, hsw_rapl_init), X86_RAPL_MODEL_MATCH(INTEL_FAM6_ATOM_DENVERTON, hsw_rapl_init), ^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH 3/3] perf/x86/intel: Enable C-state residency events for Cannon Lake 2018-03-09 12:15 [PATCH 1/3] powercap: intel_rapl: Add support for Cannon Lake Harry Pan 2018-03-09 12:15 ` [PATCH 2/3] perf/x86/intel: Add Cannon Lake support of RAPL profiling Harry Pan @ 2018-03-09 12:15 ` Harry Pan 2018-03-19 23:09 ` Benson Leung 2018-03-31 10:19 ` [tip:perf/core] " tip-bot for Harry Pan 2018-03-19 23:03 ` [PATCH 1/3] powercap: intel_rapl: Add support " Benson Leung ` (2 subsequent siblings) 4 siblings, 2 replies; 13+ messages in thread From: Harry Pan @ 2018-03-09 12:15 UTC (permalink / raw) To: LKML; +Cc: gs0622, Harry Pan, tglx, mingo, hpa, x86, Kan.liang Cannon Lake supports C1/C3/C6/C7, PC2/PC3/PC6/PC7/PC8/PC9/PC10 state residency counters, this patch enables those counters. The MSR information is based on Intel Software Developers' Manual, Vol. 4, Order No. 335592. Signed-off-by: Harry Pan <harry.pan@intel.com> --- arch/x86/events/intel/cstate.c | 44 +++++++++++++++++++++++++++++------------- 1 file changed, 31 insertions(+), 13 deletions(-) diff --git a/arch/x86/events/intel/cstate.c b/arch/x86/events/intel/cstate.c index 72db0664a53d..9aca448bb8e6 100644 --- a/arch/x86/events/intel/cstate.c +++ b/arch/x86/events/intel/cstate.c @@ -40,50 +40,51 @@ * Model specific counters: * MSR_CORE_C1_RES: CORE C1 Residency Counter * perf code: 0x00 - * Available model: SLM,AMT,GLM + * Available model: SLM,AMT,GLM,CNL * Scope: Core (each processor core has a MSR) * MSR_CORE_C3_RESIDENCY: CORE C3 Residency Counter * perf code: 0x01 - * Available model: NHM,WSM,SNB,IVB,HSW,BDW,SKL,GLM + * Available model: NHM,WSM,SNB,IVB,HSW,BDW,SKL,GLM, + CNL * Scope: Core * MSR_CORE_C6_RESIDENCY: CORE C6 Residency Counter * perf code: 0x02 - * Available model: SLM,AMT,NHM,WSM,SNB,IVB,HSW,BDW - * SKL,KNL,GLM + * Available model: SLM,AMT,NHM,WSM,SNB,IVB,HSW,BDW, + * SKL,KNL,GLM,CNL * Scope: Core * MSR_CORE_C7_RESIDENCY: CORE C7 Residency Counter * perf code: 0x03 - * Available model: SNB,IVB,HSW,BDW,SKL + * Available model: SNB,IVB,HSW,BDW,SKL,CNL * Scope: Core * MSR_PKG_C2_RESIDENCY: Package C2 Residency Counter. * perf code: 0x00 - * Available model: SNB,IVB,HSW,BDW,SKL,KNL,GLM + * Available model: SNB,IVB,HSW,BDW,SKL,KNL,GLM,CNL * Scope: Package (physical package) * MSR_PKG_C3_RESIDENCY: Package C3 Residency Counter. * perf code: 0x01 - * Available model: NHM,WSM,SNB,IVB,HSW,BDW,SKL,KNL - * GLM + * Available model: NHM,WSM,SNB,IVB,HSW,BDW,SKL,KNL, + * GLM,CNL * Scope: Package (physical package) * MSR_PKG_C6_RESIDENCY: Package C6 Residency Counter. * perf code: 0x02 * Available model: SLM,AMT,NHM,WSM,SNB,IVB,HSW,BDW - * SKL,KNL,GLM + * SKL,KNL,GLM,CNL * Scope: Package (physical package) * MSR_PKG_C7_RESIDENCY: Package C7 Residency Counter. * perf code: 0x03 - * Available model: NHM,WSM,SNB,IVB,HSW,BDW,SKL + * Available model: NHM,WSM,SNB,IVB,HSW,BDW,SKL,CNL * Scope: Package (physical package) * MSR_PKG_C8_RESIDENCY: Package C8 Residency Counter. * perf code: 0x04 - * Available model: HSW ULT only + * Available model: HSW ULT,CNL * Scope: Package (physical package) * MSR_PKG_C9_RESIDENCY: Package C9 Residency Counter. * perf code: 0x05 - * Available model: HSW ULT only + * Available model: HSW ULT,CNL * Scope: Package (physical package) * MSR_PKG_C10_RESIDENCY: Package C10 Residency Counter. * perf code: 0x06 - * Available model: HSW ULT, GLM + * Available model: HSW ULT,GLM,CNL * Scope: Package (physical package) * */ @@ -486,6 +487,21 @@ static const struct cstate_model hswult_cstates __initconst = { BIT(PERF_CSTATE_PKG_C10_RES), }; +static const struct cstate_model cnl_cstates __initconst = { + .core_events = BIT(PERF_CSTATE_CORE_C1_RES) | + BIT(PERF_CSTATE_CORE_C3_RES) | + BIT(PERF_CSTATE_CORE_C6_RES) | + BIT(PERF_CSTATE_CORE_C7_RES), + + .pkg_events = BIT(PERF_CSTATE_PKG_C2_RES) | + BIT(PERF_CSTATE_PKG_C3_RES) | + BIT(PERF_CSTATE_PKG_C6_RES) | + BIT(PERF_CSTATE_PKG_C7_RES) | + BIT(PERF_CSTATE_PKG_C8_RES) | + BIT(PERF_CSTATE_PKG_C9_RES) | + BIT(PERF_CSTATE_PKG_C10_RES), +}; + static const struct cstate_model slm_cstates __initconst = { .core_events = BIT(PERF_CSTATE_CORE_C1_RES) | BIT(PERF_CSTATE_CORE_C6_RES), @@ -557,6 +573,8 @@ static const struct x86_cpu_id intel_cstates_match[] __initconst = { X86_CSTATES_MODEL(INTEL_FAM6_KABYLAKE_MOBILE, snb_cstates), X86_CSTATES_MODEL(INTEL_FAM6_KABYLAKE_DESKTOP, snb_cstates), + X86_CSTATES_MODEL(INTEL_FAM6_CANNONLAKE_MOBILE, cnl_cstates), + X86_CSTATES_MODEL(INTEL_FAM6_XEON_PHI_KNL, knl_cstates), X86_CSTATES_MODEL(INTEL_FAM6_XEON_PHI_KNM, knl_cstates), -- 2.13.5 ^ permalink raw reply related [flat|nested] 13+ messages in thread
* Re: [PATCH 3/3] perf/x86/intel: Enable C-state residency events for Cannon Lake 2018-03-09 12:15 ` [PATCH 3/3] perf/x86/intel: Enable C-state residency events for Cannon Lake Harry Pan @ 2018-03-19 23:09 ` Benson Leung 2018-03-19 23:12 ` Puthikorn Voravootivat 2018-03-31 10:19 ` [tip:perf/core] " tip-bot for Harry Pan 1 sibling, 1 reply; 13+ messages in thread From: Benson Leung @ 2018-03-19 23:09 UTC (permalink / raw) To: Harry Pan, LKML Cc: gs0622, tglx, mingo, hpa, x86, Kan.liang, puthik, Benson Leung, bleung [-- Attachment #1.1: Type: text/plain, Size: 5051 bytes --] Hi Harry, On 03/09/2018 04:15 AM, Harry Pan wrote: > Cannon Lake supports C1/C3/C6/C7, PC2/PC3/PC6/PC7/PC8/PC9/PC10 > state residency counters, this patch enables those counters. > > The MSR information is based on Intel Software Developers' Manual, > Vol. 4, Order No. 335592. > > Signed-off-by: Harry Pan <harry.pan@intel.com> Reviewed-by: Benson Leung <bleung@chromium.org> > --- > arch/x86/events/intel/cstate.c | 44 +++++++++++++++++++++++++++++------------- > 1 file changed, 31 insertions(+), 13 deletions(-) > > diff --git a/arch/x86/events/intel/cstate.c b/arch/x86/events/intel/cstate.c > index 72db0664a53d..9aca448bb8e6 100644 > --- a/arch/x86/events/intel/cstate.c > +++ b/arch/x86/events/intel/cstate.c > @@ -40,50 +40,51 @@ > * Model specific counters: > * MSR_CORE_C1_RES: CORE C1 Residency Counter > * perf code: 0x00 > - * Available model: SLM,AMT,GLM > + * Available model: SLM,AMT,GLM,CNL > * Scope: Core (each processor core has a MSR) > * MSR_CORE_C3_RESIDENCY: CORE C3 Residency Counter > * perf code: 0x01 > - * Available model: NHM,WSM,SNB,IVB,HSW,BDW,SKL,GLM > + * Available model: NHM,WSM,SNB,IVB,HSW,BDW,SKL,GLM, > + CNL > * Scope: Core > * MSR_CORE_C6_RESIDENCY: CORE C6 Residency Counter > * perf code: 0x02 > - * Available model: SLM,AMT,NHM,WSM,SNB,IVB,HSW,BDW > - * SKL,KNL,GLM > + * Available model: SLM,AMT,NHM,WSM,SNB,IVB,HSW,BDW, > + * SKL,KNL,GLM,CNL > * Scope: Core > * MSR_CORE_C7_RESIDENCY: CORE C7 Residency Counter > * perf code: 0x03 > - * Available model: SNB,IVB,HSW,BDW,SKL > + * Available model: SNB,IVB,HSW,BDW,SKL,CNL > * Scope: Core > * MSR_PKG_C2_RESIDENCY: Package C2 Residency Counter. > * perf code: 0x00 > - * Available model: SNB,IVB,HSW,BDW,SKL,KNL,GLM > + * Available model: SNB,IVB,HSW,BDW,SKL,KNL,GLM,CNL > * Scope: Package (physical package) > * MSR_PKG_C3_RESIDENCY: Package C3 Residency Counter. > * perf code: 0x01 > - * Available model: NHM,WSM,SNB,IVB,HSW,BDW,SKL,KNL > - * GLM > + * Available model: NHM,WSM,SNB,IVB,HSW,BDW,SKL,KNL, > + * GLM,CNL > * Scope: Package (physical package) > * MSR_PKG_C6_RESIDENCY: Package C6 Residency Counter. > * perf code: 0x02 > * Available model: SLM,AMT,NHM,WSM,SNB,IVB,HSW,BDW > - * SKL,KNL,GLM > + * SKL,KNL,GLM,CNL > * Scope: Package (physical package) > * MSR_PKG_C7_RESIDENCY: Package C7 Residency Counter. > * perf code: 0x03 > - * Available model: NHM,WSM,SNB,IVB,HSW,BDW,SKL > + * Available model: NHM,WSM,SNB,IVB,HSW,BDW,SKL,CNL > * Scope: Package (physical package) > * MSR_PKG_C8_RESIDENCY: Package C8 Residency Counter. > * perf code: 0x04 > - * Available model: HSW ULT only > + * Available model: HSW ULT,CNL > * Scope: Package (physical package) > * MSR_PKG_C9_RESIDENCY: Package C9 Residency Counter. > * perf code: 0x05 > - * Available model: HSW ULT only > + * Available model: HSW ULT,CNL > * Scope: Package (physical package) > * MSR_PKG_C10_RESIDENCY: Package C10 Residency Counter. > * perf code: 0x06 > - * Available model: HSW ULT, GLM > + * Available model: HSW ULT,GLM,CNL > * Scope: Package (physical package) > * > */ > @@ -486,6 +487,21 @@ static const struct cstate_model hswult_cstates __initconst = { > BIT(PERF_CSTATE_PKG_C10_RES), > }; > > +static const struct cstate_model cnl_cstates __initconst = { > + .core_events = BIT(PERF_CSTATE_CORE_C1_RES) | > + BIT(PERF_CSTATE_CORE_C3_RES) | > + BIT(PERF_CSTATE_CORE_C6_RES) | > + BIT(PERF_CSTATE_CORE_C7_RES), > + > + .pkg_events = BIT(PERF_CSTATE_PKG_C2_RES) | > + BIT(PERF_CSTATE_PKG_C3_RES) | > + BIT(PERF_CSTATE_PKG_C6_RES) | > + BIT(PERF_CSTATE_PKG_C7_RES) | > + BIT(PERF_CSTATE_PKG_C8_RES) | > + BIT(PERF_CSTATE_PKG_C9_RES) | > + BIT(PERF_CSTATE_PKG_C10_RES), > +}; > + > static const struct cstate_model slm_cstates __initconst = { > .core_events = BIT(PERF_CSTATE_CORE_C1_RES) | > BIT(PERF_CSTATE_CORE_C6_RES), > @@ -557,6 +573,8 @@ static const struct x86_cpu_id intel_cstates_match[] __initconst = { > X86_CSTATES_MODEL(INTEL_FAM6_KABYLAKE_MOBILE, snb_cstates), > X86_CSTATES_MODEL(INTEL_FAM6_KABYLAKE_DESKTOP, snb_cstates), > > + X86_CSTATES_MODEL(INTEL_FAM6_CANNONLAKE_MOBILE, cnl_cstates), > + > X86_CSTATES_MODEL(INTEL_FAM6_XEON_PHI_KNL, knl_cstates), > X86_CSTATES_MODEL(INTEL_FAM6_XEON_PHI_KNM, knl_cstates), > > Thank you! -- Benson Leung Staff Software Engineer Chrome OS Kernel Google Inc. bleung@google.com Chromium OS Project bleung@chromium.org [-- Attachment #2: OpenPGP digital signature --] [-- Type: application/pgp-signature, Size: 833 bytes --] ^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH 3/3] perf/x86/intel: Enable C-state residency events for Cannon Lake 2018-03-19 23:09 ` Benson Leung @ 2018-03-19 23:12 ` Puthikorn Voravootivat 0 siblings, 0 replies; 13+ messages in thread From: Puthikorn Voravootivat @ 2018-03-19 23:12 UTC (permalink / raw) To: Benson Leung Cc: harry.pan, linux-kernel, gs0622, tglx, mingo, hpa, x86, Kan.liang, bleung On Mon, Mar 19, 2018 at 4:09 PM Benson Leung <bleung@google.com> wrote: > Hi Harry, > On 03/09/2018 04:15 AM, Harry Pan wrote: > > Cannon Lake supports C1/C3/C6/C7, PC2/PC3/PC6/PC7/PC8/PC9/PC10 > > state residency counters, this patch enables those counters. > > > > The MSR information is based on Intel Software Developers' Manual, > > Vol. 4, Order No. 335592. > > > > Signed-off-by: Harry Pan <harry.pan@intel.com> > Reviewed-by: Benson Leung <bleung@chromium.org> Tested-by: Puthikorn Voravootivat <puthik@chromium.org> > > --- > > arch/x86/events/intel/cstate.c | 44 +++++++++++++++++++++++++++++------------- > > 1 file changed, 31 insertions(+), 13 deletions(-) > > > > diff --git a/arch/x86/events/intel/cstate.c b/arch/x86/events/intel/cstate.c > > index 72db0664a53d..9aca448bb8e6 100644 > > --- a/arch/x86/events/intel/cstate.c > > +++ b/arch/x86/events/intel/cstate.c > > @@ -40,50 +40,51 @@ > > * Model specific counters: > > * MSR_CORE_C1_RES: CORE C1 Residency Counter > > * perf code: 0x00 > > - * Available model: SLM,AMT,GLM > > + * Available model: SLM,AMT,GLM,CNL > > * Scope: Core (each processor core has a MSR) > > * MSR_CORE_C3_RESIDENCY: CORE C3 Residency Counter > > * perf code: 0x01 > > - * Available model: NHM,WSM,SNB,IVB,HSW,BDW,SKL,GLM > > + * Available model: NHM,WSM,SNB,IVB,HSW,BDW,SKL,GLM, > > + CNL > > * Scope: Core > > * MSR_CORE_C6_RESIDENCY: CORE C6 Residency Counter > > * perf code: 0x02 > > - * Available model: SLM,AMT,NHM,WSM,SNB,IVB,HSW,BDW > > - * SKL,KNL,GLM > > + * Available model: SLM,AMT,NHM,WSM,SNB,IVB,HSW,BDW, > > + * SKL,KNL,GLM,CNL > > * Scope: Core > > * MSR_CORE_C7_RESIDENCY: CORE C7 Residency Counter > > * perf code: 0x03 > > - * Available model: SNB,IVB,HSW,BDW,SKL > > + * Available model: SNB,IVB,HSW,BDW,SKL,CNL > > * Scope: Core > > * MSR_PKG_C2_RESIDENCY: Package C2 Residency Counter. > > * perf code: 0x00 > > - * Available model: SNB,IVB,HSW,BDW,SKL,KNL,GLM > > + * Available model: SNB,IVB,HSW,BDW,SKL,KNL,GLM,CNL > > * Scope: Package (physical package) > > * MSR_PKG_C3_RESIDENCY: Package C3 Residency Counter. > > * perf code: 0x01 > > - * Available model: NHM,WSM,SNB,IVB,HSW,BDW,SKL,KNL > > - * GLM > > + * Available model: NHM,WSM,SNB,IVB,HSW,BDW,SKL,KNL, > > + * GLM,CNL > > * Scope: Package (physical package) > > * MSR_PKG_C6_RESIDENCY: Package C6 Residency Counter. > > * perf code: 0x02 > > * Available model: SLM,AMT,NHM,WSM,SNB,IVB,HSW,BDW > > - * SKL,KNL,GLM > > + * SKL,KNL,GLM,CNL > > * Scope: Package (physical package) > > * MSR_PKG_C7_RESIDENCY: Package C7 Residency Counter. > > * perf code: 0x03 > > - * Available model: NHM,WSM,SNB,IVB,HSW,BDW,SKL > > + * Available model: NHM,WSM,SNB,IVB,HSW,BDW,SKL,CNL > > * Scope: Package (physical package) > > * MSR_PKG_C8_RESIDENCY: Package C8 Residency Counter. > > * perf code: 0x04 > > - * Available model: HSW ULT only > > + * Available model: HSW ULT,CNL > > * Scope: Package (physical package) > > * MSR_PKG_C9_RESIDENCY: Package C9 Residency Counter. > > * perf code: 0x05 > > - * Available model: HSW ULT only > > + * Available model: HSW ULT,CNL > > * Scope: Package (physical package) > > * MSR_PKG_C10_RESIDENCY: Package C10 Residency Counter. > > * perf code: 0x06 > > - * Available model: HSW ULT, GLM > > + * Available model: HSW ULT,GLM,CNL > > * Scope: Package (physical package) > > * > > */ > > @@ -486,6 +487,21 @@ static const struct cstate_model hswult_cstates __initconst = { > > BIT(PERF_CSTATE_PKG_C10_RES), > > }; > > > > +static const struct cstate_model cnl_cstates __initconst = { > > + .core_events = BIT(PERF_CSTATE_CORE_C1_RES) | > > + BIT(PERF_CSTATE_CORE_C3_RES) | > > + BIT(PERF_CSTATE_CORE_C6_RES) | > > + BIT(PERF_CSTATE_CORE_C7_RES), > > + > > + .pkg_events = BIT(PERF_CSTATE_PKG_C2_RES) | > > + BIT(PERF_CSTATE_PKG_C3_RES) | > > + BIT(PERF_CSTATE_PKG_C6_RES) | > > + BIT(PERF_CSTATE_PKG_C7_RES) | > > + BIT(PERF_CSTATE_PKG_C8_RES) | > > + BIT(PERF_CSTATE_PKG_C9_RES) | > > + BIT(PERF_CSTATE_PKG_C10_RES), > > +}; > > + > > static const struct cstate_model slm_cstates __initconst = { > > .core_events = BIT(PERF_CSTATE_CORE_C1_RES) | > > BIT(PERF_CSTATE_CORE_C6_RES), > > @@ -557,6 +573,8 @@ static const struct x86_cpu_id intel_cstates_match[] __initconst = { > > X86_CSTATES_MODEL(INTEL_FAM6_KABYLAKE_MOBILE, snb_cstates), > > X86_CSTATES_MODEL(INTEL_FAM6_KABYLAKE_DESKTOP, snb_cstates), > > > > + X86_CSTATES_MODEL(INTEL_FAM6_CANNONLAKE_MOBILE, cnl_cstates), > > + > > X86_CSTATES_MODEL(INTEL_FAM6_XEON_PHI_KNL, knl_cstates), > > X86_CSTATES_MODEL(INTEL_FAM6_XEON_PHI_KNM, knl_cstates), > > > > > Thank you! > -- > Benson Leung > Staff Software Engineer > Chrome OS Kernel > Google Inc. > bleung@google.com > Chromium OS Project > bleung@chromium.org ^ permalink raw reply [flat|nested] 13+ messages in thread
* [tip:perf/core] perf/x86/intel: Enable C-state residency events for Cannon Lake 2018-03-09 12:15 ` [PATCH 3/3] perf/x86/intel: Enable C-state residency events for Cannon Lake Harry Pan 2018-03-19 23:09 ` Benson Leung @ 2018-03-31 10:19 ` tip-bot for Harry Pan 1 sibling, 0 replies; 13+ messages in thread From: tip-bot for Harry Pan @ 2018-03-31 10:19 UTC (permalink / raw) To: linux-tip-commits Cc: torvalds, linux-kernel, acme, bleung, peterz, tglx, mingo, puthik, alexander.shishkin, jolsa, eranian, vincent.weaver, harry.pan, hpa Commit-ID: 1159e09476536250c2a0173d4298d15114df7a89 Gitweb: https://git.kernel.org/tip/1159e09476536250c2a0173d4298d15114df7a89 Author: Harry Pan <harry.pan@intel.com> AuthorDate: Fri, 9 Mar 2018 20:15:48 +0800 Committer: Ingo Molnar <mingo@kernel.org> CommitDate: Sat, 31 Mar 2018 11:28:36 +0200 perf/x86/intel: Enable C-state residency events for Cannon Lake Cannon Lake supports C1/C3/C6/C7, PC2/PC3/PC6/PC7/PC8/PC9/PC10 state residency counters, this patch enables those counters. ( The MSR information is based on Intel Software Developers' Manual, Vol. 4, Order No. 335592. ) Tested-by: Puthikorn Voravootivat <puthik@chromium.org> Signed-off-by: Harry Pan <harry.pan@intel.com> Reviewed-by: Benson Leung <bleung@chromium.org> Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com> Cc: Arnaldo Carvalho de Melo <acme@redhat.com> Cc: Jiri Olsa <jolsa@redhat.com> Cc: Kan.liang@intel.com Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Stephane Eranian <eranian@google.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Vince Weaver <vincent.weaver@maine.edu> Cc: gs0622@gmail.com Link: http://lkml.kernel.org/r/20180309121549.630-3-harry.pan@intel.com Signed-off-by: Ingo Molnar <mingo@kernel.org> --- arch/x86/events/intel/cstate.c | 44 +++++++++++++++++++++++++++++------------- 1 file changed, 31 insertions(+), 13 deletions(-) diff --git a/arch/x86/events/intel/cstate.c b/arch/x86/events/intel/cstate.c index 72db0664a53d..9aca448bb8e6 100644 --- a/arch/x86/events/intel/cstate.c +++ b/arch/x86/events/intel/cstate.c @@ -40,50 +40,51 @@ * Model specific counters: * MSR_CORE_C1_RES: CORE C1 Residency Counter * perf code: 0x00 - * Available model: SLM,AMT,GLM + * Available model: SLM,AMT,GLM,CNL * Scope: Core (each processor core has a MSR) * MSR_CORE_C3_RESIDENCY: CORE C3 Residency Counter * perf code: 0x01 - * Available model: NHM,WSM,SNB,IVB,HSW,BDW,SKL,GLM + * Available model: NHM,WSM,SNB,IVB,HSW,BDW,SKL,GLM, + CNL * Scope: Core * MSR_CORE_C6_RESIDENCY: CORE C6 Residency Counter * perf code: 0x02 - * Available model: SLM,AMT,NHM,WSM,SNB,IVB,HSW,BDW - * SKL,KNL,GLM + * Available model: SLM,AMT,NHM,WSM,SNB,IVB,HSW,BDW, + * SKL,KNL,GLM,CNL * Scope: Core * MSR_CORE_C7_RESIDENCY: CORE C7 Residency Counter * perf code: 0x03 - * Available model: SNB,IVB,HSW,BDW,SKL + * Available model: SNB,IVB,HSW,BDW,SKL,CNL * Scope: Core * MSR_PKG_C2_RESIDENCY: Package C2 Residency Counter. * perf code: 0x00 - * Available model: SNB,IVB,HSW,BDW,SKL,KNL,GLM + * Available model: SNB,IVB,HSW,BDW,SKL,KNL,GLM,CNL * Scope: Package (physical package) * MSR_PKG_C3_RESIDENCY: Package C3 Residency Counter. * perf code: 0x01 - * Available model: NHM,WSM,SNB,IVB,HSW,BDW,SKL,KNL - * GLM + * Available model: NHM,WSM,SNB,IVB,HSW,BDW,SKL,KNL, + * GLM,CNL * Scope: Package (physical package) * MSR_PKG_C6_RESIDENCY: Package C6 Residency Counter. * perf code: 0x02 * Available model: SLM,AMT,NHM,WSM,SNB,IVB,HSW,BDW - * SKL,KNL,GLM + * SKL,KNL,GLM,CNL * Scope: Package (physical package) * MSR_PKG_C7_RESIDENCY: Package C7 Residency Counter. * perf code: 0x03 - * Available model: NHM,WSM,SNB,IVB,HSW,BDW,SKL + * Available model: NHM,WSM,SNB,IVB,HSW,BDW,SKL,CNL * Scope: Package (physical package) * MSR_PKG_C8_RESIDENCY: Package C8 Residency Counter. * perf code: 0x04 - * Available model: HSW ULT only + * Available model: HSW ULT,CNL * Scope: Package (physical package) * MSR_PKG_C9_RESIDENCY: Package C9 Residency Counter. * perf code: 0x05 - * Available model: HSW ULT only + * Available model: HSW ULT,CNL * Scope: Package (physical package) * MSR_PKG_C10_RESIDENCY: Package C10 Residency Counter. * perf code: 0x06 - * Available model: HSW ULT, GLM + * Available model: HSW ULT,GLM,CNL * Scope: Package (physical package) * */ @@ -486,6 +487,21 @@ static const struct cstate_model hswult_cstates __initconst = { BIT(PERF_CSTATE_PKG_C10_RES), }; +static const struct cstate_model cnl_cstates __initconst = { + .core_events = BIT(PERF_CSTATE_CORE_C1_RES) | + BIT(PERF_CSTATE_CORE_C3_RES) | + BIT(PERF_CSTATE_CORE_C6_RES) | + BIT(PERF_CSTATE_CORE_C7_RES), + + .pkg_events = BIT(PERF_CSTATE_PKG_C2_RES) | + BIT(PERF_CSTATE_PKG_C3_RES) | + BIT(PERF_CSTATE_PKG_C6_RES) | + BIT(PERF_CSTATE_PKG_C7_RES) | + BIT(PERF_CSTATE_PKG_C8_RES) | + BIT(PERF_CSTATE_PKG_C9_RES) | + BIT(PERF_CSTATE_PKG_C10_RES), +}; + static const struct cstate_model slm_cstates __initconst = { .core_events = BIT(PERF_CSTATE_CORE_C1_RES) | BIT(PERF_CSTATE_CORE_C6_RES), @@ -557,6 +573,8 @@ static const struct x86_cpu_id intel_cstates_match[] __initconst = { X86_CSTATES_MODEL(INTEL_FAM6_KABYLAKE_MOBILE, snb_cstates), X86_CSTATES_MODEL(INTEL_FAM6_KABYLAKE_DESKTOP, snb_cstates), + X86_CSTATES_MODEL(INTEL_FAM6_CANNONLAKE_MOBILE, cnl_cstates), + X86_CSTATES_MODEL(INTEL_FAM6_XEON_PHI_KNL, knl_cstates), X86_CSTATES_MODEL(INTEL_FAM6_XEON_PHI_KNM, knl_cstates), ^ permalink raw reply related [flat|nested] 13+ messages in thread
* Re: [PATCH 1/3] powercap: intel_rapl: Add support for Cannon Lake 2018-03-09 12:15 [PATCH 1/3] powercap: intel_rapl: Add support for Cannon Lake Harry Pan 2018-03-09 12:15 ` [PATCH 2/3] perf/x86/intel: Add Cannon Lake support of RAPL profiling Harry Pan 2018-03-09 12:15 ` [PATCH 3/3] perf/x86/intel: Enable C-state residency events for Cannon Lake Harry Pan @ 2018-03-19 23:03 ` Benson Leung 2018-03-19 23:14 ` Benson Leung 2018-03-20 9:58 ` Rafael J. Wysocki 4 siblings, 0 replies; 13+ messages in thread From: Benson Leung @ 2018-03-19 23:03 UTC (permalink / raw) To: Harry Pan, LKML; +Cc: gs0622, rjw, linux-pm [-- Attachment #1.1: Type: text/plain, Size: 1181 bytes --] Hi Harry, On 03/09/2018 04:15 AM, Harry Pan wrote: > Cannon Lake microarchitecture is similar to Kaby Lake in terms of > RAPL, this patch enables CNL RAPL support. > > Signed-off-by: Harry Pan <harry.pan@intel.com> Reviewed-by: Benson Leung <bleung@chromium.org> > --- > drivers/powercap/intel_rapl.c | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/drivers/powercap/intel_rapl.c b/drivers/powercap/intel_rapl.c > index 35636e1d8a3d..295d8dcba48c 100644 > --- a/drivers/powercap/intel_rapl.c > +++ b/drivers/powercap/intel_rapl.c > @@ -1162,6 +1162,7 @@ static const struct x86_cpu_id rapl_ids[] __initconst = { > RAPL_CPU(INTEL_FAM6_SKYLAKE_X, rapl_defaults_hsw_server), > RAPL_CPU(INTEL_FAM6_KABYLAKE_MOBILE, rapl_defaults_core), > RAPL_CPU(INTEL_FAM6_KABYLAKE_DESKTOP, rapl_defaults_core), > + RAPL_CPU(INTEL_FAM6_CANNONLAKE_MOBILE, rapl_defaults_core), > > RAPL_CPU(INTEL_FAM6_ATOM_SILVERMONT1, rapl_defaults_byt), > RAPL_CPU(INTEL_FAM6_ATOM_AIRMONT, rapl_defaults_cht), > Thanks! -- Benson Leung Staff Software Engineer Chrome OS Kernel Google Inc. bleung@google.com Chromium OS Project bleung@chromium.org [-- Attachment #2: OpenPGP digital signature --] [-- Type: application/pgp-signature, Size: 833 bytes --] ^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH 1/3] powercap: intel_rapl: Add support for Cannon Lake 2018-03-09 12:15 [PATCH 1/3] powercap: intel_rapl: Add support for Cannon Lake Harry Pan ` (2 preceding siblings ...) 2018-03-19 23:03 ` [PATCH 1/3] powercap: intel_rapl: Add support " Benson Leung @ 2018-03-19 23:14 ` Benson Leung 2018-03-19 23:19 ` Puthikorn Voravootivat 2018-03-20 9:58 ` Rafael J. Wysocki 4 siblings, 1 reply; 13+ messages in thread From: Benson Leung @ 2018-03-19 23:14 UTC (permalink / raw) To: Harry Pan, LKML Cc: gs0622, rjw, linux-pm, puthik, Benson Leung, 'Benson Leung' [-- Attachment #1.1: Type: text/plain, Size: 1128 bytes --] +puthik@google.com On 03/09/2018 04:15 AM, Harry Pan wrote: > Cannon Lake microarchitecture is similar to Kaby Lake in terms of > RAPL, this patch enables CNL RAPL support. > > Signed-off-by: Harry Pan <harry.pan@intel.com> > --- > drivers/powercap/intel_rapl.c | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/drivers/powercap/intel_rapl.c b/drivers/powercap/intel_rapl.c > index 35636e1d8a3d..295d8dcba48c 100644 > --- a/drivers/powercap/intel_rapl.c > +++ b/drivers/powercap/intel_rapl.c > @@ -1162,6 +1162,7 @@ static const struct x86_cpu_id rapl_ids[] __initconst = { > RAPL_CPU(INTEL_FAM6_SKYLAKE_X, rapl_defaults_hsw_server), > RAPL_CPU(INTEL_FAM6_KABYLAKE_MOBILE, rapl_defaults_core), > RAPL_CPU(INTEL_FAM6_KABYLAKE_DESKTOP, rapl_defaults_core), > + RAPL_CPU(INTEL_FAM6_CANNONLAKE_MOBILE, rapl_defaults_core), > > RAPL_CPU(INTEL_FAM6_ATOM_SILVERMONT1, rapl_defaults_byt), > RAPL_CPU(INTEL_FAM6_ATOM_AIRMONT, rapl_defaults_cht), > -- Benson Leung Staff Software Engineer Chrome OS Kernel Google Inc. bleung@google.com Chromium OS Project bleung@chromium.org [-- Attachment #2: OpenPGP digital signature --] [-- Type: application/pgp-signature, Size: 833 bytes --] ^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH 1/3] powercap: intel_rapl: Add support for Cannon Lake 2018-03-19 23:14 ` Benson Leung @ 2018-03-19 23:19 ` Puthikorn Voravootivat 0 siblings, 0 replies; 13+ messages in thread From: Puthikorn Voravootivat @ 2018-03-19 23:19 UTC (permalink / raw) To: harry.pan; +Cc: linux-kernel, gs0622, rjw, linux-pm, Benson Leung, bleung On Mon, Mar 19, 2018 at 4:14 PM Benson Leung <bleung@google.com> wrote: > +puthik@google.com > On 03/09/2018 04:15 AM, Harry Pan wrote: > > Cannon Lake microarchitecture is similar to Kaby Lake in terms of > > RAPL, this patch enables CNL RAPL support. > > > > Signed-off-by: Harry Pan <harry.pan@intel.com> Tested-by: Puthikorn Voravootivat <puthik@chromium.org> > > --- > > drivers/powercap/intel_rapl.c | 1 + > > 1 file changed, 1 insertion(+) > > > > diff --git a/drivers/powercap/intel_rapl.c b/drivers/powercap/intel_rapl.c > > index 35636e1d8a3d..295d8dcba48c 100644 > > --- a/drivers/powercap/intel_rapl.c > > +++ b/drivers/powercap/intel_rapl.c > > @@ -1162,6 +1162,7 @@ static const struct x86_cpu_id rapl_ids[] __initconst = { > > RAPL_CPU(INTEL_FAM6_SKYLAKE_X, rapl_defaults_hsw_server), > > RAPL_CPU(INTEL_FAM6_KABYLAKE_MOBILE, rapl_defaults_core), > > RAPL_CPU(INTEL_FAM6_KABYLAKE_DESKTOP, rapl_defaults_core), > > + RAPL_CPU(INTEL_FAM6_CANNONLAKE_MOBILE, rapl_defaults_core), > > > > RAPL_CPU(INTEL_FAM6_ATOM_SILVERMONT1, rapl_defaults_byt), > > RAPL_CPU(INTEL_FAM6_ATOM_AIRMONT, rapl_defaults_cht), > > > -- > Benson Leung > Staff Software Engineer > Chrome OS Kernel > Google Inc. > bleung@google.com > Chromium OS Project > bleung@chromium.org ^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH 1/3] powercap: intel_rapl: Add support for Cannon Lake 2018-03-09 12:15 [PATCH 1/3] powercap: intel_rapl: Add support for Cannon Lake Harry Pan ` (3 preceding siblings ...) 2018-03-19 23:14 ` Benson Leung @ 2018-03-20 9:58 ` Rafael J. Wysocki 4 siblings, 0 replies; 13+ messages in thread From: Rafael J. Wysocki @ 2018-03-20 9:58 UTC (permalink / raw) To: Harry Pan; +Cc: LKML, gs0622, Rafael J. Wysocki, Linux PM, Joe Konno On Fri, Mar 9, 2018 at 1:15 PM, Harry Pan <harry.pan@intel.com> wrote: > Cannon Lake microarchitecture is similar to Kaby Lake in terms of > RAPL, this patch enables CNL RAPL support. > > Signed-off-by: Harry Pan <harry.pan@intel.com> I have applied an analogous patch from Joe Konno that was posted earlier. Thanks! > --- > drivers/powercap/intel_rapl.c | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/drivers/powercap/intel_rapl.c b/drivers/powercap/intel_rapl.c > index 35636e1d8a3d..295d8dcba48c 100644 > --- a/drivers/powercap/intel_rapl.c > +++ b/drivers/powercap/intel_rapl.c > @@ -1162,6 +1162,7 @@ static const struct x86_cpu_id rapl_ids[] __initconst = { > RAPL_CPU(INTEL_FAM6_SKYLAKE_X, rapl_defaults_hsw_server), > RAPL_CPU(INTEL_FAM6_KABYLAKE_MOBILE, rapl_defaults_core), > RAPL_CPU(INTEL_FAM6_KABYLAKE_DESKTOP, rapl_defaults_core), > + RAPL_CPU(INTEL_FAM6_CANNONLAKE_MOBILE, rapl_defaults_core), > > RAPL_CPU(INTEL_FAM6_ATOM_SILVERMONT1, rapl_defaults_byt), > RAPL_CPU(INTEL_FAM6_ATOM_AIRMONT, rapl_defaults_cht), > -- > 2.13.5 > ^ permalink raw reply [flat|nested] 13+ messages in thread
end of thread, other threads:[~2018-03-31 10:20 UTC | newest] Thread overview: 13+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2018-03-09 12:15 [PATCH 1/3] powercap: intel_rapl: Add support for Cannon Lake Harry Pan 2018-03-09 12:15 ` [PATCH 2/3] perf/x86/intel: Add Cannon Lake support of RAPL profiling Harry Pan 2018-03-19 23:05 ` Benson Leung 2018-03-19 23:11 ` Puthikorn Voravootivat 2018-03-31 10:19 ` [tip:perf/core] perf/x86/intel: Add Cannon Lake support for " tip-bot for Harry Pan 2018-03-09 12:15 ` [PATCH 3/3] perf/x86/intel: Enable C-state residency events for Cannon Lake Harry Pan 2018-03-19 23:09 ` Benson Leung 2018-03-19 23:12 ` Puthikorn Voravootivat 2018-03-31 10:19 ` [tip:perf/core] " tip-bot for Harry Pan 2018-03-19 23:03 ` [PATCH 1/3] powercap: intel_rapl: Add support " Benson Leung 2018-03-19 23:14 ` Benson Leung 2018-03-19 23:19 ` Puthikorn Voravootivat 2018-03-20 9:58 ` Rafael J. Wysocki
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