* [U-Boot] arm socfpga: Revert "spi: cadence_qspi_apb: Support 32 bit AHB address"
@ 2017-12-03 15:59 Frank Mori Hess
2017-12-04 4:15 ` Vignesh R
0 siblings, 1 reply; 12+ messages in thread
From: Frank Mori Hess @ 2017-12-03 15:59 UTC (permalink / raw)
To: u-boot
This reverts commit dac3bf20fb2c9b03476be0d73db620f62ab3cee1.
My u-boot spl crashes in a loop when I boot off a
cadence qspi flash. I narrowed it down to the changes from commit
dac3bf20fb2c9b03476be0d73db620f62ab3cee1 which removes
CQSPI_INDIRECTTRIGGER_ADDR_MASK. Restoring the mask allows the spl to
successfully load the main u-boot. My board is an Altera HPS cyclone
V socfpga. It has an ahb base address of 0xffa00000 and for some
reason, without the CQSPI_INDIRECTTRIGGER_ADDR_MASK the board reboots
when cadence_qspi_apb_indirect_read_execute tries to read from the ahb
base address. I'm was using version 2016.11 of u-boot.
Signed-off-by: Frank Mori Hess <fmh6jj@gmail.com>
---
drivers/spi/cadence_qspi_apb.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c
index e02f2217f4..b300f36607 100644
--- a/drivers/spi/cadence_qspi_apb.c
+++ b/drivers/spi/cadence_qspi_apb.c
@@ -47,6 +47,7 @@
#define CQSPI_INST_TYPE_QUAD 2
#define CQSPI_STIG_DATA_LEN_MAX 8
+#define CQSPI_INDIRECTTRIGGER_ADDR_MASK 0xFFFFF
#define CQSPI_DUMMY_CLKS_PER_BYTE 8
#define CQSPI_DUMMY_BYTES_MAX 4
@@ -560,7 +561,7 @@ int cadence_qspi_apb_indirect_read_setup(struct cadence_spi_platdata *plat,
addr_bytes = cmdlen - 1;
/* Setup the indirect trigger address */
- writel((u32)plat->ahbbase,
+ writel(((u32)plat->ahbbase & CQSPI_INDIRECTTRIGGER_ADDR_MASK),
plat->regbase + CQSPI_REG_INDIRECTTRIGGER);
/* Configure the opcode */
@@ -710,7 +711,7 @@ int cadence_qspi_apb_indirect_write_setup(struct cadence_spi_platdata *plat,
return -EINVAL;
}
/* Setup the indirect trigger address */
- writel((u32)plat->ahbbase,
+ writel(((u32)plat->ahbbase & CQSPI_INDIRECTTRIGGER_ADDR_MASK),
plat->regbase + CQSPI_REG_INDIRECTTRIGGER);
/* Configure the opcode */
--
2.11.0
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [U-Boot] arm socfpga: Revert "spi: cadence_qspi_apb: Support 32 bit AHB address"
2017-12-03 15:59 [U-Boot] arm socfpga: Revert "spi: cadence_qspi_apb: Support 32 bit AHB address" Frank Mori Hess
@ 2017-12-04 4:15 ` Vignesh R
2017-12-04 13:11 ` Frank Mori Hess
0 siblings, 1 reply; 12+ messages in thread
From: Vignesh R @ 2017-12-04 4:15 UTC (permalink / raw)
To: u-boot
On Sunday 03 December 2017 09:29 PM, Frank Mori Hess wrote:
> This reverts commit dac3bf20fb2c9b03476be0d73db620f62ab3cee1.
>
> My u-boot spl crashes in a loop when I boot off a
> cadence qspi flash. I narrowed it down to the changes from commit
> dac3bf20fb2c9b03476be0d73db620f62ab3cee1 which removes
> CQSPI_INDIRECTTRIGGER_ADDR_MASK. Restoring the mask allows the spl to
> successfully load the main u-boot. My board is an Altera HPS cyclone
> V socfpga. It has an ahb base address of 0xffa00000 and for some
> reason, without the CQSPI_INDIRECTTRIGGER_ADDR_MASK the board reboots
> when cadence_qspi_apb_indirect_read_execute tries to read from the ahb
> base address. I'm was using version 2016.11 of u-boot.
This breaks TI platforms where INDIRECTTRIGGER_ADDR is 32bit wide.
Instead please try this patch series which adds cdns,trigger-address DT
property: http://patchwork.ozlabs.org/patch/838589/
Regards
Vignesh
>
> Signed-off-by: Frank Mori Hess <fmh6jj@gmail.com>
> ---
> drivers/spi/cadence_qspi_apb.c | 5 +++--
> 1 file changed, 3 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c
> index e02f2217f4..b300f36607 100644
> --- a/drivers/spi/cadence_qspi_apb.c
> +++ b/drivers/spi/cadence_qspi_apb.c
> @@ -47,6 +47,7 @@
> #define CQSPI_INST_TYPE_QUAD 2
>
> #define CQSPI_STIG_DATA_LEN_MAX 8
> +#define CQSPI_INDIRECTTRIGGER_ADDR_MASK 0xFFFFF
>
> #define CQSPI_DUMMY_CLKS_PER_BYTE 8
> #define CQSPI_DUMMY_BYTES_MAX 4
> @@ -560,7 +561,7 @@ int cadence_qspi_apb_indirect_read_setup(struct cadence_spi_platdata *plat,
> addr_bytes = cmdlen - 1;
>
> /* Setup the indirect trigger address */
> - writel((u32)plat->ahbbase,
> + writel(((u32)plat->ahbbase & CQSPI_INDIRECTTRIGGER_ADDR_MASK),
> plat->regbase + CQSPI_REG_INDIRECTTRIGGER);
>
> /* Configure the opcode */
> @@ -710,7 +711,7 @@ int cadence_qspi_apb_indirect_write_setup(struct cadence_spi_platdata *plat,
> return -EINVAL;
> }
> /* Setup the indirect trigger address */
> - writel((u32)plat->ahbbase,
> + writel(((u32)plat->ahbbase & CQSPI_INDIRECTTRIGGER_ADDR_MASK),
> plat->regbase + CQSPI_REG_INDIRECTTRIGGER);
>
> /* Configure the opcode */
>
^ permalink raw reply [flat|nested] 12+ messages in thread
* [U-Boot] arm socfpga: Revert "spi: cadence_qspi_apb: Support 32 bit AHB address"
2017-12-04 4:15 ` Vignesh R
@ 2017-12-04 13:11 ` Frank Mori Hess
2017-12-04 16:41 ` Vignesh R
0 siblings, 1 reply; 12+ messages in thread
From: Frank Mori Hess @ 2017-12-04 13:11 UTC (permalink / raw)
To: u-boot
Since your commit broke my platform to fix yours, shouldn't it be reverted
and TI platforms use your pending patch queue?
On Dec 3, 2017 23:14, "Vignesh R" <vigneshr@ti.com> wrote:
On Sunday 03 December 2017 09:29 PM, Frank Mori Hess wrote:
> This reverts commit dac3bf20fb2c9b03476be0d73db620f62ab3cee1.
>
> My u-boot spl crashes in a loop when I boot off a
> cadence qspi flash. I narrowed it down to the changes from commit
> dac3bf20fb2c9b03476be0d73db620f62ab3cee1 which removes
> CQSPI_INDIRECTTRIGGER_ADDR_MASK. Restoring the mask allows the spl to
> successfully load the main u-boot. My board is an Altera HPS cyclone
> V socfpga. It has an ahb base address of 0xffa00000 and for some
> reason, without the CQSPI_INDIRECTTRIGGER_ADDR_MASK the board reboots
> when cadence_qspi_apb_indirect_read_execute tries to read from the ahb
> base address. I'm was using version 2016.11 of u-boot.
This breaks TI platforms where INDIRECTTRIGGER_ADDR is 32bit wide.
Instead please try this patch series which adds cdns,trigger-address DT
property: http://patchwork.ozlabs.org/patch/838589/
Regards
Vignesh
>
> Signed-off-by: Frank Mori Hess <fmh6jj@gmail.com>
> ---
> drivers/spi/cadence_qspi_apb.c | 5 +++--
> 1 file changed, 3 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb
.c
> index e02f2217f4..b300f36607 100644
> --- a/drivers/spi/cadence_qspi_apb.c
> +++ b/drivers/spi/cadence_qspi_apb.c
> @@ -47,6 +47,7 @@
> #define CQSPI_INST_TYPE_QUAD 2
>
> #define CQSPI_STIG_DATA_LEN_MAX 8
> +#define CQSPI_INDIRECTTRIGGER_ADDR_MASK 0xFFFFF
>
> #define CQSPI_DUMMY_CLKS_PER_BYTE 8
> #define CQSPI_DUMMY_BYTES_MAX 4
> @@ -560,7 +561,7 @@ int cadence_qspi_apb_indirect_read_setup(struct
cadence_spi_platdata *plat,
> addr_bytes = cmdlen - 1;
>
> /* Setup the indirect trigger address */
> - writel((u32)plat->ahbbase,
> + writel(((u32)plat->ahbbase & CQSPI_INDIRECTTRIGGER_ADDR_MASK),
> plat->regbase + CQSPI_REG_INDIRECTTRIGGER);
>
> /* Configure the opcode */
> @@ -710,7 +711,7 @@ int cadence_qspi_apb_indirect_write_setup(struct
cadence_spi_platdata *plat,
> return -EINVAL;
> }
> /* Setup the indirect trigger address */
> - writel((u32)plat->ahbbase,
> + writel(((u32)plat->ahbbase & CQSPI_INDIRECTTRIGGER_ADDR_MASK),
> plat->regbase + CQSPI_REG_INDIRECTTRIGGER);
>
> /* Configure the opcode */
>
^ permalink raw reply [flat|nested] 12+ messages in thread
* [U-Boot] arm socfpga: Revert "spi: cadence_qspi_apb: Support 32 bit AHB address"
2017-12-04 13:11 ` Frank Mori Hess
@ 2017-12-04 16:41 ` Vignesh R
2017-12-04 17:01 ` Frank Mori Hess
0 siblings, 1 reply; 12+ messages in thread
From: Vignesh R @ 2017-12-04 16:41 UTC (permalink / raw)
To: u-boot
Hi,
On 04-Dec-17 6:41 PM, Frank Mori Hess wrote:
> Since your commit broke my platform to fix yours, shouldn't it be
> reverted and TI platforms use your pending patch queue?
>
Socfpga DT defined ahb base as 0xffa00000 while masked upper bits in the
code, which was confusing. And seems that my patch did work on some
socfgpa board looking at the original commit message.
If the patch is reverted then, applying pending patches alone will not
help because my patch would be needed anyway to make sure we don't mask
31-20 bits on TI platforms.
Therefore instead of reverting and the re-applying, I would recommend to
ping SPI maintainer to get http://patchwork.ozlabs.org/patch/838589/
merged as early as possible.
> On Dec 3, 2017 23:14, "Vignesh R" <vigneshr@ti.com
> <mailto:vigneshr@ti.com>> wrote:
>
>
>
> On Sunday 03 December 2017 09:29 PM, Frank Mori Hess wrote:
> > This reverts commit dac3bf20fb2c9b03476be0d73db620f62ab3cee1.
> >
> > My u-boot spl crashes in a loop when I boot off a
> > cadence qspi flash. I narrowed it down to the changes from commit
> > dac3bf20fb2c9b03476be0d73db620f62ab3cee1 which removes
> > CQSPI_INDIRECTTRIGGER_ADDR_MASK. Restoring the mask allows the spl to
> > successfully load the main u-boot. My board is an Altera HPS cyclone
> > V socfpga. It has an ahb base address of 0xffa00000 and for some
> > reason, without the CQSPI_INDIRECTTRIGGER_ADDR_MASK the board reboots
> > when cadence_qspi_apb_indirect_read_execute tries to read from the ahb
> > base address. I'm was using version 2016.11 of u-boot.
>
> This breaks TI platforms where INDIRECTTRIGGER_ADDR is 32bit wide.
> Instead please try this patch series which adds cdns,trigger-address DT
> property: http://patchwork.ozlabs.org/patch/838589/
> <http://patchwork.ozlabs.org/patch/838589/>
>
> Regards
> Vignesh
>
> >
> > Signed-off-by: Frank Mori Hess <fmh6jj@gmail.com
> <mailto:fmh6jj@gmail.com>>
> > ---
> > drivers/spi/cadence_qspi_apb.c | 5 +++--
> > 1 file changed, 3 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/spi/cadence_qspi_apb.c
> b/drivers/spi/cadence_qspi_apb.c
> > index e02f2217f4..b300f36607 100644
> > --- a/drivers/spi/cadence_qspi_apb.c
> > +++ b/drivers/spi/cadence_qspi_apb.c
> > @@ -47,6 +47,7 @@
> > #define CQSPI_INST_TYPE_QUAD 2
> >
> > #define CQSPI_STIG_DATA_LEN_MAX 8
> > +#define CQSPI_INDIRECTTRIGGER_ADDR_MASK 0xFFFFF
> >
> > #define CQSPI_DUMMY_CLKS_PER_BYTE 8
> > #define CQSPI_DUMMY_BYTES_MAX 4
> > @@ -560,7 +561,7 @@ int
> cadence_qspi_apb_indirect_read_setup(struct cadence_spi_platdata *plat,
> > addr_bytes = cmdlen - 1;
> >
> > /* Setup the indirect trigger address */
> > - writel((u32)plat->ahbbase,
> > + writel(((u32)plat->ahbbase & CQSPI_INDIRECTTRIGGER_ADDR_MASK),
> > plat->regbase + CQSPI_REG_INDIRECTTRIGGER);
> >
> > /* Configure the opcode */
> > @@ -710,7 +711,7 @@ int
> cadence_qspi_apb_indirect_write_setup(struct cadence_spi_platdata *plat,
> > return -EINVAL;
> > }
> > /* Setup the indirect trigger address */
> > - writel((u32)plat->ahbbase,
> > + writel(((u32)plat->ahbbase & CQSPI_INDIRECTTRIGGER_ADDR_MASK),
> > plat->regbase + CQSPI_REG_INDIRECTTRIGGER);
> >
> > /* Configure the opcode */
> >
>
>
^ permalink raw reply [flat|nested] 12+ messages in thread
* [U-Boot] arm socfpga: Revert "spi: cadence_qspi_apb: Support 32 bit AHB address"
2017-12-04 16:41 ` Vignesh R
@ 2017-12-04 17:01 ` Frank Mori Hess
2017-12-04 17:13 ` Vignesh R
0 siblings, 1 reply; 12+ messages in thread
From: Frank Mori Hess @ 2017-12-04 17:01 UTC (permalink / raw)
To: u-boot
On Mon, Dec 4, 2017 at 11:41 AM, Vignesh R <vigneshr@ti.com> wrote:
> Hi,
>
> On 04-Dec-17 6:41 PM, Frank Mori Hess wrote:
>> Since your commit broke my platform to fix yours, shouldn't it be
>> reverted and TI platforms use your pending patch queue?
>>
>
> Socfpga DT defined ahb base as 0xffa00000 while masked upper bits in the
> code, which was confusing. And seems that my patch did work on some
> socfgpa board looking at the original commit message.
There is nothing in the original commit message that suggests it
worked on any socfpga board, unless you mean
"Since AHB address is passed from DT
and read as u32 value, it anyway does not make sense to mask upper bits."
which is simply wrong.
> If the patch is reverted then, applying pending patches alone will not
> help because my patch would be needed anyway to make sure we don't mask
> 31-20 bits on TI platforms.
No it won't needed, see http://patchwork.ozlabs.org/patch/838592/ that
patch series writes plat->trigger_address instead of ahbbase (masked
or not).
^ permalink raw reply [flat|nested] 12+ messages in thread
* [U-Boot] arm socfpga: Revert "spi: cadence_qspi_apb: Support 32 bit AHB address"
2017-12-04 17:01 ` Frank Mori Hess
@ 2017-12-04 17:13 ` Vignesh R
0 siblings, 0 replies; 12+ messages in thread
From: Vignesh R @ 2017-12-04 17:13 UTC (permalink / raw)
To: u-boot
On 04-Dec-17 10:31 PM, Frank Mori Hess wrote:
> On Mon, Dec 4, 2017 at 11:41 AM, Vignesh R <vigneshr@ti.com> wrote:
>> Hi,
>>
>> On 04-Dec-17 6:41 PM, Frank Mori Hess wrote:
>>> Since your commit broke my platform to fix yours, shouldn't it be
>>> reverted and TI platforms use your pending patch queue?
>>>
>>
>> Socfpga DT defined ahb base as 0xffa00000 while masked upper bits in the
>> code, which was confusing. And seems that my patch did work on some
>> socfgpa board looking at the original commit message.
>
> There is nothing in the original commit message that suggests it
> worked on any socfpga board, unless you mean
>
> "Since AHB address is passed from DT
> and read as u32 value, it anyway does not make sense to mask upper bits."
>
> which is simply wrong.
>
There is a "Tested-by:" tag in the commit as well as:
https://patchwork.ozlabs.org/patch/609955/
>> If the patch is reverted then, applying pending patches alone will not
>> help because my patch would be needed anyway to make sure we don't mask
>> 31-20 bits on TI platforms.
>
> No it won't needed, see http://patchwork.ozlabs.org/patch/838592/ that
> patch series writes plat->trigger_address instead of ahbbase (masked
> or not).
>
Okay, but reverting this patch would mean Jason has to rebase above
patch. Instead applying that patch would anyway fix the issue.
^ permalink raw reply [flat|nested] 12+ messages in thread
* [U-Boot] arm socfpga: Revert "spi: cadence_qspi_apb: Support 32 bit AHB address"
2017-12-03 15:54 ` Fabio Estevam
@ 2017-12-03 16:42 ` Frank Mori Hess
0 siblings, 0 replies; 12+ messages in thread
From: Frank Mori Hess @ 2017-12-03 16:42 UTC (permalink / raw)
To: u-boot
It looks like the change I'm trying to revert got rejected a couple
years ago in another form:
https://lists.denx.de/pipermail/u-boot/2015-August/224556.html
In particular at the end Marek says:
>> /* Indirect mode configurations */
>> writel((plat->sram_size/2), plat->regbase + CQSPI_REG_SRAMPARTITION);
>> - writel((u32)plat->ahbbase & CQSPI_INDIRECTTRIGGER_ADDR_MASK,
>> + writel((u32)plat->trigger_base,
>> plat->regbase + CQSPI_REG_INDIRECTTRIGGER);
>
>Here you actually changed to logic of the code, which breaks it for SoCFPGA.
>plat->ahbbase & CQSPI_INDIRECTTRIGGER_ADDR_MASK = 0x0 for SoCFPGA, but now
>you changed it such that 0xffa00000 is written into the register. Same does
>apply for all your changes below.
On Sun, Dec 3, 2017 at 10:54 AM, Fabio Estevam <festevam@gmail.com> wrote:
> On Sun, Dec 3, 2017 at 1:51 PM, Frank Mori Hess <fmh6jj@gmail.com> wrote:
>> On Sun, Dec 3, 2017 at 10:49 AM, Fabio Estevam <festevam@gmail.com> wrote:
>>> On Sun, Dec 3, 2017 at 1:36 PM, Frank Mori Hess <fmh6jj@gmail.com> wrote:
>>>> This reverts commit dac3bf20fb2c9b03476be0d73db620f62ab3cee1.
>>>
>>> Please explain the reasoning for the revert.
>>
>> It looks like my original post got stuck in moderation:
>
> You should explain inside the commit log why you think it is a good
> idea to do the revert.
--
Frank
^ permalink raw reply [flat|nested] 12+ messages in thread
* [U-Boot] arm socfpga: Revert "spi: cadence_qspi_apb: Support 32 bit AHB address"
2017-12-03 15:51 ` Frank Mori Hess
@ 2017-12-03 15:54 ` Fabio Estevam
2017-12-03 16:42 ` Frank Mori Hess
0 siblings, 1 reply; 12+ messages in thread
From: Fabio Estevam @ 2017-12-03 15:54 UTC (permalink / raw)
To: u-boot
On Sun, Dec 3, 2017 at 1:51 PM, Frank Mori Hess <fmh6jj@gmail.com> wrote:
> On Sun, Dec 3, 2017 at 10:49 AM, Fabio Estevam <festevam@gmail.com> wrote:
>> On Sun, Dec 3, 2017 at 1:36 PM, Frank Mori Hess <fmh6jj@gmail.com> wrote:
>>> This reverts commit dac3bf20fb2c9b03476be0d73db620f62ab3cee1.
>>
>> Please explain the reasoning for the revert.
>
> It looks like my original post got stuck in moderation:
You should explain inside the commit log why you think it is a good
idea to do the revert.
^ permalink raw reply [flat|nested] 12+ messages in thread
* [U-Boot] arm socfpga: Revert "spi: cadence_qspi_apb: Support 32 bit AHB address"
2017-12-03 15:49 ` Fabio Estevam
@ 2017-12-03 15:51 ` Frank Mori Hess
2017-12-03 15:54 ` Fabio Estevam
0 siblings, 1 reply; 12+ messages in thread
From: Frank Mori Hess @ 2017-12-03 15:51 UTC (permalink / raw)
To: u-boot
On Sun, Dec 3, 2017 at 10:49 AM, Fabio Estevam <festevam@gmail.com> wrote:
> On Sun, Dec 3, 2017 at 1:36 PM, Frank Mori Hess <fmh6jj@gmail.com> wrote:
>> This reverts commit dac3bf20fb2c9b03476be0d73db620f62ab3cee1.
>
> Please explain the reasoning for the revert.
It looks like my original post got stuck in moderation:
---------- Forwarded message ----------
From: Frank Mori Hess <fmh6jj@gmail.com>
Date: Sat, Dec 2, 2017 at 7:50 PM
Subject: commit dac3bf20fb2c9b03476be0d73db620f62ab3cee1 breaks cadence driver
To: u-boot at lists.denx.de
Hi,
I've been debugging why u-boot spl crashes in a loop when I boot off a
cadence qspi flash. I narrowed it down to the changes from commit
dac3bf20fb2c9b03476be0d73db620f62ab3cee1 which removes
CQSPI_INDIRECTTRIGGER_ADDR_MASK. Restoring the mask allows the spl to
successfully load the main u-boot. My board is an Altera HPS cyclone
V socfpga. It has an ahb base address of 0xffa00000 and for some
reason, without the CQSPI_INDIRECTTRIGGER_ADDR_MASK the board reboots
when cadence_qspi_apb_indirect_read_execute tries to read from the ahb
base address. I'm using version 2016.11 of u-boot.
--
Frank
--
Frank
--
Frank
^ permalink raw reply [flat|nested] 12+ messages in thread
* [U-Boot] arm socfpga: Revert "spi: cadence_qspi_apb: Support 32 bit AHB address"
2017-12-03 15:36 Frank Mori Hess
2017-12-03 15:49 ` Fabio Estevam
@ 2017-12-03 15:50 ` Frank Mori Hess
1 sibling, 0 replies; 12+ messages in thread
From: Frank Mori Hess @ 2017-12-03 15:50 UTC (permalink / raw)
To: u-boot
Oops, ignore that patch I didn't merge it correctly
On Sun, Dec 3, 2017 at 10:36 AM, Frank Mori Hess <fmh6jj@gmail.com> wrote:
> This reverts commit dac3bf20fb2c9b03476be0d73db620f62ab3cee1.
>
> Signed-off-by: Frank Mori Hess <fmh6jj@gmail.com>
> ---
> drivers/spi/cadence_qspi_apb.c | 5 +++--
> 1 file changed, 3 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c
> index e02f2217f4..b300f36607 100644
> --- a/drivers/spi/cadence_qspi_apb.c
> +++ b/drivers/spi/cadence_qspi_apb.c
> @@ -47,6 +47,7 @@
> #define CQSPI_INST_TYPE_QUAD 2
>
> #define CQSPI_STIG_DATA_LEN_MAX 8
> +#define CQSPI_INDIRECTTRIGGER_ADDR_MASK 0xFFFFF
>
> #define CQSPI_DUMMY_CLKS_PER_BYTE 8
> #define CQSPI_DUMMY_BYTES_MAX 4
> @@ -560,7 +561,7 @@ int cadence_qspi_apb_indirect_read_setup(struct cadence_spi_platdata *plat,
> addr_bytes = cmdlen - 1;
>
> /* Setup the indirect trigger address */
> - writel((u32)plat->ahbbase,
> + writel(((u32)plat->ahbbase & CQSPI_INDIRECTTRIGGER_ADDR_MASK),
> plat->regbase + CQSPI_REG_INDIRECTTRIGGER);
>
> /* Configure the opcode */
> @@ -710,7 +711,7 @@ int cadence_qspi_apb_indirect_write_setup(struct cadence_spi_platdata *plat,
> return -EINVAL;
> }
> /* Setup the indirect trigger address */
> - writel((u32)plat->ahbbase,
> + writel(((u32)plat->ahbbase & CQSPI_INDIRECTTRIGGER_ADDR_MASK),
> plat->regbase + CQSPI_REG_INDIRECTTRIGGER);
>
> /* Configure the opcode */
> --
> 2.11.0
>
>
--
Frank
^ permalink raw reply [flat|nested] 12+ messages in thread
* [U-Boot] arm socfpga: Revert "spi: cadence_qspi_apb: Support 32 bit AHB address"
2017-12-03 15:36 Frank Mori Hess
@ 2017-12-03 15:49 ` Fabio Estevam
2017-12-03 15:51 ` Frank Mori Hess
2017-12-03 15:50 ` Frank Mori Hess
1 sibling, 1 reply; 12+ messages in thread
From: Fabio Estevam @ 2017-12-03 15:49 UTC (permalink / raw)
To: u-boot
On Sun, Dec 3, 2017 at 1:36 PM, Frank Mori Hess <fmh6jj@gmail.com> wrote:
> This reverts commit dac3bf20fb2c9b03476be0d73db620f62ab3cee1.
Please explain the reasoning for the revert.
^ permalink raw reply [flat|nested] 12+ messages in thread
* [U-Boot] arm socfpga: Revert "spi: cadence_qspi_apb: Support 32 bit AHB address"
@ 2017-12-03 15:36 Frank Mori Hess
2017-12-03 15:49 ` Fabio Estevam
2017-12-03 15:50 ` Frank Mori Hess
0 siblings, 2 replies; 12+ messages in thread
From: Frank Mori Hess @ 2017-12-03 15:36 UTC (permalink / raw)
To: u-boot
This reverts commit dac3bf20fb2c9b03476be0d73db620f62ab3cee1.
Signed-off-by: Frank Mori Hess <fmh6jj@gmail.com>
---
drivers/spi/cadence_qspi_apb.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c
index e02f2217f4..b300f36607 100644
--- a/drivers/spi/cadence_qspi_apb.c
+++ b/drivers/spi/cadence_qspi_apb.c
@@ -47,6 +47,7 @@
#define CQSPI_INST_TYPE_QUAD 2
#define CQSPI_STIG_DATA_LEN_MAX 8
+#define CQSPI_INDIRECTTRIGGER_ADDR_MASK 0xFFFFF
#define CQSPI_DUMMY_CLKS_PER_BYTE 8
#define CQSPI_DUMMY_BYTES_MAX 4
@@ -560,7 +561,7 @@ int cadence_qspi_apb_indirect_read_setup(struct cadence_spi_platdata *plat,
addr_bytes = cmdlen - 1;
/* Setup the indirect trigger address */
- writel((u32)plat->ahbbase,
+ writel(((u32)plat->ahbbase & CQSPI_INDIRECTTRIGGER_ADDR_MASK),
plat->regbase + CQSPI_REG_INDIRECTTRIGGER);
/* Configure the opcode */
@@ -710,7 +711,7 @@ int cadence_qspi_apb_indirect_write_setup(struct cadence_spi_platdata *plat,
return -EINVAL;
}
/* Setup the indirect trigger address */
- writel((u32)plat->ahbbase,
+ writel(((u32)plat->ahbbase & CQSPI_INDIRECTTRIGGER_ADDR_MASK),
plat->regbase + CQSPI_REG_INDIRECTTRIGGER);
/* Configure the opcode */
--
2.11.0
^ permalink raw reply related [flat|nested] 12+ messages in thread
end of thread, other threads:[~2017-12-04 17:13 UTC | newest]
Thread overview: 12+ messages (download: mbox.gz / follow: Atom feed)
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2017-12-03 15:59 [U-Boot] arm socfpga: Revert "spi: cadence_qspi_apb: Support 32 bit AHB address" Frank Mori Hess
2017-12-04 4:15 ` Vignesh R
2017-12-04 13:11 ` Frank Mori Hess
2017-12-04 16:41 ` Vignesh R
2017-12-04 17:01 ` Frank Mori Hess
2017-12-04 17:13 ` Vignesh R
-- strict thread matches above, loose matches on Subject: below --
2017-12-03 15:36 Frank Mori Hess
2017-12-03 15:49 ` Fabio Estevam
2017-12-03 15:51 ` Frank Mori Hess
2017-12-03 15:54 ` Fabio Estevam
2017-12-03 16:42 ` Frank Mori Hess
2017-12-03 15:50 ` Frank Mori Hess
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