From: Masahiro Yamada <yamada.masahiro@socionext.com> To: linux-arm-kernel <linux-arm-kernel@lists.infradead.org> Cc: Mark Rutland <mark.rutland@arm.com>, DTML <devicetree@vger.kernel.org>, Linux Kernel Mailing List <linux-kernel@vger.kernel.org>, Rob Herring <robh+dt@kernel.org>, Frank Rowand <frowand.list@gmail.com> Subject: Re: [PATCH] ARM: dts: uniphier: rename cache controller nodes to follow json-schema Date: Sat, 29 Feb 2020 15:07:27 +0900 [thread overview] Message-ID: <CAK7LNARGNmg8VtwZgxets5NYLnNrzp1eryEOEFGyCxDvKiVisQ@mail.gmail.com> (raw) In-Reply-To: <20200227123726.12910-1-yamada.masahiro@socionext.com> On Thu, Feb 27, 2020 at 9:38 PM Masahiro Yamada <yamada.masahiro@socionext.com> wrote: > > Follow the standard nodename pattern > "^(cache-controller|cpu)(@[0-9a-f,]+)*$" defined in > schemas/cache-controller.yaml of dt-schema. > > Otherwise, after the dt-binding is converted to json-schema, > 'make ARCH=arm dtbs_check' will show a warning like this: > > l2-cache@500c0000: $nodename:0: 'l2-cache@500c0000' does not match '^(cache-controller|cpu)(@[0-9a-f,]+)*$' > > Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> > --- Applied to linux-uniphier. > > arch/arm/boot/dts/uniphier-ld4.dtsi | 2 +- > arch/arm/boot/dts/uniphier-pro4.dtsi | 2 +- > arch/arm/boot/dts/uniphier-pro5.dtsi | 4 ++-- > arch/arm/boot/dts/uniphier-pxs2.dtsi | 2 +- > arch/arm/boot/dts/uniphier-sld8.dtsi | 2 +- > 5 files changed, 6 insertions(+), 6 deletions(-) > > diff --git a/arch/arm/boot/dts/uniphier-ld4.dtsi b/arch/arm/boot/dts/uniphier-ld4.dtsi > index 197bee7d8b7f..06e7400d2940 100644 > --- a/arch/arm/boot/dts/uniphier-ld4.dtsi > +++ b/arch/arm/boot/dts/uniphier-ld4.dtsi > @@ -51,7 +51,7 @@ > ranges; > interrupt-parent = <&intc>; > > - l2: l2-cache@500c0000 { > + l2: cache-controller@500c0000 { > compatible = "socionext,uniphier-system-cache"; > reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, > <0x506c0000 0x400>; > diff --git a/arch/arm/boot/dts/uniphier-pro4.dtsi b/arch/arm/boot/dts/uniphier-pro4.dtsi > index b02bc8a6346b..1c866f0306fc 100644 > --- a/arch/arm/boot/dts/uniphier-pro4.dtsi > +++ b/arch/arm/boot/dts/uniphier-pro4.dtsi > @@ -59,7 +59,7 @@ > ranges; > interrupt-parent = <&intc>; > > - l2: l2-cache@500c0000 { > + l2: cache-controller@500c0000 { > compatible = "socionext,uniphier-system-cache"; > reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, > <0x506c0000 0x400>; > diff --git a/arch/arm/boot/dts/uniphier-pro5.dtsi b/arch/arm/boot/dts/uniphier-pro5.dtsi > index f84a43a10f38..da772429b55a 100644 > --- a/arch/arm/boot/dts/uniphier-pro5.dtsi > +++ b/arch/arm/boot/dts/uniphier-pro5.dtsi > @@ -131,7 +131,7 @@ > ranges; > interrupt-parent = <&intc>; > > - l2: l2-cache@500c0000 { > + l2: cache-controller@500c0000 { > compatible = "socionext,uniphier-system-cache"; > reg = <0x500c0000 0x2000>, <0x503c0100 0x8>, > <0x506c0000 0x400>; > @@ -144,7 +144,7 @@ > next-level-cache = <&l3>; > }; > > - l3: l3-cache@500c8000 { > + l3: cache-controller@500c8000 { > compatible = "socionext,uniphier-system-cache"; > reg = <0x500c8000 0x2000>, <0x503c8100 0x8>, > <0x506c8000 0x400>; > diff --git a/arch/arm/boot/dts/uniphier-pxs2.dtsi b/arch/arm/boot/dts/uniphier-pxs2.dtsi > index 989b2a241822..7044f8700cb2 100644 > --- a/arch/arm/boot/dts/uniphier-pxs2.dtsi > +++ b/arch/arm/boot/dts/uniphier-pxs2.dtsi > @@ -157,7 +157,7 @@ > ranges; > interrupt-parent = <&intc>; > > - l2: l2-cache@500c0000 { > + l2: cache-controller@500c0000 { > compatible = "socionext,uniphier-system-cache"; > reg = <0x500c0000 0x2000>, <0x503c0100 0x8>, > <0x506c0000 0x400>; > diff --git a/arch/arm/boot/dts/uniphier-sld8.dtsi b/arch/arm/boot/dts/uniphier-sld8.dtsi > index fbfd25050a04..09992163e1f4 100644 > --- a/arch/arm/boot/dts/uniphier-sld8.dtsi > +++ b/arch/arm/boot/dts/uniphier-sld8.dtsi > @@ -51,7 +51,7 @@ > ranges; > interrupt-parent = <&intc>; > > - l2: l2-cache@500c0000 { > + l2: cache-controller@500c0000 { > compatible = "socionext,uniphier-system-cache"; > reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, > <0x506c0000 0x400>; > -- > 2.17.1 > > > _______________________________________________ > linux-arm-kernel mailing list > linux-arm-kernel@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel -- Best Regards Masahiro Yamada
WARNING: multiple messages have this Message-ID (diff)
From: Masahiro Yamada <yamada.masahiro@socionext.com> To: linux-arm-kernel <linux-arm-kernel@lists.infradead.org> Cc: Mark Rutland <mark.rutland@arm.com>, DTML <devicetree@vger.kernel.org>, Rob Herring <robh+dt@kernel.org>, Frank Rowand <frowand.list@gmail.com>, Linux Kernel Mailing List <linux-kernel@vger.kernel.org> Subject: Re: [PATCH] ARM: dts: uniphier: rename cache controller nodes to follow json-schema Date: Sat, 29 Feb 2020 15:07:27 +0900 [thread overview] Message-ID: <CAK7LNARGNmg8VtwZgxets5NYLnNrzp1eryEOEFGyCxDvKiVisQ@mail.gmail.com> (raw) In-Reply-To: <20200227123726.12910-1-yamada.masahiro@socionext.com> On Thu, Feb 27, 2020 at 9:38 PM Masahiro Yamada <yamada.masahiro@socionext.com> wrote: > > Follow the standard nodename pattern > "^(cache-controller|cpu)(@[0-9a-f,]+)*$" defined in > schemas/cache-controller.yaml of dt-schema. > > Otherwise, after the dt-binding is converted to json-schema, > 'make ARCH=arm dtbs_check' will show a warning like this: > > l2-cache@500c0000: $nodename:0: 'l2-cache@500c0000' does not match '^(cache-controller|cpu)(@[0-9a-f,]+)*$' > > Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> > --- Applied to linux-uniphier. > > arch/arm/boot/dts/uniphier-ld4.dtsi | 2 +- > arch/arm/boot/dts/uniphier-pro4.dtsi | 2 +- > arch/arm/boot/dts/uniphier-pro5.dtsi | 4 ++-- > arch/arm/boot/dts/uniphier-pxs2.dtsi | 2 +- > arch/arm/boot/dts/uniphier-sld8.dtsi | 2 +- > 5 files changed, 6 insertions(+), 6 deletions(-) > > diff --git a/arch/arm/boot/dts/uniphier-ld4.dtsi b/arch/arm/boot/dts/uniphier-ld4.dtsi > index 197bee7d8b7f..06e7400d2940 100644 > --- a/arch/arm/boot/dts/uniphier-ld4.dtsi > +++ b/arch/arm/boot/dts/uniphier-ld4.dtsi > @@ -51,7 +51,7 @@ > ranges; > interrupt-parent = <&intc>; > > - l2: l2-cache@500c0000 { > + l2: cache-controller@500c0000 { > compatible = "socionext,uniphier-system-cache"; > reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, > <0x506c0000 0x400>; > diff --git a/arch/arm/boot/dts/uniphier-pro4.dtsi b/arch/arm/boot/dts/uniphier-pro4.dtsi > index b02bc8a6346b..1c866f0306fc 100644 > --- a/arch/arm/boot/dts/uniphier-pro4.dtsi > +++ b/arch/arm/boot/dts/uniphier-pro4.dtsi > @@ -59,7 +59,7 @@ > ranges; > interrupt-parent = <&intc>; > > - l2: l2-cache@500c0000 { > + l2: cache-controller@500c0000 { > compatible = "socionext,uniphier-system-cache"; > reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, > <0x506c0000 0x400>; > diff --git a/arch/arm/boot/dts/uniphier-pro5.dtsi b/arch/arm/boot/dts/uniphier-pro5.dtsi > index f84a43a10f38..da772429b55a 100644 > --- a/arch/arm/boot/dts/uniphier-pro5.dtsi > +++ b/arch/arm/boot/dts/uniphier-pro5.dtsi > @@ -131,7 +131,7 @@ > ranges; > interrupt-parent = <&intc>; > > - l2: l2-cache@500c0000 { > + l2: cache-controller@500c0000 { > compatible = "socionext,uniphier-system-cache"; > reg = <0x500c0000 0x2000>, <0x503c0100 0x8>, > <0x506c0000 0x400>; > @@ -144,7 +144,7 @@ > next-level-cache = <&l3>; > }; > > - l3: l3-cache@500c8000 { > + l3: cache-controller@500c8000 { > compatible = "socionext,uniphier-system-cache"; > reg = <0x500c8000 0x2000>, <0x503c8100 0x8>, > <0x506c8000 0x400>; > diff --git a/arch/arm/boot/dts/uniphier-pxs2.dtsi b/arch/arm/boot/dts/uniphier-pxs2.dtsi > index 989b2a241822..7044f8700cb2 100644 > --- a/arch/arm/boot/dts/uniphier-pxs2.dtsi > +++ b/arch/arm/boot/dts/uniphier-pxs2.dtsi > @@ -157,7 +157,7 @@ > ranges; > interrupt-parent = <&intc>; > > - l2: l2-cache@500c0000 { > + l2: cache-controller@500c0000 { > compatible = "socionext,uniphier-system-cache"; > reg = <0x500c0000 0x2000>, <0x503c0100 0x8>, > <0x506c0000 0x400>; > diff --git a/arch/arm/boot/dts/uniphier-sld8.dtsi b/arch/arm/boot/dts/uniphier-sld8.dtsi > index fbfd25050a04..09992163e1f4 100644 > --- a/arch/arm/boot/dts/uniphier-sld8.dtsi > +++ b/arch/arm/boot/dts/uniphier-sld8.dtsi > @@ -51,7 +51,7 @@ > ranges; > interrupt-parent = <&intc>; > > - l2: l2-cache@500c0000 { > + l2: cache-controller@500c0000 { > compatible = "socionext,uniphier-system-cache"; > reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, > <0x506c0000 0x400>; > -- > 2.17.1 > > > _______________________________________________ > linux-arm-kernel mailing list > linux-arm-kernel@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel -- Best Regards Masahiro Yamada _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2020-02-29 6:08 UTC|newest] Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top 2020-02-27 12:37 [PATCH] ARM: dts: uniphier: rename cache controller nodes to follow json-schema Masahiro Yamada 2020-02-27 12:37 ` Masahiro Yamada 2020-02-29 6:07 ` Masahiro Yamada [this message] 2020-02-29 6:07 ` Masahiro Yamada
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